A platform architecture design method for the operating mode of a multi-core CPU

Abstract

A platform architecture design method for the operating mode of a multi-core CPU. The platform architecture design method includes the following steps: The homogeneous multi-core CPU first starts the main core, and the main core is core0 of the homogeneous multi-core CPU; The main core wakes up the slave cores during the initialization phase; After the slave cores are started, the slave cores operate in a combined manner of AMP / SMP; The main core runs the general underlying software of the platform. Here, CPU is the central processing unit, AMP is asymmetric multi-processing, and SMP is symmetric multi-processing. The EHMP operating mode proposed by the present invention combines the advantages of the traditional AMP and SMP modes, follows the principle of realizing high-reliability and high-real-time functions in the bare-running mode and realizing non-strong real-time functions in the operating system mode, takes into account the reliability, real-time performance and CPU processing power of the product, and ensures the security of multi-core operation and system reliability.

Description

Technical Field

[0001] The present invention belongs to the technical field of embedded systems of secondary equipment in power systems, and relates to a platform architecture design method for the operating mode of a multi-core CPU. Background Art

[0002] In secondary power equipment, with the update and upgrade of embedded chip technology, the use of multi-core CPUs is becoming more and more common. Currently, the common operating modes of multi-core CPUs include AMP (Asymmetric Multi-Processing) and SMP (Symmetric Multi-Processing). In the AMP mode, each core runs its own program independently, and the coupling degree between multiple cores is relatively low. It can obtain excellent real-time performance and reliability by running a single core bare, or it can run an operating system on a single core to complete non-real-time task processing. The SMP mode can uniformly schedule multiple cores under one operating system, multiplying the processing power of a single system, and is suitable for complex non-real-time applications.

[0003] Secondary power equipment includes relay protection, safety automatic devices, measurement and control, network gateways, PMUs, clocks, etc. Some products have high requirements for reliability and real-time performance and are suitable for the AMP bare-running scheme; some products do not require real-time performance, but have complex functions and high requirements for CPU processing power and are suitable for the SMP operating system scheme. Therefore, it is difficult to meet the requirements of various secondary power equipment using only one of the traditional AMP or SMP modes, resulting in a large number of software versions for the underlying framework of the multi-core CPU platform, which not only increases the workload of development and maintenance, but also has an adverse impact on system reliability.

[0004] In addition, the main core of the traditional AMP mode usually runs the operating system. The main core is responsible for the startup and boot of slave cores and is the core of the multi-core AMP system. The startup speed of the operating system is relatively slow, and the code is huge and complex, making it difficult to achieve complete security and controllability, which reduces the reliability of the AMP system to a certain extent. Summary of the Invention

[0005] In order to solve the problems existing in the prior art, the purpose of the present invention is to provide a platform architecture design method for the operating mode of a multi-core CPU: an enhanced hybrid multi-processing mode, also known as EHMP (Enhanced Hybrid Multi-processing). It solves the problem that the underlying architecture of multi-core processors in secondary power equipment is not unified and it is difficult to simultaneously consider reliability, real-time performance, and CPU processing power.

[0006] The present invention adopts the following technical solutions:

[0007] A platform architecture design method for the operating mode of a multi-core CPU, the platform architecture design method comprising the following steps:

[0008] Step 1, the homogeneous multi-core CPU first starts the main core,

[0009] wherein, the main core is core0 of the homogeneous multi-core CPU;

[0010] Step 2, after the main core starts, it enters the initialization stage, and within a preset duration in the initialization stage, the main core wakes up the slave cores;

[0011] Step 3, after the main core wakes up the slave cores, the slave cores start immediately, and the slave cores run in the AMP mode or the SMP mode;

[0012] Step 4, the main core runs the platformized general underlying software, which is responsible for the expansion of the peripheral communication interface and monitoring the running state of the slave cores;

[0013] wherein, CPU is the central processing unit, AMP is asymmetric multi-processing, and SMP is symmetric multi-processing.

[0014] In Step 1, after the CPU is powered on, it first confirms the main core and the slave cores. The single core that starts first is the main core, and the remaining cores are slave cores.

[0015] The startup sequence of the slave cores is controlled by the main core.

[0016] In Step 2, after the main core starts up, it wakes up the slave cores in sequence according to the operating mode configuration of the multi-core CPU. The unused slave cores will not be woken up and will always be in the sleep state to reduce power consumption.

[0017] In Step 2, the preset duration is 500 ms.

[0018] In Step 3, after the slave cores start up, according to the operating mode configuration of the multi-core CPU, the slave cores can deploy and run in any combination of operating modes. All slave cores run the bare-metal program / operating system individually, that is, the slave core AMP operating mode; all slave cores run a single operating system together, that is, the slave core SMP operating mode; some slave cores run an operating system, and the rest run the bare-metal program / operating system individually, and all slave cores are in the SMP / AMP hybrid operating mode.

[0019] In a quad-core CPU, the number of slave cores is 1 to 3.

[0020] In Step 3, if there are multiple scenarios of running the operating system in the SMP mode, the operating system is not limited as long as it can support running on the homogeneous multi-core CPU; the operating system supports binding application programs to specific cores.

[0021] In step 4, after the main core wakes up and starts the slave cores, it will continue to independently run the bare-metal program to implement the underlying general functions. The main core implements the expansion of the peripheral communication interface and adopts an inter-core real-time detection strategy to monitor the running status of each slave core, and performs self-recovery processing on the slave core with abnormal operation.

[0022] In step 4, the main core of the homogeneous multi-core CPU system runs the platformized general underlying software in bare-metal form.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0024] The present invention proposes an EHMP (Enhanced Hybrid Multi-processing) multi-core homogeneous CPU platform architecture design scheme, following the principle of implementing high-reliability and high-real-time functions in bare-metal mode and non-strong real-time functions in operating system mode, unifying the underlying architecture of multi-core processors in various secondary power equipment. The main core adopts the bare-metal mode to implement the underlying general functions, ensuring the stable, safe and reliable operation of the multi-core CPU underlying infrastructure, with excellent real-time performance and flexible expansion ability. The slave cores can freely select the AMP or SMP combination configuration according to the application function requirements, effectively taking into account the reliability, real-time performance and processing power of the product. The present invention can be applied to various secondary power equipment such as relay protection, security automatic devices, measurement and control, network gateways, PMUs, clocks, etc., greatly improving the operation safety and system reliability of the multi-core CPU. Description of the Drawings

[0025] Figure 1 It is a schematic diagram of the multi-core CPU operation mode method;

[0026] Figure 2 It is a schematic diagram of the slave core SMP operation mode state in the multi-core CPU operation mode;

[0027] Figure 3 It is a schematic diagram of the slave core hybrid operation mode state in the multi-core CPU operation mode. Detailed Embodiments

[0028] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. The embodiments described in this application are only a part of the embodiments of the present invention, rather than all embodiments. Based on the spirit of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0029] The following embodiments all use the Allwinner T3 CPU as a multi-core CPU sample, and the Allwinner T3 is a quad-core CPU.

[0030] Embodiment 1

[0031] Figure 1 Schematic diagram of the operation mode method for a multi-core CPU, as Figure 1 described, the implementation steps of the multi-core enhanced hybrid processing mode include:

[0032] Step 1: After the multi-core CPU is powered on, the main core is started first.

[0033] In this step, core0 is started first, that is, core0 is used as the main core, and the other three cores are used as slave cores.

[0034] Step 2: The main core wakes up the slave cores.

[0035] In this step, the main core core0 has to wake up the three slave cores core1, core2, and core3 in sequence.

[0036] Step 3: The slave cores perform free combinations of operation modes.

[0037] In this step, the three slave cores run the same operating system and application programs.

[0038] Step 4: The main core runs the bare-metal business.

[0039] In this step, core0 runs its own bare-metal business program, and tasks with high real-time and reliability requirements are all run in the bare-metal program of core0.

[0040] At this time, the operating states of each core, the operating system, and the application are as Figure 2 shown. In the current embodiment, for the embedded device of the power system, tasks with high reliability and strong real-time performance are placed in the bare-metal program of core0; advanced application functions with less strict real-time requirements are deployed in the operating system jointly run by the slave cores in the SMP mode.

[0041] Figure 3 Schematic diagram of the state of the hybrid operation mode of the slave cores in the multi-core CPU operation mode.

[0042] Embodiment 2

[0043] Figure 1 Schematic diagram of the method for the multi-core enhanced hybrid multi-core processing mode of the multi-core CPU, as Figure 1 described, the steps of the multi-core enhanced symmetric multi-processing method include:

[0044] Step 1: After the multi-core CPU is powered on, the main core is started first.

[0045] In this step, core0 is started first, that is, core0 is used as the main core, and the other three cores are used as slave cores.

[0046] Step 2, the master core wakes up the slave cores.

[0047] In this step, the master core core0 needs to wake up the three slave cores core1, core2, and core3 in sequence.

[0048] Step 3, the slave cores perform free combinations of operating modes.

[0049] In this step, core1 of the three slave cores runs naked, core2 sleeps without running programs, core3 runs the operating system, and core1 and core3 run application programs independently.

[0050] Step 4, the master core runs naked-running services.

[0051] In this step, core0 and core1 run naked-running programs. Tasks with high real-time performance and high reliability are all run on the naked-running cores, and complex application functions with general real-time requirements are run on the operating system of core3.

[0052] The above has made a detailed description of the preferred embodiments of this patent. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those of ordinary skill in the art, various changes can be made without departing from the gist of this patent.

[0053] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: it is still possible to modify the specific embodiments of the present invention or make equivalent substitutions. Any modification or equivalent substitution that does not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A platform architecture design method for the operation mode of a multi-core CPU, characterized in that The platform architecture design method includes the following steps: Step 1, the homogeneous multi-core CPU first starts the main core, wherein, the main core is core0 of the homogeneous multi-core CPU; the startup sequence of the slave cores is controlled by the main core; Step 2, after the main core starts, it enters the initialization phase, and within a preset duration in the initialization phase, the main core wakes up the slave cores; Step 3, after the main core wakes up the slave cores, the slave cores start immediately and run in the AMP or SMP mode; In Step 3, after the slave cores start up, according to the configuration of the multi-core CPU operation mode, the slave cores can deploy the operation mode in any combination. All slave cores run the bare-metal program / operating system individually, that is, the slave core AMP operation mode; all slave cores run a single operating system together, that is, the slave core SMP operation mode; some slave cores run an operating system, and the rest run the bare-metal program / operating system individually, and all slave cores are in the SMP / AMP hybrid operation mode; Step 4, the main core runs the platformized general underlying software, which is used to be responsible for the extension of the peripheral communication interface and monitoring the operation status of the slave cores; wherein, CPU is the central processing unit, AMP is asymmetric multi-processing, and SMP is symmetric multi-processing; In Step 4, after the main core wakes up and starts the slave cores, the main core realizes the extension of the peripheral communication interface, and adopts the inter-core real-time detection strategy to monitor the operation status of each slave core, and performs self-recovery processing on the slave cores with abnormal operation; In Step 4, the main core runs the platformized general underlying software in the bare-metal form.

2. The platform architecture design method of a multi-core CPU operation mode according to claim 1, characterized in that: In Step 1, after the CPU is powered on, it first confirms the main core and the slave cores. The single core that starts first is the main core, and the remaining cores are the slave cores.

3. The platform architecture design method of a multi-core CPU operation mode according to claim 1, characterized in that: In Step 2, after the main core starts up, it wakes up the slave cores in sequence according to the configuration of the multi-core CPU operation mode. The unused slave cores will not be woken up and will always be in the sleep state to reduce power consumption.

4. The platform architecture design method of a multi-core CPU operation mode according to claim 1, characterized in that: In Step 2, the preset duration is 500 ms.

5. The platform architecture design method of a multi-core CPU operation mode according to claim 1, characterized in that: In a quad-core CPU, the number of slave cores is 1-3.

6. The platform architecture design method of a multi-core CPU operation mode according to claim 1, characterized in that: In Step 3, if there are multiple scenarios of running the operating system in the SMP mode, the operating system is not limited and is used to support running on the homogeneous multi-core CPU; the operating system supports binding application programs to specific cores.

Images