A method for detecting over-erasure phenomenon of non-volatile memory

Abstract

The present invention discloses a method for detecting over-erasure of a non-volatile memory, comprising: step S1, powering on the non-volatile memory to be detected, so that the non-volatile memory releases internal configuration information; step S2, detecting leakage initialization; step S3, performing leakage detection on all global bit lines of the non-volatile memory, if the global bit line currently being detected has leakage, then entering step S4; step S4, sequentially performing leakage detection on all local bit lines in the global bit line currently having leakage, if the local bit line currently being detected has leakage, then entering step S5; step S5, performing over-erasure repair operation on the local bit line currently having leakage. The present invention can quickly detect and / or eliminate over-erasure caused by erroneous power failure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor memory, and in particular to a method for detecting over-erasure of a non-volatile memory. Background Art

[0002] For floating gate flash memory, since the charge is stored in the floating gate of the storage cell, when there is more charge in the floating gate, the threshold voltage of the storage cell is high, and when there is less charge in the floating gate, the threshold voltage of the storage cell is low. In this way, it is possible to distinguish whether the storage is "0" or "1" according to the amount of stored charge. General definition: during programming, the charge is attracted to the floating gate, there is more charge in the floating gate, the threshold voltage of the storage cell is high, and the stored data is "0". On the contrary, during programming, the charge is sucked out of the floating gate, there is less charge in the floating gate, the threshold voltage of the storage cell is low, and the stored data is "1". The voltage of the word line and the voltage of the bit line on a storage cell have an impact on the floating gate. It can be seen that the final voltage on the floating gate is determined by the voltage of the word line and the bit line.

[0003] like Figure 1 As shown, Figure 1 This is the basic process of general power-on. The power-on circuit is initialized, and then waits for the power-on voltage to stabilize. The chip (flash memory or floating gate flash memory) starts to read the internal configuration information. After reading the information, the configuration is judged to be successful, the chip is configured, and the power-on is completed. The user can perform read, write and erase operations.

[0004] However, due to the chip's misoperation, the power supply suddenly failed during the last erasing process, resulting in the failure of chip erasing. Since the erased storage unit was not repaired in time, the reading and writing of the unerased storage unit failed.

[0005] Specifically, when performing a read operation, a VREAD (e.g., 5V) voltage is applied to the word line of the memory cell to be read, a VGBL (e.g., 1V) voltage is applied to the corresponding bit line, and a VDSEL (e.g., 0V) voltage is applied to the word line of the memory cell that does not need to be read. However, due to the compact characteristics of the memory cell, some memory cells share word lines in the row direction, and other memory cells share bit lines in the column direction. When more memory cells share bit lines, the bit line voltage will also contribute to the floating gate. When the memory cell is over-erased or the charge in the floating gate is too little, the memory cell that is not selected (does not need to be read) will also be slightly turned on, contributing additional leakage current. When reading "0", this leakage current may cause the signal that should have read "0" to become a "1" signal.

[0006] Therefore, in the erasing process of floating gate flash memory, it is necessary to correct this over erase correction (OEC) so that a certain amount of charge is maintained on the floating gate of the erased memory cell to prevent the information of the unerased and programmed memory cells from being read incorrectly.

[0007] In addition, if the storage device where the storage unit being erased is located suddenly loses power or is suddenly interrupted, this OEC method cannot be executed. When reading the non-erased area is re-enabled next time, the "0" storage unit may be misread, causing the chip to fail. Summary of the invention

[0008] The object of the present invention is to provide a method for detecting over-erasure of a non-volatile memory, so as to achieve the purpose of quickly detecting and / or eliminating the over-erasure caused by erroneous power failure.

[0009] In order to achieve the above objectives, the present invention is implemented by the following technical solutions:

[0010] A method for detecting over-erasure of a non-volatile memory comprises: step S1, powering on a non-volatile memory to be detected, so that the non-volatile memory releases internal configuration information.

[0011] Step S2, initializing the leakage detection. Step S3, performing leakage detection on all global bit lines of the non-volatile memory, if leakage exists in the global bit line currently being detected, proceeding to step S4.

[0012] Step S4: perform leakage detection on all local bit lines in the global bit line with leakage in sequence, and if the local bit line under detection has leakage, proceed to step S5. Step S5: perform over-erasing repair operation on the local bit line with leakage.

[0013] Preferably, the non-volatile memory comprises: a plurality of first physical blocks, each of the first physical blocks comprises a plurality of second physical blocks, adjacent second physical blocks are connected by word lines, a plurality of the second physical blocks share input signals of a selection tube and a common source signal, and each of the second physical blocks is provided with a global bit line.

[0014] Preferably, each of the second physical blocks includes: a plurality of rows of memory cells, a plurality of columns of memory cells and a global bit line, each row word line is used to connect all gates of each row of memory cells, each column local bit line is used to connect all drains of each column of memory cells, the sources of all the memory cells are connected to each other and connected to the source terminal voltage; all the local bit lines are connected to the global bit line via selection tubes.

[0015] Preferably, the gate of each of the selection tubes corresponds to the input selection signal, the drain of each of the selection tubes is connected to the corresponding global bit line; and the source of each of the selection tubes is connected to the corresponding local bit line.

[0016] Preferably, before executing step S3, the method further includes: when performing leakage detection, enabling all word lines of the non-volatile memory to a first preset voltage value, opening the gates of all selection tubes of the non-volatile memory at the same time, and enabling all selection signals to a second preset voltage value or a power supply voltage.

[0017] Preferably, the step S4 and the step S5 include: enabling all word lines of the global bit line currently having leakage to a third preset voltage value or 0V; enabling the gates of any part of the selection tubes so that the gate voltages of the corresponding selection tubes are enabled to a fourth preset voltage value or the power supply voltage, selecting a group of local bit lines in the global bit line currently having leakage to perform leakage detection, and if all the local bit lines to be tested currently have no leakage, performing leakage detection on the next group of local bit lines;

[0018] If the local bit line to be tested currently has leakage, the erase repair operation will be performed on the local bit line currently having leakage. After the repair, the leakage detection will be performed again on the local bit line currently having been erased and repaired. If the local bit line currently having been erased and repaired still has leakage, the erase repair operation will be performed again on the local bit line that has been erased and repaired. This cycle will be repeated until the local bit line currently having been erased and repaired has no leakage.

[0019] Preferably, it also includes: returning to the global bit line that currently has leakage, and then determining whether the global bit line is the last global bit line, and if not, carrying to the next global bit line in the non-volatile memory, and repeating steps S2 to S5; until the detection of the last global bit line is completed, the non-volatile memory is restored to a non-detection state, and the power-on is terminated.

[0020] The present invention has at least one of the following advantages:

[0021] The present invention proposes a method for quickly detecting over-erasure (leakage) of a non-volatile memory. First, detect whether the first group or the first global bit line is leaking. If it is leaking, then detect the leakage of multiple local bit lines in the global bit line. If the current single local bit line is leaking, then use weak programming repair technology to repair the over-erased unit. If the current global bit line is not leaking, continue to detect the next group of global bit lines until the leakage of the last group of global bit lines is detected, and then complete the power-on process. In this way, the over-erasure phenomenon caused by erroneous power failure can be quickly detected and eliminated. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of a flow chart of a power-on process of a non-volatile memory provided in the prior art;

[0023] Figure 2 A schematic diagram of the structure of a second physical block of a non-volatile memory provided by an embodiment of the present invention;

[0024] Figure 3 A simplified structural diagram of a second physical block of a non-volatile memory provided by an embodiment of the present invention;

[0025] Figure 4 A simplified structural diagram of a first physical block of a non-volatile memory provided by an embodiment of the present invention;

[0026] Figure 5 A schematic flow chart of a method for detecting over-erasure of a non-volatile memory provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following is a further detailed description of a method for detecting over-erasure of a non-volatile memory proposed by the present invention in combination with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In order to make the purposes, features and advantages of the present invention more obvious and easy to understand, please refer to the accompanying drawings. It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no technical substantive significance. Any structural modification, change in proportional relationship or adjustment of size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope of the technical content disclosed by the present invention.

[0028] Combination Figure 2 to Figure 4 In a method for detecting over-erasure of a non-volatile memory provided in this embodiment, the non-volatile memory comprises: a plurality of first physical blocks Block, each of the first physical blocks Block comprises a plurality of second physical blocks Block, word lines between adjacent second physical blocks Block are connected, a plurality of second physical blocks Block share an input signal of a selection tube and a common source signal VS, and each of the second physical blocks Block is provided with a global bit line GBL.

[0029] In this embodiment, please refer to Figure 4The number of the second physical blocks block is k+1, and the corresponding number of the global bit lines GBL is k+1, which are named as the first global bit line GBL0 to the k+1th global bit line GBLk in sequence.

[0030] Please refer to Figure 2 and Figure 3 Each of the second physical blocks block includes: a plurality of row storage units and a plurality of column storage units. In this embodiment, each of the second physical blocks block includes n+1 row storage units and m+1 column storage units.

[0031] Each row word line is used to connect all gates of each row of storage cells, each column local bit line is used to connect all drains of each column of storage cells, the sources of all the storage cells are connected to each other and connected to the source terminal voltage; all the local bit lines are connected to the global bit line through the selection tube.

[0032] In this embodiment, there are n+1 word lines, which are named as the first word line WL0 to the n+1th word line WLn, and there are m+1 local bit lines, which are named as the first bit line LBL0 to the m+1th bit line LBLm.

[0033] The gate of each of the selection tubes corresponds to the input selection signal LBLS, the drain of each of the selection tubes is connected to the corresponding global bit line; and the source of each of the selection tubes inputs the source signal LBL.

[0034] In this embodiment, the number of the selection tubes is m+1. It can be understood that the gate of the first selection tube inputs the first selection signal LBLS0, and so on, the gate of the m+1th selection tube inputs the m+1th selection signal LBLSm.

[0035] The source of the first selection tube is connected to the first bit line LBL0, and so on, the source of the m+1th selection tube is connected to the m+1th bit line LBLm.

[0036] The drains of all the selection tubes are connected to corresponding global bit lines.

[0037] The word line input signal WL[0:n], the word lines of each row are connected together, the selection tube input signal LBLS[0:m], each GBL unit shares the selection tube input signal, and shares the source signal VS in the same BLOCK, multiple global bit line signals GBL[0:k].

[0038] Please refer to Figure 5 , this embodiment provides a method for detecting over-erasure of a non-volatile memory, comprising:

[0039] Step S1, power on the non-volatile memory to be tested, so that the non-volatile memory releases internal configuration information. The power-on circuit is initialized, and then waits for the power-on voltage to stabilize, the chip starts to read the internal configuration information, and after reading the information, the configuration is judged to be successful, and the chip is configured internally.

[0040] Step S2, initializing the leakage detection. Step S3, performing leakage detection on all global bit lines of the non-volatile memory, if leakage exists in the global bit line currently being detected, proceeding to step S4.

[0041] Step S4: perform leakage detection on all local bit lines in the global bit line with leakage in sequence, and if the local bit line under detection has leakage, proceed to step S5. Step S5: perform over-erasing repair operation on the local bit line with leakage.

[0042] Before executing the step S3, it also includes: when performing leakage detection, all word lines of the non-volatile memory are enabled to a first preset voltage value, the gates of all selection tubes of the non-volatile memory are opened at the same time, and all selection signals are enabled to a second preset voltage value or a power supply voltage.

[0043] The steps S4 and S5 include: enabling all word lines of the global bit line that currently has leakage to a third preset voltage value or 0V; enabling the gates of any part of the selection tubes so that the gate voltages of the corresponding selection tubes are enabled to a fourth preset voltage value or the power supply voltage, and selecting a group of local bit lines within the global bit line that currently has leakage for leakage detection; if all the local bit lines to be tested currently have no leakage, the next group of local bit lines is subjected to leakage detection.

[0044] If the local bit line to be tested currently has leakage, the erase repair operation is performed on the local bit line currently having leakage. After the repair is completed, the leakage detection is performed again on the local bit line currently having been erased and repaired. If the local bit line currently having been erased and repaired still has leakage, the erase repair operation is performed again on the local bit line that has been erased and repaired, and the cycle is repeated until the local bit line currently having been erased and repaired has no leakage.

[0045] The method further includes: returning to the global bit line with leakage, and then determining whether the global bit line is the last global bit line, and if not, carrying to the next global bit line in the non-volatile memory, and repeating steps S2 to S5; until the last global bit line is detected, the non-volatile memory is restored to a non-detection state, and the power-on is completed. After the power-on is completed, the user can perform read, write, and erase operations.

[0046] After releasing the internal configuration information, leakage detection initialization is performed, and then global bit line leakage detection is carried out. For the leakage detection of the global bit lines, all word lines WL0 to WLn of each second physical block block in the first physical block Block are enabled to a certain voltage or 0V; all the gates of the selection transistors of each second physical block block are simultaneously opened, and the selection signals LBLS0 to LBLSm of all the gates of the selection transistors of each second physical block block are enabled to a certain voltage or the power supply voltage, the source signal VS = 0V, and one or a group of global bit lines GBL are selected for leakage detection. If there is no leakage in the currently detected one or a group of global bit lines GBL, the address of the global bit line advances to the next one or a group of global bit lines GBL. If there is leakage in the currently (one, or all or part within a group) global bit lines GBL, it stops at the address of the current one or a group of global bit lines GBL, and then the leakage detection of the local word lines under the current one or a group of global bit lines GBL is carried out.

[0047] For the leakage detection of the local word lines, all word lines WL0 to WLn of the second physical block block corresponding to the current one or a group of global bit lines are enabled to a certain voltage or 0V; part of the gates of the selection transistors are enabled, that is, one or several of the selection signals LBLS0 to LBLSm are enabled to a certain voltage or the power supply voltage, the source signal VS = 0V, and one or a group of local bit lines LBL are selected for leakage detection. If there is no leakage, the address of the local bit line advances to the next local bit line LBL or the next group of local bit lines LBL. If there is leakage in the currently (one, or a group) local bit line LBL, it stops at the current local bit line LBL for erase repair. If there is no leakage in the currently (one, or a group) local bit line LBL, it stops at the current local bit line LBL for erase repair. After the repair, the leakage detection of the current local bit line LBL is performed again. If it is still leaking, the erase repair is performed again, and this cycle is repeated j (for example: 1 < j < 10) times; if there is no leakage, the local address advances to the next local bit line LBL for detection / repair until the last local bit line LBL within the current one or a group of global bit lines GBL is detected / repaired, and then it returns to the address of the global bit line of the current one or a group of global bit lines GBL, and then it is judged whether it is the last one or a group of global bit lines GBL. If not, it advances to the next one or a group of global bit lines GBL. As described above, the global detection of the current global bit line GBL is carried out. Until the last global bit line GBL is detected and all possible erase repairs that need to be repaired are completed, the chip returns to the non-detection state and the power-on ends.

[0048] Detect the leakage of all global bit lines in a first physical block Block in turn. If the global bit line has no leakage, if the current global bit line has leakage, then detect whether the local bit line of the current global bit line has leakage. If so, the corresponding storage power supply of the local bit line is repaired. The detection selection of the local bit line can select one local bit line at a time, or multiple local bit lines can be selected for simultaneous detection. If the local bit line has no leakage, there is no need to repair the local bit line. After all local bit lines in the current global bit line are detected, return to the address of the current global bit line and continue to perform leakage detection on the next global bit line until all global bit lines are fully detected.

[0049] The word line voltages of the same second physical block can be selected together or partially, and the word line voltage can be 0V or a certain preset voltage.

[0050] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0051] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A method for detecting over-erasure of a non-volatile memory, characterized in that: include: Step S1, powering on the non-volatile memory to be detected so that the non-volatile memory releases internal configuration information; Step S2, detecting leakage initialization; Step S3, performing leakage detection on all global bit lines of the non-volatile memory, if leakage exists in the global bit line currently being detected, proceeding to step S4; Step S4, performing leakage detection on all local bit lines in the global bit line currently having leakage in sequence, and if leakage exists in the local bit line currently being detected, proceeding to step S5; The step S4 specifically includes: enabling the gates of all word lines and any part of the selection tubes in the global bit lines that currently have leakage in the non-volatile memory; selecting a group of local bit lines in the global bit lines that currently have leakage to perform leakage detection, and if the group of local bit lines has leakage, executing step S5; if the group of local bit lines does not have leakage, returning to step S4 to perform leakage detection on the next group of local bit lines; Step S5: performing an over-erasing repair operation on the local bit line currently having leakage.

2. The method for detecting over-erasure of a non-volatile memory according to claim 1, wherein: The non-volatile memory includes: a plurality of first physical blocks, each of the first physical blocks includes a plurality of second physical blocks, word lines between adjacent second physical blocks are connected, a plurality of second physical blocks share input signals of a selection tube and a common source signal, and each of the second physical blocks is provided with a global bit line.

3. The method for detecting over-erasure of a non-volatile memory according to claim 2, wherein: Each of the second physical blocks includes: a plurality of rows of memory cells, a plurality of columns of memory cells and a global bit line, each row word line is used to connect all gates of each row of memory cells, each column local bit line is used to connect all drains of each column of memory cells, the sources of all the memory cells are connected to each other and connected to the source voltage; all the local bit lines are connected to the global bit line via a selection tube.

4. The method for detecting over-erasure of a non-volatile memory according to claim 3, wherein: The gate of each selection tube corresponds to the input selection signal, the drain of each selection tube is connected to the corresponding global bit line; and the source of each selection tube is connected to the local bit line.

5. The method for detecting over-erasure of a non-volatile memory according to claim 4, characterized in that: Before executing the step S3, it also includes: when performing leakage detection, all word lines of the non-volatile memory are enabled to a first preset voltage value, the gates of all selection tubes of the non-volatile memory are opened at the same time, and all selection signals are enabled to a second preset voltage value or a power supply voltage.

6. The method for detecting over-erasure of a non-volatile memory according to claim 5, characterized in that: The steps S4 and S5 include: enabling all word lines of the global bit lines that currently have leakage to a third preset voltage value or 0V; enabling the gate voltage of the gate of any part of the selection tubes to a fourth preset voltage value or a power supply voltage, selecting a group of local bit lines in the global bit lines that currently have leakage to perform leakage detection, and if all the local bit lines to be tested currently have no leakage, performing leakage detection on the next group of local bit lines; If the local bit line to be tested currently has leakage, the erase repair operation is performed on the local bit line currently having leakage. After the repair is completed, the leakage detection is performed again on the local bit line currently having been erased and repaired. If the local bit line currently having been erased and repaired still has leakage, the erase repair operation is performed again on the local bit line that has been erased and repaired, and the cycle is repeated until the local bit line currently having been erased and repaired has no leakage.

7. The method for detecting over-erasure of a non-volatile memory according to claim 6, wherein: Also includes: Return to the global bit line currently leaking electricity, and then determine whether the global bit line is the last global bit line. If not, carry to the next global bit line in the non-volatile memory, and repeat steps S2 to S5; Until the detection of the last global bit line is completed, the non-volatile memory is restored to the non-detection state and the power-on is completed.

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