Packaging structure and forming method thereof

Abstract

Some embodiments of the present disclosure provide a packaging structure and a method for forming the same. The packaging structure includes a packaging substrate, an intermediate substrate, a first semiconductor device, a second semiconductor device, and a protective layer. The intermediate substrate is disposed above the packaging substrate. The first semiconductor device and the second semiconductor device are disposed above the intermediate substrate, wherein the first semiconductor device and the second semiconductor device are different types of electronic devices. The protective layer is formed above the intermediate substrate to surround the first semiconductor device and the second semiconductor device. The second semiconductor device is exposed from the protective layer, while the first semiconductor device is not exposed from the protective layer.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to semiconductor packages. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Continuous advances in semiconductor manufacturing processes have resulted in semiconductor devices with finer features and / or higher levels of integration. Functional density (i.e., the number of interconnect structures per unit chip area) generally increases, while feature size (i.e., the smallest component that can be produced using a manufacturing process) decreases. Such scaling processes generally provide benefits by increasing manufacturing efficiency and reducing associated costs.

[0003] The chip package not only provides protection for the semiconductor device from environmental pollution, but also provides a connection interface for the semiconductor device packaged therein. Smaller package structures that utilize less area or lower height have been developed to package semiconductor devices.

[0004] Although existing packaging techniques have been generally adequate for their intended purposes, existing packaging techniques have not been entirely satisfactory in all respects. Summary of the invention

[0005] According to some embodiments of the present disclosure, a packaging structure is provided. The packaging structure includes a packaging substrate, an intermediate substrate, a first semiconductor device, a second semiconductor device, and a protective layer. The intermediate substrate is disposed above the packaging substrate. The first semiconductor device and the second semiconductor device are disposed above the intermediate substrate, wherein the first semiconductor device and the second semiconductor device are different types of electronic devices. The protective layer is formed above the intermediate substrate to surround the first semiconductor device and the second semiconductor device. The second semiconductor device is exposed from the protective layer, while the first semiconductor device is not exposed from the protective layer.

[0006] According to some embodiments of the present disclosure, a packaging structure is provided. The packaging structure includes a packaging substrate, an intermediate substrate, a first semiconductor device, a second semiconductor device, a covering film, and a protective layer. The intermediate substrate is disposed above the packaging substrate. The first semiconductor device and the second semiconductor device are disposed above the intermediate substrate. The covering film is formed on a top surface of the first semiconductor device. The protective layer is formed above the intermediate substrate to surround the first semiconductor device, the covering film, and the second semiconductor device. The second semiconductor device is exposed from the protective layer, while the first semiconductor device is not exposed from the protective layer.

[0007] According to some embodiments of the present disclosure, a method for forming a package structure is provided, the method comprising stacking an intermediate substrate disposed on a package substrate. The method also comprises disposing a first semiconductor device and a second semiconductor device on the intermediate substrate. The method further comprises forming a protective layer on the intermediate substrate to surround the first semiconductor device and the second semiconductor device. In addition, the method comprises removing a portion of the protective layer so that the second semiconductor device is exposed from the protective layer, while the first semiconductor device is not exposed from the protective layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When reading the accompanying drawings, the various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that the various features are not necessarily drawn to scale. In fact, the size of the various features may be arbitrarily enlarged or reduced to make a clear description.

[0009] Figures 1A to 1E are cross-sectional views of various stages of a process for forming a package structure according to some embodiments.

[0010] FIG. 2A to FIG. 2C are cross-sectional views of various stages of a process for forming a package structure according to some embodiments.

[0011] Figure 3 is a cross-sectional view of a package structure according to some embodiments.

[0012] Figure 4 is a cross-sectional view of a package structure according to some embodiments.

[0013] Figure 5 is a cross-sectional view of a package module according to some embodiments.

[0014] The reference numerals are described as follows:

[0015] 100: Carrier substrate

[0016] 102: Packaging substrate, redistribution substrate

[0017] 104: Insulation layer

[0018] 106, 114: Conductive characteristics

[0019] 108, 120, 122: Conductive elements

[0020] 110: Intermediate substrate

[0021] 110A: Top surface of interposer substrate

[0022] 112: Plate

[0023] 116, 126, 130: Conductive structure

[0024] 118, 132: Bottom filling components

[0025] 124, 128: Semiconductor devices

[0026] 124A, 128A: Top surface of semiconductor device

[0027] 134,506: Protective layer

[0028] 134A: Top surface of protective layer

[0029] 134B, 134D: Open

[0030] 134C: Covering

[0031] 136: Conductive bump

[0032] 200: Covering film

[0033] 200A: Top surface of the cover film

[0034] 500: Internal connection structure

[0035] 502, 504: Semiconductor grains

[0036] D1: Direction

[0037] G, G': distance

[0038] H1, H2, H3: Height DETAILED DESCRIPTION

[0039] The following disclosure provides many different embodiments or examples to implement the different features of the present disclosure. The following describes embodiments of specific components and their arrangements to illustrate the present disclosure. Of course, these embodiments are merely examples and should not be used to limit the scope of the present disclosure. For example, the specification describes a first feature formed on or above a second feature, which may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, repeated reference symbols and / or marks may be used in different examples of the present disclosure. This repetition is for the purpose of simplicity and clarity, and is not used to limit the specific relationship between the various embodiments and / or structures discussed.

[0040] In addition, spatial terms such as "below," "below," "lower," "above," "upper," and similar terms are used to facilitate description of the relationship between one element or feature and another element or feature in the figure. In addition to the orientation shown in the drawings, these spatial terms are intended to include different orientations of the device in use or operation. The device / apparatus may be turned to different orientations (rotated 90 degrees or other orientations), and the spatial terms used herein may be interpreted accordingly.

[0041] The term "substantially" in the specification, such as "substantially flat" or "substantially coplanar", etc., can be understood by those skilled in the art. In some embodiments, the adjective can be substantially removed. Where applicable, the term "substantially" may also include embodiments of "entirely", "completely", "all", etc. Where applicable, the term "substantially" may also relate to 90% or higher, such as 95% or higher, in particular 99% or higher, including 100%. In addition, terms such as "substantially parallel" or "substantially perpendicular" should be interpreted as not excluding minor deviations from a specific arrangement, and may, for example, include deviations of up to 10°. The term "substantially" does not exclude "completely", for example, a composition that is "substantially free" of Y may be completely free of Y.

[0042] Terms such as "about" used in conjunction with a specific distance or size should be interpreted as not excluding minor deviations from the specific distance or size and may include deviations of up to 10%, for example. The term "about" relative to a numerical value X may mean X ± 5 or 10%.

[0043] Some embodiments of the present disclosure are described below. Additional operations may be provided before, during and / or after the stages described in these embodiments. In different embodiments, some of the stages described may be replaced or eliminated. Additional features may be added to the conductor device structure. In different embodiments, some of the features described may be replaced or eliminated. Although some embodiments are discussed below with operations performed in a specific order, these operations may also be performed in other logical orders.

[0044] Some embodiments of the present disclosure may relate to 3D packages or 3D-IC devices. Other features and processes may also be included. For example, a test structure may be included to help perform verification testing on the 3D package or 3D-IC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of the 3D package or 3D-IC, using probes and / or probe cards, etc. Verification testing may be performed on intermediate structures and final structures. Additionally, the structures and methods disclosed herein may be used in conjunction with a test method for intermediate verification of known good die to increase yield and reduce costs.

[0045] Figures 1A to 1E is a cross-sectional view of various stages of a process for forming a package structure according to some embodiments. Figure 1A As shown, according to some embodiments, a packaging substrate 102 is formed on a carrier substrate 100. The carrier substrate 100 may be a glass substrate, a semiconductor substrate or other suitable substrate. Figure 1E After the carrier substrate 100 is removed (as shown), the package substrate 102 may be used to provide electrical connections between a semiconductor device (to be described below) in the package structure and an external electronic device.

[0046] The packaging substrate 102 may be used for routing. In some embodiments, the packaging substrate 102 is a redistribution substrate. In some alternative embodiments, the packaging substrate 102 is a build-up substrate including a core and a build-up layer on the opposite side of the core. In the subsequent discussion of the embodiments of the present disclosure, a redistribution substrate is shown as an example of the packaging substrate 102, however, the teachings disclosed in some exemplary embodiments may also be easily applied to a build-up substrate. Figure 1A As shown, the redistribution substrate 102 includes a plurality of laminated insulating layers 104 and a plurality of conductive features 106 surrounded by the insulating layers 104. The conductive features 106 may include conductive lines, conductive vias and / or conductive pads. In some embodiments, some conductive vias are stacked on top of each other. The upper conductive vias are substantially aligned with the lower conductive vias. In some embodiments, some vias are staggered vias. The upper conductive vias are not aligned with the lower conductive vias.

[0047] The insulating layer 104 may include or be made of one or more polymer materials. The polymer material may include polybenzoxazole (PBO), polyimide (PI), epoxy resin, or a combination of the foregoing materials. In some embodiments, the polymer material is photosensitive. Therefore, a photolithography process may be used to form an opening having a desired pattern in the insulating layer 104.

[0048] In some other embodiments, part or all of the insulating layer 104 includes or is made of a dielectric material other than a polymer material. The dielectric material may include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more other suitable materials, or a combination thereof.

[0049] Conductive features 106 may include conductive wires that provide electrical connections in the horizontal direction and conductive vias that provide electrical connections in the vertical direction. Conductive features 106 may include or be made of copper, aluminum, gold, cobalt, titanium, nickel, silver, graphene, one or more other suitable conductive materials, or a combination of the foregoing materials. In some embodiments, conductive features 106 include multiple sublayers. For example, each conductive feature 106 includes multiple sublayers, including titanium / copper, titanium / nickel / copper, titanium / copper / titanium, aluminum / titanium / nickel / silver, other suitable multiple sublayers, or a combination of the foregoing sublayers.

[0050] The formation of the redistribution substrate 102 may involve multiple deposition or coating processes, multiple patterning processes, and / or multiple planarization processes.

[0051] The deposition or coating process may be used to form the insulating layer and / or the conductive layer. The deposition or coating process may include a spin coating process, an electroplating process, an electroless process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, one or more other suitable processes, or a combination of the foregoing processes.

[0052] The patterning process may be used to pattern the formed insulating layer and / or the formed conductive layer. The patterning process may include a photolithography process, an energy beam drilling process (e.g., a laser beam drilling process, an ion beam drilling process, or an electron beam drilling process), an etching process, a mechanical drilling process, one or more other suitable processes, or a combination of the foregoing processes.

[0053] The planarization process may be used to provide a flat top surface for the formed insulating layer and / or the formed conductive layer to facilitate subsequent processes. The planarization process may include a mechanical grinding process, a chemical mechanical polishing (CMP) process, one or more other suitable processes, or a combination of the foregoing processes.

[0054] like Figure 1AAs shown, according to some embodiments, the redistribution substrate 102 also includes a plurality of conductive elements 108 formed thereon. Each conductive element 108 may be exposed or protruding from the topmost surface of the insulating layer 104 and may be electrically connected to one of the conductive features 106. The conductive elements 108 may be used to hold or receive conductive features such as conductive pillars and / or conductive balls.

[0055] The conductive element 108 may include or be made of copper, aluminum, gold, cobalt, titanium, tin, one or more other suitable materials, or a combination of the foregoing materials. The conductive element 108 may be formed using an electroplating process, an electroless plating process, a placement process, a printing process, a physical vapor deposition process, a chemical vapor deposition process, one or more other suitable processes, or a combination of the foregoing processes.

[0056] like Figure 1B As shown, according to some embodiments, an interposer substrate 110 is stacked above the redistribution substrate 102. In some embodiments, the interposer substrate 110 is bonded to the conductive element 108 via a conductive structure 116. The conductive structure 116 may include solder bumps, solder balls, conductive pillars, other suitable conductive elements, or a combination of the foregoing conductive elements.

[0057] In some embodiments, the interposer substrate 110 includes a plate 112 and a plurality of conductive features 114. The conductive features 114 may include or be made of copper, aluminum, cobalt, nickel, gold, silver, tungsten, one or more other suitable materials, or a combination of the foregoing materials. The plate 112 may include or be made of a polymer material, a ceramic material, a metal material, a semiconductor material, one or more other suitable materials, or a combination of the foregoing materials. For example, the plate 112 includes a resin, a prepreg, glass, and / or ceramic. In the case where the plate 112 is made of a metal material or a semiconductor material (e.g., silicon), a dielectric layer may be formed between the plate 112 and the conductive features 114 to prevent short circuits.

[0058] In the case where the plate 112 includes or is made of a polymer material, the plate 112 may further include a filler dispersed in the polymer material. The polymer material may include or be made of an epoxy-based resin, a polyimide-based resin, one or more other suitable polymer materials, or a combination of the foregoing materials. Examples of fillers may include fibers (e.g., silica fibers and / or carbon-containing fibers), particles (e.g., silica particles and / or carbon-containing particles), or a combination of fibers and particles.

[0059] In some embodiments, the interposer substrate 110 includes more filler than the redistribution substrate 102. In some embodiments, the interposer substrate 110 includes more filler than the redistribution substrate 102. In some embodiments, the interposer substrate 110 includes more filler than the insulating layer 104 of the redistribution substrate 102. In some embodiments, the insulating layer 104 of the redistribution substrate 102 includes or is made of a polymer material. In some embodiments, the insulating layer 104 of the redistribution substrate 102 does not include filler. In these cases, the redistribution substrate 102 does not include filler.

[0060] In some embodiments, the interposer substrate 110 and the carrier substrate 100 are pressed against each other at high temperature. As a result, the interposer substrate 110 is bonded to the redistribution substrate 102 via the conductive structure 116. In some embodiments, a thermal compression process is used to achieve the above bonding process.

[0061] Afterwards, if Figure 1B As shown, according to some embodiments, an underfill element 118 is formed to surround and protect the conductive structure 116. The underfill element 118 may include or be made of an insulating material such as an underfill material. The underfill material may include epoxy, resin, filler material, stress release agent (SRA), adhesion promoter, other suitable materials or a combination of the foregoing materials. In some embodiments, a liquid underfill material is dispersed in the gap between the interposer substrate 110 and the redistribution substrate 102 to strengthen the conductive structure 116 and the overall strength of the package structure. After the aforementioned dispersion operation, the underfill material is cured to form the underfill element 118. The underfill element 118 may also provide a heat conduction path for the package structure. In some other embodiments, the underfill element 118 is not formed.

[0062] like Figure 1B As shown, according to some embodiments, the interposer substrate 110 also includes a plurality of conductive elements 120 and a plurality of conductive elements 122 formed thereon. Each conductive element 120, 122 may be exposed or protruded from the top surface of the substrate 112 and may be electrically connected to one of the conductive features 114. The conductive elements 120 and 122 may be used to hold or receive conductive features such as conductive pillars and / or conductive balls. The materials and formation methods of the conductive elements 120 and 122 may be the same as or similar to those of Figure 1A The conductive element 108 is shown in FIG.

[0063] like Figure 1CAs shown, according to some embodiments, a plurality of semiconductor devices 124 and a plurality of semiconductor devices 128 are stacked on the interposer substrate 110. For simplicity, only one semiconductor device 124 and one semiconductor device 128 are shown. In some embodiments, the semiconductor device 124 and / or the semiconductor device 128 include one or more semiconductor dies or chips, which may be any type of integrated circuit, such as a processor, a logic circuit, a memory, an analog circuit, a digital circuit, a mixed signal, etc. In some embodiments, the semiconductor device 124 and / or the semiconductor device 128 include one or more active devices, such as a transistor, a diode, a photodiode, or other suitable active devices. Alternatively, in some embodiments, the semiconductor device 124 and / or the semiconductor device 128 include one or more passive devices, such as a resistor, a capacitor, an inductor, or other suitable passive devices.

[0064] In some embodiments, semiconductor device 124 and semiconductor device 128 are different types of semiconductor devices that provide different functions. For example, semiconductor device 124 is a memory device, and semiconductor device 128 is a processor device. However, other combinations of semiconductor devices 124 and semiconductor devices 128 may also be used.

[0065] In some embodiments, semiconductor device 124 and semiconductor device 128 have different sizes. Figure 1C As shown, a height H1 of the semiconductor device 124 in a direction D1 substantially perpendicular to a top surface 110A of the interposer substrate 110 is smaller than a height H2 of the semiconductor device 128 in the direction D1 .

[0066] In some embodiments, each semiconductor device 124 is bonded to the conductive element 120 via a plurality of conductive structures 126, and each semiconductor device 128 is bonded to the conductive element 122 via a plurality of conductive structures 130. In this way, the various semiconductor devices 124, 128 communicate with each other via the interposer substrate 110. Therefore, the signal transmission speed is improved. The conductive structures 126 and / or the conductive structures 130 may include conductive pillars, solder bumps, solder balls, one or more other suitable conductive elements, or a combination of the foregoing conductive elements. The materials and formation methods of the conductive structures 126 and 130 may be the same as or similar to those of Figure 1B In some embodiments, a bottom filling element 132 is formed to surround and protect the conductive structure 126 and the conductive structure 130. The material and the formation method of the bottom filling element 132 can be the same as or similar to Figure 1B The underfill element 118 is shown in FIG.

[0067] In some embodiments not shown, the conductive elements 120 and / or the conductive elements 122 are omitted, and the semiconductor device 124 and / or the semiconductor device 128 are bonded to the pad area (composed of some conductive features 114) of the interposer substrate 110 via solder bumps, solder balls, conductive pillars, one or more suitable conductive elements, or a combination of the foregoing conductive elements.

[0068] like Figure 1D As shown, according to some embodiments, a protection layer 134 is formed to surround and protect the semiconductor device 124 and the semiconductor device 128. In some embodiments, the protection layer 134 is separated from the conductive structure 126 under the semiconductor device 124 and the conductive structure 130 under the semiconductor device 128 by the bottom filling element 132. However, the embodiments of the present disclosure are not limited thereto. Many changes and / or modifications may be made to the embodiments of the present disclosure. In some other embodiments, the bottom filling element 132 is not formed. In these cases, the protection layer 134 may directly contact the conductive structure 126 under the semiconductor device 124 and the conductive structure 130 under the semiconductor device 128.

[0069] In some embodiments, the protective layer 134 includes or is made of an insulating material, such as a molding material. The molding material may include a polymer material, such as an epoxy resin in which a filler is dispersed. In some embodiments, the molding material (e.g., a liquid molding material) is dispensed onto the top surface 110A of the interposer substrate 110 and / or over the semiconductor devices 124 and the semiconductor devices 128. Thereafter, in some embodiments, a thermal process is used to cure the liquid molding material and convert it into the protective layer 134.

[0070] In some embodiments, a planarization process is performed on the protective layer 134 to partially remove the protective layer 134. Figure 1D As shown, the top surface 128A of each semiconductor device 128 is exposed, but the top surface 124A of each semiconductor device 124 is not exposed. In some embodiments, after the planarization process, the top surface 128A of each semiconductor device 128 is substantially flush with the top surface 134A of the protection layer 134, and the top surface 124A of each semiconductor device 124 is separated from the top surface 134A of the protection layer 134 by a distance G. The planarization process may include a grinding process, a chemical mechanical polishing process, an etching process, a dry grinding process, one or more other applicable processes, or a combination of the foregoing processes.

[0071] Afterwards, if Figure 1EAs shown, according to some embodiments, the carrier substrate 100 is removed to expose the surface of the package substrate 102. In some embodiments, before forming the package substrate 102, a release film (not shown) is first formed on the carrier substrate 100. The release film 101 is a temporary bonding material that facilitates the separation operation between the carrier substrate 100 and the package substrate 102.

[0072] like Figure 1E As shown, in some embodiments, a plurality of conductive bumps 136 are formed above the surface of the package substrate 102 that was originally covered by the carrier substrate 100. Each conductive bump 136 can be electrically connected to one of the conductive features 106 of the package substrate 102. The conductive bumps 136 enable the package structure to be electrically connected to an external device (not shown). The conductive bumps 136 include or are solder bumps, for example, tin-containing solder bumps. The tin-containing solder bumps may further include copper, silver, gold, aluminum, lead, one or more other suitable materials, or a combination of the foregoing materials. In some embodiments, the tin-containing solder bumps are lead-free.

[0073] In some embodiments, after removing the carrier substrate 100, a solder ball (or solder element) is disposed on the exposed conductive feature 106. Thereafter, a reflow process is performed to melt the solder ball into a conductive bump 136. In some other embodiments, before disposing the solder ball, an under bump metallization (UBM) element is formed over the exposed conductive feature 106. In some other embodiments, a solder element is electroplated onto the exposed conductive feature 106. Thereafter, a reflow process is used to melt the solder element to form the conductive bump 136.

[0074] Afterwards, in some embodiments, a singulation process is performed. Thus, a plurality of separated package structures are formed. Figure 1E , one of the package structures is shown. The protective layer 134 has an opening 134B that exposes the top surface 128A of each semiconductor device 128. In the case where the semiconductor device 128 (e.g., a processor device) in operation may generate a large amount of heat, the opening 134B in the protective layer 134 helps to quickly dissipate heat from the semiconductor device 128 and avoid overheating.

[0075] Additionally, if Figure 1EAs shown, the protective layer 134 further has a covering portion 134C covering the top surface 124A of each semiconductor device 124. In some embodiments, the covering portion 134C substantially covers the entire top surface 124A of the semiconductor device 124. In some embodiments, the covering portion 134C is directly disposed on the top surface 124A of the semiconductor device 124. Therefore, the covering portion 134C of the protective layer 134 can reduce warpage in the semiconductor device 124, which will be explained below. In some embodiments, because high temperatures are used in the reflow process or thermal process as described above, the semiconductor device 124 is prone to warpage or bending, and the warpage in the semiconductor device 124 may cause irregular joints or cracks in the underlying conductive structure 126. Because the covering portion 134C covers and compresses the semiconductor device 124, the warpage in the semiconductor device 124 can be reduced.

[0076] Therefore, the performance and reliability of the semiconductor device in the package structure are improved. Therefore, the overall performance (including electrical performance and mechanical performance) and reliability of the package structure are also improved.

[0077] Many variations and / or modifications may be made to the embodiments of the present disclosure. FIG. 2A to FIG. 2C are cross-sectional views of various stages of a process for forming a package structure according to some embodiments.

[0078] like Figure 2A As shown, providing or receiving similar Figure 1C . Then, according to some embodiments, a covering film 200 is formed above each semiconductor device 124. In some embodiments, the covering film 200 is directly disposed on (ie, directly contacts) the top surface 124A of the semiconductor device 124. In some embodiments, the covering film 200 substantially covers the entire top surface 124A of the semiconductor device 124. Figure 2A As shown, in some embodiments, a sum of a height H1 of the semiconductor device 124 in a direction D1 substantially perpendicular to the top surface 110A of the interposer substrate 110 and a height H3 of the cover film 200 in the direction D1 (i.e., H1+H3) is smaller than a height H2 of the semiconductor device 128 in the direction D1.

[0079] In some embodiments, the cover film 200 includes an organic polymer material (e.g., epoxy resin, resin, etc.), and the organic polymer material has or does not have hardeners, fillers (e.g., silica fillers, glass fillers, aluminum oxide, silicon oxide, etc.), adhesion promoters, combinations of the foregoing materials, etc. Alternatively, the cover film 200 includes copper, aluminum, gold, titanium, other suitable metal materials, alloys of the foregoing materials, or combinations of the foregoing materials. The cover film 200 can be formed using a placement process, a printing process, a physical vapor deposition process, a chemical vapor deposition process, one or more other suitable processes, or a combination of the foregoing processes.

[0080] like Figure 2B As shown, according to some embodiments, a protective layer 134 is formed to surround and protect the semiconductor device 124, the capping film 200, and the semiconductor device 128. The material and the formation method of the protective layer 134 may be the same as or similar to Figure 1D In some embodiments, the cover film 200 includes a material different from the protective layer 134. For example, the protective layer 134 includes a molding material as described above, while the cover film 200 includes an organic polymer material or a metal material as described above. In some embodiments, the hardness of the cover film 200 is higher than that of the protective layer 134.

[0081] In some embodiments, a planarization process is performed on the protective layer 134 to partially remove the protective layer 134. Figure 2B As shown, the top surface 128A of each semiconductor device 128 is exposed, but the top surface 200A of each capping film 200 above the corresponding semiconductor device 124 is not exposed. In some embodiments, after the planarization process, the top surface 128A of each semiconductor device 128 is substantially flush with the top surface 134A of the protection layer 134, and the top surface 200A of each capping film 200 is separated from the top surface 134A of the protection layer 134 by a distance G'. The planarization process may include a grinding process, a chemical mechanical polishing process, an etching process, a dry grinding process, one or more other applicable processes, or a combination of the foregoing processes.

[0082] Afterwards, if Figure 2C As shown, according to some embodiments, the carrier substrate 100 is removed to expose the surface of the packaging substrate 102. Figure 1E As shown, in some embodiments, a conductive bump 136 is formed on the surface of the package substrate 102 originally covered by the carrier substrate 100. The material and the formation method of the conductive bump 136 may be the same as or similar to Figure 1E The conductive bumps 136 are shown in FIG.

[0083] Afterwards, in some embodiments, a segmentation process is performed. Thus, a plurality of separated packaging structures are formed. Figure 2C In FIG. 1 , one of the packaging structures is shown. Figure 1E In the package structure shown in FIG. 1 , the protection layer 134 has an opening 134B that exposes the top surface 128A of each semiconductor device 128. The opening 134B helps to quickly dissipate heat from the semiconductor device 128 and prevent overheating.

[0084] Additionally, if Figure 2C As shown, the protective layer 134 further has a covering portion 134C covering the top surface 200A of each covering film 200, so that the covering film 200 is interposed between the covering portion 134C and the top surface 124A of the corresponding semiconductor device 124. Because the covering portion 134C and the covering film 200 cover and press the semiconductor device 124, the warpage in the semiconductor device 124 can be reduced. The rigidity of the covering film 200 also prevents the bending of the semiconductor device 124.

[0085] Therefore, the performance and reliability of the semiconductor device in the package structure are improved. Therefore, the overall performance (including electrical performance and mechanical performance) and reliability of the package structure are also improved.

[0086] Many variations and / or modifications may be made to the embodiments of the present disclosure. Figure 3 is a cross-sectional view of a packaging structure according to some embodiments. Figure 3 In the embodiment, the cover film 200 is formed to cover a portion of the top surface 124A of the semiconductor device 124, but not the entire top surface 124A, and the other parts of the package structure are equivalent to Figure 2C 124. In some embodiments, the cover film 200 may cover 90% to 95% of the top surface 124A of the semiconductor device 124. It has been observed that providing such a coverage ratio over the semiconductor device 124 can effectively reduce the warpage that occurs in the semiconductor device 124. However, the embodiments of the present disclosure are not limited thereto. As long as the warpage in the semiconductor device 124 can be reduced, other coverage ratios of the cover film 200 may also be used over the semiconductor device 124.

[0087] Many variations and / or modifications may be made to the embodiments of the present disclosure. Figure 4 is a cross-sectional view of a packaging structure according to some embodiments. Figure 4 In the embodiment, the protection layer 134 has not only an opening 134B exposing the top surface 128A of each semiconductor device 128, but also an opening 134D exposing the top surface 200A of each cover film 200 above the corresponding semiconductor device 124, and the other parts of the package structure are equivalent to Figure 2C Other parts of the package structure are shown in FIG.

[0088] like Figure 4 As shown, in some embodiments, the cover film 200 is selected so that the sum of the height H1 of the semiconductor device 124 in the direction D1 substantially perpendicular to the top surface 110A of the interposer substrate 110 and the height H3 of the cover film 200 in the direction D1 (i.e., H1+H3) is equal to the height H2 of the semiconductor device 128 in the direction D1. Therefore, after a planarization process is performed on the protection layer 134 to partially remove the protection layer 134, the top surface 134A of the protection layer 134 is substantially flush with the top surface 200A of the cover film 200 and the top surface 128A of the semiconductor device 128. This helps to quickly dissipate heat from the semiconductor device 128 and the semiconductor device 124 through the opening 134B and the opening 134D and avoid overheating. In some embodiments where the cover film 200 includes a metal material, this further helps to remove heat from the semiconductor device 124.

[0089] although Figure 4 The cover film 200 is shown to cover the entire top surface 124A of the semiconductor device 124. However, in other embodiments not shown, the cover film 200 may also cover a portion of the top surface 124A of the semiconductor device 124. Figure 2C as well as Figure 3 In the embodiment of the present invention, the rigidity of the cover film 200 also prevents the semiconductor device 124 from warping or bending.

[0090] Many variations and / or modifications may be made to the embodiments of the present disclosure. For example, Figures 1A to 4 The semiconductor device 124 and / or the semiconductor device 128 in the package structure shown in FIG. 1 may also include or be one or more package modules (eg, Figure 5 shown).

[0091] Figure 5 is a cross-sectional view of a packaging module according to some embodiments. Figure 5 As shown, according to some embodiments, the package module includes an interconnect structure 500 and one or more semiconductor dies 502, 504 formed on the interconnect structure 500. In various embodiments, the semiconductor dies 502, 504 may be any type of semiconductor dies as described above. The semiconductor dies 502, 504 may be bonded to the interconnect structure 500 by flip-chip bonding, wire bonding, and / or any other applicable bonding method. In some embodiments, the interconnect structure 500 is an intermediate substrate that carries the semiconductor dies 502, 504 and provides electrical connections between the semiconductor dies 502, 504 and the intermediate substrate 110 (see Figures 1A to 4 In these cases, the interconnect structure 500 has a structure similar to that of the interposer substrate 110. Figure 5 As shown, according to some embodiments, the package module further includes a protection layer 506 formed on the interposer substrate 110 to surround and protect the semiconductor dies 502 and 504. The material and the formation method of the protection layer 506 may be the same as or similar to Figure 1D The protective layer 134 is shown in FIG.

[0092] Although there are only two types of semiconductor devices in the package structure of the aforementioned embodiment, more types of semiconductor devices may be used in other embodiments.

[0093] Some embodiments of the present disclosure form a packaging structure, which includes a packaging substrate, an intermediate substrate above the packaging substrate, and a plurality of semiconductor devices above the intermediate substrate. A protective layer is formed to surround and protect the semiconductor devices. Some semiconductor devices are exposed through a plurality of openings in the protective layer so that the generated heat can be quickly dissipated. Some other semiconductor devices are buried in the protective layer or covered by an additional covering film, so that the warping in the semiconductor device can be reduced. The performance and reliability of the semiconductor device in the packaging structure are improved. Therefore, the overall performance (including electrical performance and mechanical performance) and reliability of the packaging structure are also improved.

[0094] According to some embodiments of the present disclosure, a packaging structure is provided. The packaging structure includes a packaging substrate, an intermediate substrate, a first semiconductor device, a second semiconductor device, and a protective layer. The intermediate substrate is disposed above the packaging substrate. The first semiconductor device and the second semiconductor device are disposed above the intermediate substrate, wherein the first semiconductor device and the second semiconductor device are different types of electronic devices. The protective layer is formed above the intermediate substrate to surround the first semiconductor device and the second semiconductor device. The second semiconductor device is exposed from the protective layer, while the first semiconductor device is not exposed from the protective layer.

[0095] In some embodiments, the protective layer includes a covering portion covering a top surface of the first semiconductor device and an opening exposing a top surface of the second semiconductor device. In some embodiments, the covering portion is directly disposed on the top surface of the first semiconductor device. In some embodiments, the package structure further includes a covering film formed between the covering portion and the top surface of the first semiconductor device, and the covering film includes a material different from the protective layer. In some embodiments, the covering film is directly disposed on the top surface of the first semiconductor device. In some embodiments, the covering film covers a portion of the top surface of the first semiconductor device. In some embodiments, the covering film has a higher hardness than the protective layer.

[0096] According to some embodiments of the present disclosure, a packaging structure is provided. The packaging structure includes a packaging substrate, an intermediate substrate, a first semiconductor device, a second semiconductor device, a covering film, and a protective layer. The intermediate substrate is disposed above the packaging substrate. The first semiconductor device and the second semiconductor device are disposed above the intermediate substrate. The covering film is formed on a top surface of the first semiconductor device. The protective layer is formed above the intermediate substrate to surround the first semiconductor device, the covering film, and the second semiconductor device. The second semiconductor device is exposed from the protective layer, while the first semiconductor device is not exposed from the protective layer.

[0097] In some embodiments, the protective layer includes a first opening exposing a top surface of the cover film and a second opening exposing a top surface of the second semiconductor device. In some embodiments, a top surface of the protective layer is flush with the top surface of the cover film and the top surface of the second semiconductor device. In some embodiments, the cover film is directly disposed on the top surface of the first semiconductor device. In some embodiments, the cover film covers a portion of the top surface of the first semiconductor device. In some embodiments, the cover film covers the entire top surface of the first semiconductor device. In some embodiments, the cover film includes a material different from the protective layer. In some embodiments, the cover film has a higher hardness than the protective layer.

[0098] According to some embodiments of the present disclosure, a method for forming a package structure is provided, the method comprising stacking an intermediate substrate disposed on a package substrate. The method also comprises disposing a first semiconductor device and a second semiconductor device on the intermediate substrate. The method further comprises forming a protective layer on the intermediate substrate to surround the first semiconductor device and the second semiconductor device. In addition, the method comprises removing a portion of the protective layer so that the second semiconductor device is exposed from the protective layer, while the first semiconductor device is not exposed from the protective layer.

[0099] In some embodiments, after removing the portion of the protective layer, the protective layer includes a covering portion remaining on a top surface of the first semiconductor device and an opening exposing a top surface of the second semiconductor device. In some embodiments, before forming the protective layer, the method of forming a package structure further includes forming a covering film over the first semiconductor device, wherein after removing the portion of the protective layer, the covering film is located between the covering portion and the top surface of the first semiconductor device. In some embodiments, the covering film directly contacts the top surface of the first semiconductor device. In some embodiments, the covering film is formed to cover a portion of the top surface of the first semiconductor device.

[0100] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. It should be understood by those skilled in the art that the present disclosure can be easily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments introduced herein. It should also be understood by those skilled in the art that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions and modifications may be made to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A packaging structure, comprising: a packaging substrate; an intermediate substrate, disposed above the packaging substrate; A first semiconductor device and a second semiconductor device are disposed above the interposer substrate, wherein the first semiconductor device and the second semiconductor device are different types of electronic devices; a covering film covering a top surface of the first semiconductor device; as well as a protective layer formed over the interposer substrate to surround the first semiconductor device and the second semiconductor device, wherein the second semiconductor device is exposed from the protective layer and the first semiconductor device is not exposed from the protective layer, wherein the protective layer includes a covering portion covering a top surface of the covering film; The covering film has a higher hardness than the covering portion. 2 . The package structure as claimed in claim 1 , wherein the protection layer further comprises an opening exposing a top surface of the second semiconductor device. 3 . The package structure as claimed in claim 2 , wherein the covering portion is directly disposed on the top surface of the first semiconductor device. The package structure as claimed in claim 2 , wherein the cover film comprises a material different from that of the protection layer. 5 . The package structure of claim 4 , wherein the cover film is directly disposed on the top surface of the first semiconductor device. The package structure as claimed in claim 4 , wherein the cover film covers a portion of the top surface of the first semiconductor device. 7 . The package structure as claimed in claim 4 , wherein the cover film has a higher hardness than the protection layer.

8. A packaging structure, comprising: a packaging substrate; an intermediate substrate, disposed above the packaging substrate; A first semiconductor device and a second semiconductor device are disposed above the interposer substrate; a capping film formed on a top surface of the first semiconductor device and directly contacting the top surface of the first semiconductor device; as well as a protection layer formed over the interposer substrate to surround the first semiconductor device, the cover film, and the second semiconductor device, wherein the second semiconductor device is exposed from the protection layer and the first semiconductor device is not exposed from the protection layer, wherein the protection layer includes a cover portion covering a top surface of the cover film; The covering film has a higher hardness than the covering portion. 9 . The package structure as claimed in claim 8 , wherein the protection layer comprises a first opening exposing the top surface of the cover film and a second opening exposing a top surface of the second semiconductor device. 10 . The package structure as claimed in claim 9 , wherein a top surface of the protection layer is flush with the top surface of the cover film and the top surface of the second semiconductor device. 11 . The package structure of claim 8 , wherein the cover film covers a portion of the top surface of the first semiconductor device. 12 . The package structure of claim 8 , wherein the cover film covers the entire top surface of the first semiconductor device. 13 . The package structure as claimed in claim 8 , wherein the cover film comprises a material different from that of the protection layer. The package structure as claimed in claim 8 , wherein the cover film has a higher hardness than the protection layer.

15. A method for forming a package structure, comprising: An intermediate substrate stacked on a packaging substrate; Disposing a first semiconductor device and a second semiconductor device above the interposer substrate; forming a capping film over the first semiconductor device; forming a protection layer above the interposer substrate to surround the first semiconductor device and the second semiconductor device; as well as removing a portion of the protective layer so that the second semiconductor device is exposed from the protective layer, while the first semiconductor device is not exposed from the protective layer, wherein after removing the portion of the protective layer, the protective layer includes a covering portion remaining on a top surface of the first semiconductor device and covering a top surface of the covering film; The covering film has a higher hardness than the covering portion. 16 . The method for forming a package structure as claimed in claim 15 , wherein after removing the portion of the protection layer, the protection layer further comprises an opening exposing a top surface of the second semiconductor device. 17 . The method for forming a package structure as claimed in claim 16 , wherein after removing the portion of the protection layer, the covering film is located between the covering portion and the top surface of the first semiconductor device. 18 . The method for forming a package structure as claimed in claim 17 , wherein the cover film directly contacts the top surface of the first semiconductor device. 19 . The method for forming a package structure according to claim 17 , wherein the cover film is formed to cover a portion of the top surface of the first semiconductor device.

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