Semiconductor device, nonvolatile memory device, and memory device

Abstract

The present application relates to a semiconductor device, a nonvolatile memory device, and a storage device. The semiconductor device includes a semiconductor die, a semiconductor integrated circuit, an external crack detection structure, a plurality of internal crack detection structures, and a plurality of path selection circuits. The semiconductor die includes a center region and an edge region surrounding the center region. The semiconductor integrated circuit is in a plurality of sub-regions of the center region. The external crack detection structure is in the edge region. The plurality of internal crack detection structures are respectively in the plurality of sub-regions. The path selection circuits are configured to control electrical connections between the external crack detection structure and the plurality of internal crack detection structures. Through the selective electrical connections of the external crack detection structure and the internal crack detection structures, cracks in the center region can be effectively detected in addition to cracks in the edge region.

Description

TECHNICAL FIELD

[0001] Example embodiments relate generally to semiconductor integrated circuits, and more particularly to semiconductor devices and non-volatile memory devices including crack detection structures. BACKGROUND

[0002] Generally, integrated circuits are manufactured by forming a repetitive pattern in a wafer of semiconductor material. The wafer can be diced or cut into a plurality of semiconductor dies, and each semiconductor die can be packaged into a semiconductor chip. During the dicing and packaging processes, cracks can occur in the semiconductor dies. To reduce the yield of defective products, the semiconductor dies are inspected to detect cracks. SUMMARY

[0003] Some example embodiments can provide semiconductor devices and non-volatile memory devices for enhancing detectability of penetration of various types of cracks.

[0004] According to an example embodiment, a semiconductor device includes a semiconductor die, a semiconductor integrated circuit, an external crack detection structure, a plurality of internal crack detection structures, and a plurality of path selection circuits. The semiconductor die includes a center region and an edge region surrounding the center region. The semiconductor integrated circuit is in a plurality of sub-regions of the center region. The external crack detection structure is in the edge region. The plurality of internal crack detection structures are respectively formed in the plurality of sub-regions. The plurality of path selection circuits control electrical connections between the external crack detection structure and the plurality of internal crack detection structures.

[0005] According to an example embodiment, a non-volatile memory device includes a first semiconductor die, a second semiconductor die, a memory cell structure, a peripheral circuit, an external crack detection structure, a plurality of internal crack detection structures, and a plurality of path selection circuits. The first semiconductor die is stacked on the second semiconductor die in a vertical direction, and each of the first semiconductor die and the second semiconductor die includes a center region and an edge region surrounding the center region. The memory cell structure is in a plurality of upper sub-regions of the center region of the first semiconductor die. The peripheral circuit is in a plurality of lower sub-regions of the center region of the second semiconductor die. The external crack detection structure is in the edge regions of the first semiconductor die and the second semiconductor die. The plurality of internal crack detection structures are respectively in the plurality of upper sub-regions and in the plurality of lower sub-regions. The plurality of path selection circuits control electrical connections between the external crack detection structure and the plurality of internal crack detection structures.

[0006] According to an example embodiment, a storage device includes one or more nonvolatile memory devices and a processing circuit configured to control access to the nonvolatile memory devices. As described above, each nonvolatile memory device includes a first semiconductor die, a second semiconductor die, a memory cell structure, a peripheral circuit, an external crack detection structure, the plurality of internal crack detection structures, and the plurality of path selection circuits.

[0007] Through the selective electrical connection of the external crack detection structure and the internal crack detection structure, the semiconductor device and the nonvolatile memory device according to the example embodiment can effectively detect cracks in a central region in addition to cracks in an edge region.

[0008] In addition, the semiconductor device and the nonvolatile memory device according to the example embodiment can use a three-dimensional crack detection structure extending in a vertical direction to thoroughly detect various types of crack penetration. The semiconductor device and the nonvolatile memory device according to the example embodiment can reduce or prevent the yield of inferior products while having enhanced detectability of cracks and crack locations. BRIEF DESCRIPTION OF DRAWINGS

[0009] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a top view illustrating a layout of a semiconductor device according to an example embodiment.

[0011] Figure 2 is a block diagram illustrating a test system according to an example embodiment. Figure 1 is a diagram illustrating an example embodiment of a path selection circuit included in the semiconductor device of

[0012] Figure 3A and Figure 3B is a diagram illustrating a switching operation of the path selection circuit of Figure 2

[0013] Figure 4 is a block diagram illustrating a test system according to an example embodiment.

[0014] Figure 5 and Figure 6 is a timing diagram illustrating an example of a signal for detecting a crack in a semiconductor device according to an example embodiment.

[0015] Figure 7 is a top view illustrating a layout of a semiconductor device according to an example embodiment.

[0016] Figure 8 is a perspective view of a three-dimensional crack detection structure according to an example embodiment.

[0017] ​Figure 9 、 Figure 10 、 Figure 11 and Figure 12 is a cross-sectional view showing a vertical structure of a three-dimensional crack detection structure according to an example embodiment.

[0018] Figure 13 is a perspective view of a three-dimensional crack detection structure according to an example embodiment.

[0019] Figure 14 and Figure 15 is a cross-sectional view showing a vertical structure of a three-dimensional crack detection structure according to an example embodiment.

[0020] Figure 16 is a diagram for describing a method of detecting a crack in a semiconductor device according to an example embodiment.

[0021] Figure 17 is a perspective view of a three-dimensional crack detection structure according to an example embodiment.

[0022] Figure 18 is a perspective view of a non-volatile memory device according to an example embodiment.

[0023] Figure 19 is a block diagram showing a non-volatile memory device according to an example embodiment.

[0024] Figure 20 is a top view of a non-volatile memory device according to an example embodiment.

[0025] Figure 21 is a cross-sectional view taken along line I-I' in Figure 20 .

[0026] Figure 22 is a cross-sectional view taken along line II-II' in Figure 20 .

[0027] Figure 23 is a circuit diagram showing an equivalent circuit of a memory block as described with reference to Figures 20-22 .

[0028] Figure 24 is a diagram for describing a manufacturing process of a stacked semiconductor device according to an example embodiment.

[0029] Figure 25 and Figure 26 is a cross-sectional view showing a vertical structure of a three-dimensional crack detection structure according to an example embodiment.

[0030] Figure 27A and Figure 27Bis a top view showing a layout of a first semiconductor die of a nonvolatile memory device according to an example embodiment.

[0031] Figure 28A 、 Figure 28B and Figure 28C is a top view showing a layout of a second semiconductor die of a nonvolatile memory device according to an example embodiment.

[0032] Figure 29 is a block diagram showing a memory device according to an example embodiment. DETAILED DESCRIPTION

[0033] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all example embodiments are shown. Like references may be made to like elements throughout the description. The description can omit repeated description of a full disclosure of the drawings.

[0034] Figure 1 is a top view showing a layout of a semiconductor device according to an example embodiment.

[0035] Referring to Figure 1 , the semiconductor device 1000 includes at least one semiconductor die. The semiconductor die includes a center region CREG and an edge region EREG surrounding the center region CREG. The center region CREG can be divided into a plurality of sub-regions SREG1, SREG2, SREG3, and SREG4, and various semiconductor integrated circuits depending on a kind or type of the semiconductor device 1000 can be formed in the plurality of sub-regions SREG1-SREG4. For example, the semiconductor device 1000 can be a nonvolatile memory device, and a memory integrated circuit as will be described hereinafter can be formed in the center region CREG of the semiconductor die.

[0036] An outer crack detection structure OCDS is formed in the edge region EREG, and a plurality of inner crack detection structures ICDS1-ICDS4 are formed in the plurality of sub-regions SREG1-SREG4, respectively. A plurality of path selection circuits PS1, PS2, PS3, and PS4 control electrical connections between the outer crack detection structure OCDS and the plurality of inner crack detection structures ICDS1-ICDS4. The plurality of path selection circuits PS1-PS4 can operate in response to a plurality of switch signals SS1, SS2, SS3, and SS4, respectively.

[0037] The external crack detection structure OCDS can be divided into a plurality of loop segments LPS1, LPS2, LPS3, LPS4, and LPS5, and the plurality of loop segments LPS1-LPS5 can be electrically connected via a plurality of path selection circuits PS1-PS4 to form a conductive loop having an input end node ENI and an output end node ENO. The input end node ENI can be connected to a test input pad PTI that receives a test input signal TSI, and the output end node ENO can be connected to a test output pad PTO that outputs a test output signal TSO.

[0038] Figure 2 is a diagram illustrating an example embodiment of a path selection circuit included in a semiconductor device. Figure 1 Figure 2 Only an example embodiment of a first path selection circuit PS1 corresponding to a first internal crack detection structure ICDS1 included in the semiconductor device 100 is illustrated, and the same description can be applied to other path selection circuits PS2-PS4. Figure 1

[0039] Referring to Figure 2 , a first end of a first internal crack detection structure ICDS1 of the plurality of internal crack detection structures ICDS1-ICDS4 can be connected to the path selection circuit PS1, and a second end of the first internal crack detection structure ICDS1 can be connected to a second loop segment LPS2 of the plurality of loop segments LPS1-LPS5.

[0040] The first path selection circuit PS1 can include an external switch SWO1 and an internal switch SWI1. The external switch SWO1 can be connected between the first loop segment LPS1 and the second loop segment LPS2. The internal switch SWI1 can be connected between the first internal crack detection structure ICDS1 and the first loop segment LPS1.

[0041] The first end of the first internal crack detection structure ICDS1 can be connected to the internal switch SWI1, and the second end of the first internal crack detection structure ICDS1 can be connected to the second loop segment LPS2.

[0042] The external switch SWO1 can receive an external connection signal SSO1 to turn on in response to activation of the external connection signal SSO1, and the internal switch SWI1 can receive an internal connection signal SSI1 to turn on in response to activation of the internal connection signal SSI1. As such, Figure 1 The switch signal SS1 in the semiconductor device 100 can include one external connection signal SSO1 and one internal connection signal SSI1.

[0043] Figure 3A and Figure 3B is a diagram illustrating an example embodiment of a path selection circuit included in a semiconductor device. Figure 2 ​​a diagram showing switching operation of the path selection circuit.

[0044] Referring to Figure 3A and Figure 3B One of the external connection signal SSO1 and the internal connection signal SSI1 can be selectively activated, and one of the external switch SWO1 and the internal switch SWI1 can be selectively turned on. As shown in FIG. 4A, when the external switch SWO1 is turned on, a crack in the edge region EREG can be detected. In contrast, as shown in FIG. 4B, when the internal switch SWI1 is turned on, a crack in the first sub region SREG1 of the plurality of sub regions SREG1-SREG4 can be detected. Figure 3A Figure 3B

[0045] Figure 4 is a block diagram illustrating a test system according to an example embodiment.

[0046] Referring to Figure 4 , the test system can include a tester 500 and a semiconductor device 1000.

[0047] The semiconductor device 1000 can include the crack detection structure as described above, i.e., the outer crack detection structure OCDS and the plurality of inner crack detection structures ICDS1-ICDS4. The outer crack detection structure OCDS can form a conductive loop through the plurality of path selection circuits PS1-PS4 to electrically connect the input node ENI and the output node ENO in a ring shape. The input node ENI and the output node ENO of the outer crack detection structure OCDS can be connected to a test input pad PTI and a test output pad PTO formed on a surface of a semiconductor die of the semiconductor device 1000, so that the conductive loop can be connected to the tester 500 through the test input pad PTI and the test output pad PTO.

[0048] The tester 500 can include a crack detector CDET 510. The crack detector 510 can apply a test input signal TSI to the test input pad PTI and then receive a test output signal TSO through the test output pad PTO, where the test output signal TSO corresponds to the test input signal TSI after passing through the crack detection structure in the semiconductor device 1000. The crack detector 510 can determine the occurrence of a crack by comparing the test input signal TSI and the test output signal TSO.

[0049] Figure 5 and Figure 6 is a timing diagram illustrating an example of signals for detecting a crack in a semiconductor device according to an example embodiment.

[0050] Referring to Figure 5 , Figure 4 ​​The crack detector 510 in the test signal generator 500 can compare the phases of the test input signal TSI and the test output signal TSO to measure a delay time or a phase difference between the test input signal TSI and the test output signal TSO. The crack detector 510 can determine the occurrence of a crack, i.e., whether a crack has occurred, based on the delay time.

[0051] The crack detector 510 can generate and apply the test input signal TSI including a pulse, and can receive the test output signal including a pulse. If the delay time of the test output signal TSO is shorter than a predetermined reference time tRT or an alternative desired reference time tRT, as a first case CS1, it can be determined that no crack has occurred. If the delay time of the test output signal TSO is longer than the reference time tRT, as a second case CS2, it can be determined that a crack has occurred. If the test output signal TSO does not include a pulse, as a third case CS3, it can be determined that the conductive path of the crack detection structure is completely cut off.

[0052] Referring to Figure 6 The occurrence of a crack can be detected for different conductive paths during a plurality of test time periods T1 to T5. In Figure 6 In the test signal generator 500, SWO1, SWO2, SWO3, and SWO4 denote external connection signals applied to external switches of the first to fourth path selection circuits PS1 to PS4, respectively, and SWI1, SWI2, SWI3, and SWI4 denote internal connection signals applied to internal switches of the first to fourth path selection circuits PS1 to PS4, respectively.

[0053] The first test time period T1 corresponds to crack detection with respect to a conductive loop including only the external crack detection structure OCDS. The second test time period T2 corresponds to crack detection with respect to a conductive loop via the first internal crack detection structure ICDS1. The third test time period T3 corresponds to crack detection with respect to a conductive loop via the second internal crack detection structure ICDS2. The fourth test time period T4 corresponds to crack detection with respect to a conductive loop via the third internal crack detection structure ICDS3. The fifth test time period T5 corresponds to crack detection with respect to a conductive loop via the fourth internal crack detection structure ICDS4.

[0054] In Figure 6 In the test signal generator 500, the first case CS1 denotes that no crack has occurred with respect to the external crack detection structure OCDS and the internal crack detection structures ICDS1 to ICDS4, the second case CS2 denotes that a crack has occurred with respect to the second internal crack detection structure ICDS2, and the third case CS3 denotes that a crack has occurred with respect to the external crack detection structure OCDS.

[0055] With this test method, in addition to the occurrence of a crack, the crack location can also be effectively detected. The detection of the crack location can allow a portion of the semiconductor device 1000 to be screened, rather than discarding the entire semiconductor device 1000.

[0056] Figure 7 is a top view showing a layout of a semiconductor device according to an example embodiment.

[0057] Figure 7 The semiconductor device 1001 of Figure 1 the semiconductor device 1000 is substantially the same as that of Figure 1 the semiconductor device 1000, and the repeated description is omitted. In Figure 7 the semiconductor device 1000, each internal crack detection structure has a ring shape around each sub-region, whereas in the semiconductor device 1001, each internal crack detection structure can pass only through the inside of each sub-region.

[0058] Hereinafter, a direction substantially perpendicular to a top surface of a substrate is referred to as a first direction or a vertical direction Z (or D1), and two directions substantially parallel to the top surface of the substrate and intersecting each other are referred to as a second direction X (or D2) and a third direction Y (or D3). For example, the second direction X and the third direction Y can be perpendicular to each other.

[0059] Figure 8 is a perspective view of a three-dimensional crack detection structure according to an example embodiment.

[0060] Figure 8 With reference to , the outer crack detection structure OCDSa can include a single conductive loop LOOPa. As described below, the semiconductor die can include a first conductive layer and a second conductive layer provided below the first conductive layer. The conductive layers can include a metal layer in which metal line segments are patterned and / or a polysilicon layer in which polysilicon line segments are patterned. The outer crack detection structure OCDSa can extend in the vertical direction Z through the first conductive layer and the second conductive layer.

[0061] The outer crack detection structure OCDSa can include a plurality of top horizontal line segments HLT formed in the first conductive layer, a plurality of bottom horizontal line segments HLB formed in the second conductive layer, and a plurality of vertical line segments VL connecting the top horizontal line segments HLT and the bottom horizontal line segments HLB, respectively, to form the outer crack detection structure OCDSa. The top horizontal line segments HLT, the vertical line segments VL, and the bottom horizontal line segments HLB can be alternately disposed along the outer crack detection structure OCDSa and can connect the input end node ENI and the output end node ENO in a ring shape, thereby surrounding a central region of the semiconductor die.

[0062] In some example embodiments, the input end node ENI and the output end node ENO can be connected to input-output pads formed on a surface of the semiconductor die, such that the external crack detection structure OCDSa can be connected to an external tester through the input-output pads. In some example embodiments, the input end node ENI and the output end node ENO can be connected to a crack test circuit formed in a portion of a central region of the semiconductor die.

[0063] Figure 9 、 Figure 10 、 Figure 11 and Figure 12 are cross-sectional views showing a vertical structure of a three-dimensional crack detection structure according to example embodiments.

[0064] Referring to Figure 9 , the semiconductor die can include a semiconductor substrate SUB and a dielectric layer in which an upper structure is formed. The dielectric layer can include a plurality of conductive layers ML1, ML2, ML3, PL1, and PL2 in which a conductive line pattern is formed. The conductive layers can include one or more metal layers ML1, ML2, and ML3 and one or more polysilicon layers PL1 and PL2. The polysilicon layers can include a gate polysilicon layer PL1 in which a gate of a transistor (not shown) in a semiconductor integrated circuit is formed. If the semiconductor integrated circuit is a semiconductor memory device, the polysilicon layers can further include a bit line polysilicon layer PL2 in which a bit line (not shown) in the semiconductor integrated circuit is formed.

[0065] The external crack detection structure OCDSa can include a plurality of top horizontal line segments HLT formed in the first conductive layer ML1, a plurality of bottom horizontal line segments HLB formed in the second conductive layer PL2, and a plurality of vertical line segments VL respectively connecting the top horizontal line segments HLT and the bottom horizontal line segments HLB to form the external crack detection structure OCDSa.

[0066] In Figure 9 example embodiments, the first conductive layer ML1 can correspond to an uppermost metal layer among metal layers ML1, ML2, and ML3 formed above the semiconductor substrate SUB, and the second conductive layer PL2 can correspond to a bit line polysilicon layer formed between the semiconductor substrate SUB and the metal layers ML1, ML2, and ML3. The top horizontal line segments HLT can include a metal line pattern MP1 formed in the uppermost metal layer ML1, and the bottom horizontal line segments HLB can include a polysilicon line pattern PP formed in the bit line polysilicon layer PL2.

[0067] The vertical line segments VL can include vertical contacts VC1, VC2, and VC3 to provide electrical connections between the metal line pattern MP1 in the uppermost metal layer ML1 and the polysilicon line pattern PP in the bit line polysilicon layer PL2. The vertical line segments VL can also include conductive line patterns MP2 and MP3 in the respective intermediate conductive layers ML2 and ML3. In some embodiments, the conductive line patterns in one or both of the intermediate conductive layers ML2 and ML3 can be omitted. For example, the metal line pattern MP2 in the intermediate conductive layer ML2 can be omitted, and Figure 9 The two vertical contacts VC1 and VC2 in

[0068] Hereafter, repeated descriptions of Figure 9 may be omitted.

[0069] Referring to Figure 10 , the outer crack detection structure OCDSa can include a plurality of top horizontal line segments HLT formed in the first conductive layer ML1, a plurality of bottom horizontal line segments HLB formed in the second conductive layer PL1, and a plurality of vertical line segments VL connecting the top horizontal line segments HLT and the bottom horizontal line segments HLB, respectively, to form the outer crack detection structure OCDSa.

[0070] In Figure 10 embodiments, the first conductive layer ML1 can correspond to an uppermost metal layer among metal layers ML1, ML2, and ML3 formed above a semiconductor substrate SUB, and the second conductive layer PL1 can correspond to a gate polysilicon layer formed between the semiconductor substrate SUB and the metal layers ML1, ML2, and ML3. The top horizontal line segments HLT can include metal line patterns MP1 formed in the uppermost metal layer ML1, and the bottom horizontal line segments HLB can include polysilicon line patterns PP1 formed in the gate polysilicon layer PL1. Further, the vertical line segments VL can include vertical contacts VC1, VC2, VC3, and VC4 to provide electrical connections between the metal line patterns MP1 in the uppermost metal layer ML1 and the polysilicon line patterns PP1 in the gate polysilicon layer PL1.

[0071] Referring to Figure 11 , the outer crack detection structure OCDSa can include a plurality of top horizontal line segments HLT formed in the first conductive layer ML1, a plurality of bottom horizontal line segments HLB formed in the second conductive layer MLB, and a plurality of vertical line segments VL connecting the top horizontal line segments HLT and the bottom horizontal line segments HLB, respectively, to form the outer crack detection structure OCDSa.

[0072] In Figure 11In an embodiment, the first conductive layer ML1 can correspond to an uppermost metal layer among metal layers ML1, ML2, and ML3 formed over the semiconductor substrate SUB, and the second conductive layer MLB can correspond to a metal layer formed on a bottom surface of the semiconductor substrate SUB. The top horizontal line segment HLT can include a metal line pattern MP1 formed in the uppermost metal layer ML1, and the bottom horizontal line segment HLB can include a metal line pattern MPB formed in the metal layer MLB on the bottom surface of the semiconductor substrate SUB. Further, the vertical line segment VL can also include a through substrate via TSV.

[0073] As described with reference to Figure 9 , Figure 10 and Figure 11 , the three-dimensional crack detection structure according to example embodiments can be extended to various depths in the vertical direction Z. Using the three-dimensional crack detection structure, various types of crack penetration can be more thoroughly detected.

[0074] As compared to the outer crack detection structure OCDSa of Figure 10 , a portion of the bottom horizontal line segment HLB in the gate polysilicon layer PL1 can be omitted, and a path selection circuit PS can be formed in the omitted area, as shown in Figure 12 . The path selection circuit PS, which receives a signal SI and outputs a signal SO, can include a transistor formed using the semiconductor substrate SUB, and the transistor can function as a switch as described above.

[0075] Figure 13 is a perspective view of a three-dimensional crack detection structure according to example embodiments.

[0076] Referring to Figure 13 , the outer crack detection structure OCDSb can include a first conductive loop LOOPc and a second conductive loop LOOPd. As described below, the semiconductor die can include a first conductive layer, a second conductive layer below the first conductive layer, and a third conductive layer below the second conductive layer. The conductive layers can include metal layers in which metal line segments are patterned and / or polysilicon layers in which polysilicon line segments are patterned. The first conductive loop LOOPc can be extended in a three-dimensional shape between the second conductive layer and the third conductive layer in the vertical direction Z. The second conductive loop LOOPd can be formed in a two-dimensional shape in the first conductive layer.

[0077] The first conductive loop LOOPc can include a plurality of first top horizontal line segments HLT formed in the second conductive layer, a plurality of bottom horizontal line segments HLB formed in the third conductive layer, and a plurality of vertical line segments VL respectively connecting the first top horizontal line segments HLT and the bottom horizontal line segments HLB to form the first conductive loop LOOPc. The second conductive loop LOOPd can include a plurality of second top horizontal line segments HL formed on the first conductive layer. The first top horizontal line segments HLT, the vertical line segments VL, and the bottom horizontal line segments HLB can be alternately disposed along the first conductive loop LOOPc and connect the first input end node ENI1 and the first output end node ENO1 in a ring shape so as to surround a central region of the semiconductor die. The second top horizontal line segments HL can connect the second input end node ENI2 and the second output end node ENO2 in a ring shape so as to surround the central region of the semiconductor die.

[0078] In some example embodiments, the input end nodes ENI1 and ENI2 and the output end nodes ENO1 and ENO2 can be connected to input-output pads formed on a surface of the semiconductor die, such that the conductive loops LOOPc and LOOPd can be connected to an external tester through the input-output pads. In some example embodiments, the input end nodes ENI1 and ENI2 and the output end nodes ENO1 and ENO2 can be connected to a crack test circuit, such as a crack detector formed in a portion of the central region of the semiconductor die.

[0079] Figure 14 and Figure 15 are cross-sectional views illustrating a vertical structure of a three-dimensional crack detection structure according to example embodiments. Hereinafter, a description repeated with Figures 8-13 may be omitted.

[0080] Referring to Figure 14 , the first conductive loop LOOPc can include a plurality of first top horizontal line segments HLT formed in the second conductive layer ML2, a plurality of bottom horizontal line segments HLB formed in the third conductive layer PL2, and a plurality of vertical line segments VL respectively connecting the first top horizontal line segments HLT and the bottom horizontal line segments HLB to form the first conductive loop LOOPc. The second conductive loop LOOPd can include a plurality of second top horizontal line segments HL formed in the first conductive layer ML1 above the second conductive layer ML2.

[0081] In Figure 14In an embodiment of the first conductive layer ML1 can correspond to an uppermost metal layer among metal layers ML1, ML2 and ML3 formed above the semiconductor substrate SUB, the second conductive layer ML2 can be a metal layer below the uppermost metal layer ML1, and the third conductive layer PL2 can correspond to a bit line polysilicon layer formed between the semiconductor substrate SUB and the metal layers ML1, ML2 and ML3. The first top horizontal line segment HLT can include a metal line pattern MP2 formed in the second metal layer ML2, and the bottom horizontal line segment HLB can include a polysilicon line pattern PP formed in the bit line polysilicon layer PL2. The second top horizontal line segment HL can include a metal line pattern MP1 formed in the first metal layer ML1.

[0082] Referring to Figure 15 , the first conductive loop LOOPc can include a plurality of first top horizontal line segments HLT formed in the second conductive layer ML2, a plurality of bottom horizontal line segments HLB formed in the third conductive layer PL1, and a plurality of vertical line segments VL respectively connecting the first top horizontal line segments HLT and the bottom horizontal line segments HLB to form the first conductive loop LOOPc. The second conductive loop LOOPd can include a plurality of second top horizontal line segments HL formed in the first conductive layer ML1 above the second conductive layer ML2.

[0083] In Figure 15 an embodiment, the first conductive layer ML1 can correspond to an uppermost metal layer among metal layers ML1, ML2 and ML3 formed above the semiconductor substrate SUB, the second conductive layer ML2 can be a metal layer below the uppermost metal layer ML1, and the third conductive layer PL1 can correspond to a gate polysilicon layer formed between the semiconductor substrate SUB and the metal layers ML1, ML2 and ML3. The first top horizontal line segment HLT can include a metal line pattern MP2 formed in the metal layer ML2, and the bottom horizontal line segment HLB can include a polysilicon line pattern PP1 formed in the gate polysilicon layer PL1. The second top horizontal line segment HL can include a metal line pattern MP1 formed in the first metal layer ML1.

[0084] As described with reference to Figure 14 and Figure 15 , the three-dimensional crack detection structure according to an example embodiment can be extended to various depths in the vertical direction Z. Using the three-dimensional crack detection structure, various types of cracks penetrating can be more thoroughly detected.

[0085] Figure 16 is a diagram for describing a method of detecting a crack in a semiconductor device according to an example embodiment.

[0086] The semiconductor device can include a three-dimensional crack detection structure, for example, the first conductive loop LOOPc and the second conductive loop LOOPd as described above.

[0087] As described above, the crack detector CDET 520 can be included in an external tester or an internal circuit of a semiconductor device. The crack detector 520 can apply the first test input signal TSI1 to the first input end node ENI1 and then receive the first test output signal TSO1 through the first output end node ENO1. Also, the crack detector 520 can apply the second test input signal TSI2 to the second input end node ENI2 and then receive the second test output signal TSO2 through the second output end node ENO2.

[0088] The first test output signal TSO1 corresponds to the first test input signal TSI1 after passing through the first conductive loop LOOPc, and the second test output signal TSO2 corresponds to the second test input signal TSI2 after passing through the second conductive loop LOOPd. The crack detector 520 can determine the occurrence of a crack by comparing the first test input signal TSI1 and the first test output signal TSO1 and by comparing the second test input signal TSI2 and the second test output signal TSO2.

[0089] Figure 17 is a perspective view of a three-dimensional crack detection structure according to an example embodiment.

[0090] Referring to Figure 17 , the external crack detection structure OCDSc can include a first conductive loop LOOPe and a second conductive loop LOOPf. As described above, the semiconductor die can include a first conductive layer, a second conductive layer below the first conductive layer, and a third conductive layer below the second conductive layer. The conductive layers can include a metal layer in which metal line segments are patterned and / or a polysilicon layer in which polysilicon line segments are patterned. The first conductive loop LOOPe can extend in a vertical direction Z between the second conductive layer and the third conductive layer in a three-dimensional shape. The second conductive loop LOOPf can be formed in the first conductive layer in a two-dimensional shape.

[0091] The first conductive loop LOOPe can include a plurality of first top horizontal line segments HLT formed in the second conductive layer, a plurality of bottom horizontal line segments HLB formed in the third conductive layer, and a plurality of vertical line segments VL respectively connecting the first top horizontal line segments HLT and the bottom horizontal line segments HLB to form the first conductive loop LOOPe. The second conductive loop LOOPf can include a plurality of second top horizontal line segments HL formed on the first conductive layer. The first top horizontal line segments HLT, the vertical line segments VL, and the bottom horizontal line segments HLB can be alternately disposed along the first conductive loop LOOPe and connect the first input end node ENI1 and the first output end node ENO1 in a ring shape so as to surround a central region of the semiconductor die. The second top horizontal line segments HL can connect the second input end node ENI2 and the second output end node ENO2 in a ring shape so as to surround the central region of the semiconductor die. As shown in FIG. 8, the end nodes ENI1 and ENO1 of the first conductive loop LOOPe can be connected to the intermediate nodes N1 and N2 of the second conductive loop LOOPf, such that the first conductive loop LOOPe and the second conductive loop LOOPf can form a combined conductive loop. Figure 17

[0092] In some example embodiments, the second input end node ENI2 and the second output end node ENO2 can be connected to input-output pads formed on a surface of the semiconductor die, such that the combined conductive loop can be connected to an external tester through the input-output pads. In some example embodiments, the second input end node ENI2 and the second output end node ENO2 can be connected to a crack test circuit, such as a crack detector formed in a portion of the central region of the semiconductor die.

[0093] Figure 18 is a perspective view of a non-volatile memory device according to an example embodiment.

[0094] Referring to Figure 18 , the non-volatile memory device can include a peripheral circuit region PCR in which a peripheral circuit is formed and a memory cell region MCR in which a memory cell array is formed.

[0095] The peripheral circuit region PCR can include a semiconductor substrate and a peripheral circuit formed on the semiconductor substrate, as will be described below. Figure 19 The elements shown in FIG. 1 (except for the memory cell array 100) can be formed in the peripheral circuit region PCR. The memory cell region MCR can include a memory cell array. As such, as will be described below, a size of the non-volatile memory device can be reduced by employing a circuit-on-periphery (COP) structure in which a peripheral circuit is formed on a semiconductor substrate and a memory cell array is stacked on the peripheral circuit. ​

[0096] Figure 19 is a block diagram illustrating a non-volatile memory device according to an example embodiment.

[0097] Referring to Figure 19 The non-volatile memory device 30 can include a memory cell array 100, a page buffer circuit 410, a data input / output (I / O) circuit 420, an address decoder 430, a control circuit 450, and / or a voltage generator 460.

[0098] The memory cell array 100 can be coupled to the address decoder 430 through a plurality of string select lines SSL, a plurality of word lines WL, and a plurality of ground select lines GSL. In addition, the memory cell array 100 can be coupled to the page buffer circuit 410 through a plurality of bit lines BL.

[0099] The memory cell array 100 can include a plurality of memory cells coupled to the plurality of word lines WL and the plurality of bit lines BL. In an example embodiment of the inventive concept, the memory cell array 100 can be a three-dimensional memory cell array formed in a three-dimensional structure (or a vertical structure) on a substrate. In this case, the memory cell array 100 can include a plurality of NAND strings oriented vertically such that at least one memory cell is located above another memory cell.

[0100] The control circuit 450 can receive a command (signal) CMD and an address (signal) ADDR from a memory controller (not shown) and control erase, program, and read operations of the non-volatile memory device 30 based on the command signal CMD and the address signal ADDR. The erase operation can include performing a series of erase cycles, and the program operation can include performing a series of program cycles. Each erase cycle can include an erase operation and an erase verify operation. Each program cycle can include a program operation and a program verify operation. The read operation can include a normal read operation and a data recovery read operation.

[0101] For example, the control circuit 450 can generate a control signal CTL for controlling the voltage generator 460 based on the command signal CMD and can generate a page buffer control signal PBC for controlling the page buffer circuit 410 and generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit 450 can provide the row address R_ADDR to the address decoder 430 and provide the column address C_ADDR to the data input / output circuit 420.

[0102] The address decoder 430 can be coupled to the memory cell array 100 by a plurality of string select lines SSL, a plurality of word lines WL, and a plurality of ground select lines GSL. During a program operation or a read operation, the address decoder 430 can determine one of the plurality of word lines WL as a selected word line and the remaining word lines of the plurality of word lines WL other than the selected word line as unselected word lines based on the row address R_ADDR.

[0103] Additionally, during a program operation or a read operation, the address decoder 430 can determine one of the plurality of string select lines SSL as a selected string select line and the remaining string select lines of the plurality of string select lines SSL other than the selected string select line as unselected string select lines based on the row address R_ADDR.

[0104] The voltage generator 460 can generate a word line voltage VWL for an operation of the memory cell array 100 of the non-volatile memory device 30 based on a control signal CTL. The voltage generator 460 can receive power PWR from a memory controller. The word line voltage VWL can be applied to the plurality of word lines WL through the address decoder 430.

[0105] For example, during a program operation, the voltage generator 460 can apply a program voltage to the selected word line and can apply a program pass voltage to the unselected word lines. Additionally, during a program verify operation, the voltage generator 460 can apply a program verify voltage to the selected word line and can apply a verify pass voltage to the unselected word lines.

[0106] Additionally, during a normal read operation, the voltage generator 460 can apply a read voltage to the selected word line and can apply a read pass voltage to the unselected word lines. During a data recovery read operation, the voltage generator 460 can apply a read voltage to a word line adjacent to the selected word line and can apply a recovery read voltage to the selected word line.

[0107] The page buffer circuit 410 can be coupled to the memory cell array 100 by a plurality of bit lines BL. The page buffer circuit 410 can include a plurality of buffers. In some example embodiments, each buffer can be connected to only one bit line. In other example embodiments, each buffer can be connected to two or more bit lines.

[0108] The page buffer circuit 410 can temporarily store data to be programmed in a selected page of the memory cell array 100 or data read out from the selected page of the memory cell array 100.

[0109] The data input / output circuit 420 can be coupled to the page buffer circuit 410 through data lines DL. During a program operation, the data input / output circuit 420 can receive program data DATA received from a memory controller and provide the program data DATA to the page buffer circuit 410 based on a column address C_ADDR received from the control circuit 450. During a read operation, the data input / output circuit 420 can provide read data DATA that has been read from the memory cell array 100 and stored in the page buffer circuit 410 to the memory controller based on a column address C_ADDR received from the control circuit 450.

[0110] In addition, the page buffer circuit 410 and the data input / output circuit 420 can read data from a first region of the memory cell array 100 and write this read data to a second region of the memory cell array 100 (e.g., without transferring the data to a source external to the non-volatile memory device 30, such as a memory controller). In other words, the page buffer circuit 410 and the data input / output circuit 420 can perform a copy-back operation.

[0111] Figure 19 One or more elements can be implemented by processing circuitry, such as hardware including a logic circuit, a hardware / software combination, such as a processor executing software, or a combination thereof. For example, the processing circuitry can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), or the like.

[0112] Figure 20 is a top view of a non-volatile memory device according to an example embodiment. Figure 21 is a cross-sectional view taken along line I-I’ in Figure 20 Figure 22 is a cross-sectional view taken along line II-II’ in Figure 20

[0113] In some example embodiments, the non-volatile memory device can have a cell-on-periphery (COP) structure in which memory cell structures are stacked on peripheral circuitry. The memory cell structures can have a vertical NAND flash device structure in which a plurality of NAND flash cells are formed vertically (e.g., in a first direction D1) with respect to a top surface of a substrate.

[0114] For clarity and brevity of description, some elements of the non-volatile memory device are not shown in Figure 20 Figure 20 ​​​The base layer patterns 201a, 201b, and 201c, the separation layer pattern 206, the second impurity region 266, the molding protective layer 212, the first connection contact 248a, and the second connection contact 248b are shown, and other elements described above are omitted.

[0115] Referring to Figures 20-22 The memory device can include a peripheral circuit structure formed in a peripheral circuit region PCR and a memory cell structure formed in a memory cell region MCR.

[0116] The peripheral circuit can include, for example, a transistor including a gate structure 130 and a source / drain region 103 formed on a substrate 101, a lower insulating layer 140 and 160, a lower contact 145, and / or a lower wiring 150 and 310.

[0117] The substrate 101 can include a semiconductor material, for example, single crystalline silicon or single crystalline germanium. The gate structure 130 can include a gate insulating layer pattern 110 and a gate electrode 120 stacked on the substrate 101. The transistor can be disposed on the substrate 101.

[0118] The gate insulating layer pattern 110 can include, for example, silicon oxide or metal oxide. The gate electrode 120 can include, for example, metal, metal nitride, or doped polysilicon. The source / drain region 103 can include n-type impurities or p-type impurities.

[0119] The first lower insulating layer 140 can be formed on the substrate 101 to cover structures such as the transistor, and the lower contact 145 can extend through the first lower insulating layer 140 to be electrically connected to the source / drain region 103.

[0120] The lower wiring 150 and 310 can be disposed on the first lower insulating layer 140 and can be electrically connected to the lower contact 145 and the through-substrate via 320, respectively. The second lower insulating layer 160 can be formed on the first lower insulating layer 140 to cover the lower wiring 150 and 310. Figure 21 A non-limiting example is shown in which the lower wiring 150 and 310 are formed in the same layer, but the lower wiring 150 and 310 can be distributed in different wiring layers.

[0121] The first lower insulating layer 140 and the second lower insulating layer 160 can include an insulating material, for example, silicon oxide. The lower contact 145 and the lower wiring 150 and 310 can include, for example, metal, metal nitride, or doped polysilicon.

[0122] The memory cell structure can include first to third base layer patterns 201a, 201b, and 201c, a channel 225, a gate line 260, a bit line 285, and a connection wiring 296, etc.

[0123] The separation layer pattern 206 can extend in the second direction D2, and a plurality of separation layer patterns 206 can be arranged along the third direction D3. Accordingly, the base layer can be physically divided into the first to third base layer patterns 201a, 201b, and 201c. Figures 20-22 Three base layer patterns 201a, 201b, and 201c are illustrated; however, the number of base layer patterns is not limited thereto.

[0124] The base layer patterns 201a, 201b, and 201c can include polysilicon or single-crystal silicon. In some embodiments, the base layer patterns 201a, 201b, and 201c can further include a p-type impurity such as boron (B). In this case, the base layer patterns 201a, 201b, and 201c can serve as a p-type well.

[0125] The separation layer pattern 206 can linearly extend in the second direction D2. The base layer patterns 201a, 201b, and 201c can be physically separated by the separation layer pattern 206. The separation layer pattern 206 can include an insulating layer pattern, for example, silicon oxide.

[0126] The channel 225 can be disposed on the base layer patterns 201a, 201b, and 201c, and can extend in the first direction D1 from a top surface of the base layer patterns 201a, 201b, and 201c. The channel 225 can have a hollow cylindrical or cup shape. The channel 225 can include polysilicon or single-crystal silicon, and can include an impurity region doped with, for example, a p-type impurity such as boron.

[0127] A plurality of channels 225 can be arranged in the second direction D2 to form a channel row, and a plurality of channel rows can be arranged in the third direction D3. In some example embodiments, the channels 225 included in adjacent channel rows can be arranged to face each other in a zigzag arrangement. Accordingly, the density of the channels 225 in a unit area of the base layer patterns 201a, 201b, and 201c can be increased.

[0128] A fill layer pattern 230 can be formed in the inner space of the channel 225. The fill layer pattern 230 can have a columnar or solid cylindrical shape. The fill layer pattern 230 can include an insulating layer pattern, for example, silicon oxide.

[0129] According to an embodiment, the channel 225 can have a columnar or solid cylindrical shape. In this case, the fill layer pattern 230 can be omitted.

[0130] A dielectric layer structure 220 can be formed on the outer sidewall of the channel 225. The dielectric layer structure 220 can have a cup shape with a center bottom open, or a straw shape.

[0131] The dielectric layer structure 220 can include a tunnel insulating layer, a charge storage layer, and a blocking layer that can be sequentially stacked from the outer sidewall of the channel 225. The blocking layer can include silicon oxide or metal oxide such as hafnium oxide or aluminum oxide. The charge storage layer can include nitride such as silicon nitride or metal oxide, and the tunnel insulating layer can include oxide such as silicon oxide. For example, the dielectric layer structure 220 can have an oxide-nitride-oxide (ONO) layer stack structure.

[0132] The pad 240 can be formed on the fill layer pattern 230, the channel 225, and the dielectric layer structure 220. For example, the fill layer pattern 230, the channel 225, and the dielectric layer structure 220 can be covered or enclosed by the pad 240. The pad 240 can include polysilicon or single-crystal silicon. The pad 240 can further include an n-type impurity, for example, phosphorus (P) or arsenic (As).

[0133] As shown in FIG. 2A, a plurality of pads 240 can be arranged in the second direction D2 to form pad rows substantially corresponding to the channel rows. The plurality of pad rows can be arranged in the third direction D3. Figure 21

[0134] The gate lines 260 (e.g., 260a to 260f) can be disposed on the outer sidewall of the dielectric layer structure 220 and can be spaced apart from each other in the first direction D1. In an example embodiment, each gate line 260 can surround the channels 225 of at least one channel row and can extend in the second direction D2.

[0135] For example, as shown in FIG. 2A, each gate line 260 can surround six channel rows, however, the number of channel rows surrounded by each gate line 260 is not limited thereto. Figures 20-22 For example, the lowermost gate line 260a can be used as a ground select line (GSL). The four gate lines 260b, 260c, 260d, and 260e on the GSL can be used as word lines. The uppermost gate line 260f on the word lines can be used as a string select line (SSL).

[0136] In this case, the GSL, the word lines, and the SSL can be formed at a single level, four levels, and a single level, respectively. However, each of the number of levels of the GSL, the word lines, and the SSL is not particularly limited. According to some embodiments, the GSL and the SSL can each be formed at two levels, and the word lines can be formed at 2^n levels, such as 4, 8, or 16 levels. The number of stacks of the gate lines 260 can be determined in consideration of circuit design and / or integration of a semiconductor device.

[0137]

[0138] ​​The insulating intermediate layers 202 (e.g., 202a, 202b, 202c, 202d, 202e, 202f, and 202g) can be disposed between the gate lines 260 along the first direction D1. The insulating intermediate layers 202 can include a silicon oxide-based material, for example, silicon dioxide (SiO2), silicon carbon oxide (SiOC), or silicon fluorine oxide (SiOF). The gate lines 260 can be insulated from each other by the insulating intermediate layers 202 along the first direction D1.

[0139] The gate line cut regions 256 can be formed through the gate lines 260 and the insulating intermediate layers 202 along the first direction D1. The gate line cut regions 256 can have a trench shape or a groove shape extending in the second direction D2.

[0140] The gate line cut patterns 270 extending in the second direction D2 can be disposed on the second impurity regions 266. The plurality of second impurity regions 266 and the gate line cut patterns 270 can be arranged along the third direction D3. In some embodiments, the second impurity regions 266 can include an n-type impurity, for example, phosphorus (P) or arsenic (As). The gate line cut patterns 270 can include an insulating layer pattern, for example, silicon oxide. A metal silicide pattern, such as a cobalt silicide pattern and / or a nickel silicide pattern, can be further formed on the second impurity regions 266.

[0141] In some example embodiments, the cell blocks sharing the gate lines 260 can be defined by the gate line cut patterns 270. The cell blocks can be divided into sub-cell blocks by the separation layer patterns 206. Accordingly, the size or the dimension of the individual blocks can be reduced, and thus, segmented operation control can be implemented.

[0142] In some embodiments, one of the second impurity regions 266 and one of the gate line cut patterns 270 can be provided for each base layer pattern 201a, 201b, and 201c. As Figure 22 shown, for example, the second impurity region 266 can be formed at a center region of the second base layer pattern 201b, and the gate line cut pattern 270 can be disposed on the second impurity region 266.

[0143] A connection contact and a connection wiring can be provided for each base layer pattern 201a, 201b, and 201c to transmit an electrical signal and / or a voltage from a peripheral circuit.

[0144] In an example embodiment, a molding protective layer 212 can be formed on edge portions of the base layer patterns 201a, 201b, and 201c and the separation layer pattern 206. The first connection contact 248a can extend through the molding protective layer 212 to contact the first impurity region 248 formed at the edge portion of the base layer pattern 201a, 201b, and 201c. The second connection contact 248b can extend through the molding protective layer 212, the base layer patterns 201a, 201b, and 201c, and the second lower insulating layer 160 to contact the lower wiring 150. The first insulating layer pattern 241a and the second insulating layer pattern 241b can be formed on sidewalls of the first connection contact 248a and the second connection contact 248b, respectively.

[0145] The first plug 291 and the second plug 293 can extend through the upper insulating layer 275 to contact the first connection contact 248a and the second connection contact 248b, respectively. A connection wiring 296 can be disposed on the upper insulating layer 275 to electrically connect the first plug 291 and the second plug 293.

[0146] The upper gate line cut pattern 252 can be formed in the upper gate line cut region 250. The upper gate line cut pattern 252 can include an insulating material, such as silicon oxide.

[0147] In an example embodiment, the upper gate line cut region 250 or the upper gate line cut pattern 252 can be provided for separating the SSLs in each cell block. In this case, the upper gate line cut region 250 or the upper gate line cut pattern 252 can extend through the uppermost insulating intermediate layer 202g and the SSL 260f, and can partially extend through the insulating intermediate layer 202f directly under the SSL 260f.

[0148] The upper insulating layer 275 can be formed on the uppermost insulating intermediate layer 202g, the pad 240, the upper gate line cut pattern 252, the gate line cut pattern 270, the first connection contact 248a, and the second connection contact 248b.

[0149] The bit line contact 280 can be formed through the upper insulating layer 275 to contact the pad 240. A plurality of bit line contacts 280 can be formed to define an array comparable to the arrangement of the channels 225 or the pads 240.

[0150] The bit line 285 can be disposed on the upper insulating layer 275 to be electrically connected to the bit line contact 280. For example, the bit line 285 can extend in the third direction D3 to be electrically connected to the plurality of bit line contacts 280. The bit line 285 and the separation layer pattern 206 can extend in directions substantially perpendicular to each other.

[0151] According to the above-described example embodiment, the base layer patterns 201a, 201b, and 201c can be physically separated by the separation layer pattern 206. Accordingly, the first to third base layer patterns 201a, 201b, and 201c can be independently or separately operated.

[0152] The cell block can be further divided or partitioned by the separation layer pattern 206, and thus signal interference or disturbance due to a large size of the cell block can be reduced. Accordingly, reliability of the semiconductor device can be improved.

[0153] Figure 23 is a circuit diagram illustrating an equivalent circuit of a memory block as described with reference to Figures 20-22 FIG. 1.

[0154] The memory cell array can include a plurality of memory blocks. Figure 23 The memory block BLKi can be formed in a three-dimensional structure (or a vertical structure) on a substrate. For example, a plurality of NAND strings or cell strings included in the memory block BLKi can be formed in a first direction D1 perpendicular to an upper surface of the substrate.

[0155] Referring to Figure 23 , the memory block BLKi can include the NAND strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33 coupled between the bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the NAND strings NS11 to NS33 can include a string selection transistor SST, a plurality of memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8, and a ground selection transistor GST. In Figure 23 , each of the NAND strings NS11 to NS33 is illustrated as including eight memory cells MC1 to MC8. However, the example embodiments are not limited thereto. In some example embodiments, each of the NAND strings NS11 to NS33 can include any number of memory cells.

[0156] Each string selection transistor SST can be connected to a corresponding string selection line (one of SSL1 to SSL3). The plurality of memory cells MC1 to MC8 can be connected to corresponding gate lines GTL1, GTL2, GTL3, GTL4, GTL5, GTL6, GTL7, and GTL8, respectively. The gate lines GTL1 to GTL8 can be word lines, some of which can be dummy word lines. In addition, some of the gate lines GTL1 to GTL8 can be middle switching lines, and memory cells connected to the middle switching lines can be referred to as middle switching transistors. Each ground selection transistor GST can be connected to a corresponding ground selection line (one of GSL1 to GSL3). Each string selection transistor SST can be connected to a corresponding bit line (e.g., one of BL1, BL2, and BL3), and each ground selection transistor GST can be connected to a common source line CSL.

[0157] Word lines having substantially the same height (e.g., WL1) can be commonly connected, and the ground selection lines GSL1 to GSL3 and the string selection lines SSL1 to SSL3 can be separated. In addition, gate lines corresponding to the middle switching lines can be separated, as will be described below. In Figure 23 In this case, the memory block BLKi is shown as being coupled to eight gate lines GTL1 to GTL8 and three bit lines BL1 to BL3. However, example embodiments are not limited thereto. Each memory block in the memory cell array 100 can be coupled to any number of word lines and any number of bit lines.

[0158] Figure 24 is a diagram for describing a manufacturing process of a stacked semiconductor device according to an example embodiment.

[0159] Referring to Figure 24 , various integrated circuits can be formed in the first wafer WF1 and the second wafer WF2. The same circuit can be integrated in the first wafer WF1 and the second wafer WF2, or different circuits can be integrated in the first wafer WF1 and the second wafer WF2. For example, a pixel array can be formed in the first wafer WF1, and other circuits can be formed in the second wafer WF2. Even Figure 24 The vertical stacking of two wafers WF1 and WF2 (e.g., the first wafer WF1 stacked on the second wafer WF2) is shown, but three or more wafers can be vertically stacked.

[0160] After the integrated circuits are formed in the first wafer WF1 and the second wafer WF2, the first wafer WF1 and the second wafer WF2 are bonded. The bonded wafers WF1 and WF2 are diced and separated into a plurality of chips, each of which corresponds to a semiconductor device 1003 including a vertically stacked first semiconductor die SD1 and a second semiconductor die SD2 (e.g., the first semiconductor die SD1 is stacked on the second semiconductor die SD2, etc.). Each diced portion of the first wafer WF1 corresponds to the first semiconductor die SD1, and each diced portion of the second wafer WF2 corresponds to the second semiconductor die SD2.

[0161] According to example embodiments, each semiconductor device 1003 can include a first semiconductor die SD1 and a second semiconductor die SD2 stacked in a vertical direction. Each of the semiconductor dies SD1 and SD2 includes a central region and an edge region surrounding the central region. Memory cell structures are formed in a plurality of upper sub-regions of the central region of the first semiconductor die SD1. Peripheral circuits are formed in a plurality of lower sub-regions of the central region of the second semiconductor die SD2. An external crack detection structure is formed in the edge region of the first semiconductor die SD1 and the second semiconductor die SD2. A plurality of internal crack detection structures are formed in the plurality of upper sub-regions and the plurality of lower sub-regions, respectively. A plurality of path selection circuits are provided to control electrical connections between the external crack detection structure and the plurality of internal crack detection structures.

[0162] In some example embodiments, the external crack detection structure can include a single conductive loop, such as described with reference to the examples of Figure 8 In other example embodiments, the three-dimensional crack detection structure can include two conductive loops, such as described with reference to the examples of Figure 13 Even though the example embodiments are described with reference to a single conductive loop covering the plurality of semiconductor dies SD1 and SD2, it should be understood that two conductive loops can be formed to cover the plurality of semiconductor dies SD1 and SD2. Figure 25 Figure 26 It should be understood that the two conductive loops can be formed to cover the plurality of semiconductor dies SD1 and SD2.

[0163] Figure 25 Figure 26 are cross-sectional views showing vertical structures of the three-dimensional crack detection structure according to example embodiments.

[0164] Reference is made to Figure 25 ​​, an outer crack detection structure OCDSd can be formed in the first semiconductor die SD1 and the second semiconductor die SD2. A memory cell structure can be formed in the first semiconductor die SD1, and a peripheral circuit can be formed in the second semiconductor die SD2. The second semiconductor die SD2 can include a semiconductor substrate SUB2 and a dielectric layer DLY2 in which an upper structure of the second semiconductor substrate SUB2 is formed. The first semiconductor die SD1 and the second semiconductor die SD2 can include a plurality of conductive layers. For example, the first semiconductor die SD1 can include a first metal layer ML1, and the dielectric layer DLY2 can include a second metal layer ML2 and a second polysilicon layer PL2. The metal layers ML1 and ML2 can be the uppermost metal layers in the respective semiconductor dies SD1 and SD2. The second polysilicon layer PL2 can include a bit line polysilicon layer in which a bit line in a semiconductor integrated circuit is formed.

[0165] The outer crack detection structure OCDSd can include a plurality of top horizontal line segments HLT formed in a first conductive layer ML1 of the first semiconductor die SD1 (i.e., the uppermost semiconductor die in the stack structure), a plurality of bottom horizontal line segments HLB formed in a second conductive layer PL2 of the second semiconductor die SD2 (i.e., the lowermost semiconductor die in the stack structure), and a plurality of vertical line segments VL connecting the top horizontal line segments HLT and the bottom horizontal line segments HLB, respectively, to form the outer crack detection structure OCDSd.

[0166] In Figure 25 embodiments, the first conductive layer ML1 can correspond to the uppermost metal layer among the metal layers of the first semiconductor die SD1, and the second conductive layer PL2 can correspond to a polysilicon layer of the second semiconductor die SD2. The top horizontal line segments HLT can include metal line patterns MP1 formed in the metal layer ML1 of the first semiconductor die SD1, and the bottom horizontal line segments HLB can include polysilicon line patterns PP2 formed in the polysilicon layer PL2 of the second semiconductor die SD2.

[0167] The vertical line segments VL can include vertical through-silicon vias TSV and VC2 to connect the metal line patterns MP1 in the metal layer ML1 and the polysilicon line patterns PP2 in the polysilicon layer PL2. As Figure 25 indicated. The vertical through-silicon vias can include through-substrate vias TSV that penetrate the first semiconductor die SD1. The vertical line segments VL can further include conductive line patterns MP2 formed in an intermediate conductive layer ML2.

[0168] Referring to Figure 26The outer crack detection structure OCDSd can include a plurality of top horizontal line segments HLT formed in the first conductive layer ML1 of the first semiconductor die SD1 (i.e., the uppermost semiconductor die in the stacked structure), a plurality of bottom horizontal line segments HLB formed in the second conductive layer MLB of the second semiconductor die SD2 (i.e., the lowermost semiconductor die in the stacked structure), and a plurality of vertical line segments VL connecting the top horizontal line segments HLT and the bottom horizontal line segments HLB, respectively, to form the outer crack detection structure OCDSd.

[0169] In Figure 26 an embodiment, the first conductive layer ML1 can correspond to an uppermost metal layer among metal layers of the first semiconductor die SD1, and the second conductive layer MLB can correspond to a metal layer on a bottom surface of the second semiconductor die SD2. The top horizontal line segments HLT can include metal line patterns MP1 formed in the metal layer ML1 of the first semiconductor die SD1, and the bottom horizontal line segments HLB can include metal line patterns MPB formed in the metal layer MLB on the bottom surface of the second semiconductor die SD2.

[0170] The vertical line segments VL can include vertical vias TSV1, VC2, and TSV2 to connect the metal line patterns MP1 in the metal layer ML1 and the metal line patterns MPB in the metal layer MLB. As shown in Figure 26 , the vertical vias can include through-substrate vias TSV1 and TSV2 penetrating the first semiconductor die SD1 and the second semiconductor die SD2, respectively. The vertical line segments VL can further include conductive line patterns MP2 and PP2 formed in the intermediate conductive layers ML2 and PL2, respectively.

[0171] As described with reference to Figure 25 and Figure 26 , the outer crack detection structure OCDSd according to an example embodiment can extend to various depths in the vertical direction Z. Using a three-dimensional crack detection structure, various types of cracks can be thoroughly detected for penetration.

[0172] Figure 27A and Figure 27B are top views showing a layout of a first semiconductor die of a non-volatile memory device according to an example embodiment, Figure 28A , Figure 28B and Figure 28C are top views showing a layout of a second semiconductor die of a non-volatile memory device according to an example embodiment.

[0173] Referring to Figures 27A-28CThe plurality of sub-areas of the central area as described above can correspond to a plurality of memory planes PLN. In the first semiconductor die SD1, each memory plane PLN can include a plurality of memory cell array regions, e.g., two memory cell array regions MCA. In the second semiconductor die SD2, each memory plane PLN can include a plurality of peripheral circuit regions, e.g., four peripheral circuit regions PR. Further, the first semiconductor die SD1 can also include an external crack detection structure OCDSu, an internal crack detection structure ICDS, a path selection circuit PS, and a test input pad PTIu and a test output pad PTOu; the second semiconductor die SD2 can also include an external crack detection structure OCDSd’, an internal crack detection structure ICDS, a path selection circuit PS, and a test input pad PTId and a test output pad PTOd.

[0174] Figure 27A An example embodiment is shown in which each memory plane PLN corresponds to one upper sub-area, Figure 27B An example embodiment is shown in which each memory plane PLN corresponds to two upper sub-areas. Figure 28A An example embodiment is shown in which each memory plane PLN corresponds to one lower sub-area, Figure 28B An example embodiment is shown in which each memory plane PLN corresponds to two lower sub-areas, Figure 28C An example embodiment is shown in which each memory plane PLN corresponds to four lower sub-areas. The non-volatile memory device according to the example embodiment can be implemented as a combination of a layout of Figure 27A and 27B and a layout of Figure 28A , Figure 28B and Figure 28C Thus, according to the example embodiment, in the non-volatile memory device, the number of the plurality of upper sub-areas can be equal to or different from the number of the plurality of lower sub-areas.

[0175] Figure 29 is a block diagram showing a storage device according to an example embodiment.

[0176] Referring to Figure 29 , the storage device 2000 includes a plurality of non-volatile memory devices (NVMs) 1100 and a storage controller 1200. The storage device 2000 can be a solid state drive (SSD).

[0177] The nonvolatile memory device 1100 may optionally be configured to receive a high voltage VPP. The nonvolatile memory device 1100 may correspond to the above-described nonvolatile memory device according to example embodiments. Therefore, the nonvolatile memory device 1100 may include a crack detection structure according to example embodiments.

[0178] The memory controller 1200 is connected to the nonvolatile memory device 1100 via a plurality of channels CH1 to CHi. The memory controller 1200 includes one or more processors 1210, a buffer memory 1220, an error correction code (ECC) circuit 1230, a host interface 1250, and a nonvolatile memory interface 1260. The buffer memory 1220 stores data for driving the memory controller 1200. The buffer memory 1220 includes a plurality of memory lines, each of which stores data or commands. The ECC circuit 1230 calculates an error correction code value for the data to be programmed during a write operation and uses the error correction code value to correct errors in the read data during a read operation. During a data recovery operation, the ECC circuit 1230 corrects errors in the data recovered from the nonvolatile memory device 1100.

[0179] Figure 29 One or more elements of the system may be implemented by: a processing circuit such as hardware including logic circuits; a hardware / software combination such as a processor executing software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like.

[0180] The crack detection structure according to the example embodiments can be applied to any device and system in which a semiconductor integrated circuit is formed. For example, the crack detection structure can be applied to systems such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), universal flash memory (UFS), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, portable computers, digital televisions, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, and the like.

[0181] The foregoing is illustrative of example embodiments and should not be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made to the example embodiments without materially departing from the inventive concept.

[0182] This application claims priority to Korean Patent Application No. 10-2019-0110551, filed on September 6, 2019, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor device comprising: a semiconductor die including a center region and an edge region surrounding the center region; a semiconductor integrated circuit in a plurality of sub-regions of the center region; an external crack detection structure in the edge region; a plurality of internal crack detection structures, each of the plurality of internal crack detection structures including a loop in a respective sub-region of the plurality of sub-regions; and a plurality of path selection circuits configured to control electrical connections between the external crack detection structure and the plurality of internal crack detection structures.

2. The semiconductor device of claim 1, wherein the external crack detection structure is divided into a plurality of loop segments, and the plurality of loop segments are electrically connected via the plurality of path selection circuits to form a conductive loop.

3. The semiconductor device of claim 2, wherein a first end of each of the plurality of internal crack detection structures is connected to a respective path selection circuit of the plurality of path selection circuits, and a second end of the each of the plurality of internal crack detection structures is connected to one of the plurality of loop segments.

4. The semiconductor device of claim 2, wherein each of the plurality of path selection circuits includes: an external switch connected between two loop segments of the plurality of loop segments; and an internal switch connected between a respective internal crack detection structure of the plurality of internal crack detection structures and a first loop segment of the two loop segments.

5. The semiconductor device of claim 4, wherein a first end of the respective internal crack detection structure of the plurality of internal crack detection structures is connected to the internal switch, and a second end of the respective internal crack detection structure of the plurality of internal crack detection structures is connected to a second loop segment of the two loop segments.

6. The semiconductor device of claim 4, wherein the external switch is configured to receive an external connection signal to turn on in response to activation of the external connection signal, and the internal switch is configured to receive an internal connection signal to turn on in response to activation of the internal connection signal.

7. The semiconductor device of claim 6, wherein one of the external connection signal and the internal connection signal is selectively activated, and one of the external switch and the internal switch is selectively turned on.

8. The semiconductor device of claim 7, wherein when the external switch is turned on, a crack in the edge region is detected, and when the internal switch is turned on, a crack in each of the plurality of sub-regions is detected.

9. The semiconductor device of claim 1, wherein the external crack detection structure is a three-dimensional crack detection structure in a ring shape surrounding the center region in the edge region, the three-dimensional crack detection structure extending in a vertical direction.

10. The semiconductor device of claim 9, wherein the semiconductor die includes a first conductive layer and a second conductive layer below the first conductive layer, and ​ ​ wherein the three-dimensional crack detection structure includes a conductive loop extending through the first conductive layer and the second conductive layer in the vertical direction.

11. The semiconductor device of claim 10, wherein the conductive loop includes: a plurality of top horizontal line segments in the first conductive layer; a plurality of bottom horizontal line segments in the second conductive layer; and a plurality of vertical line segments connecting the top horizontal line segments and the bottom horizontal line segments to form the conductive loop.

12. The semiconductor device of claim 11, wherein the first conductive layer corresponds to an uppermost metal layer among a plurality of metal layers above a semiconductor substrate of the semiconductor die, and wherein the second conductive layer corresponds to a gate polysilicon layer in which a gate electrode of a transistor of the semiconductor integrated circuit is formed.

13. The semiconductor device of claim 11, wherein the first conductive layer corresponds to a metal layer above a semiconductor substrate of the semiconductor die, and wherein the second conductive layer corresponds to a metal layer on a bottom surface of the semiconductor substrate.

14. The semiconductor device of claim 11, wherein the plurality of vertical line segments includes a through-substrate via that penetrates a semiconductor substrate of the semiconductor die.

15. A non-volatile memory device, comprising: a first semiconductor die and a second semiconductor die, the first semiconductor die being stacked on the second semiconductor die in a vertical direction, each of the first semiconductor die and the second semiconductor die including a central region and an edge region surrounding the central region; a memory cell structure in a plurality of upper sub-regions of the central region of the first semiconductor die; a peripheral circuit in a plurality of lower sub-regions of the central region of the second semiconductor die; an external crack detection structure in the edge region of the first semiconductor die and the second semiconductor die; a plurality of internal crack detection structures respectively in the plurality of upper sub-regions and respectively in the plurality of lower sub-regions, each of the plurality of internal crack detection structures including a loop in each of the plurality of upper sub-regions or a loop in each of the plurality of lower sub-regions; and a plurality of path selection circuits configured to control electrical connections between the external crack detection structure and the plurality of internal crack detection structures.

16. The non-volatile memory device of claim 15, wherein the first semiconductor die is in a first wafer and the second semiconductor die is in a second wafer, and the non-volatile memory device is provided by dicing the bonded wafers after the first wafer and the second wafer are bonded. wherein 17. The non-volatile memory device of claim 15, wherein the external crack detection structure is divided into a plurality of loop segments, and the plurality of loop segments are electrically connected via the plurality of path selection circuits to form a conductive loop.

18. The non-volatile memory device of claim 17, wherein each path selection circuit of the plurality of path selection circuits includes: ​ an external switch connected between two of the plurality of loop segments; and an internal switch connected between a respective one of the plurality of internal crack detection structures and one of the two loop segments.

19. The nonvolatile memory device of claim 15, wherein a number of the plurality of upper sub-areas is different from a number of the plurality of lower sub-areas.

20. A storage apparatus comprising: one or more nonvolatile memory devices; and processing circuitry configured to control access to the nonvolatile memory devices, each of the nonvolatile memory devices comprising: a first semiconductor die and a second semiconductor die, the first semiconductor die stacked on the second semiconductor die in a vertical direction, each of the first semiconductor die and the second semiconductor die including a center region and an edge region surrounding the center region; memory cell structures in a plurality of upper sub-areas of the center region of the first semiconductor die; peripheral circuitry in a plurality of lower sub-areas of the center region of the second semiconductor die; an external crack detection structure in the edge region of the first semiconductor die and the second semiconductor die; a plurality of internal crack detection structures, respectively in the plurality of upper sub-areas and respectively in the plurality of lower sub-areas, each of the plurality of internal crack detection structures including a loop in each of the plurality of upper sub-areas or a loop in each of the plurality of lower sub-areas; and a plurality of path selection circuits configured to control electrical connections between the external crack detection structure and the plurality of internal crack detection structures.

21. The nonvolatile memory device of claim 20, wherein the plurality of upper sub-areas and the plurality of lower sub-areas are arranged in a concentric circular pattern.

22. The nonvolatile memory device of claim 20, wherein the plurality of upper sub-areas and the plurality of lower sub-areas are arranged in a concentric rectangular pattern.

23. The nonvolatile memory device of claim 20, wherein the plurality of upper sub-areas and the plurality of lower sub-areas are arranged in a concentric hexagonal pattern.

24. The nonvolatile memory device of claim 20, wherein the plurality of upper sub-areas and the plurality of lower sub-areas are arranged in a concentric octagonal pattern.

25. The nonvolatile memory device of claim 20, wherein the plurality of upper sub-areas and the plurality of lower sub-areas are arranged in a concentric star pattern.

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