Memory, integrated circuit memory, and method for manufacturing memory

Abstract

The present invention discloses a memory, an integrated circuit memory and a method for manufacturing the memory. The memory is a device based on a 2T vertical ferroelectric memory cell, including a plurality of selection gate lines in a first layer and a plurality of word lines in a second layer, wherein there are a plurality of vertical channel structures operably arranged with the selection gate lines and the word lines. A vertical channel structure of the memory cell in these vertical channel structures is orthogonally arranged relative to the corresponding selection gate line and the corresponding word line, and forms a channel for a vertical selection transistor and a vertical ferroelectric memory transistor. The ferroelectric material is arranged at the intersection between the vertical channel structure and the corresponding word line. The gate dielectric material is arranged at the intersection between the vertical channel structure and the corresponding selection gate line. The NOR architecture memory uses a 2T vertical ferroelectric memory cell.

Description

Technical Field

[0001] The present invention relates to the technical field of memory, and in particular to a non-volatile memory based on ferroelectric FET, an integrated circuit configured therewith, and a method for manufacturing the memory. Background Art

[0002] As a non-volatile memory, ferroelectric field-effect transistor (FeFET) has been studied for some time. See Lue et al. "Device Modeling of Ferroelectric Memory Field-Effect Transistor (FeMFET)", IEEE Transactions on Electron Devices, Vol. 49, No. 10, October 2002.

[0003] It is desirable to provide a FeFET-based memory architecture that supports high-density and low-power operation. Summary of the invention

[0004] A ferroelectric memory suitable for low power, high density implementation is described. The memory described herein includes a plurality of two transistor ("2T") vertical ferroelectric memory cells, wherein each memory cell includes a vertical select transistor and a vertical ferroelectric memory transistor connected in series between a bit line and a reference line.

[0005] A plurality of 2T vertical ferroelectric memory cells may be arranged in a stacked manner using a plurality of select gate lines in a first layer and a plurality of word lines in a second layer, wherein a plurality of vertical channel structures are operably arranged with the select gate lines and the word lines. The vertical channel structures of the plurality of memory cells are arranged orthogonally relative to the corresponding select gate lines and the corresponding word lines, and form channels for the vertical select transistors and the vertical ferroelectric memory transistors. Ferroelectric material is arranged at the intersection between the vertical channel structure and the corresponding word line. Gate dielectric material is arranged at the intersection between the vertical channel structure and the corresponding select gate line.

[0006] The ferroelectric memory transistor may have a gate-all-around structure in which a vertical channel structure passes through and is surrounded by a corresponding word line. In other embodiments, the ferroelectric memory transistor may have a single gate, vertical channel structure in which memory transistors formed on opposite sides of a frustum of the vertical channel structure are aligned to the layer of the word lines, with a first word line on one side and a second word line on the other side. In still other embodiments, the ferroelectric memory transistor may have a single gate, vertical channel structure in which memory transistors are formed on opposite sides of a semi-cylindrical vertical channel structure (e.g., a separate cylindrical vertical channel structure).

[0007] The memory cell may have only two transistors (a vertical selection transistor and a vertical ferroelectric storage transistor) and no other active components between the reference line and the bit line.

[0008] The ferroelectric material may include hafnium oxide, including, for example, silicon-doped hafnium oxide and zirconium-doped hafnium oxide.

[0009] The memory arrays described herein are implemented using, for example, CMOS in a thin integrated circuit structure with logic circuits located below the memory array under array CuA technology. Alternative solutions can also be implemented with logic circuits covering the memory array. These techniques can reduce the die size required to implement integrated circuits configured with the memory technology described herein.

[0010] In general, a 2T vertical cell NOR memory technology is described that is based on ferroelectric memory materials. Memories based on this technology can operate at low power and high speed, and their programming and erasing operations are resistant to over-erasing and over-programming conditions. A 2T vertical cell NOR memory technology is described that is suitable for implementation in high-density integrated circuits.

[0011] Other aspects and advantages of the present invention will become apparent from a review of the following drawings, detailed description, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a simplified diagram of a 2T vertical ferroelectric memory cell described in this article;

[0013] Figure 2 is a simplified perspective view of a gate-all-around embodiment of a 2T vertical ferroelectric memory cell described herein;

[0014] Figure 3 is a distribution diagram of an array of all gates of a gate allaround 2T vertical ferroelectric memory cells according to an embodiment described herein;

[0015] Figure 4A is a distribution diagram of an array of 2T vertical ferroelectric memory cells having a semi-cylindrical vertical channel structure according to an alternative embodiment;

[0016] Figure 4B is a distribution diagram of an array of 2T vertical ferroelectric memory cells according to an alternative embodiment, wherein a single gate vertical channel structure has memory cells on opposite sides of the vertical channel structure;

[0017] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G , Figure 5H , Fig.5I , Figure 5J, Figure 5K , Figure 5L shows stages in the manufacturing process of a storage unit described herein;

[0018] Figure 6 An alternative embodiment of a 2T vertical memory cell having a solid plug vertical channel structure is shown;

[0019] Figure 7 Another alternative embodiment of a 2T vertical memory cell including a vertical channel structure with a hollow core is shown;

[0020] Fig. 8A is a simplified diagram of CMOS in an array implementation of a memory array having logic circuits described herein on an integrated circuit;

[0021] Figure 8B is similar to Fig. 8A A simplified distribution diagram of integrated circuits;

[0022] Fig. 9 is a simplified diagram of an embodiment of a memory array having logic circuits overlaid on an integrated circuit as described herein;

[0023] Fig.10 is a schematic circuit diagram of a portion of a NOR architecture memory array including a plurality of 2T vertical ferroelectric memory cells;

[0024] Fig.11 is a table illustrating biasing conditions for programming, erasing, and reading operations of a 2T perpendicular ferroelectric memory array described herein; and

[0025] Fig.12 is a simplified block diagram of an integrated circuit including a 2T vertical FeFET memory array.

[0026]

Explanation of symbols

[0027] 100: Main body

[0028] 110: Word line conductor

[0029] 110T: Ferroelectric memory cell transistor

[0030] 115: Ferroelectric Memory Materials

[0031] 120: Select gate conductor

[0032] 120T: Select gate transistor

[0033] 125: Gate dielectric material

[0034] 147: Bit line

[0035] 148: Contact plug

[0036] 149: Reference line conductor

[0037] 150: Vertical channel structure

[0038] 151, 152, 153, 155: Area

[0039] 211, 212, 213, 214, 261, 262, 263, 264: vertical channel structure

[0040] 221, 222: word line conductor

[0041] 233, 234: Connectors

[0042] 291, 292: bit line

[0043] 261C, 262C, 263C, 264C: Contact window

[0044] 333, 334, 433, 434: Connectors

[0045] 361, 362, 363, 364: Vertical channel structure

[0046] 361C, 362C, 363C, 364C: Contact window

[0047] 375, 376, 377, 378: Slit

[0048] 381, 382, ​​383, 384, 385, 386: word line conductors

[0049] 391, 392: bit line

[0050] 440, 441, 442, 443: Channel

[0051] 450: Ferroelectric material layer

[0052] 451: Channel Materials

[0053] 475, 477, 478: Hole

[0054] 481, 482, 483, 484, 485, 486: word lines

[0055] 491, 492: bit line

[0056] 495, 496: Vertical channel structure

[0057] 461C, 462C, 463C, 464C: Contact window

[0058] 505: Silicon oxide layer

[0059] 510: Sacrificial layer

[0060] 512, 522: Insulation layer

[0061] 520: Conductive layer

[0062] 530: Hole

[0063] 531: Bottom

[0064] 540: Reference line conductor

[0065] 551, 552, 553: Pad oxide

[0066] 560: Spacer material

[0067] 561: Spacer

[0068] 562: Top

[0069] 580: Semiconductor plug

[0070] 581: Polysilicon layer

[0071] 582: Plug structure

[0072] 588: Slit

[0073] 590: Conductive materials

[0074] 591: Insulation gasket side wall

[0075] 592: Word line conductor

[0076] 594: Interface layer

[0077] 595: Ferroelectric material layer

[0078] 596: Titanium nitride layer

[0079] 680: Epitaxial Silicon

[0080] 681: Top surface

[0081] 780: Layer

[0082] 781, 782: Thin channel semiconductor layer

[0083] 783: Plug structure

[0084] 800: CMOS Circuits

[0085] 810, 811: Vertical channel structure

[0086] 812, 813: Conductive elements

[0087] 820, 821, 822, 823: Vertical contact plugs

[0088] 830: Bit line

[0089] 840: Reference Line

[0090] 850: Integrated Circuits

[0091] 851: CMOS Circuits

[0092] 852: 2T vertical ferroelectric memory array

[0093] 853: Region

[0094] 900: CMOS Circuits

[0095] 910: Circuit memory device

[0096] 950: Column decoder

[0097] 951: Select gate line

[0098] 952: Word Line

[0099] 960: 2T vertical ferroelectric memory array

[0100] 963: Page Buffer

[0101] 964: Bit line

[0102] 965: Line

[0103] 966: Data Path Circuit

[0104] 967: Line

[0105] 968: Bias device supply voltage

[0106] 969: Controller

[0107] 971: Line

[0108] 972: Data input / output line

[0109] 974: Circuit

[0110] 1010: word line

[0111] 1011: Select gate line

[0112] 1012: word line

[0113] 1013: Select gate line

[0114] 1020: Ferroelectric transistor

[0115] 1021: Select transistor

[0116] A, B, C, D: storage unit

[0117] BL0: bit line

[0118] BL1: bit line

[0119] CSL: Common Source Line

[0120] SGL: Select Gate Line

[0121] WL: Word Line DETAILED DESCRIPTION

[0122] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0123] Reference Figures 1 to 12 , providing a detailed description of embodiments of the present invention.

[0124] Figure 1 A vertical channel, two-transistor ferroelectric memory cell is shown. The memory cell may be formed on an integrated circuit substrate with a reference line conductor 149 thereon. In the example shown, the reference line conductor 149 may include any suitable conductive material, including, as shown, an n-type doped semiconductor region in a p-type body 100 of a semiconductor, which may include a bulk semiconductor of an integrated circuit chip, a semiconductor layer on an insulator, or other types of conductor structures. A vertical channel structure 150 is disposed on the reference line conductor 149, and the vertical channel structure 150 is in electrical contact with the reference line conductor 149.

[0125] In this example, the vertical channel structure 150 extends orthogonally through the select gate conductor 120 and the word line conductor 110. The contact plug 148 contacts the top of the vertical channel structure 150 and connects the vertical channel structure 150 to the overlying bit line 147. In this example, the connection from the top of the vertical channel structure 150 to the overlying bit line 147 is passive without intervening active devices such as transistors or diodes. In this sense, the vertical channel conductor 150 is in electrical contact with the overlying bit line 147.

[0126] The gate dielectric 125 is disposed between the select gate conductor 120 and the vertical channel structure 150 in the region 153. Therefore, the select gate transistor 120T disposed on the vertical channel structure 150 may be used to connect or not connect the vertical channel structure to the reference line conductor 149.

[0127] The ferroelectric memory material 115 is disposed between the wordline conductor 110 and the vertical channel structure 150 in the region 152. Thus, the ferroelectric memory cell transistor 110T is disposed on the vertical channel structure 150 and can be used to store data as a function of the residual polarity of the ferroelectric memory material 115. In some embodiments, the ferroelectric material may include hafnium oxide, such as silicon-doped hafnium oxide and zirconium-doped hafnium oxide. Other ferroelectric materials may also be used.

[0128] like Figure 1 As shown, the vertical channel structure 150 may have a region 151, which may include a semiconductor or other type of conductive plug or filler, and the region 151 is configured to be electrically connected to the contact plug 148. Similarly, the vertical channel structure 150 can be described as including a region 152, which in this example includes a void inside the cylindrical portion of the vertical channel structure 150. This void is the result of a hollow core structure having a thin body structure formed on the sidewalls of the vertical channel structure 150 in the region 152. The vertical channel structure 150 also includes a region 153, which is configured to provide the body of the select gate transistor 120T. In this example, the region 153 of the vertical channel structure 150 is implemented using a solid core of semiconductor material. The vertical channel structure 150 also includes a region 155 in the example shown, which is configured to make electrical contact with the reference line conductor 149 without intervening active devices.

[0129] Figure 2 Yes Figure 1 3D diagram of a gate-all-around configuration of a two-transistor ferroelectric memory cell. In this example, for a similar structure, Figure 1 The component symbols used in Figure 2As shown, the word line conductor 110 and the select gate conductor 120 include strips of conductive material separated by insulating material, and the conductive material is arranged in a stack. The vertical channel structure 150 is disposed in a through hole that passes through the stack. The gate dielectric material 125 is disposed at the intersection of the vertical channel structure 150 and the select gate conductor 120. Similarly, the ferroelectric memory material 115 is disposed at the intersection of the word line conductor 110 and the vertical channel structure 150. In this example, the reference line conductor 149 is a doped region in the semiconductor body 100.

[0130] exist Figure 1 and Figure 2 In the example shown, the ferroelectric memory transistor 110T is disposed in the upper layer of the stack. In other embodiments, the bit line may be disposed below the stack, and the ferroelectric memory transistor may be disposed in the lower layer of the stack, with the select gate transistor 120T disposed between the memory transistor and the bit line.

[0131] Figure 3 2T vertical ferroelectric memory cell array described herein. The array of vertical channel structures (e.g., vertical channel structures 211, 212, 261, 262) is arranged through the stack including the word line conductor 221. In addition, an array of vertical channel structures (e.g., vertical channel structures 213, 214, 263, 264) is arranged through the stack including the word line conductor 222. Reference line conductors (not shown, e.g., Figure 1 The reference line conductor 149 (which may be a wall as described above) is disposed below the array of vertical channel structures. A connector 233 (which in this embodiment is a wall) formed, for example, by filling a trench contacts the reference line conductor below the array of vertical channel structures passing through the word line conductor 221. Similarly, a connector 234 (which may be a wall as described above) contacts the reference line conductor below the array of vertical channel structures passing through the word line conductor 222. In other alternatives, a series of vertical plugs may be used to make connections between the overlying conductors and the reference line conductors.

[0132] In this example, overlying bit lines (e.g., bit lines 291, 292) are disposed above an array of vertical channel structures. Bit line 291 is connected to vertical channel structure 261 through contact 261C and to vertical channel structure 263 through contact 263C. Bit line 292 is connected to vertical channel structure 262 through contact 262C and to vertical channel structure 264 through contact 264C.

[0133] Figure 4AAn alternative embodiment based on a semi-cylindrical vertical channel architecture is shown. In this embodiment, slits 375, 376, 377, 378 are cut in the stack along the centerline of the cylindrical vertical channel structure to form a semi-cylindrical vertical channel structure. Due to these slits, the word line conductor system is divided into word line conductors 381, 382, ​​383, 384, 385, 386.

[0134] Reference conductor (not shown, for example Figure 1 The reference line conductor 149 of FIG. 1 is disposed below the array of vertical channel structures. A connector 333 (in this embodiment, a wall shape) formed, for example, by filling a trench contacts the reference line conductor below the array of vertical channel structures passing through the word line. Similarly, a connector 334 (which may be a wall shape as described above) contacts the reference line conductor below the array of vertical channel structures passing through the word line conductor 222.

[0135] Overlying bit lines (e.g., bit lines 391, 392) are disposed above the array of vertical channel structures. Bit line 391 is connected to semi-cylindrical vertical channel structure 361 through contact window 361C, wherein semi-cylindrical vertical channel structure 361 is coupled to word line conductor 382. Furthermore, bit line 391 is connected to semi-cylindrical vertical channel structure 363 through contact window 363C, wherein semi-cylindrical vertical channel structure 363 is coupled to word line conductor 385.

[0136] The bit line 392 is connected to the semi-cylindrical vertical channel structure 362 through the contact window 362C, wherein the semi-cylindrical vertical channel structure 362 is coupled to the word line conductor 383. Moreover, the bit line 392 is connected to the semi-cylindrical vertical channel structure 364 through the contact window 364C, wherein the semi-cylindrical vertical channel structure 364 is coupled to the word line conductor 386. The vertical channel structure is adjacent to the corresponding word line and the selection gate line, but the vertical channel structure is not surrounded by the corresponding word line and the selection gate line, wherein the vertical channel structure has a ferroelectric memory transistor and a selection transistor at the intersection of the corresponding word line and the selection gate line.

[0137] Figure 4B 4 shows another embodiment based on a vertical channel structure formed on the sidewalls of the trench. In this embodiment, trenches 440-443 cut through the stack and are Figure 5L , Figure 6 or Figure 7The ferroelectric material layer (e.g., ferroelectric material layer 450) is arranged in a row in the memory cell level of the structure with the channel material (e.g., channel material 451). Then, a series of holes (e.g., holes 475, 477, 478) are cut along each channel to divide the ferroelectric memory material layer and the channel material layer into an array of vertical channel structures, which includes memory cells and switch transistors in each layer, including word lines (e.g., word lines 481, 482, 483, 484, 485, 486) in each layer.

[0138] The reference line conductor is disposed below the array of vertical channel structures. Connector 433 (in this embodiment, a wall shape as described above) contacts the reference line conductor below the array of vertical channel structures. Similarly, connector 434 (which may be a wall shape as described above) contacts the reference line conductor below the array of vertical channel structures.

[0139] The vertical channel structures are formed on opposite sides of the channel. For example, vertical channel structure 495 is disposed on the sidewall of channel 440 between holes 477 and 478. In addition, vertical channel structure 496 is disposed on the opposite sidewall of channel 440 between holes 477 and 478 relative to vertical channel structure 495. As shown, an array of vertical channel structures is formed on the sidewalls of the channel.

[0140] Overlying bit lines (only bit lines 491 and 492 are shown) are disposed above the array of vertical channel structures to access memory cells in the array. Bit line 491 is connected to the vertical channel structure on the sidewall of channel 441 through contact 461C, wherein channel 441 is operably coupled to word line 482. Similarly, bit line 491 is connected to the vertical channel structure on the sidewall of channel 443 through contact 463C, wherein channel 443 is operably coupled to word line 485. Bit line 492 is connected to the vertical channel structure through contact 462C relative to the vertical channel structure connected to contact 461C. The vertical channel structure connected to contact 462C is operably coupled to word line 483. Similarly, bit line 492 is connected to the vertical channel structure on the sidewall of channel 443 through contact 464C relative to the vertical channel structure connected to contact 463C, wherein channel 443 is operably coupled to word line 486.

[0141] The vertical channel structure is adjacent to the corresponding word line and the select gate line, but the vertical channel structure is not surrounded by the corresponding word line and the select gate line, wherein the vertical channel structure has a ferroelectric memory transistor and a select transistor at the intersection of the corresponding word line and the select gate line.

[0142] An array comprising bit lines and word lines and a vertical channel structure Figure 3 , Figure 4A and Figure 4B These connection patterns in can be repeated to form large-scale, high-density arrays. In some examples, the arrays can include memory capacities of, for example, 4 Gb (gigabits) or more in a thin integrated circuit structure.

[0143] The structure shown includes a plurality of select gate lines and a plurality of word lines, wherein the word lines are located in a top layer of the stack, wherein the structure shown has a plurality of vertical channel structures. Each of the vertical channel structures is orthogonally disposed relative to a corresponding one of the select gate lines to form a channel for a vertical select transistor, and is orthogonally disposed relative to a corresponding one of the word lines to form a channel for a vertical ferroelectric memory transistor. Figure 3 In an embodiment of the present invention, each of these vertical channel structures is orthogonally arranged relative to and surrounded by a corresponding one of these selection gate lines to form a channel for a vertical selection transistor, and is orthogonally arranged relative to and surrounded by a corresponding one of these word lines to form a channel for a vertical ferroelectric memory transistor.

[0144] FIG. 5A to FIG. 5L 1 shows stages in an exemplary fabrication method for forming a 2T vertical ferroelectric memory cell, which can be configured in a NOR architecture memory array. In this example, the method is as follows: Figure 5A Starting as shown, the stack is formed by forming a sacrificial layer 510 (e.g., silicon nitride) on a conductive layer 520 (e.g., doped polysilicon or other suitable gate conductor), the sacrificial layer 510 and the conductive layer 520 are separated by insulating layers 512, 522 (e.g., silicon oxide) on a semiconductor substrate having a reference line conductor. The reference line conductor 540 may include an n-type doped silicon substrate. In addition, a silicon oxide layer 505 is formed on top of the sacrificial layer 510.

[0145] Figure 5B The structure is shown after forming a hole, such as hole 530 , in which a vertical via structure is formed through the stack, thereby exposing the reference line conductor 540 . Figure 5C The structure after thermal oxidation or other processes to form a pad oxide 553 at the sacrificial layer 510 and a pad oxide 552 at the conductive layer 520 are labeled. In addition, in this exemplary process, a pad oxide 551 is formed at the bottom of the hole and is removed in a subsequent step.

[0146] Figure 5D Shown in the form of covered Figure 5C The structure after the spacer material 560 on the structure includes a structure covering the liner oxide 551 at the bottom of the hole. The spacer material may include polymer, silicon nitride, polysilicon or other suitable materials. Figure 5E The structure is shown after a spacer etch, which removes spacer material from the top 562 of the oxide layer 505 and the bottom 531 of the hole. The spacer etch allows the liner oxide 551 at the bottom of the hole to be removed while leaving liner oxide 553, 552 on the sidewalls of the sacrificial layer 510 and the conductive layer 520.

[0147] Fig. 5F The structure is shown after removal of spacer 561, with silicon liner oxides 552 and 553 remaining on the sidewalls.

[0148] Figure 5G A semiconductor plug 580 is shown formed in the hole, wherein the semiconductor plug 580 is filled to the level of the top surface of the conductive layer 520 and the semiconductor plug 580 is slightly above the level of the top surface of the conductive layer 520. The semiconductor plug 580 may be formed by selective epitaxial growth of silicon, for example by seeding silicon in the reference line conductor 540. This forms a good electrical contact with the reference line conductor 540. The pad oxide 552 on the sidewalls of the conductive layer 520 serves as the gate oxide of the select gate transistor.

[0149] Figure 5H The structure after forming a thin polysilicon layer 581 on the above structure is marked, wherein the thin polysilicon layer 581 is lined on the sidewalls of the hole. The polysilicon layer 581 provides a thin polysilicon channel for the ferroelectric memory cell to be formed at this level of the hole. Fig.5I As shown, the top of the vertical channel structure is filled with a plug structure 582, wherein the plug structure 582 can be formed by depositing a polysilicon layer and then performing an etch back or chemical mechanical polishing step. This process leaves a gap or hollow below the plug structure 582 in the channel polysilicon layer 581 at the level of the sacrificial layer 510.

[0150] Figure 5J The horizontally extending structures are indicated to allow viewing of the slits 588 or array of holes or other types of openings adjacent to the vertical channel structures. The slits 588 may correspond to the openings in which the vertical channel structures may be formed. Figure 3 The channel of connector 233 is shown.

[0151] Figure 5KThe next step is shown, where the sacrificial material at the sacrificial layer 510 is removed through the slits 588, creating openings below the top oxide layer 505 and the middle oxide layer and above the conductive layer 520, and exposing the silicon liner oxide 553 on the channel polysilicon layer 581 of the vertical channel structure.

[0152] Figure 5L The structure is shown after forming a layer of storage material, a storage gate material for forming word lines, and insulating liner sidewalls 591 and conductive material 590 in the slot 588. This process may include forming an interface layer 594, such as silicon nitride, or other dielectric in contact with the silicon liner oxide 553, or other dielectric in contact with the thin channel semiconductor layer 581 if the liner oxide 553 is removed. A ferroelectric material layer 595, such as silicon-doped hafnium oxide or zirconium-doped hafnium oxide, is deposited through the opening on top of the interface layer 594. Thereafter, a titanium nitride layer 596 or other buffer conductor may be formed. This provides an element of a ferroelectric memory structure suitable for storing data. By forming a ferroelectric transistor structure doped with hafnium oxide, the structure at this stage may be exposed to a post-deposition anneal to activate the ferroelectric material. After post-deposition annealing, a layer of tungsten or other metal gate word line material may be deposited to fill the gap between the oxide layer 505 and the oxide layer on top of the conductive layer 520. Finally, the hole may be etched to remove the hole. Excess material is removed from the formation of the storage material, an insulating liner sidewall 591 is formed by oxidation or deposition, and a conductive material 590 such as polysilicon or a metal such as tungsten is deposited to form a contact base line 540 with the underlying doped semiconductor. The insulating liner sidewall 591 isolates the conductive material 590 in the hole from the conductive layer 520 and the word line material 592.

[0153] Figure 5L The structure shown shows a 2T vertical ferroelectric memory cell with an epitaxial silicon body for the select gate at the level of the conductive layer 520, while the hollow core provides a thin channel polysilicon body for the memory gate at the level of the word line conductor 592.

[0154] Figure 6 and Figure 7 Indicate the alternative structure. Figure 6In the embodiment, an epitaxial silicon body 680 grown by selective epitaxial growth is used as the semiconductor body for both the ferroelectric memory transistor and the select gate transistor, wherein the top surface 681 is planarized using chemical mechanical polishing or other techniques. In this embodiment, a 2T vertical ferroelectric memory cell having an epitaxial silicon body 680 for the select gate transistor and the memory gate transistor is provided, which can have a relatively high drain saturation current Idsat and a tighter distribution than using a thin channel structure.

[0155] Figure 7 An embodiment is shown in which thin channel semiconductor layers 781, 782 are used for ferroelectric memory transistors and select gate transistors, wherein the layer 780 at the bottom of the hole is in contact with the reference line conductor 540; and a plug structure 783 at the top surface.

[0156] Top surface (including Figure 5L Plug structure 582, Figure 6 The top surface 681 of the epitaxial silicon body 680 and Figure 7 The plug structure 783 in FIG. 1 is configured to connect to an overlying bit line, such as Figure 1 As shown through a mezzanine plug or other connector.

[0157] FIG. 5A to FIG. 5L The method shown can be adapted to produce Figure 4A The semi-cylindrical vertical channel structure shown in FIG. can be adjusted to Fig.5I The stage shown is to perform slit etching aligned with the vertical channel structure in the structure. This divides the vertical channel into first and second semi-cylindrical vertical channel structures, each of which has a select gate transistor and a storage gate transistor. Similar techniques can be applied to Figure 6 and Figure 7 In the structure shown, a semi-cylindrical vertical channel structure is realized.

[0158] Fig. 8A An embodiment is shown in which an array of 2T vertical ferroelectric memory cells is implemented on a CMOS circuit 800, where the CMOS circuit 800 is used to implement logic circuits on the same integrated circuit. For example, an array of 2T vertical memory cells configured in a NOR architecture can be implemented in a thin structure (including reference line conductors 540, select gate lines, word lines, and overlying bit lines). This can facilitate the implementation of the array in a manner that partially or completely covers the CMOS circuit, thereby allowing efficient use of area on the integrated circuit.

[0159] As shown in FIG8 , CMOS circuit 800 is located below reference line conductor 540. An array of vertical channel structures 810, 811 is disposed above and in contact with reference line conductor 540. As described above, the ferroelectric memory transistor and the select gate transistor in each memory cell are disposed at the intersection of the vertical channel structures 810, 811 and the word lines. Furthermore, conductive elements 812, 813 are connected to the underlying reference line conductor 540. Overlying bit lines (e.g., bit line 830) are connected to the vertical channel structures 810, 811 through vertical contact plugs 820, 821, respectively. In this example, the overlying reference line 840 is connected to the conductive elements 812, 813 through vertical contact plugs 822, 823, respectively.

[0160] Figure 8B 850 is a simplified topology diagram of an integrated circuit 850 having a 2T vertical ferroelectric memory array 852 disposed in a layer above CMOS circuitry 851 on the integrated circuit 850. CMOS circuit embodiments (e.g., decoders or sense amplifiers of the array) and other circuitry are tailored to specific implementation requirements. In this example, other peripheral circuitry and input-output pads are disposed on the integrated circuit 850 in area 853. Utilizing a 2T vertical cell, or architecture, ferroelectric memory as described herein under a CMOS array can provide a significant savings in die size. The low power, high speed operation of the memory technology described herein makes it suitable for a variety of integrated circuit applications.

[0161] Fig. 9 As another example, the 2T vertical cell, NOR architecture ferroelectric memory described herein can be implemented underneath CMOS circuits on an integrated circuit. Fig. 8A The same reference numerals are used to illustrate the memory technology. Fig. 9 The difference is that CMOS circuit 900 is located on a metal layer, where the metal layer is used to implement the bit lines and reference lines in the memory array.

[0162] The thin array structures described herein can be stacked in multiple memory planes to provide high density 3D memory devices.

[0163] Fig.10is a schematic circuit diagram of a 2T NOR array using ferroelectric memory cell transistors as described herein. In this example, there are four two-transistor ferroelectric memory cells: memory cell A, memory cell B, memory cell C, and memory cell D. Each memory cell includes a ferroelectric transistor (e.g., ferroelectric transistor 1020) in series with a select transistor (e.g., 1021). In a simple embodiment without any intervening active devices, the ferroelectric transistor (e.g., ferroelectric transistor 1020) is connected to a bit line. In a simple embodiment without any intervening active devices, the select transistor (e.g., select transistor 1021) is connected to a common source line.

[0164] Memory cells AD are arranged between bit lines BL0 and BL1 and one or more common source lines CSL. Word line WL1010 is coupled to ferroelectric transistors in memory cells C and D, which are coupled to bit lines BL0 and BL1, respectively. Similarly, selection gate line SGL 1011 is coupled to selection transistors in memory cells C and D, which are coupled to common source line CSL. Word line WL 1012 is coupled to ferroelectric transistors in memory cells A and B, which are coupled to bit lines BL0 and BL1, respectively. Similarly, selection gate line SGL 1013 is coupled to selection transistors in memory cells A and B, which are coupled to common source line CSL.

[0165] Fig.10 The array shown is controlled by bias circuits and control logic on the integrated circuit to perform read, program and erase operations. Fig.11 The table in illustrates typical biasing conditions for this type of operation.

[0166] For programming operations, an electric field may be established across the word lines and bit lines. Thus, during a programming operation, the select gate lines for selected and unselected memory cells may be biased at 0 volts and in a non-conductive off state. The word line for the selected memory cell may be biased at a voltage on the order of positive 5 volts to positive 8 volts. The unselected word lines may remain at 0 volts. The bit lines (drains) on the selected memory cells may be biased at 0 volts, while the bit lines on the unselected memory cells may be biased at Vpgm / 2, for example, where the implementation of the select gate allows for a relatively low punchthrough threshold. The common source line may also remain at 0 volts. This programming bias will cause the selected memory cells to be programmed to a low Vt threshold, which may be less than 0 volts.

[0167] For the erase operation, a block erase operation may be performed. For block erase, the word lines in the selected block may be biased at approximately negative 5 volts, while the bit lines in the selected block are biased at approximately positive 5 volts. The select gate line may be biased at approximately 0 volts, keeping it in an off state during this operation. Likewise, the common source line may be biased at approximately 0 volts. The use of a split voltage across the bit lines and word lines may produce an effective negative 10 volts across the ferroelectric memory cell. This applied electric field will induce a high threshold erased state.

[0168] The read operation can be low voltage and low power. For example, for a read operation, the select gate line for the selected memory cell can be biased at about 1 volt or an externally applied VCCQ level such as 1.8 volts. This allows a read operation without a charge pump. The unselected select gate lines can be biased at about 0 volts.

[0169] The selected word line may be biased at about 0 volts, and the unselected word lines may be biased at about 0 volts. Since the programmed state threshold may be less than 0 volts, low voltage reading is achieved. Without a charge pump, the bit line or drain of the selected memory cell may be biased at about 1 volt or VCCQ, and the unselected bit lines may be biased at about 0 volts. Likewise, during reading, the common source line CSL may be biased at about 0 volts.

[0170] Because of the select gates in a two-transistor NOR array, over-programmed (threshold too low) or over-erased states (threshold too high) do not cause leakage or other types of operational problems. This reduces the complexity of the program and erase algorithms required for array operation.

[0171] Fig.12 9 is a simplified block diagram of an integrated circuit memory device 910 including a 2T vertical ferroelectric memory array 960 as described herein. The integrated circuit includes peripheral circuitry having a column decoder 950 including drivers for select gate lines 951 and word lines 952 coupled to the array 960. Likewise, the peripheral circuitry includes a page buffer 963 coupled to bit lines 964 of the array. In addition, addresses are applied to the page buffer 963 and the column decoder 950 on lines 965. In this simplified example, data path circuitry 966, such as a cache memory, is coupled to the page buffer on lines 967. The data path circuitry 966 may be coupled to other circuitry 974 via lines 971 and to data input / output lines 972 for off-chip communications, for example. A bias device supply voltage 968 is included to apply bias voltages used in read, program, and erase operations as described above. A bias circuit for a common source line or common source line (not shown) is also included.

[0172] The controller 969 includes logic for performing read operations, program operations, and erase operations. In various embodiments, the controller 969 may include a state machine formed by dedicated logic, programmable array logic, a general purpose processor, and combinations thereof.

[0173] Another circuit 974 in this figure is labeled "lower array." This means that the logic circuits on the integrated circuit memory device 910 can be implemented below the array 960 as described above, thereby saving chip area.

[0174] A 2T vertical memory cell utilizing ferroelectric memory technology is described that can be configured in a NOR architecture. The ferroelectric memory can operate at relatively low voltages, including read operations without the use of a charge pump or other on-chip boost circuitry. The use of a two-transistor cell prevents over-erasure and over-programming conditions, thereby simplifying programming and erasing operations. The two-transistor cell can have a variety of vertical channel body structures. In one embodiment, the select gate uses a transistor of silicon formed by selective epitaxial growth, and the storage gate uses a thin channel structure. In another embodiment, both gates can use epitaxially grown silicon as the transistor body. In yet another embodiment, both the select gate and the storage gate can use a thin channel structure.

[0175] Various distribution schemes can be implemented for the vertical channel dual transistor unit, including gate-all-around structures, single gate vertical channel structures, and semi-cylindrical vertical channel structures. In addition, the technology can be combined with CMOS in an array architecture, thereby saving a lot of area.

[0176] Generally speaking, the technology provided by using ferroelectric memory technology has a ferroelectric material including hafnium oxide, which is suitable for low-power, high-speed flash memory.

[0177] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory, in, include: a plurality of memory cells, each of the memory cells comprising a vertical selection transistor and a vertical ferroelectric storage transistor connected in series between a bit line and a reference line; and a plurality of vertical channel structures, each of the vertical channel structures forming a channel for the vertical selection transistor and forming a channel for the vertical ferroelectric memory transistor, the vertical channel structures comprising silicon material; The reference line is electrically connected to a connector, and an extension direction of the connector is orthogonal to an extension direction of the bit line.

2. The memory according to claim 1, in, include: a plurality of select gate lines and a plurality of word lines; A plurality of vertical channel structures, each of which is orthogonally disposed relative to a corresponding one of the select gate lines to form a channel for the vertical select transistor, and is orthogonally disposed relative to a corresponding one of the word lines to form a channel for the vertical ferroelectric memory transistor.

3. The memory according to claim 1, in, include: a plurality of select gate lines and a plurality of word lines; A plurality of vertical channel structures, each of which is orthogonally disposed relative to and surrounded by a corresponding one of the selection gate lines to form a channel for the vertical selection transistor, and is orthogonally disposed relative to and surrounded by a corresponding one of the word lines to form a channel for the vertical ferroelectric memory transistor.

4. The memory according to claim 1, in, The vertical ferroelectric memory transistor includes a vertical channel, a ferroelectric material layer and a word line material layer.

5. The memory according to claim 4, in, The ferroelectric material layer includes hafnium dioxide.

6. The memory according to claim 1, in, These memory cells are configured in a NOR architecture.

7. The memory according to claim 1, in, The memory cells are disposed on a substrate, the substrate includes a logic circuit, and the memory cells are disposed in an array covering the logic circuit.

8. The memory according to claim 1, in, The memory cells are arranged in an array on a substrate and include logic circuits covering the array.

9. The memory according to claim 1, in, Bias circuits are included to apply read, program, and erase operations to the memory cells.

10. An integrated circuit memory, in, include: a substrate; a reference line conductor disposed on the substrate; a stack including a select gate conductor layer and a word line conductor layer on the reference line conductor on the substrate; a plurality of vertical channel pillars disposed orthogonally relative to the select gate conductor layer and the word line conductor layer in the stack and contacting the reference line conductor; A ferroelectric memory material is disposed at the intersections of the vertical channel pillars and the word line conductor layer; a select gate dielectric material disposed at the intersections of the vertical channel pillars and the select gate conductor layer; as well as A plurality of bit lines are disposed on the vertical channel pillars and contact the vertical channel pillars; The reference line conductor is electrically connected to a connector, and the extension direction of the connector is orthogonal to the extension direction of the bit line; the ferroelectric storage material includes a bottom surface, which is higher than a top surface of the selection gate conductor layer.

11. The integrated circuit memory according to claim 10, in, The reference line conductor on the substrate includes a doped semiconductor material.

12. The integrated circuit memory according to claim 10, in, The vertical channel pillars are surrounded by select gate conductor material in the select gate conductor layer and word line conductor material in the word line conductor layer.

13. The integrated circuit memory according to claim 10, in, The select gate conductor layer is located below the word line conductor layer in the stack.

14. The integrated circuit memory according to claim 10, in, The control and bias circuits are included to set a residual polarity in the ferroelectric memory material by applying an electric field to program data.

15. The integrated circuit memory according to claim 10, in, The invention comprises a dielectric layer between the ferroelectric memory material and the vertical channel pillars, and a conductive buffer layer between the ferroelectric memory material and the word line conductor layer.

16. The integrated circuit memory according to claim 10, in, The ferroelectric memory material includes hafnium dioxide.

17. The integrated circuit memory according to claim 10, in, These vertical channel pillars are arranged in a NOR architecture.

18. The integrated circuit memory according to claim 10, in, A logic circuit is included, and wherein the stack covers the logic circuit.

19. The integrated circuit memory of claim 10, comprising a logic circuit, and wherein the logic circuit covers the stack.

20. A method of manufacturing a memory, in, include: forming a plurality of select gate lines and a plurality of word lines; forming a plurality of vertical channel structures, each of which is orthogonally arranged relative to a corresponding one of the selection gate lines to form a channel for a vertical selection transistor, and is orthogonally arranged relative to a corresponding one of the word lines to form a channel for a vertical ferroelectric memory transistor; wherein the vertical selection transistor and the vertical ferroelectric memory transistor are connected in series between a bit line and a reference line, the reference line is electrically connected to a connector, and the extension direction of the connector is orthogonal to the extension direction of the bit line; forming a ferroelectric memory material at intersections of a plurality of vertical channel pillars and a word line conductor layer; and forming a select gate dielectric material at the intersections of the vertical channel pillars and a select gate conductor layer; The ferroelectric storage material comprises a bottom surface which is higher than a top surface of the selection gate conductor layer.

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