A power switch fault self-detection circuit, method, inverter and air conditioning equipment

Abstract

The present invention discloses a power switch fault self-check circuit, method, frequency converter and air conditioning equipment. The circuit includes a plurality of sampling modules and a main control chip, wherein the sampling module is connected to the power switch in a one-to-one correspondence, wherein the first input terminal thereof inputs a first voltage, the second input terminal inputs a second voltage, the third input terminal is connected to the drain of the power switch, and the fourth input terminal inputs the gate drive signal; the circuit is used to generate an indication signal according to the on-off state of the power switch and the gate drive signal, wherein the indication signal is used to indicate whether the power switch fails; the main control chip, whose input terminal is connected to the output terminal of the sampling module, is used to determine whether the power switch fails according to the indication signal, and control the gate drive signal to be blocked when the power switch fails. Through the present invention, it is possible to implement fault self-checking before the power switch is put into use, thereby improving safety and reliability.

Description

Technical Field

[0001] The present invention relates to the field of electronic power technology, and in particular to a power switch fault self-detection circuit, method, frequency converter and air conditioning equipment. Background Art

[0002] Current inverters (such as photovoltaic inverters) include a rectifier module and an inverter module. Figure 1 The circuit structure diagram of the existing frequency converter is shown in FIG. 1 , in which the rectifier module and the inverter module both include power switches (such as insulated gate bipolar transistors, IGBTs). As efficiency requirements continue to increase, three-level and five-level frequency converters are gradually appearing on the market. With the emergence of these frequency converters, the demand for power switches is increasing, and the safety and reliability of power switches are becoming more and more important. In current frequency converters, or other devices using power switches, power switch fault self-checks are generally not performed before actual operation. When transported over long distances for a long time, or after long-term unstable operation, the module will be damaged, causing the power switch to fail. If it is put into operation directly without detection before the next use, it is likely to cause a huge safety accident.

[0003] With regard to the problem in the prior art that power switches are not tested before being put into use, which may easily lead to potential safety hazards, no effective solution has been proposed so far. Summary of the invention

[0004] The embodiments of the present invention provide a power switch fault self-detection circuit, method, inverter and air conditioning equipment to solve the problem in the prior art that the power switch is not detected before being put into use, which may cause safety hazards.

[0005] In order to solve the above technical problems, the present invention provides a power switch fault self-detection circuit, which is applied to a frequency converter, wherein the frequency converter includes a plurality of power switches, and the circuit includes: a plurality of sampling modules and a main control chip;

[0006] The sampling module is connected to the power switch in a one-to-one correspondence, a first input terminal thereof inputs a first voltage, a second input terminal thereof inputs a second voltage, a third input terminal thereof is connected to the drain of the power switch, and a fourth input terminal thereof inputs a gate drive signal of the power switch; the sampling module is used to generate an indication signal according to the on / off state of the power switch and the gate drive signal; wherein the indication signal is used to indicate whether a fault occurs to the power switch;

[0007] The main control chip, whose input end is connected to the output end of the sampling module, is used to determine whether the power switch fails according to the indication signal, and to block the gate drive signal when the power switch fails.

[0008] Furthermore, the sampling module comprises:

[0009] A voltage dividing unit, a first end of which is input with the first voltage, and a second end of which is connected with the drain of the power switch; the voltage dividing unit is used to divide the first voltage, generate a third voltage and output it to the comparator;

[0010] The comparator has a first input terminal connected to the output terminal of the voltage dividing unit, and a second input terminal inputting the second voltage, and is configured to output a high level when the third voltage is greater than the second voltage, and output a low level when the third voltage is less than the second voltage;

[0011] An exclusive-OR logic chip, whose first input terminal is connected to the output terminal of the comparator and whose second input terminal inputs the gate drive signal, is used to output a high-level indication signal when the output signal of the comparator is consistent with the gate drive signal, and output a low-level indication signal when the output signal of the comparator is inconsistent with the gate drive signal.

[0012] Furthermore, the voltage dividing unit comprises:

[0013] A first resistor and a second resistor, the first resistor and the second resistor are connected in series to form a series branch, the first end of the series branch inputs the first voltage, the second end is connected to the drain of the power switch, and the line between the first resistor and the second resistor is connected to the first input end of the comparator.

[0014] Furthermore, the sampling module also includes:

[0015] a third resistor, arranged between the first input terminal of the comparator and the output terminal of the voltage dividing unit, and used for limiting the current of the first input terminal of the comparator;

[0016] A fourth resistor is arranged at the second input terminal of the comparator and is used to limit the current of the second input terminal of the comparator.

[0017] Furthermore, the sampling module also includes:

[0018] At least one unidirectional element is connected in series between the second end of the voltage divider unit and the drain of the power switch tube, and is used to control the direction of the current.

[0019] Furthermore, the circuit further comprises:

[0020] A power supply module, whose input end is connected to a power supply, and whose output end is connected to the sampling module, is used to output the first voltage and the second voltage.

[0021] Furthermore, the circuit further comprises:

[0022] The alarm module has an input end connected to the main control chip and is used to be triggered and sound an alarm when a failure occurs in the power switch.

[0023] Furthermore, the output end of the main control chip is connected to the first circuit breaker and the second circuit breaker in the inverter, and is used to block the control signal of the first circuit breaker and / or the second circuit breaker.

[0024] The present invention also provides a frequency converter, which includes the power switch fault self-detection circuit.

[0025] The present invention also provides an air conditioning device, which includes the above-mentioned inverter.

[0026] The present invention also provides a power switch fault self-detection method, which is applied to the above power switch fault self-detection circuit, and the method comprises:

[0027] Outputting a gate drive signal to each power switch in turn to obtain an indication signal of each power switch; wherein the indication signal is generated based on the gate drive signal and the on / off state of the power switch and is used to indicate whether the power switch fails;

[0028] It is determined according to the indication signal whether a power switch corresponding to the indication signal fails.

[0029] Further, the indication signal is generated based on the gate drive signal and the on / off state of the power switch, including:

[0030] If the gate drive signal matches the on / off state of the power switch, the generated indication signal is a low level signal;

[0031] If the gate drive signal does not match the on / off state of the power switch, the generated indication signal is a high level signal.

[0032] Further, judging whether a power switch corresponding to the indication signal fails according to the indication signal includes:

[0033] If the indication signal is a low level signal, it is determined that the power switch corresponding to the indication signal has not failed;

[0034] If the indication signal is a high level signal, it is determined that a power switch corresponding to the indication signal fails.

[0035] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the power switch fault self-detection method is implemented.

[0036] By applying the technical solution of the present invention, a plurality of sampling modules are connected and arranged in a one-to-one correspondence with the power switches, and an indication signal is generated according to the on-off state of each power switch and the gate drive signal to indicate whether a power switch fails. Through the main control chip, it is determined whether the power switch fails according to the indication signal, and the gate drive signal is controlled to be blocked when the power switch fails, so that fault self-check can be implemented before the power switch is put into use, thereby improving safety and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is the circuit structure diagram of the existing frequency converter;

[0038] Figure 2 is a structural diagram of a power switch fault self-detection circuit according to an embodiment of the present invention;

[0039] Figure 3 is a structural diagram of a sampling module according to an embodiment of the present invention;

[0040] Figure 4 A partial structural diagram of a power switch fault self-detection circuit according to an embodiment of the present invention;

[0041] Figure 5 is a structural diagram of a power switch fault self-detection circuit according to another embodiment of the present invention;

[0042] Figure 6 is a flow chart of a switch fault self-detection method according to an embodiment of the present invention;

[0043] Figure 7 is a structural block diagram of a power switch fault self-detection circuit according to an embodiment of the present invention;

[0044] Figure 8 FIG. 4 is a flow chart of a power switch fault self-detection method according to another embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings, and "multiple" generally includes at least two.

[0047] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0048] It should be understood that although the terms first, second, third, etc. may be used to describe resistors in embodiments of the present invention, these resistors should not be limited to these terms. These terms are only used to distinguish different resistors. For example, without departing from the scope of embodiments of the present invention, a first resistor may also be referred to as a second resistor, and similarly, a second resistor may also be referred to as a first resistor.

[0049] As used herein, the words "if" and "if" may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0050] It should also be noted that the term "includes", "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, so that a commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the commodity or device including the elements.

[0051] The optional embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0052] Example 1

[0053] This embodiment provides a power switch fault self-detection circuit, which is applied to a frequency converter, as mentioned above. Figure 1As shown in the figure, the inverter mainly includes a rectifier circuit and an inverter circuit, wherein the rectifier circuit includes power switches Q1 to Q6, and the inverter circuit includes power switches Q7 to Q12. The above power switches are connected in series and then in parallel to form a rectifier bridge or an inverter bridge, and each switch tube includes a drain D, a gate G, and a source S. The input end of the rectifier circuit is connected to a three-phase AC power supply, and a first circuit breaker K1 is provided between the rectifier circuit and the three-phase AC power supply. The rectifier circuit and the inverter circuit are connected through a DC bus, and a second circuit breaker K2 is provided on the DC bus. By disconnecting the first circuit breaker K1 and the second circuit breaker K2, the AC voltage grid and / or photovoltaic voltage input can be prohibited, and the converter can be turned off when necessary to improve the safety and reliability of the equipment.

[0054] Figure 2 is a structural diagram of a power switch fault self-detection circuit according to an embodiment of the present invention, as shown in Figure 2 As shown, the circuit includes: multiple sampling modules and a main control chip;

[0055] The sampling module 1 is connected to the power switches Q1 to Q12 in a one-to-one correspondence, the first input terminal of the sampling module 1 inputs the first voltage V1, the second input terminal inputs the second voltage V2, the third input terminal is connected to the drain D of the power switch, and the fourth input terminal inputs the gate drive signal of the power switch; the sampling module 1 is used to generate an indication signal according to the on-off state of the power switch and the gate drive signal, wherein the indication signal is used to indicate whether a fault occurs in the power switch; the source S of the power switch inputs the source drive signal, and the gate G inputs the gate drive signal, and the power switch is driven to be turned on or off through the voltage difference formed between the source drive signal and the gate drive signal. When the power switch is driven to be turned on, the source drive signal is 0V and the gate drive signal is a positive voltage. When the power switch is driven to be turned off, the source drive signal is 0V, the gate drive signal is 0V, and the source drive signal is 12V.

[0056] The main control chip 2 has an input end connected to the output end of the sampling module 1 and is used to determine whether the power switch fails according to the indication signal output by the sampling module 1 and block the gate drive signal of the power switch when the power switch fails.

[0057] like Figure 2 As shown, the drain of each power switch is connected to the input end of the corresponding sampling module 1, and each sampling module 1 is connected to the main control chip 2 to obtain the gate drive signal of the power switch and feed back the indication signal to the main control chip 2.

[0058] The power switch fault self-check circuit of the present embodiment generates an indication signal according to the on / off state of each power switch and the gate drive signal through a plurality of sampling modules connected in a one-to-one correspondence with the power switches to indicate whether a power switch has failed. Through the main control chip, it is determined whether a power switch has failed according to the indication signal, and the gate drive signal is controlled to be blocked when a power switch has failed, so that a fault self-check can be performed before the power switch is put into use, thereby improving safety and reliability.

[0059] Example 2

[0060] This embodiment provides another power switch fault self-detection circuit. Figure 3 is a structural diagram of a sampling module according to an embodiment of the present invention, in order to realize generating an indication signal according to the on-off state of the power switch and the gate drive signal, such as Figure 3 As shown, the sampling module 1 includes:

[0061] A voltage dividing unit 11, a first end of which inputs a first voltage V1, and a second end of which is connected to a drain electrode D of the power switch; the voltage dividing unit is used to divide the first voltage V1, generate a third voltage V3 and then output it;

[0062] The comparator A has a first input terminal connected to the output terminal of the voltage divider unit 11, and a second input terminal inputting the second voltage V2, and is used to output a high level when the third voltage V3 is greater than the second voltage V2, and output a low level when the third voltage is less than the second voltage. When the power switch is turned on or off, the voltage divider unit 11 is connected to different conduction conditions, so the output value of the third voltage V3 is different, which leads to different output signals of the comparator. The output signal of the comparator A can reflect the on-off state of the power switch tube.

[0063] The same or logic chip IC has a first input terminal connected to the output terminal of the comparator A, and a second input terminal inputting a gate drive signal, and is used to output an indication signal according to the output signal and the gate drive signal of the comparator A. Specifically, if the output signal of the comparator A is consistent with the gate drive signal, the output indication signal is a high level, and if the output signal of the comparator A is inconsistent with the gate drive signal, the output indication signal is a low level, wherein the consistency means that both are high levels or both are low levels, and the indication signal output by the same or logic chip IC can reflect whether the on-off state of the power switch tube matches the gate drive signal input to its gate, and then determine whether the power switch tube fails.

[0064] Specifically, the voltage dividing unit 11 includes: a first resistor R1 and a second resistor R2, the first resistor R1 and the second resistor R2 are connected in series to form a series branch, the first end of the series branch inputs the first voltage V1, the second end is connected to the drain of the power switch, and the line between the first resistor R1 and the second resistor R2 is connected to the first input end of the comparator A. When the power switch tube is turned on, the first voltage V1 passes through the first resistor R1, the second resistor R2 and the power switch tube and then is grounded, and the third voltage V3 obtained after the voltage is divided by the first resistor R1 and the second resistor R2 is input to the first input end of the comparator A. By setting the values ​​of the first resistor R1, the second resistor R2 and the second voltage V2, the third voltage V3 is less than the second voltage V2 at this time, and the comparator A outputs a low level. When the power switch tube is turned off, the first voltage V1 is divided by the first resistor R1 to generate the third voltage V3, which is input to the first input end of the comparator A. Since there is no voltage dividing effect of the second resistor, the third voltage V3 rises to be greater than the second voltage V2 at this time, and the comparator A outputs a high level.

[0065] Since comparator A must work below a certain current value, in order to achieve current limiting, the sampling module also includes:

[0066] The third resistor R3 is arranged between the first input terminal of the comparator A and the output terminal of the voltage divider unit 11, and is used to limit the current of the first input terminal of the comparator A; the fourth resistor R4 is arranged at the second input terminal of the comparator A, and is used to limit the current of the second input terminal of the comparator A. Preferably, the third resistor R3 and the fourth resistor R4 have equal resistance values.

[0067] In order to ensure the normal functions of the first resistor R1, the second resistor R2, and the comparator A, the current can only flow from the second resistor R2 to the drain D of the power switch. Therefore, in order to achieve this purpose, the sampling module 1 also includes: at least one unidirectional element D1, which is connected in series between the second resistor R2 and the drain D of the power switch tube, with its anode connected to the second resistor R2 and its cathode connected to the drain D of the power switch tube, for controlling the current to flow from the second resistor R2 to the drain D of the power switch. In order to ensure the control effect, unidirectional elements D2 and D3 can also be set in series. The unidirectional elements D1, D2, and D3 can all be diodes.

[0068] Figure 4 FIG. 1 is a partial structural diagram of a power switch fault self-detection circuit according to an embodiment of the present invention. In order to provide a first voltage and a second voltage, as shown in FIG. Figure 4 As shown, the power switch fault self-detection circuit also includes:

[0069] The power supply module 3 has an input end connected to the power supply, and an output end including a first output terminal and a second output terminal. The first output terminal is connected to the first input terminal of the sampling module 1 for outputting a first voltage V1, and the second output terminal is connected to the second input terminal of the sampling module for outputting a second voltage V2.

[0070] Figure 5 FIG. 1 is a structural diagram of a power switch fault self-detection circuit according to another embodiment of the present invention. After a power switch fault is detected, in order to remind maintenance personnel to handle the fault in time, Figure 5 As shown, the power switch fault self-detection circuit further includes: an alarm module 4, whose input end is connected to the output end of the main control chip 2, and the alarm module 4 is used to be triggered when a power switch fails and issue an alarm.

[0071] In order to make the converter power off more thoroughly and avoid the rectifier circuit or inverter circuit from being triggered incorrectly under fault conditions, such as Figure 5 As shown, the output end of the main control chip 2 is also connected to the first circuit breaker K1 and the second circuit breaker K2 in the inverter, so as to block the control signals of the first circuit breaker and the second circuit breaker.

[0072] Example 3

[0073] This embodiment provides a power switch fault self-detection method, which is applied to the power switch fault self-detection circuit of the above embodiment. Figure 6 FIG. 1 is a flow chart of a switch fault self-detection method according to an embodiment of the present invention. Figure 6 As shown, the method includes:

[0074] S101, outputting a gate drive signal to each power switch in turn, and obtaining an indication signal of each power switch; wherein the indication signal is generated according to the gate drive signal and the on / off state of the power switch, and is used to indicate whether a fault occurs in the power switch.

[0075] In a specific implementation, a plurality of sampling modules are provided, wherein the sampling module 1 is connected to the power switches Q1 to Q12 in a one-to-one correspondence, a fixed first voltage is input to the first input terminal of the sampling module, a fixed second voltage is input to the second input terminal, the third input terminal is connected to the drain of the power switch, and the gate drive signal of the power switch is input to the fourth input terminal, so as to generate an indication signal for whether a power switch fails according to the gate drive signal and the on / off state of the power switch.

[0076] S102: Determine, according to the indication signal, whether a power switch corresponding to the indication signal fails.

[0077] The input end of the main control chip is connected to the output end of each sampling module. After obtaining the indication signal, it is determined whether the power switch fails according to the indication signal, and after determining that the power switch fails, the gate drive signal is blocked.

[0078] The power switch fault self-check method of this embodiment outputs a gate drive signal to each power switch in turn, and obtains an indication signal of each power switch, wherein the indication signal is generated according to the gate drive signal and the on-off state of the power switch, and is used to indicate whether a power switch has failed; and judging whether a power switch corresponding to the indication signal has failed according to the indication signal, it is possible to perform a fault self-check before the power switch is put into use, thereby improving safety and reliability.

[0079] Example 4

[0080] This embodiment provides another power switch fault self-check method, wherein the indication signal is generated according to the gate drive signal and the on-off state of the power switch, specifically including: if the gate drive signal matches the on-off state of the power switch, the generated indication signal is a low-level signal; if the gate drive signal does not match the on-off state of the power switch, the generated indication signal is a high-level signal. Wherein, the gate drive signal matches the on-off state of the power switch, which means that the gate drive signal is at a high level and the power switch is turned on, or the gate drive signal is at a low level and the power switch is turned off. In other cases, it is considered that the gate drive signal does not match the on-off state of the power switch.

[0081] In a specific implementation, the indication signal is generated according to the gate drive signal and the on / off state of the power switch through a voltage divider unit, a comparator and an XOR logic chip.

[0082] The first end of the voltage divider unit inputs the first voltage, and the second end is connected to the drain of the power switch, which is used to divide the first voltage, generate a third voltage V3 and then output it to the comparator; the first input end of the comparator is connected to the output end of the voltage divider unit, and the second input end is input with the second voltage V2. The comparator outputs a high level when the third voltage V3 is greater than the second voltage V2, and outputs a low level when the third voltage is less than the second voltage. When the power switch is turned on or off, the voltage divider unit is connected to different conduction conditions, so the value of the output third voltage V3 is different, which leads to different output signals of the comparator. The output signal of the comparator can reflect the on-off state of the power switch tube. The first input end of the XOR logic chip is connected to the output end of the comparator, and the second input end is input with the gate drive signal. The XOR logic chip outputs an indication signal according to the output signal of the comparator and the gate drive signal. Specifically, if the output signal of the comparator is consistent with the gate drive signal, the output indication signal is a high level; if the output signal of the comparator is inconsistent with the gate drive signal, the output indication signal is a low level, wherein consistency means both are high level or both are low level, and the indication signal output by the same or same logic chip can reflect whether the on-off state of the power switch tube matches the gate drive signal input to its gate, thereby determining whether the power switch tube fails. Specifically, judging whether the power switch corresponding to the indication signal fails according to the indication signal includes: if the indication signal is a low level signal, it indicates that the gate drive signal matches the on-off state of the power switch, and it is determined that the power switch corresponding to the indication signal has not failed; if the indication signal is a high level signal, it indicates that the gate drive signal does not match the on-off state of the power switch, and it is determined that the power switch corresponding to the indication signal fails.

[0083] Example 5

[0084] This embodiment provides a power switch fault self-detection circuit, which is applied to a frequency converter. Figure 7 FIG. 4 is a structural block diagram of a power switch fault self-detection circuit according to an embodiment of the present invention. Figure 7 As shown, the power switch fault self-detection circuit includes: a sampling module 1 and a main control chip 2, wherein the main control chip 2 is connected to the power switch and is used to receive the indication signal output by the sampling module 1, and block the gate drive signal of the power switch and the control signal of the circuit breaker (the first circuit breaker K1 and the second circuit breaker K2) of the inverter according to the indication signal.

[0085] As mentioned above Figure 3As shown in , the sampling module 1 includes a voltage dividing unit composed of a first resistor R1 and a second resistor R2. A unidirectional element D1 is arranged in series between the second resistor R2 and the drain of the power switch. The function of the unidirectional element D1 is to control the current to flow only from the second resistor R2 to the drain of the power switch. In order to ensure the control effect, a unidirectional element D2 and a unidirectional element D3 can also be arranged in series. The unidirectional elements D1, D2, and D3 can all be diodes. A comparator A is also included. A third resistor R3 is arranged at the first input end of the comparator A, and a fourth resistor R4 is arranged at the second input end. Also included is an XOR logic chip IC.

[0086] The above-mentioned power switch fault self-detection circuit also includes a power supply module 3, which can use an isolation chip or an isolation transformer to isolate the power supply and the ground. The output end of the power supply module 3 includes a first output terminal and a second output terminal, which are used to output a first voltage and a second voltage respectively.

[0087] This embodiment also provides a power switch fault self-detection method, Figure 8 FIG. 1 is a flow chart of a power switch fault self-detection method according to another embodiment of the present invention. Figure 8 As shown, the method includes:

[0088] S1, control the main control chip to be powered on and initialized.

[0089] When the system starts, the main control chip is powered on and initialized. In the initial state, the fault flags of power switches Q1 to Q12 are all 0.

[0090] S2, enters shutdown fault detection, controls the gate drive signals of power switches Q1~Q12 to be shutdown signals, and the main control chip detects the indication signals Vwarn1~Vwarn12 corresponding to each power switch in turn.

[0091] The gate drive signal VG output by the main control chip is +12V or 0V, where +12V is a turn-on signal and 0V is a turn-off signal.

[0092] S3, determine in turn whether each indication signal is a high level or a low level, if it is a high level, execute step S4, if it is a low level, execute step S5.

[0093] S4, determining that a power switch corresponding to the current indication signal fails, blocking the gate drive signal and the control signals of the first circuit breaker and the second circuit breaker.

[0094] S5, determining that the power switch corresponding to the current indication signal has not failed.

[0095] Taking the power switch Q1 as an example, when controlling Q1 to turn off, the voltage between the gate and source of the power switch needs to be -12V, that is, the gate drive signal VG1 is 0V, and the source voltage of the power switch is 12V. Figure 3 As shown in the figure, the detection module inputs the first voltage V1, generates the third voltage V3 after voltage division, and inputs the first input terminal (non-inverting input terminal) of the comparator A. At the same time, the second voltage V2 is input into the first input terminal of the comparator A. By setting the resistance values ​​of the first resistor R1 and the second resistor R2, when the power switch is turned off, the third voltage V3 is greater than the second voltage V2, and the comparator outputs a high level. When the power switch is turned on, the third voltage V3 is less than the second voltage V2, and the comparator outputs a low level.

[0096] The above mentioned Figure 3 In the example, VG1 = 0V, VE1 = +12V, and VG1 is at a low level. If the power switch does not fail, it should be in the off state. At this time, V3 = V1-V R1 , where V R1 is the voltage across the first resistor R1. Since the internal resistance of comparator A is very large, V R1 It is very small compared to the value of V1 and can be ignored. Therefore, V3=V1. When designing, V1>V2 voltage, then V3>V2. The voltage at the non-inverting input terminal of comparator A is greater than the voltage at the inverting input terminal, and the output is a high level. The output voltage Vout of comparator A and the gate drive signal VG1 of the power switch Q1 are ORed with the logic operation, that is, the level signals input at the two input terminals of the OR logic chip are one low and one high, then the output indication signal Vwarn1 is a low level, the main control board detects the low level, and controls the fault flag to remain at 0 in the initial state, that is, the indication signal Vwarn1 is a low level, indicating that the power switch has not failed.

[0097] When the power switch fails and is in the on state, V3=VD+R2 / (R1+R2)×(V1-VD), where VD is the sum of the voltage drop of the unidirectional elements D1, D2, and D3 and the on-state voltage drop of the power switch Q1. The value of VD is very small relative to V1, so V3 is approximately expressed as: V3=resistance value of the second resistor R2 / (resistance value of the first resistor R1+resistance value of the second resistor R2)×V1; at this time, V3<V2, the voltage at the in-phase input terminal of the comparator A is less than the voltage at the inverting input terminal, and the output is a low level; the output voltage Vout of the comparator A performs an exclusive OR logic operation with the gate drive signal VG1 of the power switch Q1, that is, the level signals input to the two input terminals of the exclusive OR logic chip are both low, and the output indication signal Vwarn1 is a high level. The main control board detects the high level and controls the fault flag to switch to 1, that is, the indication signal Vwarn1 is a high level, indicating that the power switch fails.

[0098] Similarly, the power switches Q2 to Q12 also perform shutdown fault self-test according to the above steps and principles.

[0099] S6, after completing the shutdown fault detection of all power switches, enter the conduction fault detection, control the gate drive signals of the power switches Q1~Q12 to be conduction signals, and the main control chip detects the indication signals Vwarn1~Vwarn12 corresponding to each power switch in turn.

[0100] The gate drive signal VG output by the main control chip is +12V or 0V, where +12V is a turn-on signal and 0V is a turn-off signal.

[0101] S7, determine in turn whether each indication signal is a high level or a low level, if it is a high level, execute step S8, if it is a low level, execute step S9.

[0102] S8, determining that a power switch corresponding to the current indication signal fails, blocking the gate drive signal and the control signals of the first circuit breaker and the second circuit breaker.

[0103] S9, after determining that the power switch corresponding to the current indication signal has not failed, return to step S2.

[0104] S10, determining whether the number of fault self-checks reaches a preset value, if yes, executing step S11, if no, returning to step S2.

[0105] S11, exit the fault self-check and enter the ready-to-start mode.

[0106] Taking the power switch Q1 as an example, when controlling Q1 to be turned on, the voltage between the gate and source of the power switch needs to be +12V, that is, at this time, the gate drive signal VG1 is 12V, and the drive signal input to the source S is 0V. Figure 3 As shown in the figure, the detection module inputs the first voltage V1, generates the third voltage V3 after voltage division, and inputs the first input terminal (non-inverting input terminal) of the comparator A. At the same time, the second voltage V2 is input into the first input terminal of the comparator A. By setting the resistance values ​​of the first resistor R1 and the second resistor R2, when the power switch is turned off, the third voltage V3 is greater than the second voltage V2, and the comparator outputs a high level. When the power switch is turned on, the third voltage V3 is less than the second voltage V2, and the comparator outputs a low level.

[0107] The above mentioned Figure 3In the figure, VG1=12V, VE1=0V, and VG1 is at a high level. If the power switch does not fail, it should be in the on state. At this time, V3=VD+resistance of the second resistor R2 / (resistance of the first resistor R1+resistance of the second resistor R2)×(V1-VD), where VD is the sum of the voltage drop of the unidirectional elements D1, D2, and D3 and the on-state voltage drop of the power switch Q1. The value of VD is very small compared to V1, so V3 is approximately expressed as: V3=resistance of the second resistor R2 / (resistance of the first resistor R1+resistance of the second resistor R2)×V1; at this time, V3 <V2, the voltage at the in-phase input terminal of comparator A is less than the voltage at the inverting input terminal, and the output is low level; the output voltage Vout of comparator A is ORed with the gate drive signal VG1 of the power switch Q1, because at this time the level signals inputted at the two input terminals of the OR logic chip are one high and one low, the output indication signal Vwarn1 is low level, the main control board detects the low level, and controls the fault flag to remain at 0 in the initial state, that is, the indication signal Vwarn1 is low level, indicating that the power switch has not failed.

[0108] When the power switch fails and is in the off state, V3 = V1-V R1 , where V R1 is the voltage across the first resistor R1. Since the internal resistance of comparator A is very large, V R1 It is very small compared to the value of V1 and can be ignored. Therefore, V3=V1. When designing, V1>V2 voltage, then V3>V2. The voltage at the non-inverting input terminal of comparator A is greater than the voltage at the inverting input terminal, and the output is high level. The output voltage Vout of comparator A and the gate drive signal VG1 of the power switch Q1 are ORed with the logic operation, that is, the level signals input at the two input terminals of the OR logic chip are both high, then the output indication signal Vwarn1 is high level, the main control board detects the high level, and controls the fault flag to switch to 1, that is, the indication signal Vwarn1 is high level, indicating that the power switch is faulty.

[0109] Similarly, the power switches Q2 to Q12 also perform conduction fault self-test according to the above steps and principles.

[0110] After the shutdown and conduction fault self-tests of all power switches are completed, the whole can be tested again, and the number of tests can be set. When the number of tests reaches the set value, the main control board feedback self-test is completed. If the corresponding indication signal of any power switch is high level during the above self-test process, the drive pulse signal of all power switches is directly blocked, and the K1 and K2 control signals are blocked. At the same time, the fault light is controlled to light up, indicating the location of the faulty power switch. If all modules are normal, the system enters the ready-to-start mode.

[0111] The power switch fault self-detection method of this embodiment detects whether the gate drive signal of the power switch matches its actual on-off state by performing an XOR logic operation on the output signal Vout of the comparator and the gate drive signal of the power switch. The final indication signal is fed back to the main control chip for fault analysis and protection, thereby improving the safety and reliability of the equipment.

[0112] Example 6

[0113] This embodiment provides a frequency converter, including a power switch, and the frequency converter also includes the power switch fault self-detection circuit in the above embodiment, which is used to perform power switch fault self-detection before the frequency converter is put into use, thereby improving the safety and reliability of the entire frequency converter.

[0114] Example 7

[0115] This embodiment provides an air-conditioning device, including the inverter described in Embodiment 6, which is used to improve the safety and reliability of the entire air-conditioning device.

[0116] Example 8

[0117] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the power switch fault self-detection method in the above embodiment.

[0118] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0119] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power switch fault self-detection circuit, applied to a frequency converter, wherein the frequency converter includes a plurality of power switches, characterized in that: The circuit comprises: a plurality of sampling modules and a main control chip; The sampling module is connected to the power switch in a one-to-one correspondence, a first input terminal of which inputs a first voltage, a second input terminal of which inputs a second voltage, a third input terminal of which is connected to the drain of the power switch, and a fourth input terminal of which inputs a gate drive signal of the power switch; the sampling module is used to generate an indication signal according to the on-off state of the power switch and the gate drive signal; wherein the indication signal is used to indicate whether the power switch fails; if the gate drive signal matches the on-off state of the power switch, the generated indication signal is a low-level signal; if the gate drive signal does not match the on-off state of the power switch, the generated indication signal is a high-level signal; wherein the gate drive signal matches the on-off state of the power switch, which means that the gate drive signal is at a high level and the power switch is turned on, or the gate drive signal is at a low level and the power switch is turned off, and in other cases, the gate drive signal does not match the on-off state of the power switch; The main control chip, whose input end is connected to the output end of the sampling module, is used to determine whether the power switch fails according to the indication signal, and to block the gate drive signal when the power switch fails.

2. The circuit according to claim 1, characterized in that The sampling module comprises: A voltage dividing unit, a first end of which is input with the first voltage, and a second end of which is connected with the drain of the power switch; the voltage dividing unit is used to divide the first voltage, generate a third voltage and output it to the comparator; The comparator has a first input terminal connected to the output terminal of the voltage dividing unit and a second input terminal inputting the second voltage, and is configured to output a high level when the third voltage is greater than the second voltage, and output a low level when the third voltage is less than the second voltage; An exclusive-OR logic chip, whose first input terminal is connected to the output terminal of the comparator and whose second input terminal inputs the gate drive signal, is used to output a high-level indication signal when the output signal of the comparator is consistent with the gate drive signal, and output a low-level indication signal when the output signal of the comparator is inconsistent with the gate drive signal.

3. The circuit according to claim 2, characterized in that The voltage dividing unit comprises: A first resistor and a second resistor, the first resistor and the second resistor are connected in series to form a series branch, the first end of the series branch inputs the first voltage, the second end is connected to the drain of the power switch, and the line between the first resistor and the second resistor is connected to the first input end of the comparator.

4. The circuit according to claim 2, characterized in that The sampling module also includes: a third resistor, arranged between the first input terminal of the comparator and the output terminal of the voltage dividing unit, and used for limiting the current of the first input terminal of the comparator; A fourth resistor is arranged at the second input terminal of the comparator, and is used to limit the current of the second input terminal of the comparator.

5. The circuit according to claim 2, characterized in that The sampling module also includes: At least one unidirectional element is connected in series between the second end of the voltage divider unit and the drain of the power switch tube, and is used to control the direction of the current.

6. The circuit according to claim 1, characterized in that The circuit further comprises: A power supply module, whose input end is connected to a power supply, and whose output end is connected to the sampling module, is used to output the first voltage and the second voltage.

7. The circuit according to claim 1, characterized in that The circuit further comprises: The alarm module has an input end connected to the main control chip and is used to be triggered and sound an alarm when a failure occurs in the power switch.

8. The circuit according to claim 1, characterized in that The output end of the main control chip is connected to the first circuit breaker and the second circuit breaker in the inverter, and is used to block the control signal of the first circuit breaker and / or the second circuit breaker.

9. A frequency converter, characterized in that: The frequency converter comprises the power switch fault self-detection circuit according to any one of claims 1 to 8.

10. An air conditioning device, characterized in that: The air conditioning device comprises the inverter according to claim 9.

11. A power switch fault self-detection method, applied to the power switch fault self-detection circuit according to any one of claims 1 to 8, characterized in that: The method comprises: Output a gate drive signal to each power switch in turn to obtain an indication signal of each power switch; wherein the indication signal is generated based on the gate drive signal and the on-off state of the power switch, and is used to indicate whether the power switch fails; if the gate drive signal matches the on-off state of the power switch, the generated indication signal is a low-level signal; if the gate drive signal does not match the on-off state of the power switch, the generated indication signal is a high-level signal; wherein the gate drive signal matches the on-off state of the power switch, which means that the gate drive signal is at a high level and the power switch is turned on, or the gate drive signal is at a low level and the power switch is turned off, and in other cases, the gate drive signal does not match the on-off state of the power switch; It is determined according to the indication signal whether a power switch corresponding to the indication signal fails.

12. The method according to claim 11, characterized in that Determining whether a power switch corresponding to the indication signal fails according to the indication signal includes: If the indication signal is a low level signal, it is determined that the power switch corresponding to the indication signal has not failed; If the indication signal is a high level signal, it is determined that a power switch corresponding to the indication signal fails.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to claim 11 or 12 is implemented.

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