Direct Memory Access Controller

Abstract

The electronic device (1) comprises a processor (2); a peripheral device (3) having a data interface and a data attribute interface; a direct memory access (DMA) controller (6; 7) for the peripheral device (3); a memory (4); a bus system (5) connecting the processor (2), the DMA controller (6; 7) and the memory (4); a data link (8; 10) between the DMA controller (6; 7) and the peripheral device (3); and a data attribute link (9; 11) between the DMA controller (6; 7) and the peripheral device (3), the data attribute link being separate from the data link (8; 10). The DMA controller (6; 7) comprises a data transfer circuit system for transferring data between the memory (4) and the data interface of the peripheral device (3) via the data link (8; 10), and for transferring data attribute information associated with the data between the memory (4) and the data attribute interface of the peripheral device (3) via the data attribute link (9; 11).

Description

Background Art

[0001] The present invention relates to electronic devices and methods including a direct memory access (DMA) controller.

[0002] As is well known, electronic devices such as system-on-chip devices use DMA controllers to transfer data between memory and peripheral devices (e.g., input / output modules, digital-to-analog converters, cryptographic processors, etc.) without requiring the processor to move the data. This can improve performance and / or save power by freeing the processor to perform other tasks or by allowing the processor to enter a low-power sleep state while transferring data. Software executing on the processor can set up a transfer by providing appropriate instructions (e.g., source and / or destination memory addresses) to the DMA controller in advance and then initiating the transfer. Once the transfer is complete, the DMA controller can interrupt the processor.

[0003] In some existing systems, peripheral devices are capable of receiving or outputting different types of data, for example, an encryption and decryption engine can receive key data, initialization vector data, and plain text data, and can output ciphertext data. When data is sent to this peripheral device via a DMA controller, the processor indicates the type or amount of the transferred data by providing data attribute information to the peripheral device, so that the peripheral device knows how to properly process the data. This data attribute information can be provided before or during the data transfer, for example, by the processor writing the information to the data attribute input hardware register of the peripheral device. When the DMA controller is used to transfer data from the peripheral device, the processor again sends the data attribute information to the peripheral device (for example, by writing to the same data attribute input hardware register, or a different register) so that the peripheral device is informed of what type of data to send to the DMA controller the next time the DMA controller requests data from the peripheral device.

[0004] While such systems may provide significant performance improvements over systems without a DMA controller, the inventors have recognized that further performance improvements are possible.

[0005] Therefore, the present invention seeks to provide methods and apparatus that support more efficient direct memory access. Summary of the Invention

[0006] According to a first aspect, the present invention provides an electronic device, comprising:

[0007] processor;

[0008] A peripheral device, the peripheral device comprising a data interface and a data attribute interface;

[0009] a direct memory access (DMA) controller for said peripheral devices;

[0010] Memory;

[0011] a bus system connecting the processor, the DMA controller, and the memory;

[0012] a data link between the DMA controller and the peripheral device; and

[0013] a data attribute link between the DMA controller and the peripheral device, the data attribute link being separate from the data link,

[0014] The DMA controller includes a data transfer circuit system for transferring data between the memory and the data interface of the peripheral device through a data link, and for transferring data attribute information associated with the data between the memory and the data attribute interface of the peripheral device through a data attribute link.

[0015] According to a second aspect, the present invention provides a method for operating an electronic device, the electronic device comprising:

[0016] processor;

[0017] A peripheral device, the peripheral device comprising a data interface and a data attribute interface;

[0018] a direct memory access (DMA) controller for said peripheral devices;

[0019] Memory;

[0020] a bus system connecting the processor, the DMA controller, and the memory;

[0021] a data link between the DMA controller and the peripheral device; and

[0022] a data attribute link between the DMA controller and the peripheral device, the data attribute link being separate from the data link,

[0023] The method comprises:

[0024] transferring data between the memory and the data interface of the peripheral device via the data link; and

[0025] Data attribute information associated with data is transferred between the memory and the data attribute interface of the peripheral device through the data attribute link.

[0026] Thus, it can be seen that according to the present invention, a dedicated data attribute link is provided between the DMA controller and the peripheral device. This allows the DMA controller to send data attribute information to the peripheral device, or receive data attribute information from the peripheral device, without requiring the processor to pass the attribute information to the peripheral device. This allows the processor to perform other tasks longer or to be in a low-power state. By simplifying the synchronization between the processor and the DMA controller, it also makes the device easier to program.

[0027] Particularly advantageously, data attribute links can allow a DMA controller to execute a sequence of two or more data transfers that may have different associated data attributes without involving the processor at any point in the execution of the transfer sequence. This is made possible by data attribute links because it avoids the need to interrupt the processor after each transfer in order for the processor to pass data attribute information for the next transfer in the sequence.

[0028] The device may include multiple peripheral devices. The DMA controller may have corresponding data links and data attribute links with each of the multiple peripheral devices. However, in other embodiments, the DMA controller has data links and data attribute links with only one peripheral device.

[0029] The DMA controller may be a receive DMA controller. The receive DMA controller may include receive data transfer circuitry for extracting data and associated data attribute information from the memory via the bus system; a data attribute interface for transmitting the data attribute information to the peripheral device via a data attribute link; and a data interface for transmitting data to the peripheral device via the data link.

[0030] The DMA controller may be a transmit DMA controller. The transmit DMA controller may include transmit data transfer circuitry for receiving data attribute information from a data attribute interface of a peripheral device via a data attribute link; and for receiving data from a data interface of the peripheral device via the data link. The transmit data transfer circuitry may be further configured to determine an address in a memory based on the received data attribute information; and to write the received data to the determined address in the memory via the bus system.

[0031] A single DMA controller can include both the receive data transfer circuitry and the transmit data transfer circuitry. Alternatively, the peripheral device can be connected to the receive DMA controller and / or a transmit DMA controller separate from the receive DMA controller. Therefore, the device can include the receive DMA controller for the peripheral device and the transmit DMA controller for the peripheral device. The receive DMA controller and the transmit DMA controller can have separate corresponding data links with the peripheral device. They can have separate corresponding data attribute links with the peripheral device. In one group of embodiments, the DMA controller is a receive DMA controller, and the transmit DMA controller has a data link from the peripheral device, but does not have a data attribute link.

[0032] The data interface of the peripheral device may include a data buffer, such as a first-in-first-out (FIFO) buffer. The data attribute interface may be or may include a hardware register. The data link may be a serial link or a parallel link. The data attribute link may be a serial link or a parallel link. The data link is preferably separate from the bus system. Similarly, the data attribute link is preferably separate from the bus system. The data link and the data attribute link are preferably not connected to any components other than the DMA controller and the peripheral device.

[0033] A DMA controller can be a bus master on a bus system.

[0034] The peripheral device may be connected directly to the bus system (e.g., separately from the DMA controller); the peripheral device may be a slave device on the bus system. The peripheral device may be configured to receive configuration data from the processor rather than through the DMA controller. The peripheral device may include a configuration register interface accessible through the bus system, such as the Arm Advanced Peripheral Bus (APB).

[0035] The DMA controller can be configured to extract a work list from the memory. The work list may include one or more of the following items: memory address, data, data length, and data attribute information. The work list may include one or more tuples (representing corresponding work), each tuple including an address, a length value, and a data attribute value or consisting of an address, a length value, and a data attribute value. The work list may occupy a continuous area in the memory. The work list may include an end marker, which may be a predetermined value, such as a zero address value. One or more memory addresses may point to a memory area for data passed to a peripheral device via a data link, or for receiving data passed from a peripheral device via a data link. The memory may store one or more such work lists. The DMA controller may include work list interpretation logic for interpreting (parsing) the work list.

[0036] The DMA controller may include a hardware worklist address register for receiving the address of the worklist. This register may be written by the processor. The DMA controller may be configured to read the worklist from the address in the worklist address register. The DMA controller may include a worklist length register for receiving the length of the worklist; alternatively, the DMA controller may simply continue parsing the worklist until it detects an end marker.

[0037] The receive DMA controller may include work list interpretation logic for sequentially processing a work list that encodes one or more receive jobs. For each consecutive receive job, the receive DMA controller may identify data attribute information and the location of the associated data in the memory from the work list. The receive DMA controller may then transfer the data attribute information to the peripheral device via a data attribute link, and transfer the data to the peripheral device via a data link. These transfers may be sent separately in time (e.g., where the data follows the attribute information), but are preferably sent simultaneously. The same data attribute information may be sent continuously when the data is sent.

[0038] The transfer DMA controller may include work list interpretation logic for sequentially processing a work list (e.g., in an embodiment where data attribute information from a peripheral device is not used), or the transfer DMA controller may include work list interpretation logic for conditionally processing a work list. The work list may contain a corresponding transfer job for each of a set of data attribute values. For each job, the transfer DMA controller may identify data attribute information from the work list and the location in memory to which data with the attribute will be written. The transfer DMA controller may receive data attribute information from the peripheral device via a data attribute link and may select a job from the work list based on the data attribute information (i.e., conditional processing). The transfer DMA controller may write the data it receives from the peripheral device to a memory address determined from the work list (e.g., from the selected job). The memory address may depend on the data attribute information received in association with the data (e.g., simultaneously), or the memory address may depend on the order of a series of jobs in the work list.

[0039] The peripheral device or DMA controller can be configured to generate an interrupt to the processor in response to completing a data transfer. For a receive DMA controller, this may occur upon reaching the end of a receive worklist. For a transmit DMA controller, this may occur once the peripheral device has no more data to output to the transmit DMA controller. In some embodiments, the receive DMA controller does not generate an interrupt upon reaching the end of a worklist, but instead generates an interrupt once the peripheral device has finished transmitting data resulting from the worklist. This allows the processor to continue executing the receive worklist and the corresponding transmit worklist without interruption.

[0040] The data attribute information may be a value from a predetermined set of data attribute values. The peripheral device may be configured to receive a plurality of different types of data and process the data differently depending on its type. The data attribute information may indicate the type.

[0041] One of the data attributes can be a bypass attribute. The peripheral device can be configured not to perform logical processing (i.e., not perform logical operations or calculations whose results depend on the data) of the bypassed data received from the receiving DMA controller, but to simply transmit the same data to the DMA controller, or a separate transmitting DMA controller. In this way, by marking the data as bypassed data in the receive work list, the DMA controller and the peripheral device can function as a memory-to-memory scatter-gather DMA engine for certain data.

[0042] Typically, a DMA controller can modify data and / or data attribute information between how it is stored in memory and how it is received or transmitted by a peripheral device, or how it can be passed on without modification. For example, the DMA controller can encode attribute information differently, or the DMA controller can perform word alignment operations on the data.

[0043] In one set of embodiments, the peripheral device is a hardware cryptographic engine (i.e., a cryptographic processor). The peripheral device can be configured to perform one or more cryptographic operations, such as stream or block cipher operations. In this case, the data attribute information can include a key attribute for use when sending a cryptographic key to the cryptographic engine. The data attribute information can also include a message attribute, or a plaintext attribute, or a ciphertext attribute, for sending message data to the cryptographic engine. The data attribute information can also include an initialization vector (IV) attribute for sending IV data to the cryptographic engine. The data attribute information can also include the aforementioned bypass attribute, which can be particularly useful in certain cryptographic operations that involve processing only portions of an input data block without modifying other portions.

[0044] As described herein, the use of a worklist can enable a cryptographic engine to perform encryption and / or decryption of one or more messages with only a single software register write.Once all cryptographic operation sequences have been completed and the output data has been transferred to memory, the processor can then be interrupted.

[0045] Of course, the cryptographic engine is just one example, and the peripheral device may alternatively be an ADC, a DAC, a digital filter, a PWM, a USB interface, an SPI interface, a UART, a Bluetooth TM Radio, LTE radio, etc.

[0046] Where appropriate, features of any aspect or embodiment described herein may be applied to any other aspect or embodiment described herein.When reference is made to different embodiments or groups of embodiments, it should be understood that these are not necessarily distinct, but may overlap. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Certain preferred embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0048] Figure 1 is a schematic diagram of a system-on-chip device embodying the present invention;

[0049] Figure 2 is a flow chart of operations performed by the second apparatus during a DMA transfer to a peripheral device;

[0050] Figure 3 is a flow chart of operations performed by a second device during a DMA transfer from a peripheral device;

[0051] Figure 4 is a list of data stored in a DMA work list for a system-on-chip device;

[0052] Figure 5 is a table showing peripheral device data stored in the memory of the apparatus;

[0053] Figure 6 is a time graph of data received by a peripheral device on the apparatus via a data link and an attribute link;

[0054] Figure 7 is a schematic diagram of a second system-on-chip device including a hardware encryption and decryption engine embodying the present invention;

[0055] Figure 8 is a schematic mapping between data in the DMA work list and password-related data stored in the memory of the second device;

[0056] Figure 9It is the first instance DMA work list (chain) used to send data to the encryption and decryption engine;

[0057] Figure 10 is a second instance DMA work list (chain) for sending data to the encryption and decryption engine; and

[0058] Figure 11 This is an example DMA work list for receiving data from the encryption and decryption engine. DETAILED DESCRIPTION

[0059] Figure 1 The figure shows a processor 2, such as an Arm TM Cortex TM -M4 system-on-chip device 1. Device 1 also has peripherals 3 and memory 4. Peripherals 3 can be any peripherals, such as input / output, cryptographic processors, DACs, ADCs, radios, etc. Memory 4 can include volatile memory (e.g., SRAM) and / or non-volatile memory (e.g., flash memory). Memory 4 can store software instructions executed by MCU 2 as well as permanent and transient data. Device 1 has an on-chip bus system 5 that supports memory-mapped peripheral access. Bus system 5 can be an Arm TM AMBA TM Bus system; it may include one or more AHBs (Advanced High Performance Buses) and / or one or more APBs (Advanced Peripheral Buses). Of course, the apparatus 1 may have other peripherals, other processors, and any other typical footprints not shown here, such as an interrupt controller, etc.

[0060] The peripheral device 3 is connected to the bus system 5 via a receive (Rx) DMA controller 6 and a transmit (Tx) DMA controller 7. These DMA controllers 6, 7 are both bus masters on the bus system 5 and implement direct memory access data transfer between the peripheral device 3 and the memory 4. In some embodiments, they can also facilitate peripheral-to-peripheral communication. The peripheral device 3 may have further connections (not shown) to the bus system 5, for example, to allow the processor 2 to write to and / or read from the register interface of the peripheral device 3.

[0061] The receive (Rx) DMA controller 6 is connected to the peripheral device 3 via a receive data link 8 for sending data to the peripheral device 3 and a receive data attribute link 9 for sending data attribute information to the peripheral device 3 .

[0062] The transmit (Rx) DMA controller 7 is connected to the peripheral device 3 through a transmit data link 10 for transmitting data to the peripheral device 3 and a transmit data attribute link 11 for transmitting data attribute information to the peripheral device 3 .

[0063] Each of these links 8, 9, 10, 11 is composed of one or more wires. In some embodiments, each of the data links 8, 10 is composed of 32 parallel wires, while each of the data attribute links 9, 11 is composed of eight parallel wires. The data attribute links 9, 11 are different from the data links 8, 10.

[0064] The DMA controllers 6, 7 can provide DMA access to multiple peripheral devices. However, in this embodiment, the DMA controllers 6, 7 only serve one peripheral device 3; any other peripheral device requiring DMA access will have its own corresponding receive and / or transmit DMA controller.

[0065] Interrupt channels 12 allow peripheral devices 3 and DMA controllers 6, 7 to issue interrupts to the processor 2. These may travel along one or more straight lines to the processor 2, or via a programmable interrupt controller (not shown).

[0066] The peripheral device 3 is capable of receiving and / or outputting various types of data.

[0067] How the peripheral device 3 processes incoming data received via receive data link 8 depends on the associated data attribute information it receives via data attribute link 9. The correlation between the data attribute information and the data may be indicated temporally, for example, by the DMA controller 6 continuously maintaining the data attribute 9 link at a particular value representing a particular attribute while simultaneously transmitting data having said attribute on data link 8.

[0068] Similarly, peripheral device 3 can communicate attributes associated with the data it outputs on transmit data link 10 by asserting a specific value on transmit attribute link 11 when outputting the data. Alternatively, the attribute information can be sent immediately before the data or using some other time connection to convey the correlation between the data and the data attribute information. How apparatus 1 responds to the data output from peripheral device 3 can depend on the associated data attribute information sent by peripheral device 3 over transmit data attribute link 11 (although this is not always the case; for example, sometimes software executing on processor 2 may ignore the output attribute information if it already knows what type of data to expect from the context).

[0069] In use, software code stored in the memory 4 is executed by the processor 2. In addition, the code may contain instructions for initiating data transfers between the memory 4 and peripheral devices via the DMA controllers 6, 7. Once the code has set the appropriate instructions, the DMA controllers 6, 7 can then carry out the complex transfer sequence without further involvement of the processor 2 until the transfer is complete.

[0070] Figure 2 The main steps performed by the apparatus 1 when transferring data from the memory 4 to the peripheral device 3 using the receive DMA controller 6 are outlined.

[0071] In a first step 21 , the processor 2 writes data to be sent to the peripheral device 3 to the memory 4 .

[0072] In a second step 22, the processor 2 writes a DMA receive work list (also referred to herein as a DMA chain) to an address in the memory 4. This DMA receive work list is a set of instructions for the receive DMA controller 6 and contains information about the location of the data in the memory 4 and attribute information associated with the data, thereby specifying the type of data stored. The format of the DMA receive work list is explained in more detail below.

[0073] In a third step 23 , the processor 2 initiates a DMA transfer to the peripheral device 3 by writing the start address of the DMA receive work list to an input register of the receive DMA controller 6 .

[0074] In a fourth step 24, such writing of the start address triggers the receive DMA controller 6 to start reading the DMA receive work list from the memory 4 and follow the instructions contained in the DMA work list to perform one or more required memory transfer operations, read data from the memory 4 and send the instructions over the data.

[0075] In a fifth step 25, the receive DMA controller 6 determines that it has reached the end of the DMA receive work list and, in response, generates an interrupt to the processor via the interrupt channel 12. In some cases, this step may be omitted, for example, if it is not necessary to interrupt the processor 2 before the peripheral device 3 has processed the received data and perhaps provided some output via the receive DMA controller 6.

[0076] Figure 3 The main steps performed by the apparatus 1 when transferring data from the peripheral device 3 to the memory 4 using the transfer DMA controller 7 are outlined.

[0077] In a first step 31, the processor 2 writes a DMA transfer work list to an address in the memory 4. This DMA transfer work list is a set of instructions for the transfer DMA controller 7. The instruction set contains information about the locations in the memory 4 where the transfer DMA controller 7 should write data with different properties, which the DMA controller 7 receives from the peripheral device 3. The format of the DMA work list is explained in more detail below.

[0078] In a second step 32 , the processor 2 initiates a DMA transfer from the peripheral device 3 by writing the start address of the DMA transfer work list into an input register of the transfer DMA controller 7 .

[0079] In a third step 33, this writing of the start address triggers the transfer DMA controller 7 to read the DMA transfer work list from the memory 4 and start receiving data and data attribute information from the peripheral device 3. The transfer DMA controller 7 uses the transfer work list to determine the location in the memory 4 to write the received data based on the attribute information output by the peripheral device 3.

[0080] In a fourth step 34 , the peripheral device 3 determines that it has finished outputting data, or the transmit DMA controller 7 determines that it has received the required amount of data, and the peripheral device 3 or transmit DMA controller 7 generates an interrupt to the processor via the interrupt channel 12 .

[0081] In an optional fifth step 35 , the processor 2 reads some or all of the output data from the memory 4 .

[0082] Figure 4 An example transmit or receive work list (DMA chain) that can be stored in memory 4 is shown. This example includes four separate transfer instructions for four different data types. The work list begins with the first transfer 41 (Data 1). This specifies the "Data 1 Location" field, which contains the 32-bit address in memory 4 from which data will be read or written. This is followed by an 8-bit "Data 1 Attribute" field, which contains an 8-bit value representing the data type in the DMA transfer from a set of predetermined attribute values. This is followed by a 24-bit "Data 1 Length" field, which contains a 24-bit value, expressed as a number of 32-bit words, equal to the length of the data to be read from or written to the Data 1 location. This is followed by the same three fields for the second transfer 42 (Data 2), the third transfer 43 (Data 3), and the fourth transfer 44 (Data 4). Individual DMA transfers are combined into a DMA work list by sequentially storing them in memory. Finally, the work list contains a predetermined end marker value 45 (e.g., 32 zero bits, rather than another Location field) indicating the end of the work list. Of course, this is merely an example, and other embodiments may use alternative data formats and values.

[0083] Figure 5 Shown corresponding to Figure 4 An example of the data structure in the memory 4 of the work list. It should be noted that in this embodiment, the address value refers to the corresponding 8-bit block, but the data is stored as a 32-bit word. Figure 2In the flowchart of , when the peripheral device 3 is receiving data, this structure will be propagated along with the data by the processor 2 (see first step 21). Figure 3 In the flowchart of , when the peripheral device 3 is transferring data, this structure will initially be empty, and the processor 2 simply allocates a suitable empty area of memory; the structure will be filled with data by the transfer DMA controller 7 (see third step 33).

[0084] Figure 6 Show when processing Figure 4 Work list to send to peripheral device 3 Figure 5 When the data in the data structure is Figure 2 At the fourth step 24 of FIG, the receive DMA controller 6 performs transfers over the receive data link 8 and the receive data attribute link 9 over time. First, the receive DMA controller 6 sends an 8-bit "Data 1 Attribute" value over the receive data attribute link 9 and continues to assert this value for the duration of the associated data output. At the same time, the receive DMA controller sends a "Data 1 Length" quantity of 32-bit words starting from the "Data 1 Location" in the memory 4 over the data link 8. Once all Data 1 words have been sent, the receive DMA controller 6 changes the value on the receive data attribute link 9 to "Data 2 Attribute" and begins sending data from the "Data 2 Location". This process repeats until all four data transfers (Data 1 to Data 4) have been completed. When the interpretation logic in the DMA controller 6 recognizes the end marker value 45, the DMA controller ceases activity on the data link 8 and the data attribute link 9. In some embodiments, this triggers an interrupt on the processor 2. The peripheral device 3 processes each of the four data transfers according to the associated data attribute value.

[0085] Transfers from peripheral devices to the transfer DMA controller 7 follow a similar pattern, but do not necessarily follow the same schedule as the work list or Figure 5 Alternatively, in some embodiments, the transmit DMA controller 7 includes conditional processing logic for performing conditional processing on data received via the transmit data link 10 based on attribute values simultaneously received via the transmit data attribute link 11. The logic detects the attribute information and determines the corresponding memory address from the transmit work list. Thus, the transmit work list effectively acts as a switch statement (select statement).

[0086] However, in other embodiments, the peripheral device 3 may output different types of data in a determined order, and the transmit DMA controller 7 may process the work list sequentially, thereby writing consecutive amounts of data equal to the "length" value in the work list to the corresponding "location" addresses in the memory 4. In such cases, any data attribute information output by the peripheral device 3 may be ignored, or there may not even be any transmit data attribute link 11.

[0087] Figure 7 An exemplary embodiment of a system-on-chip device 1' is shown, which has a Figure 1 The device has all the same features as the device 1 (wherein identical features are referenced with the same reference numerals), but wherein the peripheral device is a hardware encryption and decryption engine 3' for encrypting or decrypting data, for example using a stream cipher (eg AES or SNOW 3G).

[0088] In this embodiment, the Rx DMA controller 6' and the Tx DMA controller 7' are shown as components of the cryptographic engine 3' itself, in addition to the cryptographic core 70. This simply indicates that in this case, the DMA controllers 6', 7' only serve the cryptographic engine 3' and not any other peripheral devices.

[0089] The memory 4' (e.g., SRAM) stores a receive (Rx) work list 71 and receive (Rx) data 72 to be received by the encryption / decryption engine 3'. The Rx data 72 includes key data, initialization vector (IV) data, and plaintext data to be encrypted using the key data and IV data. The Rx data can contain multiple data types of each type, used to perform multiple consecutive encryption operations for different plaintext inputs. The Rx work list 73 includes the memory address and length of the key data, IV data, and plaintext data. The Rx work list also includes corresponding attribute information representing the "key" data type, the "IV" data type, and the "plaintext" data type, respectively. The Rx work list 71 and Rx data 72 have been written to the memory 4' by software executed on the processor 2'.

[0090] The processor 2' has also written the corresponding transmission (Tx) work list 73 into the memory 4', and has also reserved an initially empty transmission (Tx) data area 74 for receiving the ciphertext to be output by the encryption / decryption engine 3'.

[0091] The memory 4' and the processor 2' are connected to the encryption engine 3' via an AHB 5'a. The encryption engine 3' may also be connected to an APB 5'b, which may be used to access the register interface on the encryption engine 3'. Specifically, the Rx DMA controller 6' has an Rx work list address register 75 for receiving the address of the Rx work list 71; the Tx DMA controller 7' has a Tx work list address register 76 for receiving the address of the Tx work list 73; and the cryptographic core 70 may have a set of control registers 77, for example, for receiving configuration settings from the processor 2', such as which cryptographic algorithm to execute or which block cipher operation mode to use (ECB, CBC, etc.). The cryptographic core 70 also includes a receive buffer (Rx FIFO) 78 for receiving incoming data from the Rx DMA controller 6'; a cryptographic finite state machine (FSM) 79 for performing one or more cryptographic operations; and a transmit buffer (Tx FIFO) 80 for buffering outgoing data before it travels to the Tx DMA controller 7' over the transmit data link 10'.

[0092] Still Figure 7 8 , a stall link 81 is shown between the Rx DMA controller 6 ′ and the cryptographic core 70 , by which the cryptographic core 70 can stall the transfer of incoming data over the receive data link 8 ′, for example when the RxFIFO 78 is full.

[0093] In this particular embodiment, there is no transmit data attribute link from the cryptographic core 70 to the Tx DMA controller 7' because the core 70 only continuously outputs one type of data, ciphertext (or plaintext when performing a decryption operation).

[0094] The cipher block 70 requires three types of data to run the cryptographic algorithm: a key, an IV, and stream / message data. An optional bypass type is also supported for data that does not need to be encrypted but simply passes through the unchanged cipher core 70. This bypass type allows the encryption / decryption engine 3' to function as a general-purpose memory-to-memory scatter / gather DMA engine.

[0095] In use, after creating the data structure in memory 4', processor 2' writes the address of Rx Work List 71 to Rx Work List Address Register 75, and writes the address of Rx Work List 73 to Tx Work List Address Register 76. Software may also use APB connection 5'b to write to configuration register 77 before a DMA work list is started, for example to select a cryptographic algorithm or mode.

[0096] Writing the worklist address triggers the RxDMA controller 6' and TxDMA controller 7' to begin transferring data to and from the (respective) cryptographic core 70. Alternatively, a write to the start register in the control registers 77 of the cryptographic core 70 can initiate the transfer operation, for example by causing the cryptographic core 70 to deassert the stall link 81. Initially, there is no data output from the cryptographic core 70 to the Tx DMA controller 7', and the initial bytes of plaintext are processed through the Rx FIFO 78 and the cryptographic FSM 79, but after a while, data may flow both into and out of the cryptographic core 70. Once the cryptographic core 70 detects that there is no more incoming data from the Rx DMA controller 6', it generates an interrupt to the processor 2' via the interrupt line 12'. Alternatively, the cryptographic core can send an end signal to the Tx DMA controller 7', which can generate an interrupt. In this way, the processor 2' can remain dormant or perform other tasks throughout the processing of the cryptographic worklist, which may include multiple encryption and / or decryption operations and / or memory-to-memory data moves, potentially involving multiple different keys and IV data. As before, the working lists 71, 73 are read sequentially until the null pointer 45' is read indicating the end of the DMA chain.

[0097] Of course, this architecture applies to all kinds of encryption algorithms.

[0098] Figure 8 An example receiving work list 71 is shown. It is similar to Figure 4 , but with three different data locations 81, 82, and 83 instead of four. These could be the address 81 of a 64-bit key, the address 82 of a 32-bit IV, and the address 83 of a 32-bit message (e.g., for input to an RC5 encryption operation), with the actual data 72 located at the indicated addresses. These location values 81, 82, and 83 are accompanied by length and attribute values, and are followed by an end marker 45'. Together, these constitute the Rx work list 4'.

[0099] Figure 9 、 10 and 11 provide for use Figure 7 The encryption and decryption device 1 ′ performs three further instances of the reception and transmission work list of operations.

[0100] Figure 9 A received job list containing several key+IV pairs is shown. As previously mentioned, each job description ("jobdesc") is a tuple of address, length, and data attributes. The values X1-X4 indicate the number of repetitions of the set of job descriptions within the indicated brackets. The data following the key+IV pair is encrypted and decrypted using that key+IV pair.

[0101] The receive (input) work list shown here also contains data that bypasses the cryptographic FSM 79, i.e., the data is simply copied from the receive data link 8' to the transmit data link 10' and remains unchanged. This bypass data descriptor can be located before the first key descriptor or immediately before the end of the work list marker. The processor indicates that the data intended for bypass is written to the "bypass" data attribute value in the work description tuple. This bypass facility can be used for certain cryptographic operations.

[0102] Figure 10 A receive worklist is shown that only memory-to-memory transfers are performed without performing any encryption or decryption operations.

[0103] Figure 11 The transmit work list is shown as consisting of one or more tuples of memory address, data length, and attributes. However, in this case, the data attributes can be empty because the cryptographic core 3' does not output data attribute information, so the TxDMA controller 7' ignores this. It should be noted that the TxDMA controller 7' does not care whether the data output from the cryptographic core 70 has been encrypted or decrypted, or whether the data has bypassed the cryptographic FSM 79.

[0104] Assuming that the cryptographic core 70 implements a cipher stream or block operation that outputs the same number of data blocks as it receives as input, the sum of the data lengths in the transmit work list will typically be equal to the sum of the cipher and bypass data lengths in the corresponding receive work list (but excluding key data and IV data).

[0105] Those skilled in the art will appreciate that the present invention has been described by way of one or more specific embodiments thereof, but that the invention is not limited to these embodiments; many variations and modifications are possible within the scope of the appended claims.

Claims

1. An electronic device, comprising: processor; A peripheral device, the peripheral device comprising a data interface and a data attribute interface; a direct memory access (DMA) controller for said peripheral device; Memory; a bus system connecting the processor, the DMA controller, and the memory; a data link between the DMA controller and the peripheral device; as well as a data attribute link between the DMA controller and the peripheral device, the data attribute link being separate from the data link, wherein the data link and the data attribute link connect the DMA controller to the same peripheral device, wherein the peripheral device is configured to receive a plurality of different types of data and process the data differently depending on the type of the data; The DMA controller includes a data transfer circuit system for transferring data between the memory and the data interface of the peripheral device through the data link, and for transferring data attribute information associated with the data and indicating the type of the data between the memory and the data attribute interface of the peripheral device through the data attribute link.

2. The electronic device of claim 1 , wherein the DMA controller includes receive data transfer circuitry for: extracting data and associated data attribute information from the memory via the bus system; sending the data attribute information to the data attribute interface of the peripheral device via the data attribute link; and The data is sent to the data interface of the peripheral device via the data link.

3. The electronic device of claim 1 or 2, wherein the DMA controller comprises a transmit data transfer circuit system for: receiving data attribute information from the data attribute interface of the peripheral device via the data attribute link; receiving data from the data interface of the peripheral device via the data link; determining an address in the memory according to the received data attribute information; as well as The received data is written to the determined address in the memory via the bus system. 4 . The electronic device according to claim 1 , wherein the data link and the data attribute link are separate from the bus system. The electronic device according to claim 1 , wherein the data attribute interface comprises a hardware register. 6 . The electronic device according to claim 1 , wherein the data interface of the peripheral device comprises a first-in-first-out (FIFO) buffer. 7 . The electronic device according to claim 1 , wherein the data link and the data attribute link are not connected to any component other than the DMA controller and the peripheral device.

8. The electronic device of claim 1 or 2, wherein the peripheral device comprises a direct connection to the bus system separate from the DMA controller, for receiving configuration data from the processor via the direct connection.

9. An electronic device according to claim 1 or 2, wherein the DMA controller is configured to extract a work list from the memory, the work list including one or more of the following items: memory address, data, data length and the data attribute information, and wherein the DMA controller includes a work list interpretation logic for interpreting the extracted work list.

10. The electronic device of claim 9, wherein the work list interpretation logic is configured to interpret a work list comprising a plurality of work tuples, each work tuple comprising or consisting of the following items: The corresponding memory address, the corresponding length value, and the corresponding data attribute value.

11. An electronic device according to claim 9, wherein the DMA controller includes a hardware work list address register writable by the processor for receiving an address of a work list, and wherein the DMA controller is configured to read the work list from the address in the work list address register and input the work list to the work list interpretation logic.

12. The electronic device of claim 9 , wherein the DMA controller comprises work list interpretation logic for sequentially processing a work list, the work list encoding one or more receive jobs, wherein for each consecutive receive job, the DMA controller is configured to: identifying data attribute information from the work list and a location of associated data in the memory; transmitting the data attribute information to the peripheral device via the data attribute link; The associated data is communicated to the peripheral device via the data link.

13. The electronic device of claim 9 , wherein the DMA controller comprises work list interpretation logic for sequentially processing a work list, the work list encoding one or more transfer jobs, wherein the DMA controller is configured to: receiving data attribute information from the peripheral device via the data attribute link; selecting a task from the task list according to the received data attribute information; identifying, from the selected task, a memory address to which data received from the peripheral device is to be written; as well as Data transferred by the peripheral device to the DMA controller is written to the identified memory address.

14. The electronic device of claim 1 or 2, wherein the DMA controller or the peripheral device is configured to generate an interrupt to the processor in response to completing the transfer of data.

15. The electronic device according to claim 1 or 2, wherein the peripheral device being a hardware cryptographic engine configured to perform cryptographic operations, The peripheral device is configured to receive data attribute information representing a cryptographic key attribute from the DMA controller, and receive data including a cryptographic key from the DMA controller; and The peripheral device is configured to receive data attribute information indicating attributes of a message from the DMA controller, and receive data including a message from the DMA controller and input the received data to the cryptographic operation.

16. The electronic device according to claim 1 or 2, wherein: The peripheral device is a hardware cryptographic engine configured to perform cryptographic operations; and The data attribute information includes key attributes for use when sending a cryptographic key to the cryptographic engine.

17. The electronic device according to claim 1 or 2, wherein: The data link is a receiving data link; The data attribute link is a receiving data attribute link; The DMA controller is a receive DMA controller, including a receive data transfer circuit system for: extracting data and associated data attribute information from the memory via the bus system; sending the data attribute information to the data attribute interface of the peripheral device via the receive data attribute link; as well as sending data to the data interface of the peripheral device via the receive data link; as well as The electronic device further comprises: Transfer DMA controller; as well as a transfer data link between the transfer DMA controller and a transfer data interface of the peripheral device, and The transmission DMA controller includes a transmission data transfer circuit system for: receiving transmission data from the transmission data interface of the peripheral device through the transmission data link; and The received transmission data is written to an address in the memory via the bus system.

18. An electronic device according to claim 17, wherein the associated data attribute information is a value from a set of predetermined data attribute values, one of the data attribute values is a bypass attribute value, and wherein the peripheral device is configured to not perform logical processing on data received from the receiving DMA controller when the associated data attribute information has the bypass attribute value, but is configured to transmit data to the transmitting DMA controller through the transmitting data link.

19. The electronic device of claim 17 , further comprising a transfer data attribute link between the transfer DMA controller and the peripheral device, the transfer data attribute link being separate from the transfer data link, wherein the transfer DMA controller further comprises a transfer data transfer circuit system for: receiving transmission data attribute information from a transmission data attribute interface of the peripheral device via the transmission data attribute link; determining an address in the memory according to the received transmission data attribute information; and The received transmission data is written to the determined address in the memory via the bus system.

20. A method of operating an electronic device, the electronic device comprising: processor; A peripheral device, the peripheral device comprising a data interface and a data attribute interface; a direct memory access (DMA) controller for said peripheral device; Memory; a bus system connecting the processor, the DMA controller, and the memory; a data link between the DMA controller and the peripheral device; as well as a data attribute link between the DMA controller and the peripheral device, the data attribute link being separate from the data link, wherein the data link and the data attribute link connect the DMA controller to the same peripheral device, wherein the peripheral device is configured to receive a plurality of different types of data and process the data differently depending on the type of data; The method comprises: transferring data between the memory and the data interface of the peripheral device via the data link; and Data attribute information associated with data and indicating the type of data is transferred between the memory and the data attribute interface of the peripheral device through the data attribute link.

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