Variable node processing method and device for non-binary code message passing decoding

Abstract

An embodiment of the present invention provides a variable node processing unit (31) for a non-binary error correction code decoder, the variable node processing unit (31) being configured to: receive a check node message and an inherent reliability metric, and generate a variable node message based on auxiliary components derived from the check node message and the inherent reliability metric, the inherent reliability metric being derived from a received signal, the auxiliary components comprising auxiliary symbols and auxiliary reliability metrics associated with the auxiliary symbols, wherein the variable node processing unit (31) comprises: a sorting and redundancy elimination unit (313), which is configured to iteratively process the auxiliary components and determine the components of the variable node message by the following operations: iteratively sorting the auxiliary components according to a given order of the auxiliary reliability metrics, and retaining a predefined number of auxiliary components including the most reliable and all mutually different auxiliary symbols.

Description

Technical Field

[0001] The present invention relates generally to digital communications and, more particularly, to methods and apparatus for decoding signals encoded using non-binary error correction codes. Background Art

[0002] Error correction codes are implemented in various data processing systems and devices for ensuring that data is protected from errors introduced during data transmission or storage in the presence of noise and / or interference. Encoding involves adding redundant data to the original data, which enables detection and / or correction of errors.

[0003] Error correction codes are implemented in a variety of devices and systems for applications such as data communication and / or storage. Exemplary applications include, for example, voice and multimedia transmission in wireless ad-hoc networks (e.g., standardized with Wi-Fi™ 802.11), in radio communication systems (e.g., with 3G, 4G / LTE, 5G, etc.), in optical communication systems, and in digital video broadcasting (e.g., standardized with DVB-C2, DVB-S2X, and DVB-T2).

[0004] Linear error correction codes are advantageous given that they require less implementation complexity than nonlinear error correction codes.Exemplary linear error correction codes include convolutional codes and linear block codes such as Hamming codes, Reed-Solomon codes, Turbo codes, Polar codes, and low-density parity-check (LDPC) codes.

[0005] In particular, LDPC codes are very efficient. The performance of non-binary LDPC codes has been shown to be close to the Shannon limit; they provide high transmission rates close to the maximum amount of information that can be transmitted on the transmission channel. Non-binary LDPC codes are very efficient in providing high spectral efficiency coding and perform better than binary LDPC codes. However, in order to achieve such gains, it is required to develop low-complexity decoding algorithms for non-binary codes, especially for high spectral efficiency communications.

[0006] Decoding of signals encoded using linear block codes in general, and LDPC codes in particular, can be performed using an iterative message passing algorithm.

[0007] Exemplary decoding algorithms for non-binary codes (e.g., non-binary LDPC codes) include:

[0008] - the "q-array sum-product" algorithm disclosed, for example, in "L. Barnault and D. Declercq, Fast decoding algorithm for LDPC over GF(q), In Proceedings of IEEE Information Theory Workshop, pp. 70–73, April 2003";

[0009] - the "min-max" algorithm disclosed, for example, in "V. Savin, Min-max decoding for non-binary LDPC codes, In Proceedings of IEEE International Symposium on Information Theory, pp. 960–964, July 2008";

[0010] - For example, the "Extended Minimum-Maximum" (EMS) algorithm disclosed in "D. Declercq and M. Fossorier, Decoding algorithms for non-binary LDPC codes over GF, IEEE Transactions on Communications, Vol. 55, No. 4, pp. 633-643, April 2007", and

[0011] - “Trellis EMS Decoder” (T-EMS) disclosed in “J. O. Lacruz, F. García-Herrero, J. Valls, and D. Declercq, One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes, in IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 62, No. 1, pp. 177-184, January 2015” and “E. Li, F. García-Herrero, D. Declercq, K. Gunnam, J. O. Lacruz, and J. Valls, “Low latency T-EMS decoder for non-binary LDPC codes”, 2013 Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, 2013, pp. 831-835”.

[0012] The EMS algorithm is based on logarithmic scale calculations to reduce computational complexity by transforming product operations into simple summation operations. Compared with other existing iterative decoding algorithms, the EMS algorithm provides a good compromise between hardware complexity and communication performance. Nevertheless, the EMS algorithm still requires a large amount of computing and storage resources, which may not be available in actual devices or systems, such as in real-time applications or in systems that require high throughput and significantly reduced latency.

[0013] The message passing algorithm is based on exchanging messages representing coded data between a check node processing unit and a variable node processing unit associated with a graphical representation of the code used. The decoding process includes: variable node updates performed by calculating variable node messages, check node updates performed by calculating check node messages, and codeword decisions. Each check node and variable node message may include one or more components, a component including a symbol and a reliability metric associated with the symbol. At the beginning of the decoding process, the variable node message sent to the check node processing unit may include an inherent message, the inherent message including an inherent reliability metric and an inherent symbol. The inherent reliability metric is calculated only based on the channel output / observation. Therefore, the term "inherent" means that the inherent reliability metric depends only on the (transmission) channel. Each symbol associated with the inherent reliability metric is called an inherent symbol.

[0014] The greatest computational complexity involved during the decoding process using the EMS algorithm stems from the calculations performed at the check node processing units and the variable node processing units.

[0015] Most existing works on non-binary error correction code decoding architectures focus on processing at check nodes rather than at variable nodes. Few works in the literature are devoted to processing performed at variable node processing units.

[0016] The processing at the variable node processing unit includes three main steps: generating an inherent reliability metric based on the received signal, calculating the variable node message based on the inherent reliability metric and the check node message received by the variable node processing unit, and calculating the local decision. The step of calculating the variable node message includes an intermediate step, which includes calculating a component called "auxiliary component" based on the inherent reliability metric and the check node message. The auxiliary component is an intermediate component of the components used to generate the variable node message. Therefore, the components of the variable node message are determined by extracting the components including different and most reliable symbols among the auxiliary components. To this end, the step of calculating the variable node message involves a sorting sub-step and a redundancy elimination sub-step. The sorting implementation sorts the auxiliary components according to a given order of the reliability metrics included therein. Redundancy elimination implements the removal of redundancy and retains the components including different and most reliable symbols among the sorted auxiliary components. This architecture of variable node processing is described in detail in particular in the following documents:

[0017] - CLLin, SW Tu, CLChen, HCChang, and CY Lee, “An Efficient Decoder Architecture for non-binary LDPC Codes with Extended Min-Sum Algorithm,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 9, pp. 863–867, September 2016.

[0018] -E. Boutillon, L. Conde-Canencia, and AAG Houwayel, “Design of a GF(64)-LDPC decoder based on the EMS algorithm,” IEEE Transactions on Circuits and Systems I: Regular Papers, Volume 60, Issue 10, Pages 2644–2656, October 2013.

[0019] In existing variable node architectures, the sorting and redundancy elimination sub-steps are performed sequentially in a separate manner, which requires a large amount of memory and computing power, which may be unaffordable, especially in the case of decoding error correction codes built on high-order algebraic structures. Existing variable node architectures are complex, and improvements are still required to reduce the complexity of variable node message calculations. Therefore, there is a need for low-complexity and low-latency variable node processing techniques. Summary of the invention

[0020] To address these and other problems, a low complexity and low latency variable node processing unit implemented in a non-binary error correction code decoder is provided. The variable node is configured to receive a check node message and an inherent reliability metric derived from a received signal, and generate a variable node message based on an auxiliary component derived from a check node message and the inherent reliability metric, the auxiliary component including an auxiliary symbol and an auxiliary reliability metric associated with the auxiliary symbol. The variable node processing unit includes:

[0021] - a sorting and redundancy elimination unit configured to iteratively process the auxiliary components and determine the components of the variable node message by iteratively sorting the auxiliary components according to a given order of the auxiliary reliability metrics and retaining a predefined number of auxiliary components including the most reliable and all mutually different auxiliary symbols.

[0022] According to some embodiments, the variable node processing unit includes a computing unit configured to determine a first auxiliary message based on a check node message and an inherent reliability metric, and to determine a second auxiliary message based on the inherent reliability metric, wherein the inherent reliability metric is associated with a predefined number of most reliable inherent symbols and a reference reliability metric, and the auxiliary component is extracted from the first auxiliary message or the second auxiliary message.

[0023] According to some embodiments, the check node message comprises a check node component, each check node component comprising a symbol and a reliability metric associated with the symbol. In such an embodiment, the computing unit may be configured to:

[0024] - determining an auxiliary symbol included in the first auxiliary message according to a symbol included in the check node message, the auxiliary symbol being selected from the symbols included in the check node component, and

[0025] - determining each auxiliary reliability metric associated with an auxiliary symbol included in the first auxiliary message by applying an addition operation on a predefined algebraic structure, the addition operation being applied in association with the selected auxiliary symbol to the intrinsic reliability metric associated with said auxiliary symbol and to the reliability metric included in the check node component.

[0026] According to some embodiments, the variable node processing unit is further configured to: receive a reference reliability metric determined in a non-binary error correction code decoder based on an offset value and a check node component including the least reliable symbol. In such an embodiment, the calculation unit may be configured to:

[0027] - determining, from a predefined number of most reliable intrinsic symbols associated with the lowest or highest intrinsic reliability measure, an auxiliary symbol to be included in the second assistance message, the auxiliary symbol being equal to an intrinsic symbol among the most reliable intrinsic symbols; and

[0028] - determining an auxiliary reliability metric associated with an auxiliary symbol included in the second auxiliary message by applying an addition operation on a predefined algebraic structure, the addition operation being applied to the reference reliability metric and to the intrinsic reliability metric associated with an intrinsic symbol equal to the auxiliary symbol.

[0029] According to some embodiments, the predefined algebraic structure is selected from the group consisting of a field of real numbers, a field of integers, and a field of natural numbers.

[0030] According to some embodiments, the offset value is determined in the non-binary error correction code decoder according to a predefined decoding performance criterion.

[0031] According to some embodiments, the variable node processing unit is configured to: exchange variable node messages and check node messages with at least one check node processing unit during multiple iterations, the offset value is determined in the non-binary error correction code decoder depending on the number of iterations, and different offset values ​​are dynamically determined in each of the iterations.

[0032] According to some embodiments, the sorting and redundancy elimination unit comprises:

[0033] - Multiple multiplexers;

[0034] -a plurality of reliability metric comparators; and

[0035] - Multiple sign comparators;

[0036] Each multiplexer is associated with a reliability metric comparator and a symbol comparator, and each multiplexer is configured to: determine the current candidate component at each iteration depending on the comparison performed by multiple symbol comparators and multiple reliability metric comparators, and the sorting and redundancy elimination unit is configured to generate variable node components based on candidate components including the most reliable and all different symbols after processing all auxiliary components included in the first and second auxiliary messages.

[0037] According to some embodiments, the candidate components include candidate symbols and candidate reliability metrics associated with the candidate symbols. Each multiplexer may be configured to: receive at each iteration at least an auxiliary component extracted from the first or second auxiliary message and a predefined initialization component, the predefined initialization component including an initialization symbol and an initialization reliability metric associated with the initialization symbol. In such an embodiment, each multiplexer may be configured to determine at each iteration a current candidate component by selecting a component from among: at least the auxiliary component, the predefined initialization component, and a component corresponding to a candidate component determined by the multiplexer at a previous iteration; and:

[0038] - a reliability metric comparator associated with each multiplexer may be configured to perform a comparison between the auxiliary reliability metric comprised in the at least auxiliary component and a candidate reliability metric comprised in the candidate component determined by each multiplexer at a previous iteration, and

[0039] - A symbol comparator associated to each multiplexer may be configured to check redundancy of symbols by performing a comparison between auxiliary symbols comprised in at least the auxiliary component and candidate symbols comprised in the candidate component determined by said each multiplexer at a previous iteration.

[0040] According to some embodiments, at each iteration, each multiplexer 315-j may be configured to:

[0041] - Perform a retain action by setting the current candidate component equal to the candidate component determined at the previous iteration:

[0042] * if it is determined that at least the auxiliary symbol included in the auxiliary component is not redundant, there is no any of the candidate components determined at the previous iteration, and it is determined that at least the auxiliary symbol included in the auxiliary component is less reliable than the symbol included in the candidate component determined by the multiplexer 315-j at the previous iteration; or

[0043] * if it is determined that at least an auxiliary symbol included in the auxiliary component is redundant, wherein at least one of the symbols included in one of the candidate components was determined at a previous iteration by at least one of the multiplexers 315-m, wherein m varies between 1 and j-1;

[0044] - if it is determined that the auxiliary symbol included in the auxiliary component is not redundant, there is no any of the symbols included in the auxiliary component determined by the multiplexer 315-m at the previous iteration, where m varies between 1 and j-1, and it is determined that the auxiliary symbol included in the auxiliary component is more reliable than the symbol included in the candidate component determined by the multiplexer 315-j at the previous iteration, and the auxiliary symbol is less reliable than the symbol included in the candidate component determined by the multiplexer 315-(j-1) at the previous iteration, then an insertion action is performed by setting the current candidate component equal to the auxiliary component;

[0045] -If it is determined that the auxiliary symbol included in the auxiliary component is not redundant, wherein there is no any of the symbols included in the candidate component determined by the multiplexer 315-m at the previous iteration, where m=1,…,j-1, and it is determined that the auxiliary symbol included in the auxiliary component is more reliable than the symbol included in the candidate component determined by the multiplexer 315-j at the previous iteration, and the auxiliary symbol is more reliable than the symbol included in the candidate component determined by the multiplexer 315-(j-1) at the previous iteration, then a shifting action is performed by setting the current candidate component equal to the candidate component determined by the multiplexer 315-(j-1) at the previous iteration.

[0046] According to some embodiments, each of the plurality of multiplexers is configured to perform an initialization action at a first iteration by setting a current candidate component equal to an initialization component.

[0047] According to some embodiments, the variable node processing unit is further configured to: receive the intrinsic reliability metric online from the data processing unit in the non-binary error correction code decoder in response to the intrinsic reliability metric generation request delivered by the variable node processing unit

[0048] According to some embodiments, the variable node processing unit is further configured to: load at least a portion of the inherent reliability metric from the storage unit at each iteration.

[0049] A method is also provided for generating a variable node message based on an auxiliary component derived from a check node message and an inherent reliability metric, the inherent reliability metric being derived from a received signal, the auxiliary component comprising an auxiliary symbol and an auxiliary reliability metric associated with the auxiliary symbol. The method comprises:

[0050] - determining the components of the variable node message by iteratively processing the auxiliary components for ordering the auxiliary components according to a given order of auxiliary reliability metrics and retaining a predefined number of auxiliary components comprising the most reliable and all mutually different auxiliary symbols.

[0051] Advantageously, the variable node architecture according to various embodiments of the present invention has reduced latency and requires reduced storage and computing resources compared to existing architectures. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The accompanying drawings, which are incorporated in and constitute a part of this specification, are provided for illustration purposes only and, together with the general description of the invention given above and the detailed description of the embodiments given below, illustrate various embodiments of the invention.

[0053] Figure 1 is a block diagram of an exemplary application of the present invention to a communication system according to some embodiments;

[0054] Figure 2 is a block diagram of a non-binary error correction code decoder according to some embodiments in which an EMS decoding algorithm is considered;

[0055] Figure 3 is a block diagram illustrating the structure of a variable node processing unit according to some embodiments, in which the degree of the variable node processing unit is two;

[0056] Figure 4 is a flow chart illustrating a method of decoding a signal encoded using a non-binary error correction code according to some embodiments, in which an EMS decoding algorithm is used;

[0057] Figure 5 is a flow chart illustrating a method of calculating a variable node message according to some embodiments of the present invention, in which the variable node message is iteratively determined based on a check node message and an inherent reliability metric, and

[0058] Figure 6 is a flow chart illustrating a method of determining ordered variable node components comprising different symbols according to some embodiments of the present invention, wherein iterative ordering and redundancy elimination are performed. DETAILED DESCRIPTION

[0059] Embodiments of the present disclosure provide apparatus, methods, and computer program products with reduced computational complexity and reduced latency for decoding signals encoded using non-binary error correction codes. In particular, they provide an efficient low-latency, low-memory, and low-complexity variable node processing architecture implemented in an iterative message passing decoder for decoding signals encoded using non-binary error correction codes.

[0060] Methods, devices, and computer program products according to various embodiments may be implemented in several types of digital data transmission and storage devices and systems used in several types of applications. Exemplary devices and systems include, but are not limited to, computers, disks, laptops, phones, smart phones, recorders, base stations, drones, satellites, etc. Exemplary applications include magnetic and optical recording, digital television and video broadcasting, digital communications, etc.

[0061] For illustrative purposes only, some embodiments of the present disclosure will be described below with reference to digital communication systems. However, a skilled person will readily appreciate that various embodiments of the present disclosure may be integrated into other types of systems for other applications, such as positioning system memory and storage systems and spacecraft systems.

[0062] refer to Figure 1 , showing an exemplary application of the present disclosure in a digital communication system 100. The communication system 100 may be, for example:

[0063] -wired;

[0064] - Wireless (e.g. radio or visible light communication systems);

[0065] - optical (e.g., fiber-based, laser-based);

[0066] - Acoustic (e.g. underwater acoustic communication systems);

[0067] - Molecular (eg for use in underground structures (eg tunnels and pipelines) or in underwater environments).

[0068] The communication system 100 may include at least a transmitter device 10 and a receiver device 12. The transmitter device 10 (hereinafter also referred to as a "transmitter") may be configured to transmit data information via a transmission channel 11 to a receiver device 12 (hereinafter also referred to as a "receiver").

[0069] In the application of the present disclosure in a wired communication system such as a computer networking system, the transmitter 10 and / or the receiver 12 may be any device configured to operate in a wired network. Exemplary devices in such applications include computers, routers or switches connected to a small or large area wired network. In this case, the transmission channel 11 may be any type of physical cable for ensuring data transmission between different connected devices.

[0070] In the application of the present disclosure in wireless communication systems such as self-organizing wireless networks, wireless sensor networks, and radio communication systems, the transmitter 10 and the receiver 12 can be any type of fixed or mobile wireless device configured to operate in a wireless environment. Exemplary devices in such applications include laptop computers, mobile phones, and base stations. In this case, the transmission channel 11 can be any wireless propagation medium. In addition, the transmission channel 11 can accommodate several transmitters 10 and / or several receivers 12. In such an embodiment, a variety of access technologies and / or network coding technologies can be used in combination with error correction codes. Exemplary multiple access technologies include time division multiple access (TDMA), frequency division multiple access (FDMA), code division multiple access (CDMA), and space division multiple access (SDMA).

[0071] In the application of the present disclosure in optical communication systems such as optical fiber-based systems, the transmitter 10 and the receiver 12 can be any optical transceiver device configured to send and receive data information propagated on an optical link, respectively. The transmission channel 11 can be any optical fiber link designed to carry data over a short distance or a long distance. Exemplary applications for using optical fiber links over short distances include high-capacity networks such as data center interconnections. Exemplary applications for using optical fiber links over long distances include terrestrial and transoceanic transmissions. In such an embodiment, the information symbols conveyed by the transmitter 10 can be carried by optical signals polarized according to different polarization states of the optical fiber. The optical signal propagates along the optical fiber-based transmission channel 11 according to one or more propagation modes until it reaches the receiver 12. Exemplary optical communication systems include polarization division multiplexing (PDM) and mode division multiplexing (MDM) systems.

[0072] For any type of wired, wireless or optical communication system, the transmission channel 11 can be any noisy channel. The noise may be due to thermal noise of system components or interference radiation intercepted by the antenna. Other exemplary noise sources include switches, manual interruptions, electric sparks and lightning. In some embodiments, the total noise can be modeled by additive white Gaussian noise (AWGN).

[0073] Furthermore, according to some embodiments applied to digital mass storage, the transmission channel 11 may be modeled, for example, by an erasure channel, a binary symmetric channel, or a Gaussian channel. In such embodiments, the transmission channel 11 may be any type of storage device that may be sent to (written to) and received from (read from).

[0074] In addition, the transmitter 10 and the receiver 12 may be equipped with a single or multiple antennas. In particular, in the presence of multiple transmit and / or receive antennas, space-time coding and decoding techniques may be used in conjunction with error correction coding and decoding.

[0075] Furthermore, the encoded data may be sent on one or more frequency bands.When transmitting the encoded data on multiple frequency bands, the modulator 105 may use a multi-carrier modulation format such as OFDM (short for Orthogonal Frequency Division Multiplexing) and FBMC (short for Filter Bank Multi-Carrier).

[0076] According to some embodiments of the present disclosure, the transmitter 10 may include an error correction code (ECC) encoder 103 configured to encode a digital input data block 101 denoted as u into a codeword vector denoted as c using a non-binary error correction code. The receiver 12 may be configured to receive the codeword vector or a noisy replica p of the encoded data via the transmission channel 11. The receiver 12 may include an error correction code decoder 123 configured to deliver a digital output data block 125 as an estimate of the original digital input data block 101.

[0077] Digital input data 101 may be pre-compressed before being encoded by ECC encoder 103. Any source coding scheme ( Figure 1 The data encoded by the ECC encoder 103 may be further modulated by the modulator 105. The modulator 105 may be configured to map the encoded data onto an analog signal s and transmit the encoded data via the transmission channel 11.

[0078] The receiver 12 may include a corresponding processing block configured to perform the reverse function. It may include a demodulator 121 configured to generate a signal y by performing demodulation on a received signal p from a transmission channel prior to ECC decoding by an ECC decoder 123. The demodulator 121 may be configured to shift the received signal or channel output back into baseband and perform low pass filtering, sampling, and quantization. The data decoded by the ECC decoder 123 may be decoded using any source decoder ( Figure 1 The ECC decoder 123 may be configured to implement an iterative decoder (referred to as an “iterative decoding algorithm”) involving a check node processing unit and a variable node processing unit according to various embodiments of the present disclosure.

[0079] For illustrative purposes only, some embodiments of the present disclosure will be described below with reference to linear block non-binary error correction codes. However, a skilled person will readily appreciate that various embodiments of the present disclosure are applicable to any linear non-binary error correction code including non-binary convolutional codes.

[0080] Therefore, the ECC encoder 103 can be implemented by The specified linear block non-binary error correction code; n and K refer to the length of the codeword vector and the length of the coded data block respectively. The ECC encoder 103 accordingly encodes the data block u of length K into a codeword vector c, where c = (c1, ..., c n ) is a vector of length n, which includes the error correction code The algebraic structure of n elements is constructed, also called "symbols".

[0081] Linear Code It can be represented in matrix form using the generator matrix denoted by G and the parity check matrix denoted by H. Using the row representation of vectors, the dimension of the generator matrix G is K xn, while the dimension of the parity check matrix is ​​(nK) x n. These two matrices are related by the relationship GH t = 0. In addition, the entries of both matrices belong to the algebraic structure on which the error correction code is constructed. Using matrix representation, any codeword vector c satisfies the equation cH t = 0. This equation is also called the “parity check equation”. It defines nK parity check constraints, which are intended to be satisfied by any codeword vector.

[0082] Associated with the matrix representation, the linear code You can use a bipartite graph called a "Tanner graph" This graph consists of n variable nodes and nK check nodes.

[0083] Each variable node vn∈{1,2,…,n} corresponds to a column of the parity check matrix. Each check node cn∈{1,2,…,nK} corresponds to a row of the parity check matrix, that is, to a parity check equation. If the entry H of the parity check matrix vn,cn Equal to code To construct an element of the algebraic structure, the variable node vn is connected to the check node cn.

[0084] represents the set of check nodes connected to the variable node vn. Similarly, Represents the set of variable nodes connected to the check node cn.

[0085] The degree d of the variable node vn VN (or check the d of node cn CN ) corresponds to the set The cardinality (or corresponding to the set of the base number).

[0086] According to some embodiments, a non-binary error correction code The algebraic structure of the construction of can be any non-zero commutative division ring, such as a field. Exemplary fields include finite fields (also known as "Galois fields").

[0087] For illustrative purposes only, some embodiments will be described below with reference to finite fields. However, it will be readily appreciated by those skilled in the art that the present disclosure can be applied to any algebraic structure similar to a division ring, such as a non-zero commutative division ring, and to any quasi-ring, such as a finite division near-ring. Insights on the design of non-binary error correction codes on finite division near-rings can be found in the article "Non-binary LDPC codes over finite division near rings, 23rd International Conference on Telecommunications (ICT), pp. 1-7, Thessaloniki, 2016".

[0088] For non-binary linear codes constructed over a Galois field (usually denoted by GF(q), where q>2 specifies the cardinality of the code), these symbols take values ​​in GF(q). The codeword vector c is thus a vector of n symbols, each of which belongs to GF(q).

[0089] For illustration purposes only, some embodiments will be described below with reference to an ECC encoder 103 that encodes data using a non-binary LDPC code. However, a skilled person will readily appreciate that various embodiments of the present disclosure are also applicable to other non-binary codes, such as non-binary polar codes, non-binary convolutional codes, non-binary turbo codes, and generally non-binary linear block error correction codes. Non-binary error correction codes can be advantageously used for high spectral efficiency encoding.

[0090] For exemplary purposes, in one embodiment, the ECC decoder 123 implements a non-binary LDPC code decoder for decoding data encoded by the ECC encoder 103 using a non-binary LDPC code.

[0091] The present disclosure is described with reference to the EMS algorithm. However, the skilled person will readily appreciate that the various embodiments are applicable to any iterative non-binary LDPC code decoder, such as min-max and T-EMS.

[0092] refer to Figure 2 , shows the structure of an iterative non-binary LDPC decoder 123 according to some embodiments using the EMS algorithm.

[0093] The iterative decoder 123 may be configured to decode the n ) represents the received noise sequence to determine the transmitter 10's estimate of the transmitted codeword c Code word c=(c1,…,c n ) may have been used at the transmitter using a Galois field GF(q) constructed over q>2 The specified non-binary LDPC code is encoded. It can process the signal at several iterations to try to reduce the remaining decoding error at each iteration.

[0094] The iterative decoder 123 may be configured to be based on the code used at the transmitter 10 The Tanner graph representation is used to determine the estimated Each variable node in the Tanner graph is mapped to a variable node processing unit. Each check node in the Tanner graph is mapped to a check node processing unit.

[0095] Therefore, the iterative decoder 123 may include n variable node processing units 27 (also represented by 27-1 to 27-n or 27-vn (where vn=1,…,n)) and nK check node processing units 25 (also represented by 25-1 to 25-(nK) or 25-cn (where cn=1,…,nK)).

[0096] The variable node processing unit 27-vn (where vn=1, ..., n) and the check node processing unit 25-cn (where cn=1, ..., nK) can be configured to iteratively exchange messages to estimate the most reliable codeword according to the noise sequence y

[0097] The message generated by the variable node processing unit 27-vn is referred to as a “variable node message.” Similarly, the message generated by the check node processing unit 25-cn is referred to as a “check node message.”

[0098] The exchange messages between the variable node processing unit 27 - vn and the check node processing unit 25 - cn may carry data representing symbols.

[0099] According to some embodiments, the variable node message and the check node message may carry the value of the symbol and a metric measuring its reliability (hereinafter also referred to as a "reliability metric"). The value of the reliability metric is related to the reliability of the symbol. In such an embodiment, each variable node message and the check node message may include q components, the components including:

[0100] - the value of the sign in GF(q), and

[0101] - A reliability measure associated with the symbol.

[0102] In some embodiments, the reliability metric of a symbol may correspond to an estimated probability density function of the symbol, the estimated probability density function representing the probability that the symbol is correct. In particular, the reliability metric may be represented in the logarithmic domain by a log-likelihood ratio (LLR) value.

[0103] Depending on the expression of the reliability measure, the most reliable symbol may be associated with the minimum or maximum value of the reliability measure.

[0104] One definition of the LLR measure involves the expression of β i represents a fixed sign and corresponds to the most reliable sign that satisfies the following equation:

[0105] β i = argmax t＝0,…,q-1 p(α t |y i ) (1)

[0106] In equation (1), α t Indicates the sign on the Galois field.

[0107] Therefore, using the assumption that symbols in the Galois field are equally probable, for the i-th symbol c i , for equal to α t The LLR value of this symbol is recorded as LLR t (c i ), and can be expressed as:

[0108]

[0109] Using this definition of the LLR metric, the most reliable symbols are those associated with the smallest LLR values ​​according to equation (2).

[0110] For illustration purposes only, some embodiments will be described below with reference to reliability metrics represented by log-likelihood ratio (LLR) values ​​in the logarithmic domain. However, it will be readily appreciated by a skilled person that other types of decoding and reliability metrics may be used to measure the reliability of a symbol. For example, the reliability metric may be a quadratic distance or any monotonic function of the probability density function of the symbol.

[0111] The processing performed by the various variable node processing units 27-vn and check node processing units 25-cn may be implemented according to a number of scheduling mechanisms, including but not limited to the three examples described below.

[0112] According to the first embodiment, all variable node processing units 27-vn (where vn=1, ..., n) may be configured to operate in the first round, and then all check node processing units 25-cn (where cn=1, ..., nK) may be configured to update the set to be set in its corresponding The check node messages delivered to the variable node processing units in the . This particular scheduling is called "flooding scheduling". In particular, the check node processing units 25-cn can be configured to operate in series or in parallel, where from 2 to (nK) check node processing units 25-cn can operate simultaneously.

[0113] According to a second embodiment based on "horizontal scheduling", the check node processing units 25-cn (where cn = 1, ..., nK) can be configured to operate serially to update all variable node processing units 27-vn connected to them. In particular, a group of check node processing units 25-cn can be configured to operate in parallel to update all connected variable node processing units 27-vn, provided that there are no conflicting variable node processing units 27-vn (for example, when two check node processing units 25-cn are connected to the same variable node processing unit 27-vn).

[0114] According to the third embodiment based on “vertical scheduling”, the variable node processing units 27 - vn may be configured to operate serially to update all the check node processing units 25 - cn connected to them.

[0115] The iterative decoder 123 may include a data processing unit 23 configured to determine an intrinsic symbol and an intrinsic reliability measure from the received signal, the intrinsic symbol denoted as x∈GF(q) and belonging to a Galois field (generally belonging to the algebraic structure of a non-binary error correction code) and the intrinsic reliability measure denoted as I + More specifically, the data processing unit 23 may include:

[0116] a symbol generator 231 configured to generate intrinsic symbols x belonging to the algebraic structure on which the non-binary error correction code is constructed, and

[0117] - an intrinsic reliability metric generator 233 configured to generate an intrinsic reliability metric I associated with each intrinsic symbol x from the received signal + (x). Using the LLR representation of equation (2), the inherent reliability measure associated with symbol x can be determined on a logarithmic scale according to the following equation:

[0118]

[0119] In equation (3), β i refers to the most reliable symbol defined previously in equation (1).

[0120] According to some embodiments, the intrinsic reliability metric generator unit 233 may be configured to load the received signal y from the storage unit 21 , which is configured to store the received signal y.

[0121] exist Figure 2 In some of the embodiments shown, the storage unit 21 may be included in the data processing unit 23 .

[0122] In other embodiments ( Figure 2 (not shown), the storage unit 21 may be included in an iterative decoder 123 outside the data processing unit 23.

[0123] According to some embodiments, the intrinsic reliability metric generator unit 233 may be configured to determine at least a portion of the intrinsic reliability metric offline before the iterative decoding process begins. In such an embodiment, the intrinsic reliability metric generator unit 233 may be further configured to store at least a portion of the calculated intrinsic reliability metric in the storage unit 21. Such an embodiment may be advantageously implemented for decoding codes constructed on small-order algebraic structures.

[0124] In some embodiments, the intrinsic reliability metric generator unit 233 may be configured to determine the intrinsic reliability metric online during the iterative decoding process.Such an embodiment may be advantageously implemented for decoding high-order non-binary error correction codes to achieve memory savings.

[0125] In some embodiments, the intrinsic reliability metric generator unit 233 may be configured to determine at least some of the intrinsic reliability metrics offline, and to determine the remaining intrinsic reliability metrics online.

[0126] According to some embodiments ( Figure 2 ), the iterative decoder 123 may include a single data processing unit 23 configured to determine an inherent reliability metric to be delivered to all variable node processing units 27-vn (where vn=1,…,n).

[0127] In other embodiments (not shown here), the iterative decoder 123 may include multiple data processing units 23-vn (where vn=1,…,n), each data processing unit 23-vn being included in a variable node processing unit 23-vn (where vn=1,…,n).

[0128] The variable node processing unit 27-vn may be configured to receive an intrinsic reliability metric derived from the received signal y and to generate a signal from the set corresponding to the intrinsic reliability metric derived from the received signal y. The check node processing unit 25-cn receives the check node message. The variable node processing unit 27-vn may be further configured to: process the received check node message and the inherent reliability metric, calculate the local decision, and deliver the variable node message to the set At least one check node processing unit 25-cn corresponding to the check node in the.

[0129] Similarly, the check node processing unit 25-cn may be configured to process the The check node processing unit 25-cn may be further configured to deliver the check node message to the set At least one variable node processing unit 27-vn corresponding to the variable node in.

[0130] The exchange of messages may be initiated by the variable node processing unit 27-vn. The exchange of messages may be terminated if the processed signal satisfies the parity check equation or if the maximum number of iterations is reached without satisfying all parity check constraints.

[0131] Thus, the iterative decoder 123 may include a decoding decision unit 29 configured to receive a local decision calculated by a variable node processing unit 27-vn at each iteration of the decoding process and configured to:

[0132] - if the processed signal satisfies the parity check equation, delivering the processed signal as an estimate of the original codeword vector; or

[0133] If the maximum number of iterations is reached without satisfying all parity constraints, decoding failure is declared, but the codeword vector estimated at the last iteration is output.

[0134] Various embodiments of the present disclosure provide a method for implementing a degree-two (d2) in an iterative non-binary error correction code decoder. VN =2) is an efficient low complexity and low latency technology for variable node processing, the variable node processing unit being configured as:

[0135] -From the collection The check node processing unit in receives an intrinsic reliability metric derived from the received signal y and a check node message, and

[0136] - Generate a variable node message based on the check node message and the inherent reliability measure.

[0137] Figure 3 is a block diagram showing the structure of a variable node processing unit 31 with a degree d VN = 2, which is configured to: receive from a check node processing unit 33 a check node message represented as V and an inherent reliability metric, and determine a variable node message represented as U, and deliver the variable node message U to a check node processing unit 35 different from the check node processing unit 33.

[0138] In the following, the components included in the variable node message are referred to as "variable node components", while the components included in the check node message are referred to as "check node components".

[0139] According to some embodiments using the EMS algorithm, the variable node message and / or the check node message may be sorted according to their reliability, i.e., sorted according to a given order (e.g., increasing or decreasing) of the reliability metric included therein. Further, the variable node message may be truncated so as to retain only a predetermined number n VN of the most reliable variable node components, where n VN is strictly less than q (n VN < q). Similarly, the check node message may be truncated so as to retain only a predefined number n CN of the most reliable check node components, where n CN is strictly less than q (n CN < q). Further, the sorting and truncation operations may be performed by the variable node processing unit 31 or by the check node processing unit 33 and / or the check node processing unit 35.

[0140] In an embodiment, the predetermined number of variable node components n VN and the predetermined number of check node components n CN may be different, i.e., n VN ≠ n CN .

[0141] In another embodiment, the predetermined number of variable node components n VN and the predetermined number of check node components n CN may be the same, i.e., n VN = n CN .

[0142] For the purposes of clarity and simplicity, the following description of the embodiments of the present disclosure will be made with reference to the sorted and truncated check node message V and variable node message U, where the number of check node components and variable node components are equal or different. However, those skilled in the art will readily understand that the present disclosure is applicable to variable node messages and check node messages including unsorted components.

[0143] Therefore, the check node message V may include the i =(V i ⊕ ,V i + ) represents n CN Check node components (where i = 0, ..., n CN -1), check the node component V i =(V i ⊕ ,V i + ) includes the symbol V belonging to the Galois field GF(q) i ⊕ and associated with the symbol V i ⊕ Reliability metric V i + . It can be measured according to the reliability V i + The check node components are sorted in a given order (increasing or decreasing) corresponding to the decreasing reliability, so that (where i = 0,…,n CN -2) and the component with the most reliable sign is

[0144] The variable node message U may include n VN variable node components (for t=0,…,n VN -1), variable node components Includes symbols belonging to the Galois field GF(q) and associated with the symbol Reliability measure According to the reliability metric The variable node components are sorted in a given order (increasing or decreasing) corresponding to the decreasing reliability, so that (where t=0,…,n VN -2) and the component with the most reliable sign is

[0145] Additionally, the following symbols will be used in the following descriptions:

[0146] -n int represents a predefined number of the most reliable intrinsic symbols, which belong to the algebraic structure of the construction of non-binary error-correcting codes;

[0147] -x l ∈GF(q)(where l=0,…,n int -1) refers to n intThe most reliable intrinsic symbols belong to the algebraic structure of the construction of non-binary error correction codes, so that the most reliable intrinsic symbol is x0;

[0148] -I + (x l ) refers to the intrinsic symbol x belonging to the algebraic structure of the non-binary error correction code l Intrinsic reliability measure of association, Intrinsic reliability measure I + (x l ) is derived from the received sequence / signal y;

[0149] -U 1aux refers to the first assistance message, which includes n CN auxiliary components, where i = 0, ..., n CN -1, auxiliary component U 1aux,i Include auxiliary symbols and associated with the symbol Auxiliary reliability measure

[0150] -U 2aux refers to the second auxiliary message, which includes n int auxiliary components, where l = 0, ..., n int -1, auxiliary component U 2aux,l Include auxiliary symbols and associated with the symbol Auxiliary reliability measure

[0151] (where r is between 0 and n int +n CN -1) refers to the auxiliary component extracted from the first auxiliary message or the second auxiliary message. The auxiliary component may include auxiliary symbols and associated with the symbol Auxiliary reliability measure

[0152] -J refers to an offset value determined by the iterative decoder 123, and the offset value J may be an integer greater than or equal to zero (J ≥ 0);

[0153] refers to the reference reliability metric (also called the “default reliability metric”) according to the following equation, which is based on the reliability metric And the offset value J is determined, the reliability metric Included in the check node component containing the least reliable symbol (also called "reference check node component" or "default check node component"):

[0154]

[0155] A reference reliability metric refers to a calculation thereof involving a reliability metric associated with a reference check node component including the least reliable symbol;

[0156] Refers to predefined candidate symbols and predefined candidate reliability metrics In some embodiments, the predefined candidate symbol can be selected from an algebraic structure different from the algebraic structure of the construction of the non-binary error correction code. In some embodiments, the candidate reliability metric is predefined Can be equal to a predefined minimum value;

[0157] (where j is between 1 and n VN The value between ) refers to the candidate symbol and associated with the candidate symbol Candidate reliability measures for candidate components of , the candidate components corresponding to the components determined at the iterative sorting and redundancy elimination operations;

[0158] Refers to the predefined "initialization component", which includes the initialization symbol and associated with the initialization symbol Initialization reliability measure

[0159] (where j is between 1 and n VN The value between ) refers to the current candidate component determined in the current iteration of the iterative sorting and redundancy elimination process, which includes the current candidate symbol and associated with the current candidate symbol Current candidate reliability measures for

[0160] According to some embodiments, the variable node processing unit 31 may be configured to receive int The most reliable intrinsic symbols are associated with a predefined number n int Intrinsic reliability measure I + (x l ), l=0,…,n int -1, and the symbol included in the check node message V Associated n CNIntrinsic reliability measure i=0,…,n CN -1. The variable node processing unit 31 may be configured to receive n from the data processing unit 23. int +n CN An inherent reliability measure.

[0161] Considering the received checkpoint messages V and n int +n CN The variable node processing unit 31 may be configured to generate an inherent reliability metric (loaded from the storage unit 21 or received online from the inherent reliability metric generator unit 233) according to n. CN +n int Auxiliary Component (where r = 0, ..., n int +n CN -1) Determine n VN Variable node components t=0,…,n VN -1, the auxiliary component is from the check node message V and n int +n CN Intrinsic reliability measure I + (x l )(l=0,…,n int -1) and (i=0,…,n CN -1) is derived. More specifically, the variable node processing unit 31 may include:

[0162] a calculation unit 311 configured to calculate, based on the check node message V and the intrinsic reliability metric associated with the symbols included in the check node message V i=0,…,n CN -1 to calculate the first auxiliary message U 1aux , and according to the predefined number n int n int The most reliable intrinsic symbol x l ∈GF(q) associated with the intrinsic reliability measure I + (x l ), l=0,…,n int -1 and reference reliability measures To calculate the second auxiliary message U 2aux The first auxiliary message U 1aux Can include CN Auxiliary Component (where i = 0,…,n CN -1), and the second auxiliary message U 2aux Can include int Auxiliary Component (where l=0,…,n int -1);

[0163] - a sorting and redundancy elimination unit 313, which is configured to iteratively process at least the auxiliary component U extracted from the first or second auxiliary message aux,r The redundancy elimination and sorting unit 313 is configured to iteratively sort the auxiliary components U 1aux,i and U 2aux,l Sort and keep a predefined number n VN The components of the variable node message are determined based on the auxiliary components of the first and second auxiliary messages, the auxiliary components including the most reliable and all different auxiliary symbols. The iterative sorting and redundancy elimination operation refers to iteratively processing the auxiliary components included in the first and second auxiliary messages in such a way that at least the auxiliary components are processed at each iteration. The iteration may correspond to a processing time interval (e.g., a clock cycle).

[0164] The following description will be made with reference to processing the auxiliary component at each iteration, according to which the sorting and redundancy elimination unit 313 can be configured to process the auxiliary component at each iteration. However, it will be readily understood by a skilled person that the present disclosure is applicable to processing two or more auxiliary components at each of one or more iterations.

[0165] Therefore, the calculation unit 311 can be configured as:

[0166] - According to the symbols included in the check node message V Determine the first auxiliary message U 1aux Auxiliary symbols included in (where i = 0,…,n CN -1), the auxiliary symbol is selected from the symbols included in the check node component according to the following equation:

[0167]

[0168] - determining a first auxiliary message U by applying an addition operation on a predefined algebraic structure selected from the group consisting of a real number field, an integer field and a natural number field 1aux Auxiliary symbols included in Each auxiliary reliability metric associated with The addition operation is applied according to the following equation: with the auxiliary symbol Associated intrinsic reliability measures and equal to the selected auxiliary symbol Symbol Associated to be included in the check node component Reliability measures in

[0169]

[0170] According to some embodiments, the non-binary error correction code decoder 123 may be further configured according to equation (4) to: determine an offset value J, and determine a reference reliability metric according to a check node component including the least reliable symbol and the offset value In such an embodiment, the computing unit 311 may be configured to:

[0171] - According to the highest or lowest inherent reliability metric I + (x l )(where l=0,…,n int -1) Associated predefined number n int The most reliable intrinsic symbol x l , determine the second auxiliary message U 2aux Auxiliary symbols included in Auxiliary symbols According to the following equation, it is equal to the intrinsic symbol x l , where l = 0,…,n int -1:

[0172]

[0173] - Determine the second auxiliary message U by applying an addition operation on a predefined algebraic structure 2aux Auxiliary symbols included in Associated auxiliary reliability measures The addition operation is applied to the reference reliability metric according to the following equation and associated with the proper symbol x l Intrinsic reliability measure Intrinsic symbol x l Equal to the auxiliary symbol

[0174]

[0175] According to some embodiments, the decoder 123 may be configured to first determine the number n of intrinsic reliability metrics associated with the most reliable intrinsic symbols depending on one or more parameters selected from the group consisting of a signal-to-noise ratio, a number of iterations of the decoding process, and an algebraic structure of the non-binary error correction code. int .

[0176] According to some embodiments, the decoder 123 may be configured to: CN The number of intrinsic reliability measures n associated with the most reliable intrinsic symbol is determined by the number of int, the number of intrinsic reliability measures is strictly smaller than the number of check node components n int <n CN .

[0177] According to some embodiments, the non-binary error correction code decoder 123 may be configured to determine the offset value J according to a predefined decoding performance criterion.

[0178] According to some embodiments, the non-binary error correction code decoder 123 can be configured to determine the offset value J depending on the number of iterations of message exchange between the variable node processing unit 31 and the check node processing unit 33 and / or the check node processing unit 35, and different offset values ​​J are dynamically determined at each iteration of the decoding process.

[0179] In addition, according to reference Figure 2 In some embodiments, the non-binary error correction code decoder 123 may be configured to determine a different offset value J for each variable node processing unit 27 - vn (where vn=1, . . . , n).

[0180] according to Figure 3 In some embodiments shown, the sorting and redundancy elimination unit 313 can be configured to perform iterative sorting and redundancy elimination to generate variable node components through the implementation of multiplexers and comparators. Therefore, in some embodiments, the sorting and redundancy elimination unit 313 may include:

[0181] - Multiple multiplexers 315-j, where j=1, ..., n VN ;

[0182] - Multiple reliability metric comparators 319-j, where j=0, ..., n VN , which includes a first reliability metric comparator 319-0 and one or more reliability metric comparators 319-j, where j=1, ..., n VN ,as well as

[0183] - A plurality of sign comparators 317-j, where j=0, ..., n VN -1, which includes a first sign comparator 317-0 and one or more sign comparators 317-j, where j=1, ..., n VN -1.

[0184] Each multiplexer 315-j may be associated with a reliability metric comparator 319-j and a symbol comparator 317-j. In particular, multiplexer 315-1 may be associated with reliability metric comparators 319-0 and 319-1 and symbol comparator 317-0, and multiplexer 315-n may be associated with reliability metric comparators 319-0 and 319-1 and symbol comparator 317-0. VN can only be compared with the reliability metric comparator 319-n VNEach multiplexer 315-j (where j = 1, ..., n VN ) can be configured to: determine the current candidate component at each iteration (e.g., at each clock cycle) depending on the comparison performed by the plurality of symbol comparators 317-j and the plurality of reliability metric comparators 319-j. In particular, the sorting and redundancy elimination unit 313 may include a plurality of controllers 318-j, where j=1, ..., n VN , each controller 318-j is associated with a multiplexer 315-j and is configured to perform a control action (also referred to as an "action") on the multiplexer 315-j at each iteration, depending on the comparison performed by the sign comparator 317-m, where m=0,…,j-1.

[0185] Even if the check node components are ordered, the auxiliary components of the first auxiliary message may not be ordered, because the addition operation involves an inherent reliability metric associated with the symbols included in the check node message. The sorting and redundancy elimination unit 313 is therefore used to sort the auxiliary components according to a given order of the auxiliary reliability metrics, and to generate ordered variable node components derived from the sorted auxiliary components.

[0186] In addition, the auxiliary components included in the first auxiliary message and the second auxiliary message may include redundant symbols, that is, two or more auxiliary components may be included, and these auxiliary components include the same value of one or more auxiliary symbols. The symbol comparator 317-j is used for redundancy elimination so as to retain the components including the most reliable different symbols among the auxiliary components and realize the generation of the most reliable variable node components including different symbols.

[0187] At each iteration (eg, at each clock cycle), the control action performed by the controller 318-j on the multiplexer 315-j may consist of an initialization action, a retention action, an insertion action, or a shift action.

[0188] At the same time, all n included in the first and second assistance messages are processed. CN +n int auxiliary components (i.e., processing n CN +n int Iterations) (n included in the first assistance message CN The auxiliary components and the n included in the second auxiliary message int auxiliary components), the sorting and redundancy elimination unit 313 may be configured to generate variable node components according to the candidate components including the most reliable different symbols.

[0189] According to some embodiments, where one or more auxiliary components are processed at each iteration, each multiplexer 315-j (where j=1, ..., n VN) may be configured to receive at least an auxiliary component extracted from the first auxiliary message or the second auxiliary message at each iteration (eg, at each clock cycle) and the predefined initialization component C init , each multiplexer 315-j (where j = 1, ..., n VN ) is configured to be able to pass at least the auxiliary component C aux , predefined initialization component C init , and the component corresponding to the candidate component determined by the multiplexer 315-j at the previous iteration Select the component to determine the current candidate component C cand,j In such an embodiment:

[0190] - The reliability metric comparator 319-j associated with the multiplexer 315-j may be configured to perform aux At least one auxiliary reliability metric included in and the candidate component C determined by multiplexer 315-j in the previous iteration. j Reliability measures included in The comparison between

[0191] The symbol comparator 317-j associated with each multiplexer 315-j may be configured to perform a aux Auxiliary symbols included in and the candidate component C determined by multiplexer 315-j in the previous iteration. j Symbols included in Comparison between them is used to check the redundancy of symbols.

[0192] In some embodiments where the auxiliary component is processed at each iteration, each multiplexer 315-j (where j=1, ..., n VN ) may be configured to: receive the auxiliary component extracted from the first auxiliary message or the second auxiliary message and the predefined initialization component at each iteration (for example, at each clock cycle), and aux , the predetermined initialization component C init and the component corresponding to the candidate component determined by multiplexer 315-j at the previous iteration Select the component to determine the current candidate component C cand,j .

[0193] For illustrative purposes only, the following embodiments will be described with reference to an ascending order of reliability measures according to which the most reliable symbol is associated with the smallest reliability measure and with reference to processing the auxiliary component at each iteration.

[0194] Therefore, in some embodiments, receiving the auxiliary component C aux Each multiplexer 315-j (where j=1, ..., n VN ) can be configured as:

[0195] - By passing the current candidate component C cand,j Set equal to the candidate component C determined at the previous iteration j To perform the retention action:

[0196] * If in auxiliary component C aux Auxiliary symbols included in Non-redundant, where none of the candidate components C determined by multiplexer 315-m (where m=1, ..., j-1) at the previous iteration m (where m=1, ..., j-1) (i.e., if each m varies between 1 and j-1, each symbol comparator 317-m associated with each multiplexer 315-m determines ), and in the auxiliary component C aux Auxiliary symbols included in than the candidate component C determined by the multiplexer 315-j in the previous iteration. j Symbols included in unreliable (i.e., if for the ascending order of reliability metrics, the reliability metric comparator 319-j associated with the multiplexer 315-j determines or

[0197] * If in auxiliary component C aux Auxiliary symbols included in redundant, wherein the candidate component C determined by at least one of the multiplexers 315-1 at the previous iteration l A symbol included in where l varies between 1 and j-1 (i.e., at least one symbol comparator 317-1 associated with the multiplexer 315-1 determines at least one index l taking a value between 1 and j-1, ); According to the retention action, the multiplexer 315-j does not perform any specific action and retains the candidate component previously selected during the previous iteration as the current candidate component. Therefore, and

[0198] - If in the auxiliary component C aux Auxiliary symbols included in Non-redundant, where there is no candidate component C determined in the previous iteration l (where l = 1, ..., j-1) (That is, if each of the sign comparators 317-1 (where l=1, ..., j-1) determines ), and the auxiliary component C aux Auxiliary symbols included in than the candidate component C determined by the multiplexer 315-j in the previous iteration. j Symbols included in Reliable and auxiliary symbols than the candidate component C determined by the multiplexer 315-j-1 in the previous iteration. j-1 Symbols included in unreliable (i.e., if the reliability metric comparator 319-j associated with the multiplexer 315-j determines and the reliability metric comparator 319-j-1 associated with the multiplexer 315-j-1 determines ), then by taking the current candidate component C cand,j Set equal to the auxiliary component C aux According to the insertion action, the multiplexer 315-j may be configured to select the auxiliary component as the current candidate component, thereby replacing the candidate component previously selected during the previous iteration with the auxiliary component, such that and

[0199] - If in the auxiliary component C aux Auxiliary symbols included in Non-redundant, where there is no candidate component C determined in the previous iteration l Any symbol included in where l=1, ..., j-1 (i.e., if each symbol comparator 317-1 (where l=1, ..., j-1) determines ) and in the auxiliary component C aux Auxiliary symbols included in than the candidate component C determined by the multiplexer 315-j in the previous iteration. j Symbols included in Reliable and auxiliary symbols than the candidate component C determined by the multiplexer 315-j-1 in the previous iteration. j-1 Symbols included in reliable (i.e., if the reliability metric comparator 319-j associated with the multiplexer 315-j determines and the reliability metric comparator 319-j-1 associated with the multiplexer 315-j-1 determines ), then by taking the current candidate component C cand,j Set equal to the candidate component C determined by multiplexer 315-(j-1) at the previous iteration j-1According to the shifting action, each multiplexer 315-j may be configured to select the candidate component C determined by the multiplexer 315-(j-1). j-1 As the current candidate component C cand,j , so that

[0200] It should be noted that for the comparison performed in association with the multiplexer 315-1, the predefined candidate component C0 is taken into account during the symbol and reliability metric comparison. The skilled person will readily appreciate that, given that the predefined candidate components include predefined candidate symbols and predefined constant values ​​of the reliability metric, the actions determined by the controller 315-1 in such an embodiment can be advantageously simplified.

[0201] According to some embodiments, to initialize the candidate components at the first iteration, each multiplexer 315-j (where j=1, ..., n VN ) can be configured as follows: cand,j Set equal to the initialization component To perform initialization actions, and The initialization component may include an initialization symbol and a constant value of an initialization reliability metric. VN ) can be configured to determine an initial candidate component according to the initialization component. Therefore, before starting to process the auxiliary component extracted from the first or second auxiliary message, the j-th multiplexer 315-j can be configured to convert the candidate component C j and the current candidate component C cand,j Initialize to the initialization component C init , so that the candidate symbols and the current candidate symbols are based on is equal to the initialization symbol and is equal to the candidate symbol Associated reliability measures and associated with the current candidate symbol The reliability measure is based on is equal to the initial reliability measure.

[0202] In some embodiments, the initialization symbols may be selected from an algebraic structure different from the algebraic structure of the construction of the non-binary error correction code. In some embodiments, the initialization reliability metric may be a predefined maximum value.

[0203] According to some embodiments, the variable node processing unit 31 may be configured to receive the intrinsic reliability metric from the intrinsic reliability metric generation unit 233, the data processing unit 23 being configured to generate the intrinsic reliability metric online during each iteration during the decoding process; for example, in response to an intrinsic reliability metric generation request for calculating the auxiliary component of the first or second auxiliary message delivered by the variable node processing unit 31. The calculation of the intrinsic reliability metric online whenever the intrinsic reliability metric is required for the variable node processing unit update achieves the avoidance of memorization of all the intrinsic reliability metrics, so that a large amount of memory and area is advantageously saved, especially when considering high-order Galois fields.

[0204] In some embodiments, the variable node processing unit 31 can be configured to load the inherent reliability metric from the storage unit 21 at each iteration, and the data processing unit 23 is configured to pre-calculate at least a portion of the inherent reliability metric offline and store the calculated portion of the inherent reliability metric in the storage unit 21.

[0205] Figure 4 is a flow chart showing a method for decoding a signal received on a communication channel using a non-binary error correction code constructed over a Galois field GF(q) The encoding is performed and the decoding is performed according to some embodiments of the present disclosure, where for example the EMS algorithm using flooding scheduling is applied.

[0206] Therefore, the decoding process may include two phases: an initialization phase and a decoding phase.

[0207] At step 401, a received signal y may be received. The received signal may be written as a function of the transmitted codeword according to the following equation:

[0208] y=c+w (9)

[0209] In equation (9), w specifies a vector of length n that models the noise that modifies the communication channel.

[0210] At step 403, one or more decoding parameters may be determined. The decoding parameters may include a maximum number of iterations N of the EMS iterative decoding process. max , check the number of node components n CN , the number of variable node components n VN , a predefined number n of the most reliable symbols int , and offset value J.

[0211] Maximum number of iterations N maxIt can affect the decoding performance and complexity. If the available computing and memory resources are limited, or if the decoding latency is limited, a small number of iterations may be preferred to achieve increased throughput. Conversely, for example, in the presence of a high noise level, i.e., in the case of a low signal-to-noise ratio, a large number of iterations to achieve better decoding performance may be preferred. In some embodiments, the maximum number of iterations can thus be adjusted according to the noise level and / or other parameters of system operability (e.g., the size of the decoder memory unit / buffer).

[0212] In some embodiments applied to the EMS algorithm, the number of check node components and the number of variable node components can be set to be strictly less than the order of the Galois field, i.e., n CN <q and n VN <q.

[0213] In an embodiment, the number of variable node components n VN and the number of check node components n CN can be different, i.e., n VN ≠n CN .

[0214] In another embodiment, the number of variable node components n VN and the number of check node components n CN can be the same, i.e., n VN =n CN .

[0215] According to some embodiments, the number of check node components n CN can further depend on the non-binary error-correcting code (e.g., the algebraic structure on which the code is constructed) and / or on the order of the decoding iterations of the iterative decoding process and / or on the signal-to-noise ratio and / or on the computing and storage capabilities of the decoder and / or on the maximum number of iterations of the decoding process.

[0216] According to some embodiments, the number n of the intrinsic reliability metrics can be determined depending on one or more parameters selected from the group including the signal-to-noise ratio, the number of iterations of the decoding process, and the algebraic structure of the non-binary error-correcting code int .

[0217] According to some embodiments, the number n of the most reliable intrinsic symbols can be determined depending on the number of check node components n CN or equivalently the number of the intrinsic reliability metrics associated with the most reliable symbols, and the number of the most reliable intrinsic symbols is strictly less than the number of check node components n int <n int <n CN .

[0218] According to some embodiments, the offset value may be determined according to a predefined decoding performance criterion.

[0219] According to some embodiments, the offset value may be determined depending on the number of iterations of the message exchange, with a different offset value being dynamically determined (ie, updated) at each iteration of the decoding process.

[0220] At step 405, the most reliable intrinsic symbol x belonging to the Galois field can be calculated according to equation (3) based on the received signal. l Associated n int Intrinsic reliability measure I + (x l ), l=0,…,n int -1, and with the component V at the check node i Symbols included in Associated n CN Intrinsic reliability measure i=0,…,n CN -1, the intrinsic reliability metric is to be used to initialize the variable node message.

[0221] The calculated inherent reliability metric is used as the initial variable node message to be delivered by the variable node processing unit during the iterative decoding process. The exchange of variable node messages and check node messages carrying such reliability metrics during multiple iterations implements the processing signal z=(z1, z2, ..., z n ) to generate the estimate Make it closer to the MAP estimate For z to be a codeword, it should satisfy all parity check equations, i.e., Hz t = 0. The most reliable symbol β can be used i Initialize the decoded message z to z = (β1, β2, …, β n ).

[0222] Therefore, at step 409, the number of iterations may be initialized, ie, set to zero, N iter =0.

[0223] Step 411 may be performed to check whether a parity check constraint (ie, a parity check equation) is satisfied.

[0224] If it is determined at step 411 that the processed signal z satisfies the parity check equation and satisfies Hz t = 0, the decoding process may be stopped and the decoded codeword may be delivered at step 413

[0225] If it is determined at step 411 that the parity check constraint is not satisfied, step 415 may be executed to check whether the maximum number of iterations N is reached. max , that is, check whether N iter =N max If it is determined that the number of iterations executed has reached the maximum number of iterations, the decoding process may be stopped at step 417 and a decoding failure may be declared. If it is determined that the maximum number of iterations has not been reached, steps 419 to 425 may be performed to run one iteration of the exchange of check node messages and variable node messages, the check node message including n CN Check node components, while the variable node message includes n VN Variable node components.

[0226] In some embodiments, the number of check node components and the number of variable node components may be different.

[0227] At step 419, the check node message may be calculated from the variable node message. The check node components included in each check node message may be sorted according to a given order (increasing or decreasing) of the reliability metrics.

[0228] At step 421, variable node messages may be calculated, each variable node message being based on a check node message and n int +n VN The variable node components included in each variable node message may be sorted according to a given order (increasing or decreasing) of the reliability metrics.

[0229] At step 423, the processed signal z may be updated according to the reliability metric included in the variable node component.

[0230] At step 425, the iter =N iter +1 to increment the iteration count of the message exchange.

[0231] A method is also provided for determining the number of nodes that are detected based on a check node message and n derived from the received signal. int +n VN The method provided corresponds to the calculation of a variable node message performed at step 421 .

[0232] Figure 5 is a diagram illustrating the calculation of a variable node component of a variable node message U according to some embodiments of the present disclosure (where t=0,…,n VN-1) is a flowchart of a method, wherein the variable node component is iteratively determined based on a check node message V and n int +n VN An intrinsic reliability measure determines a variable node component at each iteration.

[0233] At step 501, a check node message V may be received, which includes: CN Check Node Component (where i = 0,…,n CN -1), and n int The most reliable intrinsic symbol x l ∈GF(q) associated with n int Intrinsic reliability measure I + (x l ), and n associated with the symbol included in the check node message V CN Intrinsic reliability measure

[0234] According to some embodiments, n may be received serially or sequentially. CN A check node component is provided so that the check node component is received at each iteration (eg, at each clock cycle).

[0235] Based on the check node message V and the inherent reliability metric I + (x l )and Exported n int +n VN Auxiliary components are used to determine the variable node components. One or more auxiliary components are processed at each iteration. Can include auxiliary symbols and associated with the symbol Auxiliary reliability measure

[0236] At step 503, the check node message V and the inherent reliability metric associated with the symbol included in the check node message V may be used to determine the reliability of the symbol. Determine the first auxiliary message U 1aux .

[0237] In some embodiments, the first assistance message U 1aux Can include CN Auxiliary Component where i=0,…,n CN -1, according to equation (5), the auxiliary symbol Determined by checking the symbol included in the node message, and according to equation (6), with the auxiliary symbol Associated auxiliary reliability measures By pairing with auxiliary symbols Associated intrinsic reliability measures and include in the check node component Reliability measures in Apply addition operations to equal auxiliary symbols Symbol Determined in association.

[0238] At step 505, the int The most reliable n int Symbol x l ∈GF(q) associated with the intrinsic reliability measure I + (x l ) to determine the second auxiliary message U 2aux .

[0239] In some embodiments, the second auxiliary message U 2aux Can include int Auxiliary Component (where l=0,…,n int -1), according to equation (7), the second auxiliary message U 2aux Auxiliary symbols included in According to the highest or lowest inherent reliability metric I + (x l )(where l=0,…,n int -1) The most reliable intrinsic symbol x associated with l is determined, and according to equation (8), with the second auxiliary message U 2aux Auxiliary symbols included in Associated reliability measures By applying the addition operation to the reference reliability measure and to the intrinsic symbol x l The associated intrinsic reliability measure I + (x l ) to determine.

[0240] According to some embodiments, at least a portion of the intrinsic reliability metrics I have been pre-calculated and stored. + (x l )(where x l ∈GF(q)) (e.g. in Figure 4 The intrinsic reliability metric may be loaded from the storage unit, calculated off-line during the initialization phase shown, the intrinsic reliability metric being loaded each time the calculation of the auxiliary component of the first or second auxiliary message is required.

[0241] In other embodiments, the inherent reliability metric may be calculated online (ie, during the decoding phase) in response to an inherent reliability metric request delivered whenever an inherent reliability metric is required for calculating the assistance component of the first or second assistance message.

[0242] In other embodiments, at least a portion of the inherent reliability metric may be calculated offline, and at least a portion of the inherent reliability metric may be calculated online in response to a delivered inherent reliability metric request.

[0243] The auxiliary components of the recombined first and second auxiliary messages may not be sorted (due to the calculation of the inherent reliability metric involved) and may include redundant symbols. Therefore, sorting and redundancy elimination operations are required to generate variable node components including the most reliable different symbols from the auxiliary components.

[0244] At step 507, n may be iteratively determined based on the assistance components included in the first and second assistance messages. VN variable node components, the variable node components being determined by processing at each iteration at least an auxiliary component extracted from the first or second auxiliary message, the processing comprising iteratively sorting the auxiliary components according to a given order of auxiliary reliability metrics and retaining a predefined number n of auxiliary symbols comprising all mutually distinct and most reliable symbols VN auxiliary component.

[0245] Figure 6 is a flowchart illustrating a sorting and redundancy elimination method used at step 507 according to some embodiments of the present disclosure, the sorting and redundancy elimination method being used to determine n based on the auxiliary components included in the first and second auxiliary messages VN variable node components, where sorting and redundancy elimination are performed simultaneously during a predefined number of iterations.

[0246] In an embodiment where iterations are performed during a clock cycle, the ordering and redundancy elimination requires Δ=n CN +n int The proposed architecture reduces latency by one clock cycle and reduces the memory required to compute variable node components, thus resulting in a more efficient architecture for variable node processing in terms of computational load, latency, and memory.

[0247] Furthermore, in pipelined embodiments, where the check node components are continuously received in-line (i.e., the check node components are received at each iteration of the sorting and redundancy elimination process), the latency of variable node message generation in terms of the number of clock cycles can be advantageously reduced to Δ=1+n int .

[0248] According to some embodiments, the sorting and redundancy elimination method may be based on performing n VNCurrent candidate components (where j = 1,…,n VN ) is determined based on:

[0249] - at least the auxiliary component C extracted from the first or second auxiliary message aux Auxiliary symbols included in The candidate component C determined in the previous iteration j At least one of the candidate symbols included in The comparison performed between

[0250] - at least the auxiliary component C extracted from the first or second auxiliary message aux Auxiliary reliability measures included in The candidate component C determined in the previous iteration j At least one of the candidate reliability The comparison performed between .

[0251] Depending on the comparison result, a control action may be decided at each iteration to determine the current candidate component by updating the candidate component predetermined at the previous iteration. The control action may include an initialization action, a retention action, an insertion action, or a shift action.

[0252] At step 601, the initialization component C init To execute the function used to initialize n VN Candidate component C j (where j = 1,…,n VN ) and n VN The current candidate component C cand,j The initialization action makes the candidate symbols and the current candidate symbols according to is equal to the initialization symbol and is equal to the candidate symbol Associated reliability measures and associated with the current candidate symbol The reliability measurement is based on is equal to the initial reliability measure.

[0253] At step 603 , initialization of the number of iterations of the sorting and redundancy elimination process may be performed according to Δ=0. In embodiments where iterations are performed during clock cycles, the number of iterations of the sorting and redundancy elimination process may correspond to the sorting and redundancy elimination processing time period, i.e., the delay in terms of the number of clock cycles.

[0254] At step 605, the number of iterations Δ of the sorting and redundancy elimination process can be checked to see whether it reaches n. CN +n int To control the total number n of auxiliary components included in the first and second auxiliary componentsCN +n int processing.

[0255] If it is determined at step 605 that Δ=n CN +n int , then this means that all auxiliary components included in the first and second auxiliary messages have been processed. Therefore, at step 607, the sorting and redundancy elimination operations can be stopped, and n VN The variable node component is set as the current candidate component (ie, the last updated candidate component).

[0256] If it is determined at step 605 that Δ≠n CN +n int , more precisely Δ <n CN +n int , there is at least one auxiliary component included in the first auxiliary message or the second auxiliary message that has not been processed during the sorting and redundancy elimination process. Therefore, at step 609, at least one auxiliary component extracted from the first or second auxiliary message may be received. (unprocessed auxiliary component). Steps 611 to 623 may be performed to determine n VN The current candidate component C cand,j , where j = 1,…,n VN .

[0257] The following description will be made with reference to processing the auxiliary component at each iteration. It will be readily appreciated by the skilled person that various embodiments of the present disclosure are applicable to processing of two or more auxiliary components at each of one or more iterations.

[0258] At step 611, a predefined candidate component C0 may be received, and the following comparison may be performed: between the received auxiliary component C0 extracted from the first or second auxiliary component aux Auxiliary symbols included in With the candidate component C j (where j = 1,…,n VN ) A symbol comparison between each of the (where j = 1,…,n VN ) Comparison of reliability measures between each of the .

[0259] Control actions may be performed at steps 617, 621, and 623 to determine n in parallel depending on the results of the sign and reliability metric comparisons. VN The current candidate component C cand,j (where j = 1,…,n VN). More specifically:

[0260] - Under the following conditions, an insertion action may be performed at step 621 to insert the current candidate component C cand,j Set equal to the auxiliary component C aux : If the auxiliary component C is determined at step 613 aux Auxiliary symbols included in Non-redundant, where the candidate component C determined in the previous iteration m No symbols are included (where m=1, ..., j-1) (i.e., if it is determined at step 613 Where m=1, ..., j-1), and at step 615, the auxiliary component C is determined aux Auxiliary symbols included in Than the candidate component C determined in the previous iteration j-1 Symbols included in reliable, and determine the auxiliary symbol at step 619 Than the candidate component C determined in the previous iteration j Symbols included in unreliable (i.e., if it is determined at step 615 of the current iteration that And at step 619, determine ). In the comparison involving index j=1, the predefined candidate component C0 is considered. According to the insertion action, the current candidate component C can be determined by replacing the candidate component pre-selected during the previous iteration with the auxiliary component. cand,j , so that and

[0261] - Under the following conditions, a shift action may be performed at step 615 to shift the current candidate component C cand,j Set equal to the candidate component C determined at the previous iteration j-1 : If the auxiliary component C is determined at step 613 aux Auxiliary symbols included in Non-redundant, where the candidate component C determined in the previous iteration m (where m = 1, ..., j-1) does not include any symbol (That is, if it is determined at step 613 Where m=1, ..., j-1), and at step 615, it is determined that the auxiliary component C aux Auxiliary symbols included in Than the candidate component C determined in the previous iteration j-1 Symbols included in reliable (i.e., if it is determined at step 615 of the current iteration that ). According to the shift action, the current candidate component C can be determined cand,j , so that as well as

[0262] - A retention action may be performed at step 623 to convert the current candidate component C cand,j Set equal to the candidate component C determined at the previous iteration j To determine the current candidate component:

[0263] * If it is determined at step 613 that the auxiliary component C aux Auxiliary symbols included in Non-redundant, where there is no candidate component C determined in the previous iteration m (where m=1, ..., j-1) (ie, if at each step 611 of each of the previous iterations of index m varying between 1 and j-1, it is determined ), and at step 619, determine the auxiliary component C aux Auxiliary symbols included in Than the candidate component C determined in the previous iteration j Symbols included in unreliable (i.e., if for the ascending order of the reliability metric, it is determined at step 615 of the previous iteration that );or

[0264] * If it is determined at step 613 that the auxiliary component C aux Auxiliary symbols included in Redundancy, where the candidate component C determined in the previous iteration m A symbol included in one of where m varies between 1 and j-1 (i.e., if at least one index m taking a value between 1 and j-1 was determined at step 613 of at least one previous iteration, ).

[0265] According to the retention action, the current candidate component C cand,j can be set equal to the candidate component pre-selected during the previous iteration, such that and

[0266] Step 625 may be performed to increment the number of iterations performed according to Δ=Δ+1.

[0267] The methods and apparatus described herein may be implemented by various means. For example, these techniques may be implemented in hardware, software, or a combination thereof. For hardware implementations, the processing elements of iterative decoder 123 may be implemented, for example, according to a hardware-only configuration (e.g., in one or more FPGAs, ASICs, or VLSI integrated circuits with corresponding memory) or according to a configuration using both VLSI and DSP.

[0268] While embodiments of the present disclosure have been illustrated by the description of various examples, and while these embodiments have been described in considerable detail, it is not the intention of the applicant to restrict or in any way limit the scope of the appended claims to such detail.

[0269] In particular, although the description of some embodiments of the present disclosure has been performed with reference to a specific implementation of the EMS algorithm, it should be noted that the present disclosure may also be applied to other iterative decoding algorithms such as the min-max algorithm.

[0270] Furthermore, although some embodiments of the present disclosure have been described with reference to error correction codes constructed on Galois fields, those skilled in the art will readily appreciate that the proposed embodiments may also be applied to any non-binary LDPC code and any non-binary graph error correction code constructed on a non-commutative group, such as a polynomial code (e.g., a cyclic code).

[0271] Furthermore, even though the present disclosure has some advantages in application to communication systems, it should be noted that the present disclosure is not limited to such communication devices and can be integrated in many devices such as data storage devices.

[0272] The methods described herein may be implemented by computer program instructions supplied to a processor of any type of computer to produce a machine having a processor that executes instructions to implement the functions / actions specified herein. These computer program instructions may also be stored in a computer-readable medium that can direct a computer to operate in a particular manner. To this end, the computer program instructions may be loaded onto a computer to cause the execution of a series of operational steps and thereby produce a computer-implemented process such that the executed instructions provide a process for implementing the functions specified herein.

Claims

1. A variable node processing device (31) for a non-binary error correction code decoder, the decoder being configured to determine an estimate of a codeword from a sequence received from a transmitter, the variable node processing device (31) being configured to: receive a check node message and an inherent reliability metric from a check node processing unit included in the decoder, and generate a variable node message based on an auxiliary component extracted from a first auxiliary message or a second auxiliary message, the first auxiliary message being derived from the one check node message and the inherent reliability metric, and the second auxiliary message being derived from at least a portion of the inherent reliability metric, the inherent reliability metric being derived from a received signal, the auxiliary component comprising auxiliary symbols and auxiliary reliability metrics associated with the auxiliary symbols, wherein the variable node processing device (31) comprises: - a sorting and redundancy elimination unit (313) configured to iteratively process the auxiliary components and determine the components of the variable node message by iteratively sorting the auxiliary components according to a given order of the auxiliary reliability metrics and retaining a predefined number of auxiliary components including the most reliable and all mutually different auxiliary symbols, wherein each iteration processes one auxiliary component.

2. A variable node processing device (31) according to claim 1, wherein the variable node processing device (31) includes a computing unit (311), and the computing unit (311) is configured to: determine the first auxiliary message based on the check node message and the inherent reliability metric, and determine the second auxiliary message based on the inherent reliability metric, and the inherent reliability metric is associated with a predefined number of most reliable inherent symbols and a reference reliability metric.

3. The variable node processing device (31) according to claim 2, wherein the check node message comprises check node components, each check node component comprises a symbol and a reliability metric associated with the symbol, and the calculation unit (311) is configured to: - determining an auxiliary symbol included in the first auxiliary message according to a symbol included in the check node message, the auxiliary symbol being selected from the symbols included in the check node component, and - determining each auxiliary reliability metric associated with an auxiliary symbol included in said first auxiliary message by applying an addition operation on a predefined algebraic structure, said addition operation being applied in association with a selected auxiliary symbol to an intrinsic reliability metric associated with said auxiliary symbol and to a reliability metric included in a check node component.

4. The variable node processing device (31) according to any one of the preceding claims 2 or 3, further configured to: receive a reference reliability metric determined in the non-binary error correction code decoder based on an offset value and the check node component including the least reliable symbol, the calculation unit (311) being configured to: - determining said auxiliary symbol included in said second auxiliary message according to a predefined number of most reliable inherent symbols associated with the lowest inherent reliability measure or the highest inherent reliability measure, the auxiliary symbol being equal to an inherent symbol among said most reliable inherent symbols; and - determining said auxiliary reliability metric associated with an auxiliary symbol included in said second auxiliary message by applying an addition operation on a predefined algebraic structure, said addition operation being applied to said reference reliability metric and to said intrinsic reliability metric, said intrinsic reliability metric being associated with said intrinsic symbol being equal to said auxiliary symbol.

5. The variable node processing device (31) according to claim 3, wherein the predefined algebraic structure is selected from the group consisting of a real number field, an integer field, and a natural number field.

6. The variable node processing device (31) according to claim 4, wherein the offset value is determined in the non-binary error correction code decoder according to a predefined decoding performance criterion.

7. A variable node processing device (31) according to the preceding claim 4, wherein the variable node processing device (31) is configured to: exchange variable node messages and check node messages with at least one check node processing unit (33) during multiple iterations, the offset value being determined in the non-binary error correction code decoder depending on the number of iterations, and different offset values ​​being dynamically determined at each of the iterations.

8. The variable node processing device (31) according to any one of claims 2 to 3, wherein the sorting and redundancy elimination unit (313) comprises: - a plurality of multiplexers (315-j); - a plurality of reliability metric comparators (319-j), and - a plurality of sign comparators (317-j); Each multiplexer (315-j) is associated with a reliability metric comparator (319-j) and a symbol comparator (317-j), and each multiplexer (315-j) is configured to: determine the current candidate component depending on the comparison performed by the multiple symbol comparators (317-j) and the multiple reliability metric comparators (319-j) at each iteration, and the sorting and redundancy elimination unit (313) is configured to generate a variable node component based on the candidate components including the most reliable and all different symbols after processing all the auxiliary components included in the first auxiliary message and the second auxiliary message.

9. The variable node processing device (31) according to claim 8, wherein the candidate components include candidate symbols and candidate reliability metrics associated with the candidate symbols, each multiplexer (315-j) is configured to: receive at least the auxiliary component extracted from the first auxiliary message or the second auxiliary message and a predefined initialization component at each iteration, the predefined initialization component including an initialization symbol and an initialization reliability metric associated with the initialization symbol, each multiplexer (315-j) is configured to determine a current candidate component at each iteration by selecting a component from among: the at least auxiliary component, the predefined initialization component, and a component corresponding to a candidate component determined by the multiplexer (315-j) at a previous iteration, and: - the reliability metric comparator (319-j) associated with each multiplexer (315-j) is configured to: perform a comparison between the auxiliary reliability metric included in the at least auxiliary component and the candidate reliability metric included in the candidate component determined by each multiplexer (315-j) at a previous iteration, and -The symbol comparator (317-j) associated with each multiplexer (315-j) is configured to check the redundancy of symbols by performing a comparison between the auxiliary symbol included in the at least auxiliary component and the candidate symbol included in the candidate component determined by each multiplexer (315-j) at a previous iteration.

10. The variable node processing device (31) according to claim 9, wherein at each iteration, each multiplexer (315-j) is configured to: - performing a retaining action by setting the current candidate component equal to the candidate component determined at the previous iteration: * if it is determined that the auxiliary symbol included in the at least auxiliary component is not redundant, wherein none of the candidate components was determined at a previous iteration, and it is determined that the auxiliary symbol included in the at least auxiliary component is less reliable than the symbol included in the candidate component determined by the multiplexer (315-j) at a previous iteration; or * if it is determined that the auxiliary symbol included in the at least auxiliary component is redundant, wherein at least one of the symbols included in one of the candidate components was determined by at least one of the multiplexers (315-m) at a previous iteration, wherein m varies between 1 and j-1; - if it is determined that the auxiliary symbol included in the auxiliary component is not redundant, wherein there is no any of the symbols included in the candidate components determined by the multiplexer (315-m) at the previous iteration, where m varies between 1 and j-1, and it is determined that the auxiliary symbol included in the auxiliary component is more reliable than the symbol included in the candidate component determined by the multiplexer (315-j) at the previous iteration, and the auxiliary symbol is less reliable than the symbol included in the candidate component determined by the multiplexer (315-(j-1)) at the previous iteration, then an insertion action is performed by setting the current candidate component equal to the auxiliary component; -If it is determined that the auxiliary symbol included in the auxiliary component is not redundant, wherein there is no any one of the symbols included in the candidate component determined by the multiplexer (315-m) at the previous iteration, where m=1,…,j-1, and it is determined that the auxiliary symbol included in the auxiliary component is more reliable than the symbol included in the candidate component determined by the multiplexer (315-j) at the previous iteration, and the auxiliary symbol is more reliable than the symbol included in the candidate component determined by the multiplexer (315-(j-1)) at the previous iteration, then a shifting action is performed by setting the current candidate component equal to the candidate component determined by the multiplexer (315-(j-1)) at the previous iteration.

11. The variable node processing device (31) according to claim 9, wherein each of the plurality of multiplexers (315-j) is configured to perform an initialization action at a first iteration by setting the current candidate component equal to the initialization component.

12. The variable node processing device (31) according to any one of the preceding claims 1-3 is further configured to: receive the inherent reliability metric online from the data processing unit (23) in the non-binary error correction code decoder in response to an inherent reliability metric generation request delivered by the variable node processing device (31).

13. The variable node processing device (31) according to any one of the preceding claims 1-3, further configured to: load at least a part of the inherent reliability metric from a storage unit (21) at each iteration.

14. A method implemented in a variable node processing unit included in a non-binary error correction code decoder, the decoder being configured to determine an estimate of a codeword from a sequence received from a transmitter, the method comprising: A check node message and an inherent reliability metric are received from a check node processing unit included in the decoder, and a variable node message is generated based on auxiliary components extracted from a first auxiliary message and a second auxiliary message, the first auxiliary message being derived from a check node message and an inherent reliability metric, and the second auxiliary message being derived from at least a portion of the inherent reliability metric, the inherent reliability metric being derived from a received signal, the auxiliary components comprising auxiliary symbols and auxiliary reliability metrics associated with the auxiliary symbols, wherein the method comprises: - components of the variable node message are determined by a sorting and redundancy elimination unit (313) by iteratively processing the auxiliary components for sorting them according to a given order of the auxiliary reliability metrics and retaining a predefined number of auxiliary components including the most reliable and all mutually different auxiliary symbols, wherein one auxiliary component is processed per iteration.

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