Scan signal driver and display device including the same

Abstract

This invention relates to a scan signal driver and a display device including the scan signal driver. The scan signal driver includes: a plurality of stages for outputting scan signals and sensing signals, wherein a k-th stage of the plurality of stages is connected to a k-th scan signal line and a k-th sensing signal line, and wherein the k-th stage includes: a first output unit configured to output a scan clock signal input to a first scan clock terminal as a k-th scan signal to the k-th scan signal line, and to output a sensing clock signal input to a first sensing clock terminal as a k-th sensing signal to the k-th sensing signal line, when the pull-up node has a gate on-voltage; and a second output unit configured to output a carry clock signal input to a first carry clock terminal as a k-th carry signal to a carry output terminal, when the pull-up node has a gate on-voltage.

Description

Technical Field

[0001] An exemplary embodiment of the present invention relates to a scan signal driver and a display device including the scan signal driver. Background Technology

[0002] With the development of an information-oriented society, display devices have become ubiquitous. For example, display devices are used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs. Display devices can be flat panel displays such as liquid crystal displays, field emission displays, and organic light-emitting diode displays.

[0003] The display device may include a display panel, which includes data lines, scan signal lines, multiple pixels connected to the data lines and scan signal lines, a scan signal driver for supplying scan signals to the scan signal lines, and a data driver for supplying data voltage or data signals to the data lines. The scan signal driver may be located in a non-display area of ​​the display panel.

[0004] Recently, ultra-high resolution display devices, such as 8K Ultra High Definition (UHD) televisions with a resolution of 7,680 × 4,320, have been developed. In such display devices, the number of pixels increases, and correspondingly, the area of ​​the scan signal drivers arranged in the non-display area of ​​the display panel may increase. As a result, the non-display area of ​​the display panel increases, and therefore, the bezel width of the display device increases. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, a scan signal driver includes: a plurality of stages for outputting scan signals and sensing signals, wherein a k-th stage of the plurality of stages is connected to a k-th scan signal line and a k-th sensing signal line, and wherein the k-th stage includes: a first output unit configured to output a scan clock signal input to a first scan clock terminal as a k-th scan signal to the k-th scan signal line and output a sensing clock signal input to a first sensing clock terminal as a k-th sensing signal to the k-th sensing signal line when the pull-up node has a gate on voltage; and a second output unit configured to output a carry clock signal input to a first carry clock terminal as a k-th carry signal to a carry output terminal when the pull-up node has a gate on voltage.

[0006] According to an exemplary embodiment of the present invention, a scan signal driver includes: a plurality of stages for outputting scan signals and sensing signals, wherein a first stage of the plurality of stages is connected to a first scan signal line and a first sensing signal line, and wherein the first stage includes: a first output unit configured to output a scan clock signal input to a first scan clock terminal as a first scan signal to the first scan signal line as a first scan signal when the pull-up node has a gate on voltage, and to output a sensing clock signal input to a first sensing clock terminal as a first sensing signal to the first sensing signal line; and a sensing controller configured to apply a gate on voltage to the pull-up node during a vertical blank period of the frame time when a sensing control signal having a gate on voltage is input to the sensing control terminal during an effective period of the frame time.

[0007] According to an exemplary embodiment of the present invention, a display device includes: a display panel including data lines, scan signal lines, and sensing signal lines, and pixels connected to the data lines, scan signal lines, and sensing signal lines; a data driver for applying a data voltage to the data lines; and a scan signal driver including multiple stages for applying a scan signal to the scan signal lines and applying a sensing signal to the sensing signal lines, wherein a first stage of the multiple stages is connected to a first scan signal line and a first sensing signal line, and wherein the first stage includes: a first output unit configured to output a scan clock signal input to a first scan clock terminal as a first scan signal to the first scan signal line and output a sensing clock signal input to a first sensing clock terminal as a first sensing signal to the first sensing signal line when the pull-up node has a gate on voltage; and a second output unit configured to output a carry clock signal input to a first carry clock terminal as a first carry signal to a carry output terminal when the pull-up node has a gate on voltage. Attached Figure Description

[0008] The above and other features of the inventive concept will become more apparent from the detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings.

[0009] Figure 1 This is a perspective view of a display device according to an exemplary embodiment of the present invention.

[0010] Figure 2A This is a plan view illustrating an exemplary display device according to a concept of the present invention.

[0011] Figure 2B This is a block diagram illustrating an exemplary display device according to a concept of the present invention.

[0012] Figure 3This is a circuit diagram showing in detail an exemplary embodiment of a sub-pixel according to the concept of the present invention.

[0013] Figure 4 This is a diagram illustrating the driving timing of sub-pixels in the Nth frame time period and the N+1th frame time period according to an exemplary embodiment of the present invention.

[0014] Figure 5 This is a waveform diagram illustrating the k-th scan signal to the (k+2)-th scan signal and the k-th sensing signal to the (k+2)-th sensing signal during the effective time period of the N-th frame time period, according to an exemplary embodiment of the present invention.

[0015] Figure 6 This is a waveform diagram illustrating the k-th scan signal to the (k+2)-th scan signal and the k-th sensing signal to the (k+2)-th sensing signal during the vertical blank period of the N-th frame time, according to an exemplary embodiment of the present invention.

[0016] Figure 7 This is a view illustrating an exemplary scan signal driver according to a concept of the present invention.

[0017] Figure 8 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0018] Figure 9A This is a waveform diagram illustrating, according to an exemplary embodiment of the present invention, the carry clock signal, scan clock signal, sensing clock signal, sensing control signal, (k-2)th carry signal, kth carry signal, (k+2)th carry signal, voltage of pull-up node, voltage of pull-down node, kth scan signal and kth sensing signal during the effective time period of the Nth frame.

[0019] Figure 9B This is a waveform diagram illustrating the carry clock signal, scan clock signal, and sense clock signal during the effective time period of the Nth frame, according to an exemplary embodiment of the present invention.

[0020] Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 This is a circuit diagram illustrating the operation of the kth level during the first to seventh time periods of the effective time period, according to an exemplary embodiment of the present invention.

[0021] Figure 17This is a waveform diagram illustrating, according to an exemplary embodiment of the present invention, the carry clock signal, scan clock signal, sensing clock signal, sensing control signal, (k-2)th carry signal, kth carry signal, (k+2)th carry signal, voltage of pull-up node, voltage of pull-down node, kth scan signal and kth sensing signal during the effective period and vertical blank period of the Nth frame.

[0022] Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 This is a circuit diagram illustrating the operation of the kth level during the 1' to 7' time periods of the vertical blank period, according to an exemplary embodiment of the present invention.

[0023] Figure 25 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0024] Figure 26 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0025] Figure 27 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0026] Figure 28 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0027] Figure 29 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0028] Figure 30 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0029] Figure 31 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0030] Figure 32 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0031] Figure 33 This is a view illustrating another scan signal driver according to an exemplary embodiment of the concept according to the present invention.

[0032] Figure 34This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0033] Figure 35 This is a waveform diagram illustrating, according to an exemplary embodiment of the present invention, the carry clock signal, scan clock signal, sensing clock signal, sensing control signal, (k-2)th carry signal, kth carry signal, (k+2)th carry signal, voltage of pull-up node, voltage of pull-down node, 2k-1th scan signal, 2kth scan signal, 2k-1th sensing signal, and 2kth sensing signal during the effective time period.

[0034] Figure 36 , Figure 37 , Figure 38 , Figure 39 , Figure 40 , Figure 41 and Figure 42 This is a circuit diagram illustrating the operation of the kth level during the first to seventh time periods of the effective time period, according to an exemplary embodiment of the present invention.

[0035] Figure 43 This is a waveform diagram illustrating, according to an exemplary embodiment of the present invention, the carry clock signal, scan clock signal, sensing clock signal, sensing control signal, (k-2)th carry signal, kth carry signal, (k+2)th carry signal, voltage of pull-up node, voltage of pull-down node, 2k-1th scan signal, 2kth scan signal, 2k-1th sensing signal, and 2kth sensing signal during a blank period.

[0036] Figure 44 , Figure 45 , Figure 46 , Figure 47 , Figure 48 , Figure 49 and Figure 50 This is a circuit diagram illustrating the operation of the kth level during the 1' to 7' time periods of the vertical blank period, according to an exemplary embodiment of the present invention.

[0037] Figure 51 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0038] Figure 52 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0039] Figure 53 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0040] Figure 54This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0041] Figure 55 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention. Detailed Implementation

[0042] Exemplary embodiments of the inventive concept will be described more fully below with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0043] It will be understood that when a component, such as a membrane, region, layer, or element, is referred to as being "on," "connected to," "coupled to," or "adjacent to" another component, it can be directly on, directly connected to, directly coupled to, or immediately adjacent to that other component, or there may be intermediate components present. It will also be understood that when a component is referred to as being "between" two components, it can be the only component between the two components, or there may be one or more intermediate components present. It will also be understood that when a component is referred to as "covering" another component, it can be the only component covering that other component, or one or more intermediate components may also cover that other component. Other terms used to describe relationships between components can be interpreted in a similar manner.

[0044] It will be further understood that the description of a feature or aspect within each exemplary embodiment may be used for other similar features or aspects in other exemplary embodiments, unless the context otherwise explicitly indicates otherwise.

[0045] As used in this article, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0046] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “down,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature illustrated in the figures and another element or feature. It will be understood that, in addition to the orientation depicted in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below,” “under,” or “down” to other elements or features will subsequently be oriented “above” to other elements or features. Thus, the exemplary terms “below” and “down” can include both above and below orientations.

[0047] Figure 1 This is a perspective view of a display device according to an exemplary embodiment of the present invention. Figure 2A This is a plan view illustrating an exemplary display device according to a concept of the present invention. Figure 2BThis is a block diagram illustrating an exemplary display device according to a concept of the present invention.

[0048] As used herein, the terms “above,” “top,” and “upper surface” may refer to the upper side of display panel 110 (e.g., the side indicated by the arrow in the Z-axis direction), while the terms “below,” “bottom,” and “lower surface” may refer to the lower side of display panel 110 (e.g., the opposite side in the Z-axis direction). As used herein, when viewing display panel 110 from above, the terms “left,” “right,” “upper,” and “lower” may indicate relative positions. For example, “left” may refer to the opposite direction indicated by the arrow in the X-axis direction, “right” may refer to the direction indicated by the arrow in the X-axis direction, “upper” may refer to the direction indicated by the arrow in the Y-axis direction, and “lower” may refer to the opposite direction indicated by the arrow in the Y-axis direction.

[0049] As used herein, the display device 10 of an exemplary embodiment of the present invention is used to display moving or still images. The display device 10 can be used as a display screen for portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs) as well as for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IoT). In the following description, although the display device 10 of an exemplary embodiment of the present invention is a medium or large display device including a plurality of source drivers 121, this is merely illustrative. For example, the display device 10 of an exemplary embodiment of the present invention may be a small display device including a single source driver 121, and may not include a flexible film, a source circuit board, or cables. Furthermore, when the display device 10 is a small display device, the source driver 121 and the timing controller 170 may be integrated into a single integrated circuit and arranged on a circuit board or attached to a first substrate 111 of the display panel 110. Examples of medium or large display devices include monitors, televisions, etc., while examples of small display devices include smartphones, tablet PCs, etc.

[0050] Reference Figure 1 , Figure 2A and Figure 2B The display device 10 includes a display panel 110, a data driver 120 including a source driver 121, a flexible film 122, a source circuit board 140, a first cable 150, a control circuit board 160, a timing controller 170, a power supply 180, and a scan signal driver 200.

[0051] When viewed from above, the display panel 110 can have a rectangular shape. For example, as Figure 2A As shown, when viewed from above, the display panel 110 can be a rectangle with a longer side in a first direction (X-axis direction) and a shorter side in a second direction (Y-axis direction). The corner where the longer side in the first direction (X-axis direction) intersects the shorter side in the second direction (Y-axis direction) can be a right angle or a circle with a predetermined curvature. When viewed from above, the shape of the display panel 110 is not limited to a rectangular shape, but can be various polygonal shapes, circular shapes, or elliptical shapes. Furthermore, although in Figure 2A The display panel 110 is flat, but this is only illustrative. For example, the display panel 110 may include a curved portion bent at a predetermined curvature.

[0052] The display panel 110 may include a first substrate 111 and a second substrate 112. The second substrate 112 may face the first substrate 111. The first substrate 111 and the second substrate 112 may be rigid or flexible. The first substrate 111 may be made of glass or plastic. The second substrate 112 may be formed of glass, plastic, an encapsulation film, or a barrier film. Alternatively, the second substrate 112 may be omitted.

[0053] Furthermore, the display panel 110 may be an organic light-emitting display panel using organic light-emitting diodes (LEDs), a quantum dot light-emitting display panel including a quantum dot light-emitting layer, an inorganic light-emitting display panel including inorganic semiconductors, or a micro light-emitting display panel using micro light-emitting diodes. In the following description, an organic light-emitting display panel is used as the display panel 110. However, it is to be understood that the inventive concept is not limited thereto.

[0054] The display panel 110 may include a display area DA in which sub-pixels SP are positioned to display images, and a non-display area NDA serving as a peripheral area of ​​the display area DA. In the display area DA, scan signal lines SCL, SSL, data lines DL, and a first power supply voltage line VDDL connected to the sub-pixels SP, as well as the sub-pixels SP, may be arranged. The scan signal lines SCL and SSL may extend in the display area DA in a first direction (X-axis direction). The data line DL may extend in the display area DA in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). The first power supply voltage line VDDL may extend in the display area DA in the second direction (Y-axis direction).

[0055] Each sub-pixel SP can be connected to one of the scan signal lines SCL, one of the data lines DL, and one of the sensing signal lines SSL. Figure 2AIn this design, each sub-pixel SP is connected to a scan signal line SCL, a data line DL, and a sensing signal line SSL, but the inventive concept is not limited thereto. Sub-pixels SP can also be connected together to a first power supply voltage line VDDL.

[0056] Each sub-pixel SP may include a driving transistor, at least one switching transistor, a light-emitting element, and a capacitor. The switching transistor may be turned on in response to a scan signal from the scan signal line SCL, allowing a data voltage from the data line DL to be applied to the gate electrode of the driving transistor. When the data voltage is applied to the gate electrode of the driving transistor, the driving transistor can supply a driving current to the light-emitting element, allowing light to be emitted. The driving transistor and at least one switching transistor may be thin-film transistors. The light-emitting element may emit light according to the driving current from the driving transistor. The light-emitting element may be an organic light-emitting diode including a first electrode, an organic emitting layer, and a second electrode. The capacitor can maintain a constant data voltage applied to the gate electrode of the driving transistor.

[0057] The non-display area NDA may include the area extending from the outer edge of the display area DA to the edge of the display panel 110. In the non-display area NDA, a scan signal driver 200 for applying scan signals to scan signal line SCL and sensing signals to sensing signal line SSL may be arranged.

[0058] The scan signal driver 200 can be connected to the display panel 110 via multiple scan control lines (not shown). The scan signal driver 200 can receive a scan control signal SCS from the timing controller 170. The scan control signal SCS may include multiple clock signals, sensing control signals, gate on-voltage, and gate off-voltage. The scan signal driver 200 can generate scan signals and sensing signals according to the scan control signal SCS, and can output the scan signals and sensing signals to the scan signal line SCL and the sensing signal line SSL. The scan signal driver 200 is positioned on both sides of the display area DA (e.g., on...). Figure 2A The example shown is located in each of the non-display areas NDA (to the left and right of the display area DA), but the inventive concept is not limited thereto. For example, the scan signal driver 200 may be located in the non-display area NDA on one side of the display area DA (e.g., the left or right side of the display area DA).

[0059] One end of each of the flexible films 122 can be attached to a first surface of the first substrate 111 of the display panel 110, while the other end of each of the flexible films 122 can be attached to the surface of a corresponding source circuit board 140. For example, because the second substrate 112 is smaller than the first substrate 111, one side of the first substrate 111 may not be covered by the second substrate 112 and may be exposed. The flexible film 122 can be attached to the side of the first substrate 111 exposed by not being covered by the second substrate 112. Each of the flexible films 122 may be attached to the first surface of the first substrate 111 and the surface of the corresponding source circuit board 140 using an anisotropic conductive film.

[0060] Each of the flexible films 122 can be a tape-on-film package or a chip-on-film assembly. The flexible films 122 can be bent so that they are located below the first substrate 111. In this case, the source circuit board 140, the first cable 150, and the control circuit board 160 can be arranged on the lower surface of the display panel 110. Although Figure 1 and Figure 2A The figure shows eight flexible films 122 attached to the first substrate 111 of the display panel 110, but the number of flexible films 122 is not limited to eight.

[0061] The source drivers 121 of the data driver 120 can be arranged on one surface of the corresponding flexible membrane 122. Each of the source drivers 121 can be implemented as an integrated circuit (IC). The data driver 120 converts digital video data DATA into analog data voltage according to the source control signal DCS from the timing controller 170, and supplies the analog data voltage to the data line DL through the flexible membrane 122.

[0062] Each of the source circuit boards 140 can be connected to the control circuit board 160 via a first cable 150. Each of the source circuit boards 140 may include a first connector 151 for connection to the first cable 150. Each of the source circuit boards 140 may be a flexible printed circuit board or a printed circuit board. The first cable 150 may be a flexible cable.

[0063] The control circuit board 160 can be connected to the source circuit board 140 via a first cable 150. To achieve this, the control circuit board 160 may include a second connector 152 for connecting to the first cable 150. The control circuit board 160 may be a flexible printed circuit board or a printed circuit board.

[0064] Despite Figure 1 and Figure 2A In the example shown, four first cables 150 connect the source circuit board 140 to the control circuit board 160, but the number of first cables 150 is not limited to four. Furthermore, although... Figure 1 and Figure 2ATwo source circuit boards 140 are shown, but the number of source circuit boards 140 is not limited to two.

[0065] Furthermore, when a small amount of flexible film 122 is present, the source circuit board 140 can be removed. In this case, the flexible film 122 can be directly connected to the control circuit board 160.

[0066] A timing controller 170 can be disposed on one surface of a control circuit board 160. The timing controller 170 can be implemented as an integrated circuit. The timing controller 170 receives digital video data DATA and timing signals from the system-on-a-chip (SoC) of the system circuit board. The timing controller 170 can generate a source control signal DCS for controlling the timing of the source driver 121 of the data driver 120, and a scan control signal SCS for controlling the timing of the scan signal driver 200 according to the timing signals. The timing controller 170 can output the scan control signal SCS to the scan signal driver 200, and can output the digital video data DATA and the source control signal DCS to the data driver 120.

[0067] Power supply 180 can generate a first power supply voltage and supply the first power supply voltage to a first power supply voltage line VDDL. Furthermore, power supply 180 can generate a second power supply voltage and supply the second power supply voltage to the cathode of the organic light-emitting diode (OLED) in each of the sub-pixels SP. The first power supply voltage can be a high-level voltage for driving the OLED, and the second power supply voltage can be a low-level voltage for driving the OLED. In other words, the first power supply voltage can have a higher level than the second power supply voltage. Additionally, power supply 180 can generate a reference voltage and supply the reference voltage to a reference voltage line connected to each of the sub-pixels SP.

[0068] Figure 3 This is a circuit diagram showing in detail an exemplary embodiment of a sub-pixel according to the concept of the present invention.

[0069] Reference Figure 3 Subpixel SP may include light-emitting element EL, driving transistor DT, first switching transistor ST1, second switching transistor ST2, and capacitor Cst.

[0070] The light-emitting element EL emits light proportional to the current supplied through the driving transistor DT. The light-emitting element EL can be, but is not limited to, an organic light-emitting diode (OLED). For example, the light-emitting element EL can be a quantum dot OLED, an inorganic OLED, or a micro OLED. When the light-emitting element EL is an organic OLED, it can include an anode, a hole transport layer, an organic light-emitting layer, an electron transport layer, and a cathode. When a voltage is applied to the anode and cathode, holes and electrons move through the hole transport layer and electron transport layer, respectively, to the organic light-emitting layer, causing them to combine in the organic light-emitting layer to emit light. The anode of the light-emitting element EL can be connected to the source electrode of the driving transistor DT, and the cathode of the light-emitting element EL can be connected to a second power supply voltage line VSSL, which is thus subjected to a low-level voltage lower than the high-level voltage.

[0071] The driving transistor DT regulates the current flowing through the first power supply voltage line VDDL based on the voltage difference between its gate and source electrodes. The first power supply voltage is supplied to the light-emitting element EL from the first power supply voltage line VDDL. The gate electrode of the driving transistor DT can be connected to the first electrode of the first switching transistor ST1, the source electrode of the driving transistor DT can be connected to the anode of the light-emitting element EL, and the drain electrode of the driving transistor DT can be connected to the first power supply voltage line VDDL, which is subjected to a high-level voltage.

[0072] The first switching transistor ST1 is turned on by the scan signal of the scan signal line SCL to connect the data line DL to the gate electrode of the driving transistor DT. The gate electrode of the first switching transistor ST1 can be connected to the scan signal line SCL, the first electrode of the first switching transistor ST1 can be connected to the gate electrode of the driving transistor DT, and the second electrode of the first switching transistor ST1 can be connected to the data line DL.

[0073] The second switching transistor ST2 is turned on by the sensing signal of the sensing signal line SSL to connect the reference voltage line RVL to the source electrode of the driving transistor DT. The gate electrode of the second switching transistor ST2 can be connected to the sensing signal line SSL, the first electrode of the second switching transistor ST2 can be connected to the reference voltage line RVL, and the second electrode of the second switching transistor ST2 can be connected to the source electrode of the driving transistor DT.

[0074] In each of the first switching transistor ST1 and the second switching transistor ST2, one of the first electrode and the second electrode can be the source electrode, and the other can be the drain electrode.

[0075] A capacitor Cst can be placed between the gate and source electrodes of the driving transistor DT. The capacitor Cst stores a voltage equal to the difference between the gate voltage and the source voltage of the driving transistor DT.

[0076] The driving transistor DT, as well as the first switching transistor ST1 and the second switching transistor ST2, can be thin-film transistors. Furthermore, although... Figure 3 The diagram shows that each of the driving transistor DT, the first switching transistor ST1, and the second switching transistor ST2 is implemented as an n-type metal-oxide-semiconductor field-effect transistor (MOSFET). However, it should be noted that the inventive concept is not limited thereto. The driving transistor DT, the first switching transistor ST1, and the second switching transistor ST2 can also be implemented as p-type MOSFETs.

[0077] Figure 4 This is a diagram illustrating the driving timing of sub-pixels in the Nth frame time period and the N+1th frame time period according to an exemplary embodiment of the present invention. Figure 5 This is a waveform diagram illustrating the k-th scan signal to the (k+2)-th scan signal and the k-th sensing signal to the (k+2)-th sensing signal during the effective time period of the N-th frame time period, according to an exemplary embodiment of the present invention. Figure 6 This is a waveform diagram illustrating the k-th scan signal to the (k+2)-th scan signal and the k-th sensing signal to the (k+2)-th sensing signal during the vertical blank period of the N-th frame time, according to an exemplary embodiment of the present invention.

[0078] Reference Figures 4 to 6 Each of the Nth frame time period and the N+1th frame time period includes an active time period ACT and a vertical blank time period VB. During the active time period ACT, a data voltage is applied to each of the sub-pixels SP. The vertical blank time period VB is an idle time period. For example, during the vertical blank time period VB, the source voltage of the drive transistor DT of each of the sub-pixels SP, which is connected to at least one scan signal line SCL, is sensed through a reference voltage line RVL.

[0079] The data driver 120 can apply a compensation data voltage to the data line DL during the active period ACT, compensating for the electron mobility of the driving transistor DT of each sub-pixel SP. The data driver 120 can also apply a sensing data voltage to the data line DL during the vertical blank period VB to compensate for the electron mobility of the driving transistor DT of each sub-pixel SP.

[0080] Furthermore, a reference voltage can be applied to the reference voltage line RVL during the active period ACT. During the vertical blank period VB, the reference voltage line RVL is connected to the analog-to-digital converter, and the source voltage of the driving transistor DT of each sub-pixel SP is converted into sensing data as digital data in the analog-to-digital converter via the reference voltage line RVL, so that it can be output to the timing controller 170.

[0081] The effective time period ACT can be longer than the vertical blank time period VB. The vertical blank time period VB of the Nth frame time period can be located between the effective time period ACT of the Nth frame time period and the effective time period ACT of the N+1th frame time period.

[0082] The scan signal driver 200 can sequentially apply scan signals to the scan signal line SCL during the active period ACT. For example... Figure 4 As shown, when the display panel 110 includes first scan signal lines SCL1 to nth scan signal lines SCLn (where n is a positive integer), the scan signal driver 200 can sequentially apply scan signals to the first scan signal lines SCL1 to nth scan signal lines SCLn. For example, as Figure 5 As shown, the scan signal driver 200 can apply a first scan signal SC1 of the gate on-voltage Von to the first scan signal line SCL1, then apply a second scan signal SC2 of the gate on-voltage Von to the second scan signal line SCL2, then apply a third scan signal SC3 of the gate on-voltage Von to the third scan signal line SCL3, and so on.

[0083] Furthermore, the scan signal driver 200 can sequentially apply sensing signals to the sensing signal lines SSL during the effective period ACT. When the display panel 110 includes first sensing signal lines to the nth sensing signal line, sensing signals can be sequentially applied from the first sensing signal line to the nth sensing signal line. For example, as Figure 5 As shown, the scan signal driver 200 can apply a first sensing signal SS1 of the gate on-voltage Von to the first sensing signal line SSL1, then apply a second sensing signal SS2 of the gate on-voltage Von to the second sensing signal line SSL2, then apply a third sensing signal SS3 of the gate on-voltage Von to the third sensing signal line SSL3, and so on.

[0084] Conversely, the scan signal driver 200 can apply a scan signal to at least one scan signal line SCL and a sensing signal to at least one sensing signal line SSL during the vertical blank period VB. For example, as Figure 4 and Figure 6As shown, during the vertical blank period VB of the Nth frame time period, the scan signal driver 200 can apply a first scan signal SC1 of the gate on-voltage Von to the first scan signal line SCL1, and can choose not to apply the scan signal of the gate on-voltage Von to the second scan signal lines SCL2 to the nth scan signal lines SCLn. In other words, the first gate off-voltage Voff can be applied to the second scan signal lines SCL2 to the nth scan signal lines SCLn. Furthermore, during the vertical blank period VB of the Nth frame time period, the scan signal driver 200 can apply a first sensing signal SS1 of the gate on-voltage Von to the first sensing signal line SSL1, and can choose not to apply the sensing signal of the gate on-voltage Von to the second sensing signal lines SSL2 to the nth sensing signal lines SSLn. Furthermore, as... Figure 4 As shown, during the vertical blank period VB of the N+1th frame, the scan signal driver 200 can apply the first scan signal SC1 with the gate on voltage Von to the second scan signal line SCL2, and can choose not to apply the scan signal with the gate on voltage Von to the first scan signal line SCL1 and the third scan signal lines SCL3 to the nth scan signal lines SCLn. In other words, the first gate off voltage Voff1 can be applied to the first scan signal line SCL1 and the third scan signal lines SCL3 to the nth scan signal lines SCLn.

[0085] like Figures 4 to 6 As shown, the pulse width W1 of the scan signal during the active period ACT differs from the pulse width W3 of the scan signal during the vertical blank period VB. The width of the scan signal refers to the length of the time period during which the scan signal is output as a gate on-state voltage. Furthermore, the pulse width W2 of the sensing signal during the active period ACT differs from the pulse width W4 of the sensing signal during the vertical blank period VB. The pulse width of the sensing signal refers to the length of the time period during which the sensing signal is output as a gate on-state voltage.

[0086] In the following text, reference will be made to Figures 7 to 23 The scan signal driver 200 is described in detail as being able to simultaneously output the k-th scan signal and the k-th sensing signal to reduce the area of ​​the scan signal driver 200, and outputting different scan signals and different sensing signals during the active period ACT and the vertical blank period VB, where k is an integer satisfying 1≤k≤n.

[0087] Figure 7 This is a view illustrating an exemplary embodiment of a scan signal driver according to a concept of the present invention. For ease of explanation, Figure 7 Only ST(k-2) of level (k-2) to ST(k+2) of level (k+2) are shown.

[0088] In the following description, "preceding level" can refer to the level preceding the level of interest. "Following level" can refer to the level following the level of interest. For example, the preceding levels of level k STk are level 1 ST1 to level (k-1) ST(k-1), while the following levels of level k STk are level (k+1) ST(k+1) to level n STn.

[0089] Reference Figure 7 On one side of multiple stages ST(k-2) to ST(k+2), carry clock lines CRC1 to CRC3 for applying carry clock signals with sequentially delayed phases, sense clock lines SEC1 to SEC4 for applying sense clock signals with sequentially delayed phases, scan clock lines SCC1 to SCC4 for applying scan clock signals with sequentially delayed phases, sense control line SES for applying sense control signals, and control clock lines SCK1 and SCK2 for applying control clock signals can be configured. Figure 7 In this context, one or both control clock lines are represented by SCK. The carry clock signal, sense clock signal, scan clock signal, sense control signal, and control clock signal can be referenced above. Figure 2B The described scan control signal SCS. Although... Figure 7 The diagram shows three carry clock lines CRC1 to CRC3, four sense clock lines SEC1 to SEC4, and four scan clock lines SCC1 to SCC4, but the number of carry clock lines CRC1 to CRC3, sense clock lines SEC1 to SEC4, and scan clock lines SCC1 to SCC4 is not limited to this.

[0090] The scan signal driver 200 includes multiple stages ST(k-2) to ST(k+2) respectively connected to scan signal lines SCLk-2 to SCLk+2 and sensing signal lines SSLk-2 to SSLk+2. Stage ST(k-2) outputs the (k-2) scan signal to the (k-2) scan signal line SCLk-2 and the (k-2) sensing signal to the (k-2) sensing signal line SSLk-2. Stage ST(k-1) outputs the (k-1) scan signal to the (k-1) scan signal line SCLk-1 and the (k-1) sensing signal to the (k-1) sensing signal line SSLk-1. Stage STk outputs the k-th scan signal to the k-th scan signal line SCLk and the k-th sensing signal to the k-th sensing signal line SSLk. The (k+1)th stage ST(k+1) outputs the (k+1)th scan signal to the (k+1)th scan signal line SCLk+1, and also outputs the (k+1)th sensing signal to the (k+1)th sensing signal line SSLk+1. The (k+2)th stage ST(k+2) outputs the (k+2)th scan signal to the (k+2)th scan signal line SCLk+2, and also outputs the (k+2)th sensing signal to the (k+2)th sensing signal line SSLk+2.

[0091] Each of stages ST(k-2) to ST(k+2) includes a start terminal CPI, a next carry input terminal CNI, a scan clock terminal SCI, a sense clock terminal SSI, a first carry clock terminal CRI1, a second carry clock terminal CRI2, a sense control terminal SEI, a first control clock terminal CCI1, a carry output terminal CO, a scan output terminal SCO, and a sense output terminal SSO.

[0092] The start terminal CPI can be connected to the start signal line or the carry output terminal CO of the previous stage. For example, as... Figure 7 As shown, the start terminal CPI of the k-th stage STk can be connected to the start signal line or the carry output terminal CO of the (k-2)-th stage ST(k-2). In this case, the start signal of the start signal line or the (k-2)-th carry signal of the (k-2)-th stage ST(k-2) can be input to the start terminal CPI of the k-th stage STk.

[0093] The next carry input terminal CNI of each of stages ST(k-2) to ST(k+2) can be connected to the carry output terminal CO of the corresponding subsequent stage. For example, as Figure 7As shown, the next carry input terminal CNI of the k-th stage STk can be connected to the carry output terminal CO of the (k+2)-th stage ST(k+2). In this case, the (k+2)-th carry signal of the (k+2)-th stage ST(k+2) can be input to the next carry input terminal CNI of the k-th stage STk.

[0094] The scan clock terminal SCI of each of stages ST(k-2) to ST(k+2) can be connected to one of the scan clock lines SCC1 to SCC4. Scan clock lines SCC1 to SCC4 can be connected to the scan clock terminals SCI of stages ST(k-2) to ST(k+2) respectively. For example, as... Figure 7 As shown, the first scan clock line SCC1 can be connected to the scan clock terminal SCI of the (k-2)th stage ST(k-2), and the second scan clock line SCC2 can be connected to the scan clock terminal SCI of the (k-1)th stage ST(k-1). The third scan clock line SCC3 can be connected to the scan clock terminal SCI of the kth stage STk, and the fourth scan clock line SCC4 can be connected to the scan clock terminal SCI of the (k+1)th stage ST(k+1), and the first scan clock line SCC1 can be connected to the scan clock terminal SCI of the (k+2)th stage ST(k+2).

[0095] The sensing clock terminal SSI of each of stages ST(k-2) to ST(k+2) can be connected to one of the sensing clock lines SEC1 to SEC4. Sensing clock lines SEC1 to SEC4 can be connected to the sensing clock terminals SSI of stages ST(k-2) to ST(k+2) respectively. For example, as... Figure 7 As shown, the first sensing clock line SEC1 can be connected to the sensing clock terminal SSI of the (k-2)th stage ST(k-2), and the second sensing clock line SEC2 can be connected to the sensing clock terminal SSI of the (k-1)th stage ST(k-1). The third sensing clock line SEC3 can be connected to the sensing clock terminal SSI of the kth stage STk, and the fourth sensing clock line SEC4 can be connected to the sensing clock terminal SSI of the (k+1)th stage ST(k+1), and the first sensing clock line SEC1 can be connected to the sensing clock terminal SSI of the (k+2)th stage ST(k+2).

[0096] Each of the first carry clock terminal CRI1 and the second carry clock terminal CRI2 of each of stages ST(k-2) to ST(k+2) can be connected to one of the carry clock lines CRC1 to CRC3. The carry clock lines CRC1 to CRC3 can be sequentially connected to the first carry clock terminal CRI1 and the second carry clock terminal CRI2 of stages ST(k-2) to ST(k+2). For example, as... Figure 7 As shown, the first carry clock line CRC1 can be connected to the first carry clock terminal CRI1 of the (k-2)th stage ST(k-2), and the second carry clock line CRC2 can be connected to the second carry clock terminal CRI2 of the (k-2)th stage ST(k-2). The second carry clock line CRC2 can be connected to the first carry clock terminal CRI1 of the (k-1)th stage ST(k-1), and the third carry clock line CRC3 can be connected to the second carry clock terminal CRI2 of the (k-1)th stage ST(k-1). The third carry clock line CRC3 can be connected to the first carry clock terminal CRI1 of the kth stage STk, and the first carry clock line CRC1 can be connected to the second carry clock terminal CRI2 of the kth stage STk. The first carry clock line CRC1 can be connected to the first carry clock terminal CRI1 of the (k+1)th stage ST(k+1), and the second carry clock line CRC2 can be connected to the second carry clock terminal CRI2 of the (k+1)th stage ST(k+1). The second carry clock line CRC2 can be connected to the first carry clock terminal CRI1 of the (k+2)th stage ST(k+2), and the third carry clock line CRC3 can be connected to the second carry clock terminal CRI2 of the (k+2)th stage ST(k+2).

[0097] The sensing control terminal SEI of each of stages ST(k-2) to ST(k+2) can be connected to the sensing control line SES. Sensing control signals can be input to the sensing control terminal SEI of each of stages ST(k-2) to ST(k+2).

[0098] The first control clock terminal CCI1 of each of stages ST(k-2) to ST(k+2) can be connected to the first control clock line SCK1. The first control clock signal can be input to the first control clock terminal CCI1 of each of stages ST(k-2) to ST(k+2).

[0099] The carry output terminal CO of each of stages ST(k-2) to ST(k+2) outputs a carry signal. The carry output terminal CO of each of stages ST(k-2) to ST(k+2) can be connected to the next carry input terminal CNI of the previous stage and the start terminal CPI of the subsequent stage. For example, as... Figure 7As shown, the carry output terminal CO of the k-th stage STk can be connected to the next carry input terminal CNI of the (k-2)-th stage ST(k-2) and the start terminal CPI of the (k+2)-th stage ST(k+2).

[0100] The scan output terminal SCO of each of stages ST(k-2) to ST(k+2) is connected to the scan signal line to output the scan signal. For example, as Figure 7 As shown, the scan output terminal SCO of the (k-2)th stage ST(k-2) can be connected to the (k-2)th scan signal line SCLk-2 to output the (k-2)th scan signal, and the scan output terminal SCO of the (k-1)th stage ST(k-1) can be connected to the (k-1)th scan signal line SCLk-1 to output the (k-1)th scan signal. The scan output terminal SCO of the kth stage STk can be connected to the kth scan signal line SCLk to output the kth scan signal, and the scan output terminal SCO of the (k+1)th stage ST(k+1) can be connected to the (k+1)th scan signal line SCLk+1 to output the (k+1)th scan signal. The scan output terminal SCO of the (k+2)th stage ST(k+2) can be connected to the (k+2)th scan signal line SCLk+2 to output the (k+2)th scan signal.

[0101] The sensing output terminal SSO of each of stages ST(k-2) to ST(k+2) is connected to the sensing signal line to output a sensing signal. For example, as Figure 7 As shown, the sensing output terminal SSO of the (k-2)th stage ST(k-2) can be connected to the (k-2)th sensing signal line SSLk-2 to output the (k-2)th sensing signal, and the sensing output terminal SSO of the (k-1)th stage ST(k-1) can be connected to the (k-1)th sensing signal line SSLk-1 to output the (k-1)th sensing signal. The sensing output terminal SSO of the kth stage STk can be connected to the kth sensing signal line SSLk to output the kth sensing signal, and the sensing output terminal SSO of the (k+1)th stage ST(k+1) can be connected to the (k+1)th sensing signal line SSLk+1 to output the (k+1)th sensing signal. The sensing output terminal SSO of the (k+2)th stage ST(k+2) can be connected to the (k+2)th sensing signal line SSLk+2 to output the (k+2)th sensing signal.

[0102] like Figure 7 As shown, because the scan signal driver 200 includes a single stage for simultaneously outputting scan signals and sensing signals, the area of ​​the scan signal driver 200 can be reduced compared to a scan signal driver that includes a stage for outputting scan signals and another stage for outputting sensing signals.

[0103] Figure 8 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0104] Reference Figure 8 The k-th stage STk includes a first output unit 210, a second output unit 220, a sense controller 230, a first pull-up node controller 240, a second pull-up node controller 250, a third pull-up node controller 260, and an inverter 270. The k-th stage STk may further include a start terminal CPI, a next carry input terminal CNI, a first carry clock terminal CRI1, a second carry clock terminal CRI2, a sense control terminal SEI, a first control clock terminal CCI1, a carry output terminal CO, a scan output terminal SCO, and a sense output terminal SSO. Furthermore, the k-th stage STk may further include a first gate cutoff terminal VOF1, a second gate cutoff terminal VOF2, and a gate on terminal VON. A gate on voltage can be applied to the gate on terminal VON, a first gate cutoff voltage can be applied to the first gate cutoff terminal VOF1, and a second gate cutoff voltage can be applied to the second gate cutoff terminal VOF2. The gate on voltage can be greater than 0V, and the first and second gate cutoff voltages can be equal to or less than 0V. The first gate cutoff voltage can have a higher level than the second gate cutoff voltage.

[0105] exist Figure 8 In the example shown, the third carry clock signal of the third carry clock line CRC3 is applied to the first carry clock terminal CRI1, the first carry clock signal of the first carry clock line CRC1 is applied to the second carry clock terminal CRI2, the third scan clock signal of the third scan clock line SCC3 is applied to the scan clock terminal SCI, and the third sense clock signal of the third sense clock line SEC3 is applied to the sense clock terminal SSI. Furthermore, in Figure 8 In the example shown, the carry signal of stage (k-2) ST(k-2) is applied to the start terminal CPI, and the carry signal of stage (k+2) ST(k+2) is applied to the next carry input terminal CNI.

[0106] exist Figure 8In the example shown, the first scan pull-up transistor SCU1, the first scan pull-down transistor SCD1, the first sensing pull-up transistor SSU1, the first sensing pull-down transistor SSD1, the first transistors T1 to T3, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, and the eleventh to thirteenth transistors T13 are implemented as n-type metal-oxide-semiconductor field-effect transistors (MOSFETs). In this example, when a gate high voltage is applied, the first scan pull-up transistor SCU1, the first scan pull-down transistor SCD1, the first sensing pull-up transistor SSU1, the first sensing pull-down transistor SSD1, the first transistors T1 to T3, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, and the eleventh to thirteenth transistors T13 are turned on. Therefore, the gate turn-on voltage can be the gate high voltage, the first gate turn-off voltage can be the first gate low voltage, and the second gate turn-off voltage can be the second gate low voltage.

[0107] When the pull-up node Q has a gate on voltage, the first output unit 210 outputs the third scan clock signal input to the scan clock terminal SCI to the scan output terminal SCO, and outputs the third sense clock signal input to the sense clock terminal SSI to the sense output terminal SSO. When the pull-down node QB has a gate on voltage, the first output unit 210 outputs the first gate off voltage to the scan output terminal SCO and the sense output terminal SSO.

[0108] The first output unit 210 may include a first scan pull-up transistor SCU1, a first scan pull-down transistor SCD1, a first sensing pull-up transistor SSU1, a first sensing pull-down transistor SSD1, a first capacitor C1, and a second capacitor C2.

[0109] The first scan pull-up transistor SCU1 is turned on by the gate conduction voltage of the pull-up node Q to output the third scan clock signal input to the scan clock terminal SCI to the scan output terminal SCO. The gate electrode of the first scan pull-up transistor SCU1 can be connected to the pull-up node Q, the first electrode of the first scan pull-up transistor SCU1 can be connected to the scan output terminal SCO, and the second electrode of the first scan pull-up transistor SCU1 can be connected to the scan clock terminal SCI.

[0110] To increase the amount of current flowing through the channel when the first scan pull-up transistor SCU1 is turned on, the first scan pull-up transistor SCU1 may further include a second gate electrode electrically connected to the pull-up node Q. In this case, the first scan pull-up transistor SCU1 may have a dual-gate structure including a gate electrode corresponding to the upper gate electrode and a second gate electrode corresponding to the lower gate electrode.

[0111] The first scan pull-down transistor SCD1 is turned on by the gate on voltage of the pull-down node QB to output the first gate off voltage input to the first gate off terminal VOF1. The gate electrode of the first scan pull-down transistor SCD1 can be connected to the pull-down node QB, the first electrode of the first scan pull-down transistor SCD1 can be connected to the first gate off terminal VOF1, and the second electrode of the first scan pull-down transistor SCD1 can be connected to the scan output terminal SCO.

[0112] To prevent or reduce leakage current flowing through the first scan pull-down transistor SCD1, the first scan pull-down transistor SCD1 may further include a second gate electrode connected to the first gate cutoff terminal VOF1. In this case, the first scan pull-down transistor SCD1 may have a dual-gate structure including a gate electrode corresponding to the upper gate electrode and a second gate electrode corresponding to the lower gate electrode.

[0113] To increase the current flowing through the channel when the first sensing pull-up transistor SSU1 is turned on, the first sensing pull-up transistor SSU1 is turned on by the gate on-state voltage of the pull-up node Q, causing the third sensing clock signal input to the sensing clock terminal SSI to be output to the sensing output terminal SSO. The gate electrode of the first sensing pull-up transistor SSU1 can be connected to the pull-up node Q, the first electrode of the first sensing pull-up transistor SSU1 can be connected to the sensing output terminal SSO, and the second electrode of the first sensing pull-up transistor SSU1 can be connected to the sensing clock terminal SSI.

[0114] The first sensing pull-up transistor SSU1 may further include a second gate electrode electrically connected to the pull-up node Q. In this case, the first sensing pull-up transistor SSU1 may have a dual-gate structure including a gate electrode corresponding to the upper gate electrode and a second gate electrode corresponding to the lower gate electrode.

[0115] The first sensing pull-down transistor SSD1 is turned on by the gate on voltage of the pull-down node QB to output the first gate off voltage input to the first gate off terminal VOF1 to the sensing output terminal SSO. The gate electrode of the first sensing pull-down transistor SSD1 can be connected to the pull-down node QB, the first electrode of the first sensing pull-down transistor SSD1 can be connected to the first gate off terminal VOF1, and the second electrode of the first sensing pull-down transistor SSD1 can be connected to the sensing output terminal SSO.

[0116] To prevent or reduce leakage current flowing through the first sensing pull-down transistor SSD1, the first sensing pull-down transistor SSD1 may further include a second gate electrode connected to the first gate cutoff terminal VOF1. In this case, the first sensing pull-down transistor SSD1 may have a dual-gate structure including a gate electrode corresponding to the upper gate electrode and a second gate electrode corresponding to the lower gate electrode.

[0117] A first capacitor C1 is positioned between the pull-up node Q and the scan output terminal SCO. One electrode of the first capacitor C1 can be connected to the pull-up node Q, and the other electrode can be connected to the scan output terminal SCO. Because the first capacitor C1 stores the voltage difference between the pull-up node Q and the scan output terminal SCO, the voltage difference between the pull-up node Q and the scan output terminal SCO can be maintained by the first capacitor C1.

[0118] A second capacitor C2 is positioned between the pull-up node Q and the sensing output terminal SSO. One electrode of the second capacitor C2 can be connected to the pull-up node Q, and the other electrode can be connected to the sensing output terminal SSO. Because the second capacitor C2 stores the voltage difference between the pull-up node Q and the sensing output terminal SSO, the voltage difference between the pull-up node Q and the sensing output terminal SSO can be maintained by the second capacitor C2.

[0119] When the pull-up node Q has a gate on voltage, the second output unit 220 outputs the third carry clock signal input to the first carry clock terminal CRI1 to the carry output terminal CO. When the pull-down node QB has a gate on voltage, the second output unit 220 outputs the first gate off voltage to the carry output terminal CO.

[0120] The second output unit 220 may include a carry pull-up transistor CU, a carry pull-down transistor CD, and a third capacitor C3.

[0121] The carry pull-up transistor CU is turned on by the gate conduction voltage of the pull-up node Q to output the third carry clock signal, which is input to the first carry clock terminal CRI1, to the carry output terminal CO. The gate electrode of the carry pull-up transistor CU can be connected to the pull-up node Q, the first electrode of the carry pull-up transistor CU can be connected to the carry output terminal CO, and the second electrode of the carry pull-up transistor CU can be connected to the first carry clock terminal CRI1.

[0122] The carry-down transistor CD is turned on by the gate on voltage of the pull-down node QB to output the second gate off voltage input to the second gate off terminal VOF2 to the carry output terminal CO. The gate electrode of the carry-down transistor CD can be connected to the pull-down node QB, the first electrode of the carry-down transistor CD can be connected to the second gate off terminal VOF2, and the second electrode of the carry-down transistor CD can be connected to the carry output terminal CO.

[0123] A third capacitor C3 is positioned between the pull-down node QB and the second gate cutoff terminal VOF2. One electrode of the third capacitor C3 can be connected to the pull-down node QB, and the other electrode can be connected to the second gate cutoff terminal VOF2. Because the third capacitor C3 stores the voltage difference between the pull-down node QB and the second gate cutoff terminal VOF2, the voltage difference between the pull-down node QB and the second gate cutoff terminal VOF2 can be maintained by the third capacitor C3.

[0124] When the gate conduction voltage sensing control signal is input to the sensing control terminal SEI during the effective period of the Nth frame time, the sensing controller 230 applies the gate conduction voltage to the pull-up node Q during the vertical blank period VB of the Nth frame time. As a result, because the first scan pull-up transistor SCU1 and the first sensing pull-up transistor SSU1 are turned on during the vertical blank period of the Nth frame time, the first output unit 210 can output the third scan clock signal input to the scan clock terminal SCI to the scan output terminal SCO, and can output the third sensing clock signal input to the sensing clock terminal SSI to the sensing output terminal SSO.

[0125] The sensing controller 230 may include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth capacitor C4.

[0126] The first transistor T1 is turned on by the gate conduction voltage of the sensing control signal input to the sensing control terminal SEI, and the carry signal of the (k+2)th stage ST(k+2) input to the next carry input terminal CNI is applied to the sensing control node S. In other words, when the carry signal of the gate conduction voltage of the (k+2)th stage ST(k+2) is input at the same time as the first transistor T1 is turned on, the sensing control node S has a gate conduction voltage.

[0127] The first transistor T1 may include the (1-1)th transistor T1-1 and the (1-2)th transistor T1-2.

[0128] The gate conduction voltage of the sensing control signal input to the sensing control terminal SEI of transistor (1-1) is turned on to connect the next carry input terminal CNI to the second electrode of transistor (1-2) T1-2. The gate electrode of transistor (1-1) T1-1 can be connected to the sensing control terminal SEI, the first electrode of transistor (1-1) T1-1 can be connected to the second electrode of transistor (1-2) T1-2, and the second electrode of transistor (1-1) T1-1 can be connected to the next carry input terminal CNI.

[0129] The gate conduction voltage of the sensing control signal input to the sensing control terminal SEI of transistor (1-2) is turned on to connect the sensing control node S to the first electrode of transistor (1-1) T1-1. The gate electrode of transistor (1-2) T1-2 can be connected to the sensing control terminal SEI, the first electrode of transistor (1-2) T1-2 can be connected to the sensing control node S, and the second electrode of transistor (1-2) T1-2 can be connected to the first electrode of transistor (1-1) T1-1.

[0130] The second transistor T2 and the third transistor T3 are turned on by the gate on-state voltage of the sensing control node S to apply the first control clock signal input to the first control clock terminal CCI1 to the pull-up node Q. In other words, the second transistor T2 and the third transistor T3 are turned on by the gate on-state voltage of the sensing control node S to connect the first control clock terminal CCI1 to the pull-up node Q. The gate electrode of the second transistor T2 can be connected to the sensing control node S, the first electrode of the second transistor T2 can be connected to the second electrode of the third transistor T3, and the second electrode of the second transistor T2 can be connected to the first control clock terminal CCI1. The gate electrode of the third transistor T3 can be connected to the sensing control node S, the first electrode of the third transistor T3 can be connected to the pull-up node Q, and the second electrode of the third transistor T3 can be connected to the first electrode of the second transistor T2.

[0131] A fourth capacitor C4 is disposed between the sensing control node S and the second gate cutoff terminal VOF2. One electrode of the fourth capacitor C4 can be connected to the sensing control node S, and the other electrode of the fourth capacitor C4 can be connected to the second gate cutoff terminal VOF2. Because the fourth capacitor C4 stores the voltage difference between the sensing control node S and the second gate cutoff terminal VOF2, the voltage difference between the sensing control node S and the second gate cutoff terminal VOF2 can be maintained by the fourth capacitor C4.

[0132] When the carry signal of stage (k-2) ST(k-2) applied to the start terminal CPI has a gate on voltage, the first pull-up node controller 240 applies the gate on voltage to the pull-up node Q. The first pull-up node controller 240 may include a sixth transistor T6.

[0133] The sixth transistor T6 is turned on by the carry signal of the gate on-state voltage of stage (k-2) ST(k-2) to connect the pull-up node Q to the gate on-state terminal VON, so that the gate on-state voltage can be applied to the pull-up node Q. The gate electrode of the sixth transistor T6 can be connected to the start terminal CPI, the first electrode of the sixth transistor T6 can be connected to the pull-up node Q, and the second electrode of the sixth transistor T6 can be connected to the gate on-state terminal VON.

[0134] When the carry signal from the input of stage (k+2) ST(k+2) to the next carry input terminal CNI has a gate on voltage, the second pull-up node controller 250 applies a second gate off voltage to the pull-up node Q. The second pull-up node controller 250 may include an eighth transistor T8.

[0135] The eighth transistor T8 is turned on by the carry signal of the gate on-state voltage of stage (k+2) ST(k+2) to connect the pull-up node Q to the carry output terminal CO, so that the second gate off-state voltage can be applied to the pull-up node Q. The gate electrode of the eighth transistor T8 can be connected to the next carry input terminal CNI, the first electrode of the eighth transistor T8 can be connected to the carry output terminal CO, and the second electrode of the eighth transistor T8 can be connected to the pull-up node Q. The channel width of the thirteenth transistor T13 can be greater than the channel width of the eleventh transistor T11.

[0136] When the third scan clock signal input to the scan clock terminal SCI or the third sense clock signal input to the sense clock terminal SSI has a gate on voltage and the pull-down node QB has a gate on voltage, the third pull-up node controller 260 applies a second gate off voltage to the pull-up node Q. The third pull-up node controller 260 may include a tenth transistor T10. The tenth transistor T10 may include a (10-1) transistor T10-1 and a (10-2) transistor T10-2.

[0137] Transistor (10-1) T10-1 is turned on by the third scan clock signal or the third sense clock signal of the gate conduction voltage to connect the pull-up node Q to the second electrode of transistor (10-2) T10-2. The gate electrode of transistor (10-1) T10-1 can be connected to the scan clock signal SCI or the sense clock signal SSI, the first electrode of transistor (10-1) T10-1 can be connected to the second electrode of transistor (10-2) T10-2, and the second electrode of transistor (10-1) T10-1 can be connected to the pull-up node Q.

[0138] Transistor (10-2) T10-2 can be turned on by the gate conduction voltage of the pull-down node QB to connect the carry output terminal CO to the first electrode of transistor (10-1) T10-1. The gate electrode of transistor (10-2) T10-2 can be connected to the pull-down node QB, the first electrode of transistor (10-2) T10-2 can be connected to the carry output terminal CO, and the second electrode of transistor (10-2) T10-2 can be connected to the first electrode of transistor (10-1) T10-1.

[0139] When the pull-up node Q has a gate on voltage, the inverter 270 applies a first gate off voltage to the pull-down node QB. Furthermore, when the pull-up node Q has a second gate off voltage, the inverter 270 can apply a gate on voltage to the pull-down node QB.

[0140] Inverter 270 may include eleventh transistor T11, twelfth transistor T12 and thirteenth transistor T13.

[0141] The eleventh transistor T11 is turned on by the gate on voltage of the pull-up node Q to apply the first carry clock signal of the second carry clock terminal CRI2 to the pull-down node QB. While the pull-up node Q has a voltage equal to or greater than the gate on voltage, the carry clock signal input to the second carry clock terminal CRI2 may have a first gate off voltage. The eleventh transistor T11 may include the (11-1) transistor T11-1 and the (11-2) transistor T11-2.

[0142] Transistor (11-1) T11-1 can be turned on by the gate conduction voltage of the pull-down node QB to connect the second carry clock terminal CRI2 to the second electrode of transistor (11-2) T11-2. The gate electrode of transistor (11-1) T11-1 can be connected to the pull-up node Q, the first electrode of transistor (11-1) T11-1 can be connected to the second electrode of transistor (11-2) T11-2, and the second electrode of transistor (11-1) T11-1 can be connected to the second carry clock terminal CRI2.

[0143] Transistor (11-2) T11-2 can be turned on by the gate on-state voltage of the pull-up node Q to connect the pull-down node QB to the first electrode of transistor (11-1) T11-1. The gate electrode of transistor (11-2) T11-2 can be connected to the pull-up node Q, the first electrode of transistor (11-2) T11-2 can be connected to the pull-down node QB, and the second electrode of transistor (11-2) T11-2 can be connected to the first electrode of transistor (11-1) T11-1.

[0144] The twelfth transistor T12 can be turned on by the gate-on voltage of the first carry clock signal of the second carry clock terminal CRI2 to connect the pull-down node QB to the gate-on terminal VON, so that the gate-on voltage can be applied to the pull-down node QB. The gate electrode of the twelfth transistor T12 can be connected to the second carry clock terminal CRI2, the first electrode of the twelfth transistor T12 can be connected to the pull-down node QB, and the second electrode of the twelfth transistor T12 can be connected to the gate-on terminal VON.

[0145] The thirteenth transistor T13 is turned on by the gate on-state voltage of the pull-down node QB to connect the pull-down node QB to the gate on-state terminal VON, so that the gate on-state voltage can be applied to the pull-down node QB. The gate electrode and the first electrode of the thirteenth transistor T13 can be connected to the pull-down node QB, and the second electrode of the thirteenth transistor T13 can be connected to the gate on-state terminal VON.

[0146] In each of the first scan pull-up transistor SCU1, the first scan pull-down transistor SCD1, the first sensing pull-up transistor SSU1, the first sensing pull-down transistor SSD1, the first transistors T1 to T3, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, and the eleventh transistors T11 to Tthirteenth transistors T13, one of the first and second electrodes can be a source electrode, and the other electrode can be a drain electrode. This source / drain relationship can be applied to other transistors described herein.

[0147] Furthermore, each of the first scan pull-up transistor SCU1, the first scan pull-down transistor SCD1, the first sensing pull-up transistor SSU1, the first sensing pull-down transistor SSD1, the first transistor T1 to the third transistor T3, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, and the eleventh transistor T11 to the thirteenth transistor T13 can be formed of amorphous silicon (a-Si), polycrystalline silicon (ploy-Si), or oxide semiconductor.

[0148] Figure 9A This is a waveform diagram illustrating, according to an exemplary embodiment of the present invention, the carry clock signal, scan clock signal, sensing clock signal, sensing control signal, (k-2)th carry signal, kth carry signal, (k+2)th carry signal, voltage of pull-up node, voltage of pull-down node, kth scan signal and kth sensing signal during the effective time period of the Nth frame.

[0149] Reference Figure 9AThe phases of the first carry clock signal to the third carry clock signals CK1_CR, CK2_CR, and CK3_CR are sequentially delayed. For example, the phase of the second carry clock signal CK2_CR can be delayed by two horizontal time intervals 2H relative to the first carry clock signal CK1_CR, and the phase of the third carry clock signal CK3_CR can be delayed by two horizontal time intervals 2H relative to the second carry clock signal CK2_CR. The first carry clock signal to the third carry clock signal CK1_CR, CK2_CR, and CK3_CR can be repeated every six horizontal time intervals 6H. The first carry clock signal to the third carry clock signal CK1_CR, CK2_CR, and CK3_CR can be generated as a gate on voltage during two horizontal time intervals 2H, and can be generated as a first gate off voltage Voff1, which is lower than the gate on voltage, during four horizontal time intervals 4H.

[0150] The phases of the first to fourth scan clock signals CK1_SC, CK2_SC, CK3_SC, and CK4_SC are sequentially delayed. For example, the phase of the second scan clock signal CK2_SC may be delayed by a horizontal time interval 1H relative to the first scan clock signal CK1_SC, the phase of the third scan clock signal CK3_SC may be delayed by a horizontal time interval 1H relative to the second scan clock signal CK2_SC, and the phase of the fourth scan clock signal CK4_SC may be delayed by a horizontal time interval 1H relative to the third scan clock signal CK3_SC. The first to fourth scan clock signals CK1_SC, CK2_SC, CK3_SC, and CK4_SC may be repeated every four horizontal time intervals 4H. The first to fourth scan clock signals CK1_SC, CK2_SC, CK3_SC, and CK4_SC may be generated as gate turn-on voltages during two horizontal time intervals 2H, and may also be generated as the first gate turn-off voltage Voff1 during two horizontal time intervals 2H. The gate on-voltage Von periods of the first scan clock signal CK1_SC and the second scan clock signal CK2_SC can overlap by a horizontal period of 1H. The gate on-voltage Von periods of the second scan clock signal CK2_SC and the third scan clock signal CK3_SC can overlap by a horizontal period of 1H. The gate on-voltage Von periods of the third scan clock signal CK3_SC and the fourth scan clock signal CK4_SC can overlap by a horizontal period of 1H. The gate on-voltage Von period of the fourth scan clock signal CK4_SC and the gate on-voltage Von period of the first scan clock signal CK1_SC can overlap by a horizontal period of 1H.

[0151] The first sensing clock signals to the fourth sensing clock signals CK1_SS, CK2_SS, CK3_SS and CK4_SS can be substantially similar to the first scan clock signals to the fourth scan clock signals CK1_SC, CK2_SC, CK3_SC and CK4_SC during the effective period ACT.

[0152] During the effective period ACT, after the carry signal CRk-2 of stage (k-2) ST(k-2) is generated as the gate on-voltage Von, the carry signal CRk of stage k STk can be generated as the gate on-voltage Von, and subsequently the carry signal CRk+2 of stage (k+2) ST(k+2) is generated as the gate on-voltage Von. This can occur sequentially. The gate on-voltage Von periods of the carry signal CRk-2 of stage (k-2), the carry signal CRk of stage k STk, and the carry signal CRk+2 of stage (k+2) ST(k+2) can not overlap with each other.

[0153] The sensing control signal SEN_ON can be generated as the gate on-voltage Von during the fifth time period t5 and the sixth time period t6 of the effective period ACT. The gate on-voltage Von period of the sensing control signal SEN_ON can overlap with the gate on-voltage Von period of the carry signal CRk+2 of the (k+2)th stage ST(k+2). The first control clock signal S_CLK1 can be generated as the second gate off-voltage Voff2 during the effective period ACT, and the second control clock signal S_CLK2 can be generated as the third gate off-voltage Voff3 during the effective period ACT.

[0154] The gate on-voltage Von can be the gate high voltage of the transistors in the scanning signal driver 200 stage and the sub-pixel SP. The first gate off-voltage Voff1, the second gate off-voltage Voff2, and the third gate off-voltage Voff3 can be the gate low voltages of the transistors in the scanning signal driver 200 stage and the sub-pixel SP. The second gate off-voltage Voff2 can be lower than the first gate off-voltage Voff1. The third gate off-voltage Voff3 can be lower than the second gate off-voltage Voff2. For example, the first gate off-voltage Voff1 can be approximately -5V, the second gate off-voltage Voff2 can be approximately -8V, and the third gate off-voltage Voff3 can be approximately -11V.

[0155] exist Figure 9AIn the example shown, the length of each of the first time period t1 to the seventh time period t7 can be equal to a horizontal time period 1H. During a horizontal time period 1H, a data voltage can be applied to a sub-pixel SP that is set in a horizontal line.

[0156] Figures 10 to 16 This is a circuit diagram illustrating the operation of the kth level during the first to seventh time periods of the effective time period, according to an exemplary embodiment of the present invention.

[0157] In the following text, reference will be made to Figures 9A to 16 Describe in detail the operations at level k during the first to seventh time periods of the effective time period.

[0158] exist Figures 10 to 16 In the example shown, the third carry clock signal of the third carry clock line CRC3 is applied to the first carry clock terminal CRI1, the first carry clock signal of the first carry clock line CRC1 is applied to the second carry clock terminal CRI2, the third scan clock signal of the third scan clock line SCC3 is applied to the scan clock terminal SCI, and the third sense clock signal of the third sense clock line SEC3 is applied to the sense clock terminal SSI. Furthermore, in Figure 8 In the example shown, the carry signal of stage (k-2) ST(k-2) is applied to the start terminal CPI, and the carry signal of stage (k+2) ST(k+2) is applied to the next carry input terminal CNI.

[0159] First, such as Figure 9A As shown, during the first time period t1, the carry signal CRk-2 of the gate on-state voltage Von of stage (k-2) ST(k-2) can be applied to the start terminal CPI of stage k STk, and the carry signal CRk+2 of the first gate off-state voltage Voff1 of stage (k+2) ST(k+2) can be applied to the next carry input terminal CNI. Furthermore, as... Figure 9A As shown, during the first time period t1, the third carry clock signal CK3_CR of the first gate cutoff voltage Voff1 can be applied to the first carry clock terminal CRI1 of the k-th stage STk, and the first carry clock signal CK1_CR of the first gate cutoff voltage Voff1 can be applied to the second carry clock terminal CRI2. Furthermore, as... Figure 9A As shown, during the first time period t1, the third scan clock signal CK3_SC of the first gate cutoff voltage Voff1 can be applied to the scan clock terminal SCI of the k-th stage STk, and the third sensing clock signal CK3_SS of the first gate cutoff voltage Voff1 can be applied to the sensing clock terminal SSI. Furthermore, as... Figure 9AAs shown, during the first time period t1, the sensing control signal SEN_ON of the first gate cutoff voltage Voff1 can be applied to the sensing control terminal SEI of the k-th stage STk, and the first control clock signal S_CLK1 of the first gate cutoff voltage Voff1 can be applied to the first control clock terminal CCI1. Therefore, as Figure 10 As shown, the sixth transistor T6, the eleventh transistor T11, the first scan pull-up transistor SCU1, the first sensing pull-up transistor SSU1, and the carry pull-up transistor CU can be turned on.

[0160] The sixth transistor T6 can be turned on by the carry signal CRk-2 of the gate on-state voltage Von of the (k-2)th stage ST(k-2) to connect the pull-up node Q to the gate on-state terminal VON. Accordingly, because the pull-up node Q has a gate on-state voltage Von, the eleventh transistor T11, the first scan pull-up transistor SCU1, the first sense pull-up transistor SSU1, and the carry pull-up transistor CU can be turned on.

[0161] The eleventh transistor T11 is turned on by the gate on voltage Von of the pull-up node Q to apply the first gate off voltage Voff1 of the first carry clock signal CK1_CR to the pull-down node QB. As a result, the first scan pull-down transistor SCD1, the first sensing pull-down transistor SSD1, and the carry pull-down transistor CD can be turned off.

[0162] The first scan pull-up transistor SCU1 is turned on by the gate on voltage Von of the pull-up node Q to output the third scan clock signal CK3_SC, which is the first gate off voltage Voff1 input to the scan clock terminal SCI, to the scan output terminal SCO. In this way, the k-th scan signal SCk of the first gate off voltage Voff1 can be applied to the k-th scan signal line SCLk.

[0163] The first sensing pull-up transistor SSU1 is turned on by the gate on voltage Von of the pull-up node Q to output the third sensing clock signal CK3_SS, which is the first gate off voltage Voff1 input to the sensing clock signal SSI, to the sensing output terminal SSO. In this way, the k-th sensing signal SSk of the first gate off voltage Voff1 can be applied to the k-th sensing signal line SSLk.

[0164] The carry pull-up transistor CU is turned on by the gate on voltage Von of the pull-up node Q to output the third carry clock signal CK3_CR, which is input to the first carry clock terminal CRI1 and the first gate off voltage Voff1, to the carry output terminal CO.

[0165] Secondly, such as Figure 9AAs shown, during the second time period t2, the carry signal CRk-2 of the gate on-state voltage Von of the (k-2)th stage ST(k-2) can be applied to the start terminal CPI of the kth stage STk, and the carry signal CRk+2 of the first gate off-state voltage Voff1 of the (k+2)th stage ST(k+2) can be applied to the next carry input terminal CNI. Furthermore, as... Figure 9A As shown, during the second time period t2, the third carry clock signal CK3_CR of the first gate cutoff voltage Voff1 can be applied to the first carry clock terminal CRI1 of the k-th stage STk, and the first carry clock signal CK1_CR of the first gate cutoff voltage Voff1 can be applied to the second carry clock terminal CRI2. Furthermore, as... Figure 9A As shown, during the second time period t2, the third scan clock signal CK3_SC of the gate on-state voltage Von can be applied to the scan clock terminal SCI of the k-th stage STk, and the third sensing clock signal CK3_SS of the gate on-state voltage Von can be applied to the sensing clock terminal SSI. Furthermore, as... Figure 9A As shown, during the second time period t2, the sensing control signal SEN_ON of the first gate cutoff voltage Voff1 can be applied to the sensing control terminal SEI of the k-th stage STk, and the first control clock signal S_CLK1 of the first gate cutoff voltage Voff1 can be applied to the first control clock terminal CCI1. Therefore, as Figure 11 As shown, the sixth transistor T6, the (10-1)th transistor T10-1, the eleventh transistor T11, the first scan pull-up transistor SCU1, the first sensing pull-up transistor SSU1, and the carry pull-up transistor CU can be turned on.

[0166] During the second time period t2, the operation of the sixth transistor T6, the eleventh transistor T11, and the carry pull-up transistor CU can be referenced above. Figure 10 The operations described in the first time period t1 are basically the same.

[0167] Transistor (10-1) T10-1 is turned on by the gate conduction voltage Von of the third scan clock signal to connect the pull-up node Q to the second electrode of transistor (10-2) T10-2.

[0168] The first scan pull-up transistor SCU1 is turned on by the gate on-state voltage Von of the pull-up node Q to output the third scan clock signal CK3_SC, which is the gate on-state voltage Von input to the scan clock terminal SCI, to the scan output terminal SCO. In this way, the k-th scan signal SCk of the gate on-state voltage Von can be applied to the k-th scan signal line SCLk.

[0169] The first sensing pull-up transistor SSU1 is turned on by the gate on-state voltage Von of the pull-up node Q to output the third sensing clock signal CK3_SS, which is the gate on-state voltage Von input to the sensing clock terminal SSI, to the sensing output terminal SSO. In this way, the k-th sensing signal SSk of the gate on-state voltage Von can be applied to the k-th sensing signal line SSLk.

[0170] When the third scan clock signal CK3_SC of the gate on-state voltage Von is applied to the scan output terminal SCO and the third sensing clock signal CK3_SS of the gate on-state voltage Von is applied to the sensing output terminal SSO, the pull-up node Q is bootstrapped by the second capacitor C2 so that the voltage can rise from the gate on-state voltage Von to a voltage Von' that is higher than the gate on-state voltage Von. This can be achieved by the voltage VQ in... Figure 9A The second time interval t2 shows an increase to Von'. Figure 9A In this context, VQB can correspond to the voltage of the pull-down node QB.

[0171] Third, such as Figure 9A As shown, during the third time period t3, the carry signal CRk-2 of the first gate cutoff voltage Voff1 of the (k-2)th stage ST(k-2) can be applied to the start terminal CPI of the kth stage STk, and the carry signal CRk+2 of the first gate cutoff voltage Voff1 of the (k+2)th stage ST(k+2) can be applied to the next carry input terminal CNI. Furthermore, as... Figure 9A As shown, during the third time period t3, the third carry clock signal CK3_CR of the gate on-voltage Von can be applied to the first carry clock terminal CRI1 of the k-th stage STk, and the first carry clock signal CK1_CR of the first gate off-voltage Voff1 can be applied to the second carry clock terminal CRI2. Furthermore, as... Figure 9A As shown, during the third time period t3, the third scan clock signal CK3_SC of the gate on-state voltage Von can be applied to the scan clock terminal SCI of the k-th stage STk, and the third sensing clock signal CK3_SS of the gate on-state voltage Von can be applied to the sensing clock terminal SSI. Furthermore, as... Figure 9A As shown, during the third time period t3, the sensing control signal SEN_ON of the first gate cutoff voltage Voff1 can be applied to the sensing control terminal SEI of the k-th stage STk, and the first control clock signal S_CLK1 of the first gate cutoff voltage Voff1 can be applied to the first control clock terminal CCI1. Therefore, as Figure 12 As shown, the eleventh transistor T11, the first scan pull-up transistor SCU1, the first sensing pull-up transistor SSU1, and the carry pull-up transistor CU can be turned on.

[0172] During the third time period t3, the operation of transistor (10-1) T10-1, eleventh transistor T11, first scan pull-up transistor SCU1, and first sensing pull-up transistor SSU1 can be the same as described above. Figure 11 The operations described for the second time period t2 are basically the same.

[0173] The carry pull-up transistor CU is turned on by the gate conduction voltage Von of the pull-up node Q to output the third carry clock signal CK3_CR, which is input to the gate conduction voltage Von of the first carry clock terminal CRI1, to the carry output terminal CO.

[0174] When the sixth transistor T6 is driven at high temperature, the threshold voltage can be negatively offset. When this occurs, the sixth transistor T6 may not be completely turned off, and correspondingly, leakage current may flow through the sixth transistor T6. Due to the leakage current of the sixth transistor T6, during the third time period t3, the pull-up node Q may not be able to bootstrap to a voltage Von' higher than the gate on-state voltage Von. As a result, the first scan pull-up transistor SCU1 and the first sensing pull-up transistor SSU1 may not be fully turned on, causing the gate on-state voltage Von to be incorrectly output to the scan output terminal SCO and the sensing output terminal SSO.

[0175] To reduce the voltage level of the pull-up node Q being lower than the gate on-state voltage Von' (which is higher than the gate on-state voltage Von) due to the leakage current of the sixth transistor T6 during the third time period t3, the carry clock signals CK1_CR, CK2_CR, and CK3_CR can oscillate between the second gate on-state voltage Von2 (which is lower than the gate on-state voltage Von) and the first gate off-state voltage Voff1. Figure 9B As shown in the diagram. Alternatively, to reduce the voltage Von' of the pull-up node Q, which is lower than the gate on-state voltage Von due to the leakage current of the sixth transistor T6 during the third time period t3, the gate on-state voltage periods CRW of the carry clock signals CK1_CR, CK2_CR, and CK3_CR can be shorter than the gate on-state voltage periods SCW of the scan clock signals CK1_SC, CK2_SC, CK3_SC, and CK4_SC, respectively, as shown in the diagram. Figure 9B As shown. Furthermore, as... Figure 9B As shown, the gate conduction voltage period CRW of the carry clock signals CK1_CR, CK2_CR and CK3_CR can be shorter than the gate conduction voltage period SSW of the sensing clock signals CK1_SS, CK2_SS, CK3_SS and CK4_SS, respectively.

[0176] Fourth, such as Figure 9AAs shown, during the fourth time period t4, the carry signal CRk-2 of the first gate cutoff voltage Voff1 of the (k-2)th stage ST(k-2) can be applied to the start terminal CPI of the kth stage STk, and the carry signal CRk+2 of the first gate cutoff voltage Voff1 of the (k+2)th stage ST(k+2) can be applied to the next carry input terminal CNI. Furthermore, as... Figure 9A As shown, during the fourth time period t4, the third carry clock signal CK3_CR of the gate on-state voltage Von can be applied to the first carry clock terminal CRI1 of the k-th stage STk, and the first carry clock signal CK1_CR of the first gate off-state voltage Voff1 can be applied to the second carry clock terminal CRI2. Furthermore, as... Figure 9A As shown, during the fourth time period t4, the third scan clock signal CK3_SC of the first gate cutoff voltage Voff1 can be applied to the scan clock terminal SCI of the k-th stage STk, and the third sensing clock signal CK3_SS of the first gate cutoff voltage Voff1 can be applied to the sensing clock terminal SSI. Furthermore, as... Figure 9A As shown, during the fourth time period t4, the sensing control signal SEN_ON of the first gate cutoff voltage Voff1 can be applied to the sensing control terminal SEI of the k-th stage STk, and the first control clock signal S_CLK1 of the first gate cutoff voltage Voff1 can be applied to the first control clock terminal CCI1. Therefore, as Figure 13 As shown, the eleventh transistor T11, the first scan pull-up transistor SCU1, the first sensing pull-up transistor SSU1, and the carry pull-up transistor CU can be turned on.

[0177] During the fourth time period t4, the operation of the eleventh transistor T11 and the carry pull-up transistor CU can be referenced above. Figure 12 The operations described for the third time period t3 are basically the same.

[0178] The first scan pull-up transistor SCU1 is turned on by the gate on voltage Von of the pull-up node Q to output the third scan clock signal CK3_SC, which is the first gate off voltage Voff1 input to the scan clock terminal SCI, to the scan output terminal SCO. In this way, the k-th scan signal SCk of the first gate off voltage Voff1 can be applied to the k-th scan signal line SCLk.

[0179] The first sensing pull-up transistor SSU1 is turned on by the gate on voltage Von of the pull-up node Q to output the third sensing clock signal CK3_SS, which is the first gate off voltage Voff1 input to the sensing clock terminal SSI, to the sensing output terminal SSO. In this way, the k-th sensing signal SSk of the first gate off voltage Voff1 can be applied to the k-th sensing signal line SSLk.

[0180] When the third scan clock signal CK3_SC of the first gate cutoff voltage Voff1 is applied to the scan output terminal SCO and the third sensing clock signal CK3_SS of the first gate cutoff voltage Voff1 is applied to the sensing output terminal SSO, the pull-up node Q is bootstrapped by the first capacitor C1 and the second capacitor C2 so that the voltage can be reduced from a voltage Von' that is higher than the gate turn-on voltage Von to the gate turn-on voltage Von.

[0181] Fifth, such as Figure 9A As shown, during the fifth time period t5, the carry signal CRk-2 of the first gate cutoff voltage Voff1 of the (k-2)th stage ST(k-2) can be applied to the start terminal CPI of the kth stage STk, and the carry signal CRk+2 of the gate on-voltage Von of the (k+2)th stage ST(k+2) can be applied to the next carry input terminal CNI. Furthermore, as... Figure 9A As shown, during the fifth time period t5, the third carry clock signal CK3_CR of the first gate cutoff voltage Voff1 can be applied to the first carry clock terminal CRI1 of the k-th stage STk, and the first carry clock signal CK1_CR of the gate on-voltage Von can be applied to the second carry clock terminal CRI2. Furthermore, as... Figure 9A As shown, during the fifth time period t5, the third scan clock signal CK3_SC of the first gate cutoff voltage Voff1 can be applied to the scan clock terminal SCI of the k-th stage STk, and the third sensing clock signal CK3_SS of the first gate cutoff voltage Voff1 can be applied to the sensing clock terminal SSI. Furthermore, as... Figure 9A As shown, during the fifth time period t5, the sensing control signal SEN_ON of the gate on-state voltage Von can be applied to the sensing control terminal SEI of the k-th stage STk, and the first control clock signal S_CLK1 of the first gate off-state voltage Voff1 can be applied to the first control clock terminal CCI1. Therefore, as Figure 14 As shown, the first transistor T1, the second transistor T2, the third transistor T3, the eighth transistor T8, the (10-2)th transistor T10-2, the twelfth transistor T12, the thirteenth transistor T13, the first scan pull-down transistor SCD1, the first sensing pull-down transistor SSD1, and the carry pull-down transistor CD can be turned on.

[0182] The eighth transistor T8 can be turned on by the carry signal CRk+2 of the gate on-state voltage Von of stage (k+2) ST(k+2) to connect the pull-up node Q to the carry output terminal CO. Accordingly, during the fifth time period T5, the third carry clock signal CK3_CR of the first gate off-state voltage Voff1 is applied to the carry output terminal CO, and correspondingly, the pull-up node Q has the first gate off-state voltage Voff1. Therefore, the eleventh transistor T11, the first scan pull-up transistor SCU1, the first sense pull-up transistor SSU1, and the carry pull-up transistor CU can be turned off.

[0183] The twelfth transistor T12 is turned on by the first carry clock signal CK1_CR, which is input to the gate on-state voltage Von of the second carry clock terminal CRI2, to connect the pull-down node QB to the gate on-state terminal VON. Accordingly, the pull-up node Q has a gate on-state voltage Von, and accordingly, the (10-2)th transistor T10-2, the thirteenth transistor T13, the first scan pull-down transistor SCD1, the first sense pull-down transistor SSD1, and the carry pull-down transistor CD can be turned on.

[0184] Transistor (10-2) T10-2 can be turned on by the gate on-state voltage Von of the pull-down node QB to connect the carry output terminal CO to the first electrode of transistor (10-1) T10-1. Therefore, when transistor (10-1) T10-1 is turned on, the pull-up node Q can be connected to the carry output terminal CO.

[0185] The thirteenth transistor T13 is turned on by the gate conduction voltage Von of the pull-down node QB to connect the pull-down node QB to the gate conduction terminal VON.

[0186] The first scan pull-down transistor SCD1 is turned on by the gate on voltage Von of the pull-down node QB to output the first gate off voltage input to the first gate off terminal VOF1. In this way, the k-th scan signal SCk of the first gate off voltage Voff1 can be applied to the k-th scan signal line SCLk.

[0187] The first sensing pull-down transistor SSD1 is turned on by the gate on voltage Von of the pull-down node QB to output the first gate off voltage input to the first gate off terminal VOF1 to the sensing output terminal SSO. In this way, the k-th sensing signal SSk of the first gate off voltage Voff1 can be applied to the k-th sensing signal line SSLk.

[0188] The carry pull-down transistor CD is turned on by the gate on voltage Von of the pull-down node QB to output the first gate off voltage input to the first gate off terminal VOF1 to the carry output terminal CO.

[0189] The first transistor T1 is turned on by the gate on-state voltage Von of the sensing control signal SEN_ON input to the sensing control terminal SEI to connect the next carry input terminal CNI to the sensing control node S. Correspondingly, the sensing control node S has the gate on-state voltage Von of the carry signal of the (k+2)th stage ST(k+2), so that the second transistor T2 and the third transistor T3 can be turned on.

[0190] The second transistor T2 and the third transistor T3 are turned on by the gate on-state voltage of the sensing control node S to apply the first control clock signal S_CLK1, which is input to the first control clock terminal CCI1, to the pull-up node Q. Accordingly, the first gate off-state voltage Voff1 of the first control clock signal S_CLK1 can be applied to the pull-up node Q.

[0191] The sensing control node S can have a gate on-state voltage Von only when the first transistor T1 is turned on, and the carry signal of the (k+2)th stage ST(k+2) input to the next carry input terminal CNI has a gate on-state voltage Von during the fifth time period t5. Therefore, while the sensing control signal SEN_ON with the first gate off-state voltage Voff1 can be input to the remaining stages during the fifth time period t5, the sensing control signal SEN_ON with the gate on-state voltage Von can be input to the stage during the vertical blank period to output the scan signal and the sensing signal during the fifth time period t5.

[0192] Sixth, such as Figure 9A As shown, during the sixth time period t6, the carry signal CRk-2 of the first gate cutoff voltage Voff1 of the (k-2)th stage ST(k-2) can be applied to the start terminal CPI of the kth stage STk, and the carry signal CRk+2 of the gate on-voltage Von of the (k+2)th stage ST(k+2) can be applied to the next carry input terminal CNI. Furthermore, as... Figure 9A As shown, during the sixth time period t6, the third carry clock signal CK3_CR of the first gate cutoff voltage Voff1 can be applied to the first carry clock terminal CRI1 of the k-th stage STk, and the first carry clock signal CK1_CR of the gate on-voltage Von can be applied to the second carry clock terminal CRI2. Furthermore, as... Figure 9A As shown, during the sixth time period t6, the third scan clock signal CK3_SC of the gate on-state voltage Von can be applied to the scan clock terminal SCI of the k-th stage STk, and the third sensing clock signal CK3_SS of the gate on-state voltage Von can be applied to the sensing clock terminal SSI. Furthermore, as... Figure 9AAs shown, during the sixth time period t6, the sensing control signal SEN_ON of the gate on-state voltage Von can be applied to the sensing control terminal SEI of the k-th stage STk, and the first control clock signal S_CLK1 of the first gate off-state voltage Voff1 can be applied to the first control clock terminal CCI1. Therefore, as Figure 15 As shown, the first transistor T1, the second transistor T2, the third transistor T3, the eighth transistor T8, the (10-1)th transistor T10-1, the (10-2)th transistor T10-2, the twelfth transistor T12, the thirteenth transistor T13, the first scan pull-down transistor SCD1, the first sensing pull-down transistor SSD1, and the carry pull-down transistor CD can be turned on.

[0193] During the sixth time period t6, the operations of the first transistor T1, the second transistor T2, the third transistor T3, the eighth transistor T8, the (10-2)th transistor T10-2, the twelfth transistor T12, the thirteenth transistor T13, the first scan pull-down transistor SCD1, the first sensing pull-down transistor SSD1, and the carry pull-down transistor CD can be referenced above. Figure 14 The operations described during the fifth time period t5 are essentially the same.

[0194] Transistor (10-1) T10-1 is turned on by the gate conduction voltage Von of the third scan clock signal to connect the pull-up node Q to the second electrode of transistor (10-2) T10-2. Since both transistor (10-1) T10-1 and transistor (10-2) T10-2 are turned on during the sixth time period t6, the pull-up node Q can be connected to the carry output terminal CO.

[0195] Seventh, such as Figure 9A As shown, during the seventh time period t7, the carry signal CRk-2 of the first gate cutoff voltage Voff1 of the (k-2)th stage ST(k-2) can be applied to the start terminal CPI of the kth stage STk, and the carry signal CRk+2 of the first gate cutoff voltage Voff1 of the (k+2)th stage ST(k+2) can be applied to the next carry input terminal CNI. Furthermore, as... Figure 9A As shown, during the seventh time period t7, the third carry clock signal CK3_CR of the first gate cutoff voltage Voff1 can be applied to the first carry clock terminal CRI1 of the k-th stage STk, and the first carry clock signal CK1_CR of the first gate cutoff voltage Voff1 can be applied to the second carry clock terminal CRI2. Furthermore, as... Figure 9AAs shown, during the seventh time period t7, the third scan clock signal CK3_SC of the gate on-state voltage Von can be applied to the scan clock terminal SCI of the k-th stage STk, and the third sensing clock signal CK3_SS of the gate on-state voltage Von can be applied to the sensing clock terminal SSI. Furthermore, as... Figure 9A As shown, during the seventh time period t7, the sensing control signal SEN_ON of the first gate cutoff voltage Voff1 can be applied to the sensing control terminal SEI of the k-th stage STk, and the first control clock signal S_CLK1 of the first gate cutoff voltage Voff1 can be applied to the first control clock terminal CCI1. Therefore, as Figure 16 As shown, the second transistor T2, the third transistor T3, the (10-2)th transistor T10-2, the thirteenth transistor T13, the first scan pull-down transistor SCD1, the first sensing pull-down transistor SSD1, and the carry pull-down transistor CD can be turned on.

[0196] During the seventh time period t7, the operation of the second transistor T2, the third transistor T3, the (10-2)th transistor T10-2, the thirteenth transistor T13, the first scan pull-down transistor SCD1, the first sensing pull-down transistor SSD1, and the carry pull-down transistor CD can be referenced above. Figure 15 The operations described during the sixth time period t6 are essentially the same.

[0197] like Figures 9A to 16 As shown, during the effective time period, the k-th stage STk can output the k-th scan signal SCk and the k-th sensing signal SSk of the gate on-voltage Von in the second time period t2 and the third time period t3, and can output the carry signal CRk of the gate on-voltage Von in the third time period t3 and the fourth time period t4.

[0198] When the pull-up node Q has a gate on-voltage Von, the carry-up transistor CU can be turned on. Furthermore, when the pull-down node QB has a first gate off-voltage Voff1, the gate-source voltage Vgs (=Voff1-Voff2) of the carry-down transistor CD is greater than 0V, allowing a current path to be formed from the first carry clock terminal CRI1 to the second gate off terminal VOF2. For example, when a third carry clock signal of the first gate off-voltage Voff1 is applied to the first carry clock terminal CRI1, a current path can be formed from the first carry clock terminal CRI1 to the second gate off terminal VOF2. In this case, the current at the first gate off-voltage Voff1 can be increased, and the power consumption can be increased accordingly. Therefore, the power supply 180 can monitor the current of the first gate cutoff voltage Voff1, and when the current of the first gate cutoff voltage Voff1 is equal to or greater than the threshold, it can control the carry clock signals CK1_CR, CK2_CR and CK3_CR to swing from the second gate cutoff voltage Voff2 to the gate on voltage Von or the second gate on voltage Von2.

[0199] Figure 17 This is a waveform diagram illustrating, according to an exemplary embodiment of the present invention, the carry clock signal, scan clock signal, sensing clock signal, sensing control signal, (k-2)th carry signal, kth carry signal, (k+2)th carry signal, voltage of pull-up node, voltage of pull-down node, kth scan signal and kth sensing signal during the effective period and vertical blank period of the Nth frame.

[0200] exist Figure 17 During the effective period ACT of the Nth frame, the first carry clock signal to the third carry clock signals CK1_CR, CK2_CR and CK3_CR, the first scan clock signal to the fourth scan clock signals CK1_SC, CK2_SC, CK3_SC and CK4_SC, and the first sensing clock signal to the fourth sensing clock signals CK1_SS, CK2_SS, CK3_SS and CK4_SS are essentially equivalent to the above reference. Figure 9A Those described.

[0201] Reference Figure 17 The first carry clock signal to the third carry clock signals CK1_CR, CK2_CR and CK3_CR can be generated as the first gate cutoff voltage Voff1 during the 1' time period t1' to the 4' time period t4' of the vertical blank time period VB of the Nth frame.

[0202] Among the first to fourth scan clock signals CK1_SC, CK2_SC, CK3_SC, and CK4_SC, the third scan clock signal CK3_SC, input to the scan clock terminal SCI of the k-th stage STk, can be generated as the gate on-state voltage Von during the 3' time period t3' of the vertical blank period VB, and can be generated as the first gate off-state voltage Voff1 during the remaining time period of the vertical blank period VB. The remaining scan clock signals CK1_SC, CK2_SC, and CK4_SC can be generated as the first gate off-state voltage Voff1 during the 1' time period t1' to the 6' time period t6' of the vertical blank period VB.

[0203] Among the first to fourth sensing clock signals CK1_SS, CK2_SS, CK3_SS, and CK4_SS, the third sensing clock signal CK3_SS, input to the sensing clock terminal SSI of the k-th stage STk, can be generated as the gate on-state voltage Von during the 3' time period t3' and the 4' time period t4' of the vertical blank time period VB, and can be generated as the first gate off-state voltage Voff1 during the remaining time period. The remaining sensing clock signals CK1_SS, CK2_SS, and CK4_SS can be generated as the first gate off-state voltage Voff1 during the 1' time period t1' to the 6' time period t6' of the vertical blank time period VB.

[0204] The carry signal CRk-2 of the (k-2)th stage ST(k-2), the carry signal CRk of the kth stage STk, and the carry signal CRk+2 of the (k+2)th stage ST(k+2) can be generated as the first gate cutoff voltage Voff1 during the vertical blank period VB.

[0205] The sensing control signal SEN_ON can be generated as the gate on-voltage Von during the 6' time period t6' of the vertical blank period VB. The first control clock signal S_CLK1 can be generated as the gate on-voltage Von during the 2' time period t2' to the 4' time period t4' of the vertical blank period VB. The second control clock signal S_CLK2 can be generated as the gate on-voltage Von during the 1' time period t1' to the 5' time period t5' of the vertical blank period VB. The gate on-voltage Von period of the second control clock signal S_CLK2 can be longer than that of the first control clock signal S_CLK1.

[0206] Figures 18 to 24 This is a circuit diagram illustrating the operation of the kth level during the 1' to 7' time periods of the vertical blank period, according to an exemplary embodiment of the present invention.

[0207] In the following text, reference will be made to Figures 18 to 24Describe in detail the operation of level k during the 1' time interval t1' to the 7' time interval t7' of the vertical blank period.

[0208] During the 1' time period t1' to the 7' time period t7', the carry signal CRk-2 of the first gate cutoff voltage Voff1 of the (k-2)th stage ST(k-2) can be applied to the start terminal CPI of the kth stage STk, and the carry signal CRk+2 of the first gate cutoff voltage Voff1 of the (k+2)th stage ST(k+2) can be applied to the next carry input terminal CNI. Furthermore, during the 1' time period t1' to the 4' time period t4', the third carry clock signal CK3_CR of the first gate cutoff voltage Voff1 can be applied to the first carry clock terminal CRI1 of the kth stage STk, and the first carry clock signal CK1_CR of the first gate cutoff voltage Voff1 can be applied to the second carry clock terminal CRI2.

[0209] First, such as Figure 17 As shown, during time period t1', the third scan clock signal CK3_SC of the first gate cutoff voltage Voff1 can be applied to the scan clock terminal SCI of the k-th stage STk, and the third sensing clock signal CK3_SS of the first gate cutoff voltage Voff1 can be applied to the sensing clock terminal SSI. Furthermore, as... Figure 17 As shown, during time period t1', the sensing control signal SEN_ON of the first gate cutoff voltage Voff1 can be applied to the sensing control terminal SEI of the k-th stage STk, and the first control clock signal S_CLK1 of the first gate cutoff voltage Voff1 can be applied to the first control clock terminal CCI1. Therefore, as Figure 18 As shown, the second transistor T2, the third transistor T3, the (10-2)th transistor T10-2, the thirteenth transistor T13, the first scan pull-down transistor SCD1, the first sensing pull-down transistor SSD1, and the carry pull-down transistor CD can be turned on.

[0210] Transistor (10-2) T10-2 can be turned on by the gate on-state voltage Von of the pull-down node QB to connect the carry output terminal CO to the first electrode of transistor (10-1) T10-1. Therefore, when transistor (10-1) is turned on, the pull-up node Q can be connected to the carry output terminal CO.

[0211] The thirteenth transistor T13 is turned on by the gate conduction voltage Von of the pull-down node QB to connect the pull-down node QB to the gate conduction terminal VON.

[0212] The first scan pull-down transistor SCD1 is turned on by the gate on voltage Von of the pull-down node QB to output the first gate off voltage input to the first gate off terminal VOF1. In this way, the k-th scan signal SCk of the first gate off voltage Voff1 can be applied to the k-th scan signal line SCLk.

[0213] The first sensing pull-down transistor SSD1 is turned on by the gate on voltage Von of the pull-down node QB to output the first gate off voltage Voff1, which is input to the first gate off terminal VOF1, to the sensing output terminal SSO. In this way, the k-th sensing signal SSk of the first gate off voltage Voff1 can be applied to the k-th sensing signal line SSLk.

[0214] The carry pull-down transistor CD is turned on by the gate on voltage Von of the pull-down node QB to output the first gate off voltage input to the first gate off terminal VOF1 to the carry output terminal CO.

[0215] The second transistor T2 and the third transistor T3 are turned on by the gate on-state voltage Von of the sensing control node S to apply the first control clock signal S_CLK1, which is input to the first control clock terminal CCI1, to the pull-up node Q. Therefore, the first gate off-state voltage Voff1 of the first control clock signal S_CLK1 can be applied to the pull-up node Q.

[0216] Second, such as Figure 17 As shown, during the 2' time period t2', the third scan clock signal CK3_SC of the first gate cutoff voltage Voff1 can be applied to the scan clock terminal SCI of the k-th stage STk, and the third sensing clock signal CK3_SS of the first gate cutoff voltage Voff1 can be applied to the sensing clock terminal SSI. Furthermore, as... Figure 17 As shown, during the 2' time period t2', the sensing control signal SEN_ON of the first gate cutoff voltage Voff1 can be applied to the sensing control terminal SEI of the k-th stage STk, and the first control clock signal S_CLK1 of the gate on-voltage Von can be applied to the first control clock terminal CCI1. Therefore, as Figure 19 As shown, the second transistor T2, the third transistor T3, the eleventh transistor T11, the first scan pull-up transistor SCU1, the first sensing pull-up transistor SSU1, and the carry pull-up transistor CU can be turned on.

[0217] The second transistor T2 and the third transistor T3 are turned on by the gate on-state voltage of the sensing control node S to apply the first control clock signal S_CLK1, which is input to the first control clock terminal CCI1, to the pull-up node Q. Accordingly, because the gate on-state voltage Von of the first control clock signal S_CLK1 is applied to the pull-up node Q, the eleventh transistor T11, the first scan pull-up transistor SCU1, the first sensing pull-up transistor SSU1, and the carry pull-up transistor CU can be turned on.

[0218] The eleventh transistor T11 is turned on by the gate on voltage Von of the pull-up node Q to apply the first gate off voltage Voff1 of the first carry clock signal CK1_CR to the pull-down node QB. As a result, the first scan pull-down transistor SCD1, the first sensing pull-down transistor SSD1, and the carry pull-down transistor CD can be turned off.

[0219] The first scan pull-up transistor SCU1 is turned on by the gate on voltage Von of the pull-up node Q to output the third scan clock signal CK3_SC, which is the first gate off voltage Voff1 input to the scan clock terminal SCI, to the scan output terminal SCO. In this way, the k-th scan signal SCk of the first gate off voltage Voff1 can be applied to the k-th scan signal line SCLk.

[0220] The first sensing pull-up transistor SSU1 is turned on by the gate on voltage Von of the pull-up node Q to output the third sensing clock signal CK3_SC, which is the first gate off voltage Voff1 input to the sensing clock terminal SSI, to the sensing output terminal SSO. In this way, the k-th sensing signal SSk of the first gate off voltage Voff1 can be applied to the k-th sensing signal line SSLk.

[0221] The carry pull-up transistor CU is turned on by the gate on voltage Von of the pull-up node Q to output the third carry clock signal CK3_CR, which is input to the first carry clock terminal CRI1 and the first gate off voltage Voff1, to the carry output terminal CO.

[0222] Third, such as Figure 17 As shown, during the 3' time period t3', the third scan clock signal CK3_SC of the gate on-state voltage Von can be applied to the scan clock terminal SCI of the k-th stage STk, and the third sensing clock signal CK3_SS of the gate on-state voltage Von can be applied to the sensing clock terminal SSI. Furthermore, as... Figure 17 As shown, during the 3' time period t3', the sensing control signal SEN_ON of the first gate cutoff voltage Voff1 can be applied to the sensing control terminal SEI of the k-th stage STk, and the first control clock signal S_CLK1 of the gate on-voltage Von can be applied to the first control clock terminal CCI1. Therefore, as Figure 20 As shown, the second transistor T2, the third transistor T3, the (10-1)th transistor T10-1, the eleventh transistor T11, the first scan pull-up transistor SCU1, the first sensing pull-up transistor SSU1, and the carry pull-up transistor CU can be turned on.

[0223] During the 3' time period t3', the operations of the second transistor T2, the third transistor T3, the eleventh transistor T11, and the carry pull-up transistor CU can be referenced above. Figure 19 The operations described for the 2' time interval t2' are basically the same.

[0224] Transistor (10-1) T10-1 is turned on by the gate conduction voltage Von of the third scan clock signal CK3_SC to connect the pull-up node Q to the second electrode of transistor (10-2) T10-2.

[0225] The first scan pull-up transistor SCU1 is turned on by the gate on-state voltage Von of the pull-up node Q to output the third scan clock signal CK3_SC, which is the gate on-state voltage Von input to the scan clock terminal SCI, to the scan output terminal SCO. In this way, the k-th scan signal SCk of the gate on-state voltage Von can be applied to the k-th scan signal line SCLk.

[0226] The first sensing pull-up transistor SSU1 is turned on by the gate on-state voltage Von of the pull-up node Q to output the third sensing clock signal CK3_SS, which is the gate on-state voltage Von input to the sensing clock terminal SSI, to the sensing output terminal SSO. In this way, the k-th sensing signal SSk of the gate on-state voltage Von can be applied to the k-th sensing signal line SSLk.

[0227] When the third scan clock signal CK3_SC of the gate on-state voltage Von is applied to the scan output terminal SCO and the third sensing clock signal CK3_SS of the gate on-state voltage Von is applied to the sensing output terminal SSO, the pull-up node Q is bootstrapped by the second capacitor C2 so that the voltage can rise from the gate on-state voltage Von to a voltage Von' that is higher than the gate on-state voltage Von. This is caused by Figure 17 The voltage VQ is shown in the diagram.

[0228] Fourth, such as Figure 17 As shown, during the 4' time period t4', the third scan clock signal CK3_SC of the first gate cutoff voltage Voff1 can be applied to the scan clock terminal SCI of the k-th stage STk, and the third sensing clock signal CK3_SS of the gate on-voltage Von can be applied to the sensing clock terminal SSI. Furthermore, as... Figure 17As shown, during the 4' time period t4', the sensing control signal SEN_ON of the first gate cutoff voltage Voff1 can be applied to the sensing control terminal SEI of the k-th stage STk, and the first control clock signal S_CLK1 of the gate on-voltage Von can be applied to the first control clock terminal CCI1. Therefore, as Figure 21 As shown, the second transistor T2, the third transistor T3, the eleventh transistor T11, the first scan pull-up transistor SCU1, the first sensing pull-up transistor SSU1, and the carry pull-up transistor CU can be turned on.

[0229] During the 4' time period t4', the operation of the second transistor T2, the third transistor T3, the eleventh transistor T11, the first sensing pull-up transistor SSU1, and the carry pull-up transistor CU can be referenced above. Figure 20 The operations described for the 3' time period t3' are basically the same.

[0230] The first scan pull-up transistor SCU1 is turned on by the gate on voltage Von of the pull-up node Q to output the third scan clock signal CK3_SC, which is the first gate off voltage Voff1 input to the scan clock terminal SCI, to the scan output terminal SCO. In this way, the k-th scan signal SCk of the first gate off voltage Voff1 can be applied to the k-th scan signal line SCLk.

[0231] When the third scan clock signal CK3_SC of the first gate cutoff voltage Voff1 is applied to the scan output terminal SCO, the pull-up node Q can be bootstrapped by the first capacitor C1 and the second capacitor C2 so that the voltage can be reduced from a voltage Von' that is higher than the gate turn-on voltage Von to a voltage Von' having a level between the gate turn-on voltage Von and the voltage Von' that is higher than the gate turn-on voltage Von. This is caused by Figure 17 The voltage VQ is shown in the diagram.

[0232] Fifth, such as Figure 17 As shown, during the 5' time period t5', the third scan clock signal CK3_SC of the first gate cutoff voltage Voff1 can be applied to the scan clock terminal SCI of the k-th stage STk, and the third sensing clock signal CK3_SS of the first gate cutoff voltage Voff1 can be applied to the sensing clock terminal SSI. Furthermore, as... Figure 17As shown, during the 5' time period t5', the sensing control signal SEN_ON of the first gate cutoff voltage Voff1 can be applied to the sensing control terminal SEI of the k-th stage STk, and the first control clock signal S_CLK1 of the first gate cutoff voltage Voff1 can be applied to the first control clock terminal CCI1. Furthermore, the first carry clock signal CK1_CR of the gate on-voltage Von can be applied to the second carry clock terminal CRI2 of the k-th stage STk during a portion of the 5' time period t5'. Therefore, as... Figure 22 As shown, the second transistor T2, the third transistor T3, the (10-2)th transistor T10-2, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first scan pull-down transistor SCD1, the first sensing pull-down transistor SSD1, and the carry pull-down transistor CD can be turned on.

[0233] During the 5' time period t5', the second transistor T2 and the third transistor T3 are turned on by the gate on-state voltage of the sensing control node S to apply the first control clock signal S_CLK1, which is input to the first control clock terminal CCI1, to the pull-up node Q. Accordingly, because the first gate off-state voltage Voff1 of the first control clock signal S_CLK1 is applied to the pull-up node Q, the eleventh transistor T11, the first scan pull-up transistor SCU1, the first sensing pull-up transistor SSU1, and the carry pull-up transistor CU can be turned off.

[0234] The twelfth transistor T12 is turned on by the first carry clock signal CK1_CR, which is input to the gate on-state voltage Von of the second carry clock terminal CRI2, to connect the pull-down node QB to the gate on-state terminal VON. Accordingly, the pull-up node Q has a gate on-state voltage Von, and accordingly, the (10-2)th transistor T10-2, the thirteenth transistor T13, the first scan pull-down transistor SCD1, the first sense pull-down transistor SSD1, and the carry pull-down transistor CD can be turned on.

[0235] Transistor (10-2) T10-2 can be turned on by the gate on-state voltage Von of the pull-down node QB to connect the carry output terminal CO to the first electrode of transistor (10-1) T10-1. Therefore, when transistor (10-1) T10-1 is turned on, the pull-up node Q can be connected to the carry output terminal CO.

[0236] The thirteenth transistor T13 is turned on by the gate conduction voltage Von of the pull-down node QB to connect the pull-down node QB to the gate conduction terminal VON.

[0237] The first scan pull-down transistor SCD1 is turned on by the gate on voltage Von of the pull-down node QB to output the first gate off voltage Voff1 input to the first gate off terminal VOF1. In this way, the k-th scan signal SCk of the first gate off voltage Voff1 can be applied to the k-th scan signal line SCLk.

[0238] The first sensing pull-up transistor SSU1 is turned on by the gate on voltage Von of the pull-down node QB to output the first gate off voltage Voff1, which is input to the first gate off terminal VOF1, to the sensing output terminal SSO. In this way, the k-th sensing signal SSk of the first gate off voltage Voff1 can be applied to the k-th sensing signal line SSLk.

[0239] The carry pull-down transistor CD is turned on by the gate on voltage Von of the pull-down node QB to output the first gate off voltage Voff1, which is input to the first gate off terminal VOF1, to the carry output terminal CO.

[0240] Sixth, such as Figure 17 As shown, during the 6' time period t6', the third scan clock signal CK3_SC of the first gate cutoff voltage Voff1 can be applied to the scan clock terminal SCI of the k-th stage STk, and the third sensing clock signal CK3_SS of the gate cutoff voltage Voff1 can be applied to the sensing clock terminal SSI. Furthermore, as... Figure 17 As shown, during the 6' time period t6', the sensing control signal SEN_ON of the gate on-state voltage Von can be applied to the sensing control terminal SEI of the k-th stage STk, and the first control clock signal S_CLK1 of the first gate off-state voltage Voff1 can be applied to the first control clock terminal CCI1. Furthermore, the first carry clock signal CK1_CR of the gate on-state voltage Von can be applied to the second carry clock terminal CRI2 of the k-th stage STk during the 6' time period t6'. Therefore, as... Figure 23 As shown, the first transistor T1, the (10-2)th transistor T10-2, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first scan pull-down transistor SCD1, the first sensing pull-down transistor SSD1, and the carry pull-down transistor CD can be turned on.

[0241] During the 6' time period t6', the operation of transistor (10-2) T10-2, transistor 11, transistor 12, transistor 13, first scan pull-down transistor SCD1, first sensing pull-down transistor SSD1, and carry pull-down transistor CD can be the same as described above. Figure 22 The operations described for the 5' time period t5' are basically the same.

[0242] The first transistor T1 is turned on by the gate on voltage Von of the sensing control signal SEN_ON input to the sensing control terminal SEI to connect the next carry input terminal CNI to the sensing control node S. Correspondingly, the sensing control node S has a first gate off voltage Voff1 for the carry signal of the (k+2)th stage ST(k+2), which allows the second transistor T2 and the third transistor T3 to be turned off.

[0243] Seventh, such as Figure 17 As shown, during the 7' time period t7', the third scan clock signal CK3_SC of the first gate cutoff voltage Voff1 can be applied to the scan clock terminal SCI of the k-th stage STk, and the third sensing clock signal CK3_SS of the first gate cutoff voltage Voff1 can be applied to the sensing clock terminal SSI. Furthermore, as... Figure 17 As shown, during the 7' time period t7', the sensing control signal SEN_ON of the first gate cutoff voltage Voff1 can be applied to the sensing control terminal SEI of the k-th stage STk, and the first control clock signal S_CLK1 of the first gate cutoff voltage Voff1 can be applied to the first control clock terminal CCI1. Furthermore, the first carry clock signal CK1_CR of the first gate cutoff voltage Voff1 can be applied to the second carry clock terminal CRI2 of the k-th stage STk during the 7' time period t7'. Therefore, as... Figure 24 As shown, transistors (10-2) T10-2, eleventh transistor T11, twelfth transistor T12, thirteenth transistor T13, first scan pull-down transistor SCD1, first sensing pull-down transistor SSD1, and carry pull-down transistor CD can be turned on.

[0244] During the 7' time period t7', the operation of transistor (10-2) T10-2, transistor eleven T11, transistor twelfth T12, transistor thirteenth T13, first scan pull-down transistor SCD1, first sensing pull-down transistor SSD1, and carry pull-down transistor CD can be the same as described above. Figure 22 The operations described for the 5' time period t5' are basically the same.

[0245] like Figures 17 to 24 As shown, the k-th stage STk can output the k-th scan signal SCk of the gate on-voltage Von during the 3' time period t3' in the vertical blank time period VB, and can output the k-th sensing signal SSk of the gate on-voltage Von during the 3' time period t3' and the 4' time period t4' in the vertical blank time period VB.

[0246] The area of ​​the scan signal driver 200 according to an exemplary embodiment of the present invention can be reduced because the k-th stage STk can simultaneously output the k-th scan signal SCk and the k-th sensing signal SSk. Furthermore, in order to apply a data voltage to the sub-pixel SP during the active period ACT, the k-th stage STk can output the k-th scan signal SCk and the k-th sensing signal SSk as gate on-voltage Von during two horizontal periods 2H. Conversely, in order to sense the source voltage of the driving transistor DT of each of the sub-pixels SP during the vertical blank period VB, the k-th stage STk can output the k-th scan signal SCk as gate on-voltage Von during four horizontal periods 4H, and can output the k-th sensing signal SSk as gate on-voltage Von during eight horizontal periods 8H.

[0247] Figure 25 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0248] Figure 25 The exemplary embodiments shown are in conjunction with Figure 8 The difference in the exemplary embodiment is that the second pull-up node controller 250 includes a (8-1) transistor T8-1 and a (8-2) transistor T8-2.

[0249] Reference Figure 25 When the carry signal CRk+2 from the input of stage (k+2) ST(k+2) to the next carry input terminal CNI has a gate on voltage Von, the second pull-up node controller 250 applies a second gate off voltage Voff2 to the pull-up node Q. The second pull-up node controller 250 may include an eighth transistor T8, and the eighth transistor T8 may include an (8-1) transistor T8-1 and an (8-2) transistor T8-2.

[0250] Transistor (8-1) T8-1 and transistor (8-2) T8-2 are turned on by the gate on-state voltage Von of the carry signal CRk+2 of stage (k+2) ST(k+2) to connect the pull-up node Q to the carry output terminal CO, so that the second gate off-state voltage Voff2 can be applied to the pull-up node Q. The gate electrode of transistor (8-1) T8-1 can be connected to the next carry input terminal CNI, the first electrode of transistor (8-1) T8-1 can be connected to the second electrode of transistor (8-2) T8-2, and the second electrode of transistor (8-1) T8-1 can be connected to the pull-up node Q. The gate electrode of transistor (8-2) T8-2 can be connected to the next carry input terminal CNI, the first electrode of transistor (8-2) T8-2 can be connected to the second gate off-state terminal VOF2 with the second gate off-state voltage Voff2 applied, and the second electrode of transistor (8-2) T8-2 can be connected to the first electrode of transistor (8-1) T8-1.

[0251] like Figure 25 As shown, when the carry signal CRk+2 of the input of the (k+2)th stage ST(k+2) to the next carry input terminal CNI has a gate on voltage Von, the second pull-up node controller 250 can connect the pull-up node Q to the second gate off terminal VOF2 with the second gate off voltage Voff2 applied instead of the carry output terminal CO, so that the second gate off voltage Voff2 can be applied to the pull-up node Q.

[0252] Furthermore, because the voltage at the pull-up node Q can be controlled by the tenth transistor T10 having a second gate cutoff voltage Voff2, therefore... Figure 25 In the example shown, the second gate cutoff terminal VOF2 connected to the first electrode of the (8-2) transistor T8-2 can be replaced with the first gate cutoff terminal VOF1 to which the first gate cutoff voltage Voff1 is applied.

[0253] Figure 26 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0254] Figure 26 The exemplary embodiments shown are in conjunction with Figure 25 The exemplary embodiment differs in that the second pull-up node controller 250 further includes a ninth transistor T9.

[0255] Reference Figure 26The ninth transistor T9 is turned on by the gate on-state voltage Von of the carry output terminal CO, connecting the carry output terminal CO between the (8-1) transistor T8-1 and the (8-2) transistor T8-2. While the ninth transistor T9 is turned on, the first electrode of the (8-1) transistor T8-1, the second electrode of the (8-2) transistor T8-2, and the carry output terminal CO can be connected to each other. Thus, while the pull-up node Q has the gate on-state voltage Von, leakage current can be prevented from flowing through the (8-1) transistor T8-1 and the (8-2) transistor T8-2.

[0256] Figure 27 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0257] Figure 27 The exemplary embodiments shown are in conjunction with Figure 8 The exemplary embodiment differs in that the second pull-up node controller 250 further includes a ninth transistor T9.

[0258] Reference Figure 27 The ninth transistor T9 is turned on by the gate on-state voltage Von of the pull-up node Q, connecting the pull-up node Q to the gate on-state terminal VON where the gate on-state voltage Von is applied. The gate electrode and the first electrode of the ninth transistor T9 can be connected to the pull-up node Q, and the second electrode can be connected to the gate on-state terminal VON. In this way, while the pull-up node Q has the gate on-state voltage Von, the potential of the pull-up node Q can be stably maintained at the gate on-state voltage Von.

[0259] Figure 28 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0260] Figure 28 The exemplary embodiments shown are in conjunction with Figure 8 The difference in the exemplary embodiment is that the sensing controller 230 further includes a fourth transistor T4.

[0261] Reference Figure 28 The second transistor T2 is turned on by the gate on-state voltage Von of the second control clock signal S_CLK2 input to the second control clock terminal CCI2, thereby connecting the first control clock terminal CCI1 to the second electrode of the third transistor T3. The gate electrode of the second transistor T2 can be connected to the second control clock terminal CCI2, the first electrode of the second transistor T2 can be connected to the second electrode of the third transistor T3, and the second electrode of the second transistor T2 can be connected to the first control clock terminal CCI1.

[0262] The third transistor T3 is turned on by the gate on-state voltage Von of the sensing control node S to connect the pull-up node Q to the first electrode of the second transistor T2. The gate electrode of the third transistor T3 can be connected to the sensing control node S, the first electrode of the third transistor T3 can be connected to the pull-up node Q, and the second electrode of the third transistor T3 can be connected to the first electrode of the second transistor T2.

[0263] The fourth transistor T4 is turned on by the gate on-state voltage Von of the pull-up node Q, connecting the gate on-state terminal VON, to which the gate on-state voltage Von is applied, between the second transistor T2 and the third transistor T3. While the fourth transistor T4 is turned on, the first electrode of the second transistor T2, the second electrode of the third transistor T3, and the gate on-state terminal VON can be connected to each other. Accordingly, the gate on-state voltage Von can be applied between the second transistor T2 and the third transistor T3. Therefore, the stress applied to the second transistor T2 and the third transistor T3 due to high drain-source voltage can be reduced.

[0264] Figure 29 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0265] Figure 29 The exemplary embodiments shown are in conjunction with Figure 28 The difference in the exemplary embodiment is that the second transistor T2 is controlled by the sensing control node S and the third transistor T3 is controlled by the second control clock signal S_CLK2 of the second control clock terminal CCI2.

[0266] Reference Figure 29 The second transistor T2 is turned on by the gate on-state voltage Von of the sensing control node S to connect the first control clock terminal CCI1 to the second electrode of the third transistor T3. The gate electrode of the second transistor T2 can be connected to the sensing control node S, the first electrode of the second transistor T2 can be connected to the second electrode of the third transistor T3, and the second electrode of the second transistor T2 can be connected to the first control clock terminal CCI1.

[0267] The third transistor T3 is turned on by the gate conduction voltage Von of the second control clock signal S_CLK2 input to the second control clock terminal CCI2, so as to connect the pull-up node Q to the first electrode of the second transistor T2. The gate electrode of the third transistor T3 can be connected to the second control clock terminal CCI2, the first electrode of the third transistor T3 can be connected to the pull-up node Q, and the second electrode of the third transistor T3 can be connected to the first electrode of the second transistor T2.

[0268] like Figure 9A and Figure 17As shown, the second control clock signal S_CLK2 input to the second control clock terminal CCI2 oscillates between the third gate cutoff voltage Voff3 and the gate on voltage Von, while the first control clock signal S_CLK1 input to the first control clock terminal CCI1 oscillates between the second gate cutoff voltage Voff2 and the gate on voltage Von. Furthermore, the sensing control node S oscillates between the first gate cutoff voltage Voff1 and the gate on voltage Von. The third gate cutoff voltage Voff3 may have a lower level than the second gate cutoff voltage Voff2, the second gate cutoff voltage Voff2 may have a lower level than the first gate cutoff voltage Voff1, and the first gate cutoff voltage Voff1 may have a lower level than the gate on voltage Von. In this case, even when the fourth transistor T4 is turned on, the gate on voltage Von is applied between the second transistor T2 and the third transistor T3, and the third gate cutoff voltage Voff3 with the lowest potential is applied to the gate electrode of the third transistor T3, thus preventing the gate high voltage VGH from leaking to the pull-up node Q through the third transistor T3.

[0269] Figure 30 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0270] Figure 30 The exemplary embodiments shown are in conjunction with Figure 28 The difference in the exemplary embodiment is that the sensing controller 230 further includes a fifth transistor T5, the inverter 270 further includes a fourteenth transistor T14, and the k-th stage STk further includes a pull-down node controller 280 having fifteenth to seventeenth transistors T15, T16 and T17.

[0271] Reference Figure 30 The gate electrode of the fourth transistor T4 can be connected to the carry output terminal CO instead of the pull-up node Q, and the second electrode of the fourth transistor T4 can be connected to the carry output terminal CO instead of the gate conduction terminal Von.

[0272] The fifth transistor T5 is turned on by the gate on-state voltage Von of the sensing control node S to connect the gate on-state terminal VON, to which the applied gate on-state voltage Von is applied, between the (1-1) transistor T1-1 and the (1-2) transistor T1-2. By means of the fifth transistor T5, leakage of the gate on-state voltage Von of the sensing control node S through the (1-1) transistor T1-1 and the (1-2) transistor T1-2 can be prevented or reduced. The gate electrode of the fifth transistor T5 can be connected to the sensing control node S, the first electrode of the fifth transistor T5 can be connected between the (1-1) transistor T1-1 and the (1-2) transistor T1-2, and the second electrode of the fifth transistor T5 can be connected to the gate on-state terminal VON.

[0273] The second electrode of transistor (11-1) T11-1 can be connected to the first gate cutoff terminal VOF1, which is subjected to the first gate cutoff voltage Voff1, instead of the second carry clock terminal CRI2.

[0274] The fourteenth transistor T14 is turned on by the gate on-state voltage Von of the pull-down node QB to connect the gate on-state terminal VON, to which the applied gate on-state voltage Von is applied, between the (11-1) transistor T11-1 and the (11-2) transistor T11-2. With the help of the fourteenth transistor T14, the threshold voltages of the (11-1) transistor T11-1 and the (11-2) transistor T11-2 are prevented from shifting negatively, and therefore, leakage of the gate on-state voltage Von of the pull-down node QB through the (11-1) transistor T11-1 and the (11-2) transistor T11-2 is prevented or reduced. The gate electrode of the fourteenth transistor T14 can be connected to the pull-down node QB, the first electrode of the fourteenth transistor T14 can be connected between the (11-1) transistor T11-1 and the (11-2) transistor T11-2, and the second electrode of the fourteenth transistor T14 can be connected to the gate on-state terminal VON.

[0275] When the sensing control node S has a gate on-state voltage Von, the pull-down node controller 280 does not apply the gate on-state voltage Von to the pull-down node QB. When the sensing control node S has a second gate off-state voltage Voff2, the pull-down node controller 280 applies the gate on-state voltage Von to the pull-down node QB. The pull-down node controller 280 may include a thirteenth transistor T13, fifteenth to seventeenth transistors T15, T16 and T17, and a fifth capacitor C5.

[0276] The thirteenth transistor T13 is essentially equivalent to Figure 8 The thirteenth transistor T13, except that its second electrode is connected to the first electrode of the sixteenth transistor T16 instead of the gate conduction terminal VON.

[0277] The fifteenth transistor T15 may include a (15-1) transistor T15-1 and a (15-2) transistor T15-2. Transistors (15-1) T15-1 and (15-2) T15-2 are turned on by the gate on-state voltage Von of the sensing control node S, connecting the gate electrode of the thirteenth transistor T13 to the first gate off-state terminal VOF1 where a first gate off-state voltage Voff1 is applied. The gate electrode of transistor (15-1) T15-1 can be connected to the sensing control node S, the first electrode of transistor (15-1) T15-1 can be connected to the second electrode of transistor (15-2) T15-2, and the second electrode of transistor (15-1) T15-1 can be connected to the gate electrode of the thirteenth transistor T13. The gate electrode of transistor (15-2) T15-2 can be connected to the sensing control node S, the first electrode of transistor (15-2) T15-2 can be connected to the first gate cutoff terminal VOF1, and the second electrode of transistor (15-2) T15-2 can be connected to the first electrode of transistor (15-1) T15-1. The first electrode of transistor (15-2) T15-2 can be connected to the second gate cutoff terminal VOF2 where the second gate cutoff voltage Voff2 is applied, instead of the first gate cutoff terminal VOF1.

[0278] The sixteenth transistor T16 is turned on by the gate conduction voltage Von of the first control clock signal S_CLK1 input to the first control clock terminal CCI1, so as to connect the gate conduction terminal VON with the applied gate conduction voltage Von to the second electrode of the thirteenth transistor T13. The gate electrode of the sixteenth transistor T16 can be connected to the first control clock terminal CCI1, the first electrode of the sixteenth transistor T16 can be connected to the second electrode of the thirteenth transistor T13, and the second electrode of the sixteenth transistor T16 can be connected to the gate conduction terminal VON.

[0279] The seventeenth transistor T17 is turned on by the gate conduction voltage Von of the carry signal CRk-2 input to the start terminal CPI of stage (k-2), so as to connect the gate conduction terminal VON with the applied gate conduction voltage Von to the gate electrode of the thirteenth transistor T13. The gate electrode of the seventeenth transistor T17 can be connected to the start terminal CPI, the first electrode of the seventeenth transistor T17 can be connected to the gate electrode of the thirteenth transistor T13, and the second electrode of the seventeenth transistor T17 can be connected to the gate conduction terminal VON.

[0280] A fifth capacitor C5 is disposed between the gate electrode of the thirteenth transistor T13 and the first gate cutoff terminal VOF1 to which the first gate cutoff voltage Voff1 is applied. One electrode of the fifth capacitor C5 can be connected to the gate electrode of the thirteenth transistor T13, and the other electrode of the fifth capacitor C5 can be connected to the first gate cutoff terminal VOF1. Because the fifth capacitor C5 stores the voltage difference between the gate electrode of the thirteenth transistor T13 and the first gate cutoff terminal VOF1, the voltage difference between the gate electrode of the thirteenth transistor T13 and the first gate cutoff terminal VOF1 can be maintained by the fifth capacitor C5.

[0281] like Figure 30 As shown, during the vertical blank period, when the sensing control node S has a gate on-state voltage Von to output the k-th scan signal SCk and the k-th sensing signal SSk, the pull-down node controller 280 of the k-th stage STk does not apply the gate on-state voltage Von to the pull-down node QB. Furthermore, because the pull-down node controller 280 of the k-th stage STk does not output the k-th scan signal SCk and the k-th sensing signal SSk during the vertical blank period, it can apply the gate on-state voltage Von to the pull-down node QB to stably maintain the potential of the pull-down node QB when the sensing control node S does not have a gate on-state voltage.

[0282] Figure 31 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0283] Figure 31 The exemplary embodiments shown are in conjunction with Figure 8 The difference in the exemplary embodiment is that the first pull-up node controller 240 further includes a seventh transistor T7, and the eighth transistor T8 of the second pull-up node controller 250 and the tenth transistor T10 of the third pull-up node controller 260 are connected to the second gate cutoff terminal VOF2 where the second gate cutoff voltage Voff2 is applied instead of the carry output terminal CO.

[0284] Reference Figure 31The sixth transistor T6 may include transistor (6-1) T6-1 and transistor (6-2) T6-2. Transistor (6-1) T6-1 and transistor (6-2) T6-2 are turned on by the gate on-state voltage Von of the carry signal input from stage (k-2) ST(k-2) to the start terminal CPI, thereby connecting the pull-up node Q to the gate on-state terminal VON. Thus, the gate on-state voltage Von can be applied to the pull-up node Q. The gate electrode and second electrode of transistor (6-1) T6-1 can be connected to the start terminal CPI, and the first electrode of transistor (6-1) T6-1 can be connected to the second electrode of transistor (6-2) T6-2. The gate electrode of transistor (6-2) T6-2 can be connected to the start terminal CPI, the first electrode of transistor (6-2) T6-2 can be connected to the pull-up node Q, and the second electrode of transistor (6-2) T6-2 can be connected to the first electrode of transistor (6-1) T6-1.

[0285] The eighth transistor T8 may include transistor (8-1) T8-1 and transistor (8-2) T8-2. Transistor (8-1) T8-1 and transistor (8-2) T8-2 are turned on by the gate on voltage Von of the carry signal input from stage (k+2) ST(k+2) to the next carry input terminal CNI, so as to connect the pull-up node Q to the second gate off terminal VOF2 with the second gate off voltage Voff2 applied. In this way, the second gate off voltage Voff2 can be applied to the pull-up node Q. The gate electrode of transistor (8-1) T8-1 can be connected to the next carry input terminal CNI, the first electrode of transistor (8-1) T8-1 can be connected to the second electrode of transistor (8-2) T8-2, and the second electrode of transistor (8-1) T8-1 can be connected to the pull-up node Q. The gate electrode of transistor (8-2) T8-2 can be connected to the next carry input terminal CNI, the first electrode of transistor (8-2) T8-2 can be connected to the second gate cutoff terminal VOF2, and the second electrode of transistor (8-2) T8-2 can be connected to the first electrode of transistor (8-1) T8-1.

[0286] The tenth transistor T10 may include a (10-1) transistor T10-1 and a (10-2) transistor T10-2. The (10-1) transistor T10-1 and the (10-2) transistor T10-2 may be turned on by the gate on-state voltage Von of the third scan clock signal or the third sense clock signal to connect the pull-up node Q to the second gate off terminal VOF2 where a second gate off voltage Voff2 is applied. The gate electrode of the (10-1) transistor T10-1 may be connected to the scan clock terminal SCI or the sense clock terminal SSI, the first electrode of the (10-1) transistor T10-1 may be connected to the second electrode of the (10-2) transistor T10-2, and the second electrode of the (10-1) transistor T10-1 may be connected to the pull-up node Q. The gate electrode of transistor (10-2) T10-2 can be connected to the scan clock terminal SCI or the sense clock terminal SSI, the first electrode of transistor (10-2) T10-2 can be connected to the second gate cutoff terminal VOF2, and the second electrode of transistor (10-2) T10-2 can be connected to the first electrode of transistor (10-1) T10-1.

[0287] The seventh transistor T7 can be turned on by the gate on-state voltage Von of the carry output terminal CO to connect between transistors (6-1) T6-1 and (6-2) T6-2, between transistors (8-1) T8-1 and (8-2) T8-2, and between transistors (10-1) T10-1 and (10-2) T10-2. With the aid of the seventh transistor T7, leakage of the gate on-state voltage Von of the pull-up node Q through transistors (6-1) T6-1 and (6-2) T6-2 can be prevented or reduced. Furthermore, with the aid of the seventh transistor T7, leakage of the gate on-state voltage Von of the pull-up node Q through transistors (8-1) T8-1 and (8-2) T8-2 can be prevented or reduced. Furthermore, by means of the seventh transistor T7, leakage of the gate conduction voltage Von of the pull-up node Q through the (10-1) transistor T10-1 and the (10-2) transistor T10-2 can be prevented or reduced.

[0288] Figure 32 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0289] Figure 32 The exemplary embodiments shown are in conjunction with Figure 31 The difference in the exemplary embodiment is that the inverter 270 includes eighteenth to twenty-first transistors T18, T19, T20 and T21 instead of eleventh to thirteenth transistors T11, T12 and T13.

[0290] Reference Figure 32 The eighteenth transistor T18 is turned on by the gate on voltage Von at the gate on terminal VON to apply the gate on voltage Von to the gate electrode of the nineteenth transistor T19. The gate electrode and second electrode of the eighteenth transistor T18 can be connected to the gate on terminal VON, and the first electrode of the eighteenth transistor T18 can be connected to the gate electrode of the nineteenth transistor T19. The gate electrode and second electrode of the eighteenth transistor T18 can be connected to the second carry clock terminal CRI2 instead of the gate on terminal VON.

[0291] The nineteenth transistor T19 is turned on when a gate on voltage Von is applied to its gate electrode to connect the pull-down node QB to the gate on terminal VON. The gate electrode of the nineteenth transistor T19 can be connected to the first electrode of the eighteenth transistor T18, the first electrode of the nineteenth transistor T19 can be connected to the pull-down node QB, and the second electrode of the nineteenth transistor T19 can be connected to the gate on terminal VON.

[0292] The twentieth transistor T20 can be turned on by the gate on-state voltage Von of the pull-up node Q to connect the gate electrode of the nineteenth transistor T19 to the second gate off-state terminal VOF2, which is subject to the second gate off-state voltage Voff2. The gate electrode of the twentieth transistor T20 can be connected to the pull-up node Q, the first electrode of the twentieth transistor T20 can be connected to the second gate off-state terminal VOF2, and the second electrode of the twentieth transistor T20 can be connected to the gate electrode of the nineteenth transistor T19. The first electrode of the twentieth transistor T20 can be connected to the third gate off-state terminal VOF3, which is subject to a third gate off-state voltage Voff3 lower than the second gate off-state voltage Voff2, instead of the second gate off-state terminal VOF2.

[0293] The twenty-first transistor T21 can be turned on by the gate on-state voltage Von of the pull-down node QB to connect the pull-up node Q to the second gate off-state terminal VOF2. The gate electrode of the twenty-first transistor T21 can be connected to the pull-up node Q, the first electrode of the twenty-first transistor T21 can be connected to the second gate off-state terminal VOF2, and the second electrode of the twenty-first transistor T21 can be connected to the pull-down node QB. The first electrode of the twenty-first transistor T21 can be connected to the third gate off-state terminal VOF3 instead of the second gate off-state terminal VOF2.

[0294] Figure 33 This is a view illustrating another scan signal driver according to an exemplary embodiment of the concept according to the present invention.

[0295] Figure 33 The exemplary embodiments shown are in conjunction with Figure 7The exemplary embodiment differs in that each of stages ST(k-2) to ST(k+1) further includes a second scan clock terminal SCI2, a second sensing clock terminal SSI2, a second scan output terminal SCO2, and a second sensing output terminal SSO2.

[0296] Reference Figure 33 Each of the first scan clock terminal SCI1 and the second scan clock terminal SCI2 of each of stages ST(k-2) to ST(k+1) can be connected to one of the scan clock lines SCC1 to SCC4. Scan clock lines SCC1 to SCC4 can be sequentially connected to the first scan clock terminal SCI1 and the second scan clock terminal SCI2 of stages ST(k-2) to ST(k+2). For example, as... Figure 33 As shown, the third scan clock line SCC3 can be connected to the first scan clock terminal SCI1 of each of the (k-1)th stage ST(k-1) and the (k+1)th stage ST(k+1), and the fourth scan clock line SCC4 can be connected to the second scan clock terminal SCI2 of each of the (k-1)th stage ST(k-1) and the (k+1)th stage ST(k+1). The first scan clock line SCC1 can be connected to the first scan clock terminal SCI1 of each of the (k-2)th stage ST(k-2) and the kth stage STk, and the second scan clock line SCC2 can be connected to the second scan clock terminal SCI2 of each of the (k-2)th stage ST(k-2) and the kth stage STk. In each of stages ST(k-2) to ST(k+1), one of the odd-numbered scan clock lines can be connected to the first scan clock terminal SCI1, and one of the even-numbered scan clock lines can be connected to the second scan clock terminal SCI2.

[0297] Each of the first sensing clock terminal SSI1 and the second sensing clock terminal SSI2 of each of stages ST(k-2) to ST(k+1) can be connected to one of sensing clock lines SEC1 to SEC4. Sensing clock lines SEC1 to SEC4 can be sequentially connected to the first sensing clock terminal SSI1 and the second sensing clock terminal SSI2 of stages ST(k-2) to ST(k+1). For example, as... Figure 33As shown, in each of the (k-2)th level ST(k-2) and the kth level STk, the first sensing clock line SEC1 can be connected to the first sensing clock terminal SSI1, and the second sensing clock line SEC2 can be connected to the second sensing clock terminal SSI2. In each of the (k-1)th level ST(k-1) and the (k+1)th level ST(k+1), the third sensing clock line SEC3 can be connected to the first sensing clock terminal SSI1, and the fourth sensing clock line SEC4 can be connected to the second sensing clock terminal SSI2. In each of the levels ST(k-2) to ST(k+1), one of the odd-numbered sensing clock lines can be connected to the first sensing clock terminal SSI1, and one of the even-numbered sensing clock lines can be connected to the second sensing clock terminal SSI2.

[0298] In each of stages ST(k-2) to ST(k+1), the first scan output terminal SCO1 is connected to the odd-numbered scan signal line to output an odd-numbered scan signal, while the second scan output terminal SCO2 is connected to the even-numbered scan signal line to output an even-numbered scan signal. For example, as Figure 33 As shown, the first scan output terminal SCO1 of the k-th stage STk can be connected to the (2k-1)-th scan signal line SCL2k-1 to output the (2k-1)-th scan signal, and the second scan output terminal SCO2 can be connected to the 2k-th scan signal line SCL2k to output the 2k-th scan signal.

[0299] In each of stages ST(k-2) to ST(k+1), the first sensing output terminal SSO1 is connected to the odd-numbered sensing signal line to output an odd-numbered sensing signal, while the second sensing output terminal SSO2 is connected to the even-numbered sensing signal line to output an even-numbered sensing signal. For example, as Figure 33 As shown, the first sensing output terminal SSO1 of the k-th stage STk can be connected to the (2k-1)-th sensing signal line SSL2k-1 to output the (2k-1)-th sensing signal, and the second sensing output terminal SSO2 can be connected to the 2k-th sensing signal line SSL2k to output the 2k-th sensing signal.

[0300] like Figure 33 As shown, each of stages ST(k-2) to ST(k+1) can simultaneously output two scan signals and two sensing signals. Therefore, the scan signal driver 200 includes a single stage for simultaneously outputting multiple scan signals and multiple sensing signals. Thus, compared to a scan signal driver that includes one stage for outputting scan signals and another stage for outputting sensing signals, the area of ​​the scan signal driver 200 can be reduced.

[0301] Figure 34This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0302] Figure 34 The exemplary embodiments shown are in conjunction with Figure 8 The difference in the exemplary embodiment is that the first output unit 210 of the k-th stage STk further includes a second scan pull-up transistor SCU2, a second sense pull-up transistor SSU2, a second scan pull-down transistor SCD2 and a second sense pull-down transistor SSD2, and the gate electrode of the (10-1) transistor T10-1 is connected to the pull-down node QB.

[0303] Reference Figure 34 When the pull-up node Q has a gate on-voltage, the first output unit 210 outputs the third scan clock signal input to the first scan clock terminal SCI1 to the first scan output terminal SCO1, and outputs the third sensing clock signal input to the first sensing clock terminal SSI1 to the first sensing output terminal SSO1. Furthermore, when the pull-up node Q has a gate on-voltage, the first output unit 210 outputs the fourth scan clock signal input to the second scan clock terminal SCI2 to the second scan clock terminal SCO2, and outputs the fourth sensing clock signal input to the second sensing clock terminal SSI2 to the second sensing output terminal SSO2. When the pull-down node QB has a gate on-voltage, the first output unit 210 outputs the first gate off-voltage to the first scan output terminal SCO1, the first sensing output terminal SSO1, the second scan output terminal SCO2, and the second sensing output terminal SSO2.

[0304] The first output unit 210 may include a first scan pull-up transistor SCU1, a second scan pull-up transistor SCU2, a first scan pull-down transistor SCD1, a second scan pull-down transistor SCD2, a first sensing pull-up transistor SSU1, a second sensing pull-up transistor SSU2, a first sensing pull-down transistor SSD1, a second sensing pull-down transistor SSD2, a first capacitor C1, a second capacitor C2, a sixth capacitor C6, and a seventh capacitor C7.

[0305] The first scan pull-up transistor SCU1, the first scan pull-down transistor SCD1, the first sensing pull-up transistor SSU1, the first sensing pull-down transistor SSD1, the first capacitor C1, and the second capacitor C2 are essentially the same as those described above. Figure 8 Those described.

[0306] The second scan pull-up transistor SCU2 is turned on by the gate conduction voltage of the pull-up node Q to output the fourth scan clock signal input to the second scan clock terminal SCI2 to the second scan output terminal SCO2. The gate electrode of the second scan pull-up transistor SCU2 can be connected to the pull-up node Q, the first electrode of the second scan pull-up transistor SCU2 can be connected to the second scan output terminal SCO2, and the second electrode of the second scan pull-up transistor SCU2 can be connected to the second scan clock terminal SCI2.

[0307] The second scan pull-down transistor SCD2 is turned on by the gate on voltage of the pull-down node QB to output the first gate off voltage input to the first gate off terminal VOF1 to the second scan output terminal SCO2. The gate electrode of the second scan pull-down transistor SCD2 can be connected to the pull-down node QB, the first electrode of the second scan pull-down transistor SCD2 can be connected to the first gate off terminal VOF1, and the second electrode of the second scan pull-down transistor SCD2 can be connected to the second scan output terminal SCO2.

[0308] The second sensing pull-up transistor SSU2 is turned on by the gate conduction voltage of the pull-up node Q to output the fourth sensing clock signal input to the second sensing clock terminal SSI2 to the second sensing output terminal SSO2. The gate electrode of the second sensing pull-up transistor SSU2 can be connected to the pull-up node Q, the first electrode of the second sensing pull-up transistor SSU2 can be connected to the second sensing output terminal SSO2, and the second electrode of the second sensing pull-up transistor SSU2 can be connected to the second sensing clock terminal SSI2.

[0309] The second sensing pull-down transistor SSD2 is turned on by the gate on voltage of the pull-down node QB to output the first gate off voltage input to the first gate off terminal VOF1 to the second sensing output terminal SSO2. The gate electrode of the second sensing pull-down transistor SSD2 can be connected to the pull-down node QB, the first electrode of the second sensing pull-down transistor SSD2 can be connected to the first gate off terminal VOF1, and the second electrode of the second sensing pull-down transistor SSD2 can be connected to the second sensing output terminal SSO2.

[0310] A sixth capacitor C6 is positioned between the pull-up node Q and the second scan output terminal SCO2. One electrode of the sixth capacitor C6 can be connected to the pull-up node Q, and the other electrode can be connected to the second scan output terminal SCO2. Because the sixth capacitor C6 stores the voltage difference between the pull-up node Q and the second scan output terminal SCO2, the voltage difference between the two terminals can be maintained by the sixth capacitor C6.

[0311] A seventh capacitor C7 is positioned between the pull-up node Q and the second sensing output terminal SSO2. One electrode of the seventh capacitor C7 can be connected to the pull-up node Q, and the other electrode can be connected to the second sensing output terminal SSO2. Because the seventh capacitor C7 stores the voltage difference between the pull-up node Q and the second sensing output terminal SSO2, the voltage difference between the two terminals can be maintained by the seventh capacitor C7.

[0312] When the pull-down node QB has a gate on voltage, the third pull-up node controller 260 applies a second gate off voltage to the pull-up node Q. The third pull-up node controller 260 may include a tenth transistor T10. The tenth transistor T10 may include a (10-1) transistor T10-1 and a (10-2) transistor T10-2.

[0313] Transistor (10-1) T10-1 and transistor (10-2) T10-2 are turned on by the gate on-state voltage Von of the pull-down node QB to connect the pull-up node Q to the carry output terminal CO. The gate electrode of transistor (10-1) T10-1 can be connected to the pull-down node QB, the first electrode of transistor (10-1) T10-1 can be connected to the second electrode of transistor (10-2) T10-2, and the second electrode of transistor (10-1) T10-1 can be connected to the pull-up node Q. The gate electrode of transistor (10-2) T10-2 can be connected to the pull-down node QB, the first electrode of transistor (10-2) T10-2 can be connected to the carry output terminal CO, and the second electrode of transistor (10-2) T10-2 can be connected to the first electrode of transistor (10-1) T10-1.

[0314] Figure 35 This is a waveform diagram illustrating, according to an exemplary embodiment of the present invention, the carry clock signal, scan clock signal, sensing clock signal, sensing control signal, (k-2)th carry signal, kth carry signal, (k+2)th carry signal, voltage of pull-up node, voltage of pull-down node, (2k-1)th scan signal, 2kth scan signal, (2k-1)th sensing signal, and 2kth sensing signal during the effective time period. Figures 36 to 42 This is a circuit diagram illustrating the operation of the kth level during the first to seventh time periods of the effective time period, according to an exemplary embodiment of the present invention.

[0315] In the following text, reference will be made to Figures 35 to 42 Describe in detail the operations of level k during the first time period t1 to the seventh time period t7 of the effective time period.

[0316] First, such as Figure 35 and Figure 36As shown, during the first time period t1, the third scan clock signal CK3_SC of the first gate cutoff voltage Voff1 can be applied to the first scan clock terminal SCI1 of the k-th stage STk, and the third sensing clock signal CK3_SS of the first gate cutoff voltage Voff1 can be applied to the first sensing clock terminal SSI1.

[0317] The second scan pull-up transistor SCU2 is turned on by the gate on voltage Von of the pull-up node Q to output the fourth scan clock signal CK4_SC, which is input to the second scan clock terminal SCI2 with the first gate off voltage Voff1, to the second scan output terminal SCO2. In this way, the 2k scan signal SC2k with the first gate off voltage Voff1 can be applied to the 2k scan signal line SCL2k.

[0318] The second sensing pull-up transistor SSU2 is turned on by the gate on voltage Von of the pull-up node Q to output the fourth sensing clock signal CK4_SS, which is input to the second sensing clock terminal SSI2 with the first gate off voltage Voff1, to the second sensing output terminal SSO2. In this way, the 2k sensing signal SS2k with the first gate off voltage Voff1 can be applied to the 2k sensing signal line SSL2k.

[0319] according to Figure 36 In an exemplary embodiment, during the first time period t1, the operation of the sixth transistor T6, the eleventh transistor T11, the first scan pull-up transistor SCU1, the first sensing pull-up transistor SSU1, and the carry pull-up transistor CU can be the same as described above. Figure 10 The operations described in the first time period t1 are basically the same.

[0320] Secondly, such as Figure 35 and Figure 37 As shown, during the second time period t2, the fourth scan clock signal CK4_SC of the first gate cutoff voltage Voff1 can be applied to the second scan clock terminal SCI2 of the k-th stage STk, and the fourth sensing clock signal CK4_SS of the first gate cutoff voltage Voff1 can be applied to the second sensing clock terminal SSI2.

[0321] according to Figure 37 In an exemplary embodiment, during the second time period t2, the operation of the second scan pull-up transistor SCU2 and the second sensing pull-up transistor SSU2 can be the same as described above. Figure 35 The operations described are the same during the first time period t1.

[0322] according to Figure 37In an exemplary embodiment, during the second time period t2, the operation of the sixth transistor T6, the eleventh transistor T11, the first scan pull-up transistor SCU1, the first sensing pull-up transistor SSU1, and the carry pull-up transistor CU can be the same as described above. Figure 11 The operations described for the second time period t2 are basically the same.

[0323] Third, such as Figure 35 and Figure 38 As shown, during the third time period t3, the fourth scan clock signal Ck4_SC of the gate conduction voltage Von can be applied to the second scan clock terminal SCI2 of the k-th stage STk, and the fourth sensing clock signal CK4_SS of the gate conduction voltage Von can be applied to the second sensing clock terminal SSI2.

[0324] The second scan pull-up transistor SCU2 is turned on by the gate on-state voltage Von of the pull-up node Q to output the fourth scan clock signal CK4_SC, which is the gate on-state voltage Von input to the second scan clock terminal SCI2, to the second scan output terminal SCO2. In this way, the 2k scan signal SC2k of the gate on-state voltage Von can be applied to the 2k scan signal line SCL2k.

[0325] The second sensing pull-up transistor SSU2 is turned on by the gate on-state voltage Von of the pull-up node Q to output the fourth sensing clock signal CK4_SS, which is the gate on-state voltage Von input to the second sensing clock terminal SSI2, to the second sensing output terminal SSO2. In this way, the 2k sensing signal SS2k of the gate on-state voltage Von can be applied to the 2k sensing signal line SSL2k.

[0326] When the fourth scan clock signal CK4_SC of the gate conduction voltage Von is applied to the second scan output terminal SCO2 and the fourth sensing clock signal CK4_SS of the gate conduction voltage Von is applied to the second sensing output terminal SSO2, the pull-up node Q is bootstrapped by the sixth capacitor C6 and the seventh capacitor C7 to make the voltage ( Figure 35 VQ in the voltage ranges from a voltage Von' that has a higher level than the gate on-voltage Von to a voltage Von that has a higher level than Von'.

[0327] according to Figure 38 In an exemplary embodiment, during the third time period t3, the operation of the eleventh transistor T11, the first scan pull-up transistor SCU1, the first sensing pull-up transistor SSU1, and the carry pull-up transistor CU can be the same as described above. Figure 12 The operations described for the third time period t3 are basically the same.

[0328] Fourth, such as Figure 35 and Figure 39As shown, during the fourth time period t4, the fourth scan clock signal CK4_SC of the gate on-voltage Von can be applied to the second scan clock terminal SCI2 of the k-th stage STk, and the fourth sensing clock signal CK4_SS of the gate on-voltage Von can be applied to the second sensing clock terminal SSI2.

[0329] according to Figure 39 In an exemplary embodiment, during the fourth time period t4, the operation of the second scan pull-up transistor SCU2 and the second sensing pull-up transistor SSU2 can be the same as described above. Figure 38 The operations described are the same during the third time period t3.

[0330] according to Figure 39 In an exemplary embodiment, during the fourth time period t4, the operation of the eleventh transistor T11, the first scan pull-up transistor SCU1, the first sensing pull-up transistor SSU1, and the carry pull-up transistor CU can be the same as described above. Figure 13 The operations described for the fourth time period t4 are basically the same.

[0331] When the third scan clock signal CK3_SC of the first gate cutoff voltage Voff1 is applied to the first scan output terminal SCO1 and the third sensing clock signal CK3_SS of the first gate cutoff voltage Voff1 is applied to the first sensing output terminal SSO1 during the fourth time period t4, the pull-up node Q is bootstrapped by the first capacitor C1 and the second capacitor C2 to make the voltage ( Figure 35 The voltage VQ in the signal can be reduced to a voltage Von' that is higher than the gate on-state voltage Von. To stably output the fourth scan clock signal CK4_SC of the gate on-state voltage Von to the second scan output terminal SCO2 and the fourth sensing clock signal CK4_SS of the gate on-state voltage Von to the second sensing output terminal SCO2, the voltage of the pull-up node Q should not be reduced. To achieve this, the capacitance of the first capacitor C1 can be less than the capacitance of the sixth capacitor C6, and the capacitance of the second capacitor C2 can be less than the capacitance of the seventh capacitor C7.

[0332] Fifth, such as Figure 35 and Figure 40 As shown, during the fifth time period t5, the fourth scan clock signal CK4_SC of the first gate cutoff voltage Voff1 can be applied to the second scan clock terminal SCI2 of the k-th stage STk, and the fourth sensing clock signal CK4_SS of the first gate cutoff voltage Voff1 can be applied to the second sensing clock terminal SSI2.

[0333] Transistor (10-1) T10-1 and transistor (10-2) T10-2 are turned on by the gate conduction voltage Von of the pull-down node QB to connect the pull-up node Q to the carry output terminal CO.

[0334] The second scan pull-down transistor SCD2 is turned on by the gate on voltage Von of the pull-down node QB to output the first gate off voltage Voff1, which is input to the first gate off terminal VOF1, to the second scan output terminal SCO2. In this way, the 2k scan signal SC2k of the first gate off voltage Voff1 can be applied to the 2k scan signal line SCL2k.

[0335] The second sensing pull-down transistor SSD2 is turned on by the gate on voltage Von of the pull-down node QB to output the first gate off voltage Voff1, which is input to the first gate off terminal VOF1, to the second sensing output terminal SSO2. In this way, the 2k sensing signal SS2k of the first gate off voltage Voff1 can be applied to the 2k sensing signal line SSL2k.

[0336] During the fifth time period t5, the operations of the first transistor T1, the second transistor T2, the third transistor T3, the eighth transistor T8, the tenth transistor T10, the twelfth transistor T12, the thirteenth transistor T13, the first scan pull-down transistor SCD1, the first sensing pull-down transistor SSD1, and the carry pull-down transistor CD can be referenced above. Figure 14 The operations described during the fifth time period t5 are essentially the same.

[0337] Sixth, such as Figure 35 and Figure 41 As shown, during the sixth time period t6, the fourth scan clock signal CK4_SC of the first gate cutoff voltage Voff1 can be applied to the second scan clock terminal SCI2 of the k-th stage STk, and the fourth sensing clock signal CK4_SS of the first gate cutoff voltage Voff1 can be applied to the second sensing clock terminal SSI2.

[0338] according to Figure 41 In an exemplary embodiment, during the sixth time period t6, the operation of the second scan pull-down transistor SCD2 and the second sensing pull-down transistor SSD2 can be the same as described above. Figure 40 The operations described are the same during the fifth time period t5.

[0339] exist Figure 41In an exemplary embodiment, during the sixth time period t6, the operation of the first transistor T1, the second transistor T2, the third transistor T3, the eighth transistor T8, the tenth transistor T10, the twelfth transistor T12, the thirteenth transistor T13, the first scan pull-down transistor SCD1, the first sensing pull-down transistor SSD1, and the carry pull-down transistor CD can be the same as described above. Figure 15 The operations described during the sixth time period t6 are essentially the same.

[0340] Seventh, such as Figure 35 and Figure 42 As shown, during the seventh time period t7, the fourth scan clock signal CK4_SC of the gate conduction voltage Von can be applied to the second scan clock terminal SCI2 of the k-th stage STk, and the fourth sensing clock signal CK4_SS of the gate conduction voltage Von can be applied to the second sensing clock terminal SSI2.

[0341] according to Figure 42 In an exemplary embodiment, during the seventh time period t7, the operation of the second scan pull-down transistor SCD2 and the second sensing pull-down transistor SSD2 can be the same as described above. Figure 40 The operations described are the same during the fifth time period t5.

[0342] according to Figure 42 In an exemplary embodiment, during the seventh time period t7, the operation of the second transistor T2, the third transistor T3, the tenth transistor T10, the thirteenth transistor T13, the first scan pull-down transistor SCD1, the first sensing pull-down transistor SSD1, and the carry pull-down transistor CD can be the same as described above. Figure 16 The operations described during the seventh time period t7 are essentially the same.

[0343] Figure 43 This is a waveform diagram illustrating, according to an exemplary embodiment of the present invention, the carry clock signal, scan clock signal, sensing clock signal, sensing control signal, (k-2)th carry signal, kth carry signal, (k+2)th carry signal, voltage of pull-up node, voltage of pull-down node, 2k-1th scan signal, 2kth scan signal, 2k-1th sensing signal, and 2kth sensing signal during a vertical blank period. Figures 44 to 50 This is a circuit diagram illustrating the operation of the kth level during the 1' to 7' time periods of the vertical blank period, according to an exemplary embodiment of the present invention.

[0344] Reference Figures 43 to 50During the 1' time period t1' to the 6' time period t6', the fourth scan clock signal CK4_SC of the first gate cutoff voltage Voff1 can be applied to the second scan clock terminal SCI2 of the k-th stage STk, and the fourth sensing clock signal CK4_SS of the first gate cutoff voltage Voff1 can be applied to the second sensing clock terminal SSI2. Therefore, even if the second scan pull-up transistor SCU2 is turned on by a voltage higher than the gate on-state voltage Von of the pull-up node Q during the 2' time period t2' to the 5' time period t5', the second scan output terminal SCO2 also outputs the first gate cutoff voltage Voff1. Furthermore, even if the second sensing pull-up transistor SSU2 is turned on by a voltage higher than the gate on-state voltage Von of the pull-up node Q during the 2' time period t2' to the 5' time period t5', the second sensing output terminal SSO2 also outputs the first gate cutoff voltage Voff1.

[0345] Furthermore, during time periods 1' (t1'), 6' (t6'), and 7' (t7'), while the second scan pull-down transistor SCD2 and the second sensing pull-down transistor SSD2 are turned on, the second scan pull-up transistor SCU2 and the second sensing pull-up transistor SSU2 are turned off. Therefore, during time periods 1' (t1'), 6' (t6'), and 7' (t7'), the second scan output terminal SCO2 outputs the first gate cutoff voltage Voff1 of the first gate cutoff terminal VOF1, and the second sensing output terminal SSO2 also outputs the first gate cutoff voltage Voff1 of the first gate cutoff terminal VOF1.

[0346] exist Figures 44 to 50 In the exemplary embodiment shown, during the time period 1' to 7' t7', the operation of transistors other than the second scan pull-up transistor SCU2, the second sensing pull-up transistor SSU2, the second scan pull-down transistor SCD2, and the second sensing pull-down transistor SSD2 can be the same as described above. Figures 18 to 24 The operations described are basically the same.

[0347] Figure 51 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0348] Figure 51 The exemplary embodiments shown are in conjunction with Figure 34 The difference in the exemplary embodiment is that the sensing controller 230 further includes a fourth transistor T4 and a fifth transistor T5, the eighth transistor T8 of the second pull-up node controller 250 includes a (8-1) transistor T8-1 and a (8-2) transistor T8-2, and the inverter 270 includes a fourteenth transistor T14 instead of a thirteenth transistor T13.

[0349] Figure 51 The second transistor T2, the third transistor T3, and the fourth transistor T4 are essentially equivalent to those referenced above. Figure 29 The second transistor T2, the third transistor T3, and the fourth transistor T4 are described.

[0350] Figure 51 The fourteenth transistor T14 is essentially equivalent to the one referenced above. Figure 30 The fourteenth transistor T14 is described, and the thirteenth transistor T13 can be removed.

[0351] Reference Figure 51 Transistor (8-1) T8-1 and transistor (8-2) T8-2 are turned on by the carry signal of the gate on-state voltage of stage (k+2) ST(k+2) to connect pull-up node Q to carry output terminal CO, so that a first gate off voltage can be applied to pull-up node Q. The gate electrode of transistor (8-1) T8-1 can be connected to the next carry input terminal CNI, the first electrode of transistor (8-1) T8-1 can be connected to the second electrode of transistor (8-2) T8-2, and the second electrode of transistor (8-1) T8-1 can be connected to pull-up node Q. The gate electrode of transistor (8-2) T8-2 can be connected to the next carry input terminal CNI, the first electrode of transistor (8-2) T8-2 can be connected to carry output terminal CO, and the second electrode of transistor (8-2) T8-2 can be connected to the first electrode of transistor (8-1) T8-1.

[0352] Furthermore, the fourth transistor T4 is turned on by the gate on-state voltage Von of the pull-up node Q to apply the gate on-state voltage Von between the second transistor T2 and the third transistor T3, between the (8-1) transistor T8-1 and the (8-2) transistor T8-2, and between the (10-1) transistor T10-1 and the (10-2) transistor T10-2. With the help of the fourth transistor T4, leakage of the gate on-state voltage of the pull-up node Q through the second transistor T2 and the third transistor T3 can be prevented or reduced. Furthermore, with the help of the fourth transistor T4, leakage of the gate on-state voltage of the pull-up node Q through the (8-1) transistor T8-1 and the (8-2) transistor T8-2 can be prevented or reduced. Furthermore, with the help of the fourth transistor T4, leakage of the gate on-state voltage of the pull-up node Q through the (10-1) transistor T10-1 and the (10-2) transistor T10-2 can be prevented or reduced.

[0353] Figure 52 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0354] Figure 52 The exemplary embodiments shown are in conjunction with Figure 34 The difference in the exemplary embodiment is that the tenth transistor T10 of the third pull-up node controller 260 includes a (10-1) transistor T10-1, a (10-2) transistor T10-2, and a (10-3) transistor T10-3.

[0355] Reference Figure 52 When the third scan clock signal input to the first scan clock terminal SCI1 has a gate on voltage, the fourth scan clock signal input to the second scan clock terminal SCI2 has a gate on voltage, and the pull-down node QB has a gate on voltage, the third pull-up node controller 260 applies a second gate off voltage to the pull-up node Q. The third pull-up node controller 260 may include a tenth transistor T10. The tenth transistor T10 may include a (10-1) transistor T10-1, a (10-2) transistor T10-2, and a (10-3) transistor T10-3.

[0356] Transistor (10-1) T10-1 is turned on by the third scan clock signal of the gate conduction voltage to connect the pull-up node Q to the second electrode of transistor (10-2) T10-2. The gate electrode of transistor (10-1) T10-1 can be connected to the first scan clock terminal SCI1, the first electrode of transistor (10-1) T10-1 can be connected to the second electrode of transistor (10-2) T10-2, and the second electrode of transistor (10-1) T10-1 can be connected to the pull-up node Q.

[0357] Transistor (10-2) T10-2 can be turned on by the gate conduction voltage of the pull-down node QB to connect the carry output terminal CO to the first electrode of transistor (10-1) T10-1 and the first electrode of transistor (10-3) T10-3. The gate electrode of transistor (10-2) T10-2 can be connected to the pull-down node QB, the first electrode of transistor (10-2) T10-2 can be connected to the carry output terminal CO, and the second electrode of transistor (10-2) T10-2 can be connected to the first electrode of transistor (10-1) T10-1 and the first electrode of transistor (10-3) T10-3.

[0358] Transistor (10-3) T10-3 is turned on by the fourth scan clock signal of the gate turn-on voltage to connect the pull-up node Q to the second electrode of transistor (10-2) T10-2. The gate electrode of transistor (10-3) T10-3 can be connected to the second scan clock terminal SCI2, the first electrode of transistor (10-3) T10-3 can be connected to the second electrode of transistor (10-2) T10-2, and the second electrode of transistor (10-3) T10-3 can be connected to the pull-up node Q.

[0359] Figure 53 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0360] Figure 53 The exemplary embodiments shown are in conjunction with Figure 52 The difference in the exemplary embodiment is that the gate electrode of the (10-1) transistor T10-1 is connected to the first sensing clock terminal SSI1 to which the third sensing clock signal is applied, and the gate electrode of the (10-3) transistor T10-3 is connected to the second sensing clock terminal SSI2 to which the fourth sensing clock signal is applied.

[0361] Figure 54 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0362] Figure 54 The exemplary embodiments shown are in conjunction with Figure 34 The difference in the exemplary embodiment is that the k-th level STk further includes a fourth pull-up node controller 290.

[0363] Reference Figure 54 When the reset signal input to the reset terminal RI of the k-th stage STk has a gate-on voltage, the fourth pull-up node controller 290 applies a second gate-off voltage to the pull-up node Q. The fourth pull-up node controller 290 may include a twenty-second transistor T22. The reset signal may appear at the beginning of the active time period ACT, at the end of the active time period ACT, or during the vertical blank time period VB of the N-th frame period.

[0364] The 22nd transistor T22 is turned on by the gate-on voltage of the reset signal input to the reset terminal RI to connect the pull-up node Q to the carry-out terminal CO. In doing so, while the 22nd transistor T22 is turned on, a second gate-off voltage for the carry-out terminal CO can be applied to the pull-up node Q. The gate electrode of the 22nd transistor T22 can be connected to the reset terminal RI, the first electrode of the 22nd transistor T22 can be connected to the carry-out terminal CO, and the second electrode of the 22nd transistor T22 can be connected to the pull-up node Q.

[0365] Note that the first electrode of the twenty-second transistor T22 can be connected to the second gate cutoff terminal VOF2, where the second gate cutoff voltage Voff2 is applied, instead of the carry output terminal CO.

[0366] Figure 55 This is a circuit diagram illustrating the k-th stage of a scan signal driver according to an exemplary embodiment of the present invention.

[0367] Figure 55 The exemplary embodiments shown are in conjunction with Figure 34 The difference in the exemplary embodiment is that the first electrode of the (11-1) transistor T11-1 can be connected to the first gate cutoff terminal VOF1 where the first gate cutoff voltage Voff1 is applied instead of the second carry clock terminal CRI2.

[0368] An exemplary embodiment of the present invention provides a scan signal driver with a reduced area for ultra-high resolution display devices, such as display devices equipped with 8K ultra-high definition (UHD) resolution.

[0369] Exemplary embodiments of the present invention provide an ultra-high resolution display device (such as a display device equipped with 8K UHD resolution) in which the area of ​​the scan signal driver is reduced.

[0370] According to the foregoing and other exemplary embodiments of the present invention, a scan signal driver includes a single stage capable of simultaneously outputting a scan signal and a sensing signal, and therefore, the area of ​​the scan signal driver can be reduced compared to a scan signal driver that includes a stage for outputting a scan signal and another stage for outputting a sensing signal.

[0371] Furthermore, a single stage can output different scanning signals and different sensing signals during the effective period and the vertical blank period.

[0372] It should be understood that all transistors described herein can be implemented as MOSFETs. Furthermore, all transistors described herein can be formed from amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or oxide semiconductors.

[0373] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A scan signal driver, comprising: Multiple stages used for outputting scan and sensing signals. Among the plurality of stages, the kth stage is connected to the kth scan signal line and the kth sensing signal line. The k-th level includes: A first output unit is configured to, when the pull-up node has a gate on-voltage, output the scan clock signal input to the first scan clock terminal as the k-th scan signal to the k-th scan signal line, and output the sensing clock signal input to the first sensing clock terminal as the k-th sensing signal to the k-th sensing signal line; and The second output unit is configured to output the carry clock signal input to the first carry clock terminal as the k-th carry signal to the carry output terminal when the pull-up node has the gate on voltage. The k-th level further includes: A sensing controller is configured to apply the gate on-voltage to the pull-up node during the vertical blank period of the frame time when a sensing control signal having the gate on-voltage is input to the sensing control terminal during the valid period of the frame time. The sensing controller includes: a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor is configured to be turned on by the gate on-voltage of the sensing control signal to apply the gate on-voltage to the sensing control node. The second transistor and the third transistor are configured to apply a first control clock signal input to the first control clock terminal to the pull-up node, and The fourth transistor is configured to be turned on by the gate on-voltage of the pull-up node to apply the gate on-voltage of the pull-up node between the second transistor and the third transistor.

2. The scan signal driver according to claim 1, wherein, The first output unit includes: A first scan pull-up transistor, configured to be turned on by the gate on-state voltage of the pull-up node to output the scan clock signal to the k-th scan signal line; and A first sensing pull-up transistor is configured to be turned on by the gate conduction voltage of the pull-up node to output the sensing clock signal to the k-th sensing signal line.

3. The scan signal driver according to claim 1, wherein, The second output unit includes a carry pull-up transistor configured to be turned on by the gate conduction voltage of the pull-up node to output the carry clock signal to the carry output terminal.

4. The scan signal driver according to claim 1, wherein, When the pull-down node has the gate on voltage, the first output unit applies a first gate off voltage to the k-th scan signal line and the k-th sensing signal line, and When the pull-down node has the gate on voltage, the second output unit applies the first gate off voltage to the carry output terminal.

5. The scan signal driver according to claim 4, wherein, The first output unit includes: A first scan pull-down transistor, configured to be turned on by the gate on-state voltage of the pull-down node to output the first gate off-state voltage input to the first gate off-state terminal to the k-th scan signal line; and A first sensing pull-down transistor is configured to be turned on by the gate on voltage of the pull-down node to output the first gate off voltage of the first gate off terminal to the k-th sensing signal line.

6. The scan signal driver according to claim 4, wherein, The second output unit includes a carry pull-down transistor configured to be turned on by the gate on voltage of the pull-down node to output the first gate off voltage of the first gate off terminal to the carry output terminal.

7. The scan signal driver according to claim 1, wherein, The second transistor is configured to be turned on by the gate conduction voltage of the sensing control node to apply the first control clock signal input to the first control clock terminal to the pull-up node.

8. The scan signal driver according to claim 7, wherein, The third transistor is configured to be turned on by the gate conduction voltage of the sensing control node to connect the second transistor to the pull-up node.

9. The scan signal driver according to claim 1, wherein, The second transistor is configured to be turned on by the gate-on voltage of the second control clock signal input to the second control clock terminal to connect the third transistor to the first control clock terminal.

10. The scan signal driver according to claim 1, wherein, The third transistor is configured to be turned on by the gate-on voltage of the second control clock signal input to the second control clock terminal to connect the second transistor and the pull-up node.

11. The scan signal driver according to claim 1, wherein, The sensing controller includes: The (1-1)th transistor is configured to be turned on by the gate on-voltage of the sensing control signal to apply the gate on-voltage to the sensing control node; The first (1-2) transistors are configured to be turned on by the gate on-voltage of the sensing control signal to connect the third transistor to the sensing control node; and A fifth transistor is configured to be turned on by the gate turn-on voltage of the sensing control node to apply the gate turn-on voltage between the (1-1) transistor and the (1-2) transistor.

12. The scan signal driver according to claim 1, wherein, The k-th level includes: A first pull-up node controller, configured to apply a gate on-voltage to the pull-up node when there is a gate on-voltage relative to a carry signal from a previous stage relative to the k-th stage; and A second pull-up node controller is configured to apply a first gate cut-off voltage to the pull-up node when there is a gate on voltage relative to a carry signal of a subsequent stage relative to the k-th stage.

13. The scan signal driver according to claim 12, wherein, The first pull-up node controller includes a sixth transistor configured to be turned on by the gate on-voltage of the carry signal from the preceding stage to apply the gate on-voltage to the pull-up node.

14. The scan signal driver according to claim 12, wherein, The first pull-up node controller includes: The (6-1)th transistor is configured to be turned on by the gate on voltage of the carry signal of the preceding stage to apply the gate on voltage to the pull-up node; The (6-2)th transistor is configured to be turned on by the gate on-voltage of the carry signal from the preceding stage to connect the (6-1)th transistor to the pull-up node; and A seventh transistor is configured to be turned on by the gate on voltage of the k-th carry signal to apply the gate on voltage of the k-th carry signal between the (6-1) transistor and the (6-2) transistor.

15. The scan signal driver according to claim 12, wherein, The second pull-up node controller includes an eighth transistor configured to be turned on by the gate-on voltage of the carry signal of the subsequent stage to connect the pull-up node to the carry output terminal.

16. The scan signal driver according to claim 12, wherein, The second pull-up node controller includes: The (8-1)th transistor, configured to be turned on by the gate on voltage of the carry signal of the subsequent stage to connect the pull-up node to a second gate off terminal to which a second gate off voltage is applied; and The (8-2) transistor is configured to be turned on by the gate on voltage of the carry signal of the subsequent stage to connect the (8-1) transistor to the second gate off terminal.

17. The scan signal driver according to claim 16, wherein, The second pull-up node controller includes a ninth transistor configured to be turned on by the gate conduction voltage of the carry output terminal to connect the carry output terminal between the (8-1) transistor and the (8-2) transistor.

18. The scan signal driver according to claim 4, wherein, The k-th level includes: A third pull-up node controller is configured to hold the pull-up node at the first gate cutoff voltage when the scan clock signal or the sense clock signal has the gate on voltage and the pull-down node has the gate on voltage; and An inverter configured to apply a first gate cutoff voltage to the pull-down node when the pull-up node has the gate on voltage.

19. The scan signal driver according to claim 18, wherein, The third pull-up node controller includes: The (10-1)th transistor, configured to be turned on by the gate on-voltage of the scan clock signal or the gate on-voltage of the sense clock signal to connect the pull-up node to the carry output terminal; and The (10-2)th transistor is configured to be turned on by the gate on voltage of the pull-down node to connect the (10-1)th transistor to the carry output terminal.

20. The scan signal driver according to claim 18, wherein, The third pull-up node controller includes: The (10-1)th transistor, configured to be turned on by the gate on-voltage of the scan clock signal or the gate on-voltage of the sense clock signal to connect the pull-up node to the carry output terminal; and The (10-2)th transistor is configured to be turned on by the gate on voltage of the scan clock signal or the gate on voltage of the sense clock signal to connect the (10-1)th transistor to the carry output terminal.

21. The scan signal driver according to claim 18, wherein, The inverter includes: The (11-1)th transistor is configured to be turned on by the gate on voltage of the pull-up node to apply the first gate off voltage to the pull-down node; The (11-2)th transistor, wherein the (11-2)th transistor is configured to be turned on by the gate on-voltage of the pull-up node to connect the pull-down node to the thirteenth transistor; and The twelfth transistor is configured to be turned on by a gate-on voltage of another carry clock signal input to the second carry clock terminal to apply the gate-on voltage to the pull-down node.

22. The scan signal driver according to claim 18, wherein, The inverter includes a thirteenth transistor configured to be turned on by the gate-on voltage of the pull-down node to apply the gate-on voltage to the pull-down node.

23. The scan signal driver according to claim 18, wherein, The inverter includes a fourteenth transistor configured to be turned on by the gate on-voltage of the pull-down node to apply the gate on-voltage between the (11-1) transistor and the (11-2) transistor.

24. The scan signal driver according to claim 1, wherein, The k-th stage is connected to the (k+1)-th scan signal line and the (k+1)-th sensing signal line, and The first output unit is configured to output another scan clock signal input to the second scan clock terminal as the (k+1)th scan signal to the (k+1)th scan signal line when the pull-up node has the gate conduction voltage, and to output another sensing clock signal input to the second sensing clock terminal as the (k+1)th sensing signal to the (k+1)th sensing signal line.

25. The scan signal driver according to claim 24, wherein, The first output unit includes: A second scan pull-up transistor, configured to be turned on by the gate on-state voltage of the pull-up node to output the other scan clock signal to the (k+1)th scan signal line; and The second sensing pull-up transistor is configured to be turned on by the gate conduction voltage of the pull-up node to output the other sensing clock signal to the (k+1)th sensing signal line.

26. The scan signal driver according to claim 24, wherein, When the pull-down node has the gate on voltage, the first output unit applies the first gate off voltage to the (k+1)th scan signal line and the (k+1)th sensing signal line.

27. The scan signal driver according to claim 26, wherein, The first output unit includes: A second scan pull-down transistor, configured to be turned on by the gate on-state voltage of the pull-down node to output the first gate off-state voltage input to the first gate off-state terminal to the (k+1)th scan signal line; and The second sensing pull-down transistor is configured to be turned on by the gate on voltage of the pull-down node to output the first gate off voltage of the first gate off terminal to the (k+1)th sensing signal line.

28. The scan signal driver according to claim 26, wherein, The k-th level includes: A first pull-up node controller is configured to apply a gate on-voltage to the pull-up node when there is a gate on-voltage relative to a carry signal of a previous stage relative to the k-th stage. A second pull-up node controller, configured to apply the first gate cut-off voltage to the pull-up node when there is a gate on voltage relative to a carry signal of a subsequent stage relative to the k-th stage; and A third pull-up node controller is configured to hold the pull-up node at the first gate cut-off voltage when the pull-down node has the gate on voltage.

29. The scan signal driver according to claim 28, wherein, The third pull-up node controller includes: The (10-1)th transistor, wherein the (10-1)th transistor is configured to be turned on by the gate conduction voltage of the pull-down node to connect the pull-up node to the carry output terminal; and The (10-2)th transistor is configured to be turned on by the gate on voltage of the pull-down node to connect the (10-1)th transistor to the carry output terminal.

30. The scan signal driver according to claim 28, wherein, The third pull-up node controller includes: The (10-1)th transistor is configured to be turned on by the gate on voltage of the scan clock signal or the gate on voltage of the sense clock signal to connect the pull-up node to the carry output terminal; The (10-2)th transistor, configured to be turned on by the gate on-voltage of the pull-down node to connect the (10-1)th transistor to the carry-out terminal; and The (10-3) transistor is configured to be turned on by the gate on voltage of the other scan clock signal or the gate on voltage of the other sense clock signal to connect the pull-up node to the (10-2) transistor.

31. The scan signal driver according to claim 28, wherein, The third pull-up node controller includes: The (10-1)th transistor, the (10-1)th transistor being configured to be turned on by the gate on voltage of the pull-down node to connect the pull-up node to a first gate off terminal to which the first gate off voltage is applied; and The (10-2)th transistor is configured to be turned on by the gate on voltage of the pull-down node to connect the (10-1)th transistor to the first gate off terminal.

32. A scan signal driver, comprising: Multiple stages used for outputting scan and sensing signals. The first stage of the plurality of stages is connected to the first scan signal line and the first sensing signal line. The first level includes: A first output unit is configured to, when the pull-up node has a gate on-voltage, output the scan clock signal input to the first scan clock terminal as a first scan signal to the first scan signal line, and output the sense clock signal input to the first sense clock terminal as a first sense signal to the first sense signal line; and A sensing controller is configured to apply the gate on-voltage to the pull-up node during the vertical blank period of the frame time when a sensing control signal having the gate on-voltage is input to the sensing control terminal during the valid period of the frame time. The sensing controller includes: a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor is configured to be turned on by the gate on-voltage of the sensing control signal to apply the gate on-voltage to the sensing control node. The second transistor and the third transistor are configured to apply a first control clock signal input to the first control clock terminal to the pull-up node, and The fourth transistor is configured to be turned on by the gate on-voltage of the pull-up node to apply the gate on-voltage of the pull-up node between the second transistor and the third transistor.

33. A display device, comprising: The display panel includes data lines, scan signal lines, and sensing signal lines, as well as pixels connected to the data lines, scan signal lines, and sensing signal lines. A data driver for applying data voltage to the data line; as well as A scan signal driver, the scan signal driver including multiple stages for applying a scan signal to the scan signal line and a sensing signal to the sensing signal line. The first stage of the plurality of stages is connected to the first scan signal line and the first sensing signal line. The first level includes: The first output unit is configured to output the scan clock signal input to the first scan clock terminal as the first scan signal to the first scan signal line when the pull-up node has a gate conduction voltage, and to output the sensing clock signal input to the first sensing clock terminal as the first sensing signal to the first sensing signal line. The second output unit is configured to output the carry clock signal input to the first carry clock terminal as a first carry signal to the carry output terminal when the pull-up node has the gate on voltage; and A sensing controller is configured to apply the gate on-voltage to the pull-up node during the vertical blank period of the frame time when a sensing control signal having the gate on-voltage is input to the sensing control terminal during the valid period of the frame time. The sensing controller includes: a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor is configured to be turned on by the gate on-voltage of the sensing control signal to apply the gate on-voltage to the sensing control node. The second transistor and the third transistor are configured to apply a first control clock signal input to the first control clock terminal to the pull-up node, and The fourth transistor is configured to be turned on by the gate on-voltage of the pull-up node to apply the gate on-voltage of the pull-up node between the second transistor and the third transistor.

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