Circuit for generating and fine-tuning the phase of a memory cell read operation

Abstract

Embodiments of the present disclosure relate to circuits for generating and fine-tuning the phase of a memory cell read operation. A read signal generator generates a read signal to control a read operation of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period corresponding to a characteristic of the read signal. The oscillating signal is passed to a frequency divider, which divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal and the duration of the read signal characteristic can be calculated based on the frequency of the oscillating signal. The read signal characteristic can then be adjusted as needed.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits and, more particularly, to memory cell read operations. Background Art

[0002] Many integrated circuits include memory cells that store data. The data stored by the memory cells may include executable software instructions, images, video files, audio files, and documents.

[0003] Memory cells are typically arranged in an array of rows and columns. The memory cells in each row are connected together by corresponding word lines. The memory cells in each column are connected together by corresponding bit lines.

[0004] Sense amplifiers are typically coupled to bit lines. Sense amplifiers help read data from memory cells. In many cases, a complex set of signals is generated to control the timing of the read operation performed by the sense amplifiers.

[0005] Engineers and scientists are constantly seeking to improve the speed at which data can be read from memory cells. The number of read cycles that can be performed per second is based in part on the frequency of the read clock signal. The higher the frequency of the read clock signal, the greater the number of read operations that can be performed per second.

[0006] However, as the frequency of the read clock signal increases, the time window for performing individual read operations decreases. This can be problematic because, as mentioned above, in some cases, read operations are controlled by a complex set of signals based on the read clock signal. These signals have specific timings and relationships with each other. The time window for some of these signal characteristics may be much shorter than the period of a single clock cycle.

[0007] In some cases, during the manufacture of integrated circuits, the timing of various read signals can be affected by process variations. For example, the circuit components that generate some of the signals may have signal propagation delays that vary depending on conditions during manufacturing. Such signal propagation delays can cause the timing of various read signals, especially read signals with very short time windows, to be incorrect. If the timing of the various signals does not fall within the selected tolerances, the read operation may fail.

[0008] These problems are magnified by the fact that measuring the timing of signals can be difficult during batch testing and qualification of integrated circuits. Typically, testing is accomplished through external test circuitry connected to one or more output pads of the integrated circuit. However, these output pads have a relatively large area and, correspondingly, a large capacitance. This large capacitance can cause the time required to fully charge or discharge the output pad to be greater than the expected duration of the signal feature to be measured, making accurate measurements impossible. For example, when attempting to measure a signal feature with an expected length of less than 10ns, the output pad may not be able to fully charge or discharge in less than 50ns, making it impossible to accurately measure the timing of the signal feature. Summary of the Invention

[0009] One embodiment is an integrated circuit having an array of memory cells. The integrated circuit includes a read signal generator that generates various read signals for controlling read operations of the memory cells. The read signal generator includes a circuit device that selectively generates an oscillating signal having a period having a duration representing a specific characteristic of one of the read signals. The integrated circuit also includes a frequency divider that receives the oscillating signal from the read signal generator and outputs a divided oscillating signal based on a frequency division ratio, the frequency of the divided oscillating signal being reduced relative to the oscillating signal. The frequency divider transmits the divided oscillating signal to an output pad of the integrated circuit.

[0010] During the test sequence of various read signals, the test circuit interfaces with the output pad and measures the period of the divided oscillating signal. The period of the divided oscillating signal corresponds to the duration of the signal feature multiplied by the division ratio. The duration of the signal feature can be obtained by dividing the period of the divided oscillating signal by the division ratio.

[0011] Thus, the integrated circuit advantageously provides a means of measuring a duration of a read signal characteristic that is shorter than the charge and discharge times of an output pad of the integrated circuit.The oscillating signal and the corresponding divided oscillating signal may be selectively generated during testing.

[0012] Additionally, in one embodiment, the read signal generator includes circuitry that enables fine-tuning of the signal characteristics. For example, if during testing, the signal characteristics are measured to be too long or too short, the signal characteristics can be fine-tuned by adjusting one or more control parameters of the read signal generator.

[0013] Embodiments of the present disclosure overcome some of the shortcomings of conventional integrated circuits by enabling accurate measurement of read signal characteristics whose duration is less than the charge or discharge time of an output pad. Additionally, if the measurement indicates that the read signal characteristic is too long or too short, one or more embodiments of the present disclosure can fine-tune the read signal characteristic. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram of an integrated circuit test system according to one embodiment.

[0015] Figure 2 is a block diagram of an integrated circuit according to one embodiment.

[0016] Figure 3 Illustrated are a number of graphs representing various read signals used to control read operations of memory cells.

[0017] Figure 4 is a schematic diagram of an electronic circuit arrangement included in an integrated circuit according to one embodiment.

[0018] Figure 5 Illustrated are a number of graphs of various oscillation signals according to one embodiment.

[0019] Figure 6 is a block diagram of an integrated circuit according to one embodiment.

[0020] Figure 7 is a flow chart of an operating process for an integrated circuit according to one embodiment. DETAILED DESCRIPTION

[0021] Figure 1 FIG. 1 is a block diagram of an integrated circuit test system 100 according to one embodiment. The integrated circuit test system 100 includes an integrated circuit 102 and a test circuit 104 . The test circuit 104 tests or measures various aspects of the integrated circuit 102 .

[0022] In one embodiment, integrated circuit 102 includes memory array 106, read signal generator 108, frequency divider 110, and output pad 112. Read signal generator 108, frequency divider 110, and output pad 112 cooperate to enable test circuit 104 to accurately measure signal characteristics with very short durations. Based on this disclosure, one skilled in the art will recognize that integrated circuit 102 may include other components besides the memory array 106. Figure 1 Many other components than those shown in FIG.

[0023] The memory array 106 includes a plurality of memory cells. Each individual memory cell can store one or more bits of data. Data can be read from the memory cells.

[0024] The memory array 106 may include nonvolatile memory cells. Nonvolatile memory cells may include memory cells that can be written to multiple times or only once. Nonvolatile memory cells may include phase change memory cells, read-only memory (ROM) cells, flash memory cells, magnetoresistive random access memory cells (MRAM), or other types of nonvolatile memory cells.

[0025] The memory array 106 may include volatile memory cells that require continuous or intermittent refreshing in order to retain stored data. The volatile memory cells may include dynamic random access memory (DRAM), static random access memory (SRAM), or other types of volatile memory cells.

[0026] The memory cells of memory array 106 are organized into rows and columns. Each row of memory cells is connected to a corresponding word line. Each column of memory cells is connected to a corresponding bit line. The bit lines and word lines facilitate reading data from the memory cells and writing data to the memory cells.

[0027] Sense amplifiers 107 are connected to memory array 106. Specifically, each sense amplifier 107 can be selectively connected to a bit line of memory array 106. During a read operation, each sense amplifier precharges a bit line and then evaluates the data value from memory array 106 connected to that bit line.

[0028] The read signal generator 108 is coupled to the sense amplifier 107 and controls the operation of the sense amplifier 107. The read signal generator 108 generates a plurality of read signals and provides the read signals to the sense amplifier 107. The read signals control the sense amplifier 107 during a read operation.

[0029] The read signal generator 108 generates the read signals based on the read clock signal. The timing of the various read signals is based in part on the rising and falling edges of the read clock signal. Additionally, the frequency of the read clock signal determines the number of read cycles that can be executed per second. The read clock signal also partially controls the timing and characteristics of the read signals.

[0030] The read clock signal is generated by an oscillator. The oscillator may be part of the read signal generator 108. Alternatively, the oscillator may be external to the read signal generator 108. The oscillator may include a crystal oscillator, a voltage-controlled oscillator, a voltage-controlled crystal oscillator, or other oscillator suitable for generating a clock signal.

[0031] In one embodiment, read signal generator 108 can generate read signals that include a precharge signal and an evaluation signal. The various forms and timings of the signals are based on a read clock signal and signal generation circuitry. The timing of these signals controls the read operation of memory array 106. A sense amplifier can generate a stop signal and provide the stop signal to the read signal generator.

[0032] In one embodiment, read signal generator 108 communicates a precharge signal and an evaluation signal to sense amplifiers 107. During a read operation, the precharge signal causes each sense amplifier to precharge a corresponding bit line. After sense amplifiers 107 have precharged the bit line, the evaluation signal causes each sense amplifier 107 to evaluate the value of the data stored in the memory cell coupled to the corresponding bit line. The sense amplifiers can generate a stop signal based in part on the evaluation signal and the precharge signal and provide the stop signal to the read signal generator. Read signal generator 108 can generate the evaluation signal and the precharge signal based in part on the stop signal.

[0033] In one embodiment, the precharge operation and the evaluation operation occur within a single cycle of the read clock signal. The timing of the precharge signal and the evaluation signal can be very precise. For example, if the period of a single clock cycle is on the order of 25 ns, the precharge signal is timed to go low within approximately 8 ns after the rising edge of the read clock signal. The evaluation signal is timed to go high within approximately 2.5 ns after the precharge signal goes low.

[0034] Compared to the period of the clock signal, these timings of 8ns and 2.5ns represent a short time window. If the timing of the read signal and the evaluation signal do not match within the selected tolerance, the read operation may not be completed correctly.

[0035] To ensure that the timing of the various read signals matches within tolerance, test circuit 104 measures the timing of the read signals. Test circuit 104 is connected to I / O pads 112 of integrated circuit 102. Test circuit 104 measures the timing of the read signals via I / O pads 112. Test circuit 104 does not directly measure the timing of the read signals. This is because the relatively large surface area of ​​I / O pads 112 results in a capacitance that is too large to charge or discharge within the short timeframes of the various characteristics and timing of the read signals.

[0036] In order to overcome the technical obstacles brought about by the short timing window of the read signal and the large capacitance of the I / O pad 112, the read signal generator 108 and the frequency divider 110 cooperate to output an adjusted signal of a duration that can be measured at the I / O pad 112 and from which the characteristics of the read signal can be derived. Specifically, during the test, the read signal generator 108 generates an oscillation signal based on the characteristics of the read signal. The oscillation signal is passed to the frequency divider 110, and the frequency divider 110 generates a divided oscillation signal by dividing the frequency of the oscillation signal. The divided oscillation signal is then output to the I / O pad 112. The test circuit 104 measures the frequency of the divided oscillation signal and calculates the frequency of the oscillation signal based on the division ratio of the frequency divider 110 and the measured frequency of the divided oscillation signal.

[0037] During testing, the read signal generator 108 can be selectively controlled to generate an oscillating signal having a period corresponding to a specific characteristic of the read signal. The read signal generator 108 includes an oscillator loop that can be selectively enabled for testing purposes. When the oscillator loop is selectively enabled during testing, the oscillator loop outputs an oscillating signal having a period corresponding to a duration of the specific characteristic of one of the read signals.

[0038] In one embodiment, the read signal generator 108 includes an oscillator loop that can be selectively enabled to measure the delay between the rising edge of the read clock signal and the falling edge of the pre-charge signal. When the oscillator loop is enabled, the oscillator loop generates an oscillation signal having a period corresponding to the delay between the rising edge of the read clock signal and the falling edge of the pre-charge signal. For example, if the pre-charge delay is approximately 8 ns, the corresponding oscillation signal has a period of approximately 8 ns.

[0039] In one embodiment, the read signal generator 108 includes an oscillator loop that can be selectively enabled to measure the delay between the falling edge of the pre-charge signal and the rising edge of the evaluation signal. When the oscillator loop is enabled, the oscillator loop generates an oscillation signal having a period corresponding to the delay between the falling edge of the pre-charge signal and the rising edge of the evaluation signal. For example, if the evaluation delay is approximately 2.5 ns, the period of the oscillation signal is approximately 2.5 ns.

[0040] In one embodiment, read signal generator 108 includes an oscillator loop that can be selectively enabled to measure the total delay between the rising edge of the read clock signal and the rising edge of the evaluation signal. This delay corresponds to the sum of the precharge delay and the evaluation delay. When the oscillator loop is enabled, it generates an oscillation signal having a period corresponding to the delay between the rising edge of the read clock signal and the rising edge of the evaluation signal. If the precharge delay is approximately 8 ns and the evaluation delay is approximately 2.5 ns, the oscillation signal has a period of approximately 10.5 ns.

[0041] In one embodiment, frequency divider 110 receives the oscillating signal from read signal generator 108. Frequency divider 110 has a frequency division ratio selected to ensure that the resulting adjusted oscillating signal has a period long enough to be measured at I / O pad 112. The frequency division ratio is selected to ensure that the oscillation period is longer than the charging and discharging times of I / O pad 112.

[0042] In one embodiment, the frequency divider 110 has a frequency division ratio of 16. This means that when the oscillation signal is provided to the frequency divider 110, the frequency divider 110 will output a divided oscillation signal having a frequency of 1 / 16 of the frequency of the oscillation signal. Thus, the period of the adjusted oscillation signal is 16 times longer than the period of the oscillation signal.

[0043] Test circuit 104 measures the divided oscillating signal at I / O pad 112. In one example, test circuit 104 measures the frequency of the divided oscillating signal and then calculates the frequency of the corresponding oscillating signal by multiplying the frequency of the adjusted oscillating signal by the division ratio of divider 110. Then, by calculating the period of the oscillating signal, test circuit 104 can calculate the duration or length of the corresponding feature of the read signal. In another example, test circuit 104 measures the period of the divided oscillating signal and calculates the period of the oscillating signal based on the division ratio of divider 110. The period of the oscillating signal corresponds to the duration of the signal feature.

[0044] In one embodiment, the test circuit 104 first measures or calculates the precharge delay by enabling the precharge oscillator loop. Then, the test circuit 104 measures the evaluation delay by enabling the oscillator loop including both the precharge delay and the evaluation delay. In this case, the evaluation delay is calculated by subtracting the precharge delay from the sum of the precharge delay and the oscillation delay.

[0045] In one embodiment, test circuit 104 can fine-tune or adjust various aspects of the read signal based on measurements of characteristics of the read signal. Read signal generator 108 includes circuitry that enables the characteristics of the read signal to be lengthened or shortened. If test circuit 108 determines that the measured characteristics of the read signal do not match within a selected tolerance, test circuit 108 can cause read signal generator 108 to lengthen or shorten the characteristics of the read signal. Read signal generator 108 can then adjust the characteristics of the read signal in response to control signals from test circuit 104.

[0046] In one embodiment, the read signal generator 108 can utilize capacitors to introduce timing delays, such as pre-charge delays and evaluation delays. The delays can be based, at least in part, on the time it takes to charge or discharge these capacitors. The capacitors can be charged or discharged using a voltage-controlled current source. The charge and discharge times of the capacitors can be adjusted by applying a control signal to the voltage-controlled current source. Adjusting the charge and discharge times of the capacitors adjusts the delay in the read signal.

[0047] Figure 2 1 is a block diagram of an integrated circuit 102 according to one embodiment. The integrated circuit 102 includes a read signal generator 108, a frequency divider 110, and an output pad 112. Figure 2 Other components of integrated circuit 102 are not shown, including memory array 106 and sense amplifier 107 .

[0048] In one embodiment, read signal generator 108 includes a precharge signal generator 116 and an evaluation signal generator 118. During normal operation of integrated circuit 102, precharge signal generator 116 generates a precharge signal that includes a precharge delay for timing the precharging of the bit line. During normal operation of integrated circuit 102, evaluation signal generator 118 generates an evaluation signal that is used to evaluate the data value stored in the memory cell during a read operation. The evaluation signal includes an evaluation delay for timing the evaluation of the data value stored in the memory cell during a read operation.

[0049] The read signal generator includes switches S1, S2, and S3 for enabling selective testing of the precharge delay, the evaluation delay, and the sum of the precharge delay and the evaluation delay. The read signal generator 108 also includes a precharge delay oscillator loop 120 and an evaluation delay oscillator loop 122. The precharge delay oscillator loop 120 and the evaluation delay oscillator loop 122 are used to test and adjust the precharge delay and the evaluation delay. During normal operation of the integrated circuit 102, the precharge delay oscillator loop 120 and the evaluation delay oscillator loop 122 are not utilized.

[0050] The precharge delay oscillator loop 120 is enabled by enabling switches S1 and S2 and disabling switch S3. The precharge oscillator loop 120 bypasses the evaluation signal generator by enabling switch S2. During the test read signal, the test circuit 104 is connected to the I / O pad 112. The test circuit input enables (closes) switches S1 and S2 and disables (opens) the command of switch S3. The oscillator loop 120 generates an oscillation signal having a period corresponding to the precharge delay. The precharge delay oscillation signal is passed to the frequency divider 110. As previously described, the precharge delay oscillation signal is divided according to the frequency division factor, and the frequency divider 110 generates a divided oscillation signal. The divided oscillation signal is passed to the I / O pad 112. The test circuit 104 analyzes the divided oscillation signal to determine the value of the precharge delay.

[0051] By enabling switch S2 and disabling switches S1 and S3, the evaluation delay oscillator loop 122 can be enabled. During the test read signal period, the test circuit is connected to the I / O pad 112. The test circuit inputs a command to enable switch S2 and disable switches S1 and S3. The evaluation delay oscillation signal is passed to the frequency divider 110. As previously described, the frequency divider 110 generates a divided oscillation signal by dividing the oscillation signal according to the frequency division factor. The divided oscillation signal is passed to the I / O pad 112, and the test circuit analyzes the divided oscillation signal to determine the value of the evaluation delay.

[0052] In one embodiment, the evaluation delay oscillator loop 122 may include both an evaluation delay and a pre-charge delay. In this case, switch S3 is enabled and switches S1 and S2 are disabled, and the evaluation delay oscillator loop 122 generates an oscillation signal having a period corresponding to the sum of the pre-charge delay and the evaluation delay. The evaluation delay oscillation signal is passed to the frequency divider 110. As previously described, the frequency divider 110 generates a divided oscillation signal by dividing the oscillation signal according to the frequency division factor. The divided oscillation signal is passed to the I / O pad 112, and the test circuit analyzes the divided oscillation signal to determine the value of the evaluation delay. The test circuit 104 can determine the evaluation delay by subtracting the pre-charge delay from the sum of the evaluation delay and the pre-charge delay. Alternatively, the pre-charge delay can be calculated by measuring the evaluation delay, the sum of the evaluation delay and the pre-charge delay, and subtracting the evaluation delay from the sum of the evaluation delay and the pre-charge delay.

[0053] In one embodiment, the pre-charge oscillator loop 120 and the evaluation oscillator loop 122 may not be enabled at the same time. The integrated circuit 102 may include control circuitry that prevents the pre-charge oscillator loop 120 and the evaluation oscillator loop 122 from being enabled at the same time. The control circuitry may also prevent the pre-charge oscillator loop 120 and the evaluation oscillator loop 122 from being enabled during standard operation of the integrated circuit 102.

[0054] In one embodiment, read signal generator 108 may include a fourth switch that is coupled immediately before or after evaluation signal generator 118. The fourth switch may be disabled as long as the evaluation delay is not intended to be used as part of the oscillator signal provided to frequency divider 110. A fifth switch may also be provided so that there is a switch immediately before and after evaluation signal generator 118.

[0055] Although Figure 2 While switches S1-S3 are shown for enabling pre-charging of the evaluation oscillator loop, other types of circuitry may be used to selectively enable and disable the pre-charging oscillator loop and the evaluation oscillator loop. For example, the pre-charging oscillator loop 120 and the evaluation oscillator loop 122 may include various arrangements of logic gates and control signal paths for enabling and disabling the pre-charging oscillator loop 120 and the evaluation oscillator loop 122.

[0056] Figure 3 A plurality of graphs representing various read signals for controlling a read operation of a memory cell are illustrated. Specifically, Figure 3 Illustrated are a graph 130 for the read clock signal, a graph 132 for the stop read signal, a graph 134 for the precharge signal, and a graph 136 for the evaluation signal. The signals cooperate to collectively control the timing of the read operation.

[0057] The read clock signal determines the frequency of the read operation. All other read signals are based at least in part on the read clock signal. The read clock signal can be generated by an oscillator. The oscillator can be part of the read signal generator 108. Alternatively, the oscillator that generates the read clock signal can be external to the read signal generator 108.

[0058] exist Figure 3 In the example shown, the read clock signal has a frequency of 40 MHz and a corresponding period of 25 ns. The read clock signal switches between a low logic level and a high logic level in a square wave. Although the transitions between logic states are shown as straight lines, in reality there is a finite slope between the transitions between a high logic state and a low logic state. Based on this disclosure, those skilled in the art will recognize that the read clock signal may have other characteristics besides the following without departing from the scope of this disclosure: Figure 3frequencies other than those shown.

[0059] In one embodiment, the read signal includes a stop read signal, shown in graph 132. Once read data is available on the data output bus, the sense amplifier generates the stop read signal. The stop read signal marks the end of the evaluation cycle during which data stored in selected memory cells is evaluated by sense amplifier 107. Sense amplifier 107 generates the stop read signal and disconnects from the bit line when the memory read operation is complete. The read signal generator 108 receives the stop read signal. In response to the stop read signal, the precharge signal goes high, allowing the next memory read operation to begin.

[0060] In one embodiment, the precharge signal causes the sense amplifier 107 to precharge the bit line. Precharging the bit line prepares the bit line for a read operation. When the precharge signal is at a high logic level, the sense amplifier 107 precharges the bit line.

[0061] In one embodiment, the evaluation signal causes sense amplifier 107 to read the data value from the selected memory cell via the bit line. The evaluation cycle of the read operation occurs when the evaluation signal is at a high logic level. The evaluation cycle of the read operation occurs after the bit line has been precharged. The evaluation cycle rising edge begins after the precharge delay after the precharge signal goes low. The falling edge of the precharge signal triggers the evaluation signal generator, which generates the rising edge of the evaluation signal only after a finite evaluation delay. The read signal generator 108 generates the evaluation signal.

[0062] The characteristics of the pre-charge signal are based in part on the read clock signal and the stop signal. The rising edge of the stop signal (i.e., when the stop signal transitions from a low logic value to a high logic value) causes the pre-charge signal to transition from a low logic value to a high logic value. The rising edge of the read clock signal causes the pre-charge signal to transition from a high logic level to a low logic level after a finite delay. Thus, in response to the transitions of the stop read signal and the read clock signal, the pre-charge signal transitions between logic states. Furthermore, when the stop read signal is not yet present, the rising edge of the read clock signal causes the pre-charge signal to go high for the first read operation.

[0063] The pre-charge signal includes a pre-charge delay. Read signal generator 108 includes circuitry that introduces a delay between the rising edge of the read clock signal and the falling edge of the pre-charge signal. Therefore, the pre-charge signal does not immediately transition from high to low on the rising edge of the read clock signal. Instead, the pre-charge signal transitions from high to low after the pre-charge delay.

[0064] The precharge delay is a timing characteristic of the precharge signal. A read operation may depend in part on whether the precharge delay falls within a selected tolerance. Figure 3 In the example of FIG, the precharge delay has a value of approximately 8 ns. In one embodiment, the selected tolerance range is 8 ns ± 0.5 ns.

[0065] The characteristics of the evaluation signal are based in part on the read clock signal and the precharge signal. A falling edge of the precharge signal causes the evaluation signal to transition from a low logic value to a high logic value. A rising edge of the stop read signal causes the evaluation signal to transition from a high logic value to a low logic value. Thus, the evaluation signal transitions between logic levels in response to transitions in the precharge signal and the stop read signal.

[0066] The evaluation signal includes an evaluation delay. Read signal generator 108 includes circuitry that introduces a delay between the falling edge of the precharge signal and the rising edge of the evaluation signal. Therefore, the evaluation signal does not immediately transition from low to high on the falling edge of the precharge signal. Instead, the evaluation signal transitions from low to high after the evaluation delay.

[0067] The evaluation delay is a timing characteristic of the evaluation signal. One purpose of the evaluation delay is to ensure that there are no transient voltages on the bit line after the precharge signal goes from high to low. Furthermore, it is desirable to have a stable current in the sense amplifier branch. Therefore, after the precharge phase, a delay is added to generate the evaluation phase. Otherwise, if the current margin between the two sense amplifier branches is small, data may be read incorrectly. Therefore, the value of the evaluation delay is selected to ensure, in part, that transient effects are adequately eliminated from the bit line. The read operation may depend in part on the evaluation delay having a value that falls within a selected tolerance. Figure 3 In the example of , the estimated delay has a value of approximately 2.5 ns. In one embodiment, the tolerance range selected for the estimated delay is 2.5 ns ± 0.5 ns.

[0068] exist Figure 3 The read signals shown in FIG are provided by way of example. Many other signal configurations and timing schemes can be utilized to read data from a memory cell. Based on this disclosure, it will be understood by those skilled in the art that the principles disclosed herein for measuring and fine-tuning very short signal characteristics can be used to measure and fine-tune characteristics of timing signals in other signal configurations and timing schemes without departing from the scope of this disclosure.

[0069] Figure 41 is a schematic diagram of an electronic circuit arrangement included in an integrated circuit 102 according to one embodiment. According to one embodiment, the electronic circuit arrangement includes a frequency divider 110, a precharge signal generator 116, and an evaluation signal generator 118. The precharge signal generator 116 and the evaluation signal generator 118 are components of the read signal generator 108 (in Figure 4 The unmarked part.

[0070] In one embodiment, precharge signal generator 116 generates a precharge signal PS and its logical complement PSN. Evaluation signal generator 118 generates an evaluation signal ES and its logical complement ESN. During a read operation of memory array 106, the precharge signal, the evaluation signal, and its logical complement are provided to sense amplifier 107.

[0071] In one embodiment, during testing, pre-charge signal generator 116 and evaluation signal generator 118 can be controlled to selectively output oscillation signals to frequency divider 110. Pre-charge signal generator 116 generates oscillation signal OS1. Evaluation signal generator 118 generates oscillation signal OS2. Oscillation signal OS1 has a frequency corresponding to the pre-charge delay. Oscillation signal OS2 has a frequency corresponding to the sum of the pre-charge delay and the evaluation delay.

[0072] The functionality of pre-charge signal generator 116 and evaluation signal generator 118 is primarily based on two oscillator control signals, OC1 and OC2. When OC1 and OC2 are both 0 or a low logic value, pre-charge signal generator 116 and evaluation signal generator 118 are in standard operating mode, in which they generate pre-charge signal PS and evaluation signal ES for read operations. When the first oscillator control signal is 1 and the second oscillator control signal is 0, oscillation signal OS1 is generated for testing purposes. When both the first oscillator control signal OC1 and the second oscillator control signal OC2 are 1, oscillation signal OS2 is generated for testing purposes.

[0073] The precharge signal generator 116 includes a first flip-flop F1, five inverters I1-I5, a buffer B1, an AND gate A1, NAND gates NA1 and NA2, an OR gate O1, NOR gates NO1 and NO2, a multiplexer MUX1, a PMOS transistor T1, NMOS transistors T2 and T3, and a delay capacitor C1. These components work together to provide the precharge signal PS and its logical complement PSN during a read operation of the memory array 106, and to selectively output the oscillation signal OS1 during testing. In light of this disclosure, those skilled in the art will recognize that the precharge signal generator 116 may include additional components or a different component configuration without departing from the scope of this disclosure.

[0074] Flip-flop F1 receives ground GND and a read clock signal RC. Flip-flop F1 also receives a precharge signal PS at its "set" input. The output of flip-flop F1 is provided to an input terminal of a NAND gate NA2. A second input of NAND gate NA2 receives the output of NAND gate NA1. NAND gate NA2 outputs signal INT1 to multiplexer MUX1.

[0075] Multiplexer MUX1 receives signal OS2 from evaluation signal generator 118 as a second input. Multiplexer MUX1 also receives second oscillator control signal OC2 from the output of AND gate A1 as a control input. Multiplexer MUX1 outputs either INT1 or OS2 as IN1, depending on the value of second oscillator control signal OC2. The purpose of second oscillator control signal OC2 is described in more detail below.

[0076] IN1 is provided to the control gates of PMOS transistor T1 and NMOS transistor T2. If IN1 is high, T1 is disabled, T2 is enabled, and the top terminal of the delay capacitor is coupled to GND. If IN1 is low, T2 is disabled, T1 is enabled, and the top terminal of the delay capacitor C1 is coupled to VDD.

[0077] The signal from the top terminal of delay capacitor C1 is passed through inverters I1-I3, NOR gate NO1 and buffer B1. The output of buffer B1 is at Figure 3 The input of buffer B1 is provided to the input of inverter I4. Inverter I4 outputs the logical complement PSN of pre-charge signal PS.

[0078] The input of buffer B1 is coupled to a first input of NOR gate NO2. The second input of NOR gate NO2 is coupled to the output of OR gate O1. The output of NOR gate NO2 is provided to a second input of NOR gate NO1.

[0079] OR gate O1 receives IN1 on a first input. OR gate O1 receives stop read signal SR on a second input. When stop read signal SR goes high, precharge signal is forced high via NOR gates NO1 and NO2.

[0080] The pre-charge signal generator 116 includes a delay circuit 140. The delay circuit 140 includes a delay capacitor C1 and inverters I1-I3. The delay capacitor C1 is primarily responsible for the pre-charge delay. In the example where the pre-charge delay is intended to be approximately eight seconds, the delay capacitor C1 provides a delay of approximately 6.5 ns. The delay provided by capacitor C1 can be selectively modified. Inverters I1-I3 provide a delay of approximately 1.5 ns. The total pre-charge delay is approximately 8 ns. In practice, the total pre-charge delay is slightly greater than the sum of the delays introduced by the delay capacitor C1 and the inverters I1-I3. This is because the other circuit components involved in generating the pre-charge signal introduce a very small amount of delay.

[0081] As previously described, due to process variations in manufacturing integrated circuits, the delay introduced by delay circuitry 140 may be slightly greater or less than expected. If the total delay falls outside a selected tolerance range, the precharge delay may need to be adjusted. Advantageously, precharge signal generator 116 allows for fine-tuning of the precharge delay during testing.

[0082] Delay capacitor C1 provides an adjustable signal delay. The signal delay provided by delay capacitor C1 is based on the capacitance of delay capacitor C1 and the current used to discharge capacitor C1. The value of this discharge current is determined by transistors T2 and T3. The value of the current flowing in the transistors is controlled by a first reference voltage VREF1 applied to the gate of transistor T3. A higher value of VREF1 increases the current flowing through transistors T2 and T3, thereby reducing the time required to discharge delay capacitor C1. A lower value of VREF1 reduces the current flowing through transistors T2 and T3, thereby increasing the time required to discharge delay capacitor C1.

[0083] Thus, if the test indicates that the pre-charge delay is too short or too long, the pre-charge delay can be adjusted by adjusting the value of the reference voltage VREF1. To increase the pre-charge delay, the value of VREF1 can be decreased. To decrease the pre-charge delay, the value of VREF1 can be increased. The test circuit 104 can provide a control signal to adjust the value of VREF1.

[0084] When the value of IN1 transitions from high to low, NMOS transistor T2 is disabled and PMOS transistor T1 is enabled. The top terminal of delay capacitor C1 is quickly charged to the power supply voltage VDD. When the value of IN1 transitions from low to high, PMOS transistor T1 is disabled and NMOS transistor T2 is enabled. The top terminal of delay capacitor C1 discharges to ground through NMOS transistors T2 and T3. Discharging C1 is much slower than charging C1 because reference voltage VREF1 forces a discharge current that is less than the charging current.

[0085] The evaluation signal generator 118 includes NAND gates NA3-NA5, inverters I6-10, a buffer B2, a multiplexer MUX2, a PMOS transistor T4, NMOS transistors N5 and N6, and a delay capacitor C2. When OC2 is set to 0, the evaluation signal generator 118 generates the evaluation signal ES and its logical complement ESN, as shown in FIG. Figure 3 As shown in .

[0086] NAND gate NA3 receives oscillator control signal OC2 at a first input and the output of inverter I10 at a second input. The output of NA3 is provided to a second input of NAND gate NA4. NA4 receives precharge signal PS at its first input. Precharge signal PS and oscillator control signal OC2 primarily control the function of evaluation signal generator 118.

[0087] A first input of MUX2 receives the output of NAND gate NA4. A second input of multiplexer MUX2 receives signal INT1 from pre-charge signal generator 116. Multiplexer MUX2 receives oscillator control signal OC2 at its control input. Multiplexer MUX2 outputs signal IN2 to the gates of transistors T4 and T5. Transistors T4-T6 and delay capacitor C2 operate in much the same manner as transistors T1-T3 and delay capacitor C1 described with respect to pre-charge signal generator 116, except that delay capacitor C2 provides a smaller delay than delay capacitor C1. Additionally, transistor T7 receives a second reference voltage VREF2 at its gate.

[0088] The outputs of the drain terminals of transistors T4 and T5 are passed to the first input of NAND gate NA5 through inverters I6-I8. The second input of NAND gate NA5 receives signal IN2. The output of NAND gate NA5 is provided to buffer B2 and inverter I9. Buffer B2 output is as shown in FIG. Figure 3 The evaluation signal ES is shown in FIG. The inverter I9 outputs a logical complement ESN of the evaluation signal ES.

[0089] Evaluation signal generator 118 includes delay circuitry 142. Delay circuitry 142 includes a delay capacitor C2 and inverters I6-I8. In an example where the evaluation delay is intended to be approximately 2.5 ns, second delay capacitor C2 provides a delay of approximately 2 ns. The delay provided by delay capacitor C2 can be selectively modified. Inverters I6-I8 provide a delay of approximately 0.5 ns. As described above, the evaluation delay can be adjusted by adjusting the value of reference voltage VREF2, just as the pre-charge delay can be adjusted by adjusting VREF1.

[0090] During the evaluation delay test, oscillator control signals OC1 and OC2 are set to 1. This enables oscillator loop 122. In this state, the evaluation signal generator generates an oscillation signal OS2. Oscillation signal OS2 has a period approximately equal to the sum of the pre-charge delay and the evaluation delay. When oscillator loop 122 is enabled, oscillation signal OS2 is passed through inverter I10 and NAND gate NA3. Because multiplexer MUX2 receives INT1 from pre-charge signal generator INT1, oscillator loop 122 includes oscillator loop 120 before returning to the output of inverter I8. As a result, oscillation signal OS2 includes the pre-charge delay and the evaluation delay. Therefore, the period of oscillation signal OS2 is approximately equal to the sum of the pre-charge delay and the evaluation delay.

[0091] Although Figure 4 While an embodiment is shown in which the evaluation delay is tested by incorporating the pre-charge delay into the oscillator loop, in other embodiments the evaluation delay may be tested separately. The oscillator loop 122 may be configured such that the pre-charge delay loop is not included in the oscillator loop 122. In this case, the oscillation signal OS2 may have a period approximately equal to the evaluation delay. However, because the evaluation delay is relatively short, it may be advantageous to indirectly measure the evaluation delay by subtracting the measured pre-charge delay from the sum of the measured pre-charge delay and the evaluation delay.

[0092] The frequency divider 110 includes flip-flops F2-F5, inverters I11-I14, and a multiplexer M3. The flip-flops F2-F5 and the inverters I11-I14 are coupled together in a frequency divider configuration. The multiplexer MUX3 receives the oscillation signals OS1 and OS2. The output of the multiplexer MUX3 is provided to the input of the flip-flop F2. When the oscillation signal OS1 or OS2 is provided from the output of the multiplexer MUX3 to the input of the flip-flop F2, the flip-flop F5 outputs a divided oscillation signal DOS. The divided oscillation signal DOS has a frequency corresponding to the frequency of the oscillation signal divided by the division ratio N. Figure 4In the example shown, the frequency divider has a division ratio of 16. In other embodiments, the frequency divider 110 may have a division ratio other than 16.

[0093] Figure 5 A plurality of graphs are illustrated, including a graph 150 of a first oscillating signal, a graph 152 of a first frequency-divided oscillating signal, a graph 154 of a second oscillating signal, and a graph 156 of a second frequency-divided oscillating signal.

[0094] refer to Figure 4 and Figure 5 During the test pre-charge delay period, OC1 is set to 1, OC2 is set to 0, and the pre-charge signal generator 116 generates the first oscillation signal OS1, as shown in FIG. Figure 5 As shown in the graph 150 of FIG. 1 , the first oscillation signal OS1 has a period of about 8 ns and a frequency of about 123 MHz. Figure 5 As shown in graph 152 of FIG1 , when OS1 is provided to frequency divider 110, the frequency divider generates a first divided oscillation signal DOS having a frequency of approximately 7.7 MHz and a period of approximately 130 nanoseconds. A period of approximately 130 nanoseconds is sufficient to charge or discharge one of I / O pads 112, allowing accurate measurement of the frequency and period of the divided oscillation signal. The value of the pre-charge delay can then be calculated by dividing the period of the first divided oscillation signal by the division factor 16.

[0095] As described above, if the calculated value of the pre-charge delay is outside the tolerance range, the pre-charge delay can be adjusted or fine-tuned. The test circuit 104 can adjust VREF1 so that the delay capacitor C1 is discharged faster or slower as needed. The pre-charge delay can then be tested again, and VREF1 can be adjusted again until the pre-charge delay falls within the selected tolerance range.

[0096] As in Figure 5 As shown in FIG, during the test evaluation delay, both OC1 and OC2 are set to 1, and the evaluation signal generator 118 generates the second oscillating signal OS2. Figure 5, the second oscillating signal OS2 has a period of approximately 10.5 ns and a frequency of approximately 95 MHz. When OS2 is provided to the frequency divider 110, the frequency divider 110 generates a second divided oscillating signal DOS having a frequency of approximately 6 MHz and a period of approximately 169 ns. The period of approximately 169 ns is sufficient to charge or discharge one of the I / O pads 112, so that the frequency and period of the second divided oscillating signal can be correctly measured. Then, by dividing the period of the oscillating signal by the frequency division factor 16, the value of the sum of the evaluation delay and the pre-charge delay can be calculated. The value of the evaluation delay can then be calculated by subtracting the pre-calculated pre-charge delay from the sum of the calculated pre-charge delay and the evaluation delay. This calculation gives an evaluation delay of approximately 2.5 ns.

[0097] As described above, if the calculated estimated delay has a value outside the selected tolerance range, the estimated delay can be adjusted or fine-tuned. Test circuit 104 can adjust VREF1 so that delay capacitor C1 discharges faster or slower as needed. The estimated delay can then be tested again, and VREF2 can be adjusted again until the estimated delay falls within the selected tolerance range.

[0098] Figure 6 1 is a block diagram of an integrated circuit 102 according to one embodiment. The integrated circuit 102 includes a digital controller 160, a read signal generator 108, a sense amplifier 107, a column decoder 162, and a memory array 106.

[0099] Memory array 106 includes a plurality of memory cells arranged in m rows and n columns. Memory array 106 includes a plurality of bit lines BL1-BLn, one for each column. Each bit line is coupled to or connected to a memory cell in a corresponding column. Memory array 106 includes a plurality of word lines WL1-WLm, one for each column. Each word line is coupled to a memory cell in a corresponding row.

[0100] Bit lines BL1-Bln are coupled to column decoder 162. Column decoder 162 is coupled to sense amplifier 107. There are j sense amplifiers. Each sense amplifier is coupled to column decoder 162 via two read lines. For example, the first sense amplifier is coupled to sense lines SA1a and SA1b. The jth sense amplifier is coupled to sense lines SAja and SAjb. During a read operation, the column decoder connects each sense amplifier to one of the bit lines according to the memory address to be read. Sense amplifier 107 precharges the bit line and evaluates the data from the bit line via read line SA. Sense amplifier 107 outputs the data value read from the memory cell via data output lines DO1-DOj.

[0101] The read signal generator 108 supplies a read signal to the sense amplifier 107. Specifically, the read signal generator 108 outputs a precharge signal PS, a complementary precharge signal PSN, an evaluation signal ES, and a complementary precharge signal ESN to each sense amplifier. The read signal controls the operation of the sense amplifier 107.

[0102] The digital controller 160 controls the read signal generator 108. When data is to be read from the memory array 106, the digital controller 160 controls the read signal generator 108 to generate a read signal. Although not shown, the digital controller 160 may also control the column decoder 162 and may provide a memory address to the column decoder 162. The integrated circuit may also include a row decoder for selecting a word line for a read operation under the control of the digital controller 160.

[0103] Although not in Figure 6 , but the memory array may include access transistors that couple the memory cells to word lines. The memory array may also include access transistors that couple the memory cells to bit lines.

[0104] In one embodiment, the memory cells may include phase change memory cells. Each phase change memory cell includes a material whose phase (such as an amorphous phase or a crystalline phase) indicates the value of the data stored therein. Data is written to the phase change memory cell by changing the phase of the material.

[0105] In one embodiment, the memory cell comprises a read-only memory cell, a flash memory cell, a magnetoresistive random access memory cell (MRAM), or other type of non-volatile memory cell.

[0106] The memory cells may include volatile memory cells that require continuous or intermittent refreshing to retain stored data. Volatile memory cells may include dynamic random access memory (DRAM), static random access memory (SRAM), or other types of volatile memory cells.

[0107] Figure 7 7 is a flow chart of a process 700 according to one embodiment. At 702, a first oscillating signal is generated using a read signal generator of an integrated circuit. At 704, a first divided oscillating signal is generated from the first oscillating signal using a frequency divider of the integrated circuit. At 706, the first divided oscillating signal is output on an output pad of the integrated circuit.

[0108] The various embodiments described above can be combined to provide other embodiments. All U.S. patent application publications and U.S. patent applications mentioned in this specification and / or listed in the application data sheet are incorporated herein by reference in their entirety. If necessary, various aspects of the embodiments can be modified to adopt the concepts of the various patents, applications and publications to provide other embodiments.

[0109] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments, along with the full scope of equivalents to which such claims are entitled. Therefore, the claims are not limited by the disclosure.

Claims

1. An electronic device comprising: memory cell array; a read signal generator configured to generate a read signal for controlling a read operation of the memory cell, the read signal generator configured to selectively generate an oscillation signal having a first frequency based on a characteristic of the read signal; a frequency divider coupled to the read signal generator, the frequency divider being configured to receive the oscillation signal from the read signal generator, and the frequency divider being configured to generate a divided oscillation signal having a second frequency based on the first frequency and a division ratio of the frequency divider; as well as an output pad coupled to the frequency divider and configured to receive the divided oscillation signal; The frequency division ratio is configured to ensure that a period of the divided oscillation signal is longer than a charging time and a discharging time of the output pad. 2 . The electronic device of claim 1 , wherein the read signal generator is configured to cause the read signal to transition between logic levels in response to transitions in the second read signal.

3. The electronic device of claim 2 , wherein the read signal generator comprises a delay circuit device configured to introduce a delay between the transition of the second read signal and the transition of the read signal, wherein the characteristic is the delay. The electronic device according to claim 3 , wherein the oscillation signal has a period equal to the delay. The electronic device of claim 3 , wherein the first frequency is based on the delay. The electronic device according to claim 3 , wherein the read signal generator is configured to adjust the delay by adjusting a reference signal. 7 . The electronic device according to claim 6 , wherein the delay circuit device comprises a capacitor, and wherein the reference signal adjusts a charging time or a discharging time of the capacitor. 8 . The electronic device of claim 1 , further comprising a sense amplifier coupled to the memory cell array and the read signal generator, the sense amplifier configured to read data from the memory cell under control of the read signal.

9. The electronic device of claim 8 , wherein the memory cell array comprises a plurality of bit lines, wherein the sense amplifier is configured to read data from the memory cell via one of the bit lines, and wherein the read signal is a precharge signal configured to cause the sense amplifier to precharge one of the bit lines.

10. The electronic device of claim 9, wherein the characteristic is a precharge delay of the precharge signal. The electronic device of claim 10 , wherein the first frequency is equal to the pre-charge delay. 12 . The electronic device of claim 11 , wherein the read signal generator generates the pre-charge signal based at least in part on a read clock signal. 13 . The electronic device of claim 8 , wherein the read signal is an evaluation signal that causes the sense amplifier to read data from one of the memory cells.

14. The electronic device of claim 13, wherein the characteristic is an evaluation delay corresponding to a delay of a logic state transition of the evaluation signal after precharging a bit line of the memory array. The electronic device of claim 14 , wherein the first frequency is equal to the evaluation delay. 16 . The electronic device of claim 15 , wherein the read signal generator is configured to generate a second read signal corresponding to a precharge signal configured to cause the sense amplifier to precharge the bit line. 17 . The electronic device of claim 16 , wherein the first frequency is equal to a sum of the evaluation delay and a pre-charge delay of the pre-charge signal. 18 . The electronic device of claim 1 , wherein the read signal generator is configured to receive an oscillator control signal that selectively causes the read signal generator to generate the oscillation signal. 19 . The electronic device according to claim 18 , wherein the oscillator control signal causes the read signal generator to generate the oscillation signal by enabling an oscillator loop.

20. The electronic device of claim 19, wherein the memory cell comprises a phase change memory cell.

21. A method for operating a memory cell, comprising: generating a first oscillating signal having a first frequency using a read signal generator of the integrated circuit; generating a first frequency-divided oscillation signal from the first oscillation signal based on the first frequency and a frequency division ratio of the frequency divider using a frequency divider of the integrated circuit; as well as Outputting the first frequency-divided oscillation signal on an output pad of the integrated circuit; The frequency division ratio is configured to ensure that a period of the first frequency-divided oscillation signal is longer than a charging time and a discharging time of the output pad.

22. The method of claim 21 , wherein generating the first oscillating signal comprises: A first oscillator loop is enabled in the read signal generator.

23. The method according to claim 22, further comprising: The first oscillating signal is generated in response to an input received from a circuit external to the integrated circuit.

24. The method of claim 22, further comprising: generating a second oscillating signal using the read signal generator; generating a second frequency-divided oscillating signal from the second oscillating signal using the frequency divider; as well as The second frequency-divided oscillation signal is outputted on the output pad.

25. The method of claim 24, wherein generating the first oscillating signal comprises: A second oscillator loop is enabled in the read signal generator.

26. The method of claim 25, wherein the second oscillator loop comprises a portion of the first oscillator loop. 27 . The method of claim 22 , wherein the read signal generator is configured to generate a read signal that controls a read operation of a memory cell of the integrated circuit.

28. The method of claim 27, wherein the read signal generator comprises a delay circuit arrangement configured to introduce a delay in the read signal, wherein the oscillator loop comprises the delay circuit arrangement.

29. The method of claim 28, wherein the first oscillating signal has the first frequency based on the delay.

30. The method of claim 28, wherein a period of the first oscillating signal is equal to the delay.

31. The method of claim 28, further comprising: The delay is adjusted in response to a signal received from a circuit external to the integrated circuit.

32. The method of claim 31 , wherein adjusting the delay comprises: Adjusts the charge or discharge rate of a capacitor.

33. A method for operating a memory cell, comprising: generating an oscillating signal having a first frequency using a read signal generator of the integrated circuit; generating, using a frequency divider of the integrated circuit, a divided oscillation signal having a second frequency based on the first frequency and a frequency division ratio of the frequency divider; outputting the divided frequency oscillation signal on an output pad of the integrated circuit; measuring the second frequency via the output pad using a test circuit; and using the test circuit, calculating the first frequency based on the second frequency and the frequency division ratio; The frequency division ratio is configured to ensure that a period of the divided oscillation signal is longer than a charging time and a discharging time of the output pad.

34. The method of claim 33, further comprising: providing a control signal from the test circuit to the integrated circuit; as well as The first frequency is adjusted in response to the control signal.

35. An integrated circuit comprising: memory cell array; a sense amplifier coupled to the memory cell; a read signal generator coupled to the sense amplifier and configured to generate a first read signal for reading data from the memory cell, pass the first read signal to the sense amplifier, and generate a first oscillation signal having a first frequency based on characteristics of the first read signal; a frequency divider coupled to the read signal generator and configured to receive the oscillation signal and generate a first frequency-divided oscillation signal having a second frequency signal by dividing the frequency of the first oscillation signal based on the first frequency and a frequency division ratio of the frequency divider; as well as an output pad coupled to the frequency divider and configured to receive the first divided signal from the frequency divider; The frequency division ratio is configured to ensure that a period of the first frequency-divided oscillation signal is longer than a charging time and a discharging time of the output pad.

36. The integrated circuit of claim 35, wherein the memory cell comprises a phase change memory cell.

37. The integrated circuit of claim 35, wherein the read signal generator comprises: a first selectively enabled oscillator loop configured to generate the first oscillation signal when enabled; as well as a second selectively enabled oscillator loop configured to generate a second oscillation signal having a third frequency, wherein the frequency divider is configured to receive the second oscillation signal and generate a second divided oscillation signal having a fourth frequency based on the third frequency and the division ratio, wherein the output pad is configured to receive the second divided oscillation signal.

38. An integrated circuit comprising: memory arrays; a read signal generator configured to generate a read signal for controlling a read operation of the memory array, the read signal generator comprising a first selectively enabled oscillator loop configured to generate a first oscillation signal having a first frequency when enabled; a frequency divider coupled to the read signal generator, the frequency divider being configured to receive the oscillation signal and generate a first frequency-divided oscillation signal having a second frequency signal based on the first frequency and a frequency division ratio of the frequency divider; as well as an output pad coupled to the frequency divider and configured to receive the first divided signal from the frequency divider; The frequency division ratio is configured to ensure that a period of the first frequency-divided oscillation signal is longer than a charging time and a discharging time of the output pad.

39. The integrated circuit of claim 38 , wherein the read signal generator comprises a second selectively enabled oscillator loop configured to generate a second oscillation signal having a third frequency, wherein the frequency divider is configured to receive the second oscillation signal and generate a second divided oscillation signal having a fourth frequency based on the third frequency and the division ratio, wherein the output pad is configured to receive the second divided oscillation signal.

40. The integrated circuit of claim 39, further comprising a multiplexer configured to selectively provide the first divided-down oscillator signal or the second divided-down oscillator signal to the output pad.

41. A method for operating a memory cell, comprising: Responsively generating a first oscillating signal having a first frequency using a read signal generator of the integrated circuit; generating a first frequency-divided oscillation signal from the first oscillation signal based on the first frequency and a frequency division ratio of the frequency divider using a frequency divider of the integrated circuit; Outputting the first frequency-divided oscillation signal on an output pad of the integrated circuit; receiving a command for adjusting the frequency of the first oscillation signal from a circuit external to the integrated circuit; and adjusting the first frequency in response to the command; The frequency division ratio is configured to ensure that a period of the first frequency-divided oscillation signal is longer than a charging time and a discharging time of the output pad.

42. The method of claim 41, wherein the external circuit is a test circuit.

43. An electronic device comprising: a read signal generator configured to generate a read signal for controlling a read operation of a memory cell, the read signal generator being configured to selectively generate an oscillation signal having a first frequency based on a characteristic of the read signal; a frequency divider coupled to the read signal generator, the frequency divider being configured to receive an oscillation signal from the read signal generator and to generate a divided oscillation signal having a second frequency based on the first frequency and a frequency division ratio of the frequency divider; as well as an output pad coupled to the frequency divider and configured to receive the divided oscillation signal; The frequency division ratio is configured to ensure that a period of the divided oscillation signal is longer than a charging time and a discharging time of the output pad. 44 . The electronic device of claim 43 , further comprising a sense amplifier configured to receive the read signal from the read signal generator.

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