Semiconductor device

Abstract

A semiconductor device capable of being arranged without misalignment of semiconductor chips in joining of the semiconductor chips is provided. The semiconductor device has semiconductor chips (20, 21) arranged in an arrangement region via solder (31), and bonding wires (15a to 15d) arranged in a manner of crossing a groove portion (14) in a length direction at a gap (A) in plan view. With such bonding wires (15a to 15d), the solder (31) melted by reflow soldering in a manufacturing process of the semiconductor device is blocked from diffusing to the gap (A) side of the arrangement region. Therefore, the diffused solder (31) is prevented from being joined at the gap (A), and misalignment of the semiconductor chips (20, 21) is suppressed.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device. BACKGROUND

[0002] A semiconductor device including a semiconductor chip such as an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or the like is used as a power conversion device, for example. Such a semiconductor device includes the semiconductor chip, and a ceramic circuit board to which the semiconductor chip is arranged via solder. The ceramic circuit board is provided with an insulating board, and a plurality of circuit boards formed on the insulating board. Any of the plurality of circuit boards is arranged with the semiconductor chip via solder. Further, a cylindrical contact member for mounting an external connection terminal is provided on a predetermined region of the circuit board via solder. Further, there is a semiconductor device using a metal base board, which is formed with a groove portion in a portion of the circuit board in the vicinity of a position at which the semiconductor chip is fused. The groove portion is used as a positioning when the semiconductor chip is arranged on the circuit board.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT DOCUMENTS

[0005] Patent Document 1: Japanese Patent Application Publication No. 2014-187179

[0006] Patent Document 2: Japanese Patent Application Publication No. H1-293557 SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] In recent years, miniaturization and large capacity of semiconductor devices are being required. Therefore, improvement of mounting density of semiconductor chips is being promoted, and the interval between semiconductor chips is being reduced. However, there is a case where, in a semiconductor device in which semiconductor chips are arranged via solder in a pair of arrangement regions formed by a groove portion of a circuit board and joined, the solder spreads and overflows from the pair of arrangement regions. The semiconductor chips are displaced in arrangement position due to the spread of the solder. Further, there is a case where the semiconductor chips contact each other due to the spread of the solder. Furthermore, if the spread solder reaches the groove portion, there is a possibility that a void is contained therein. In this case, if the semiconductor chips are displaced up to the groove portion, there is a void in the lower portion of the semiconductor chips. If there is a void, the heat dissipation property or the like of the semiconductor chips is reduced.

[0009] The present application has been made in view of the above, and has an object to provide a semiconductor device which can be arranged without misalignment of semiconductor chips in joining of the semiconductor chips in close proximity.

[0010] Technical Solution

[0011] According to one aspect of the present application, there is provided a semiconductor device including: a substrate having a circuit board and an insulating board on which the circuit board is formed on a front surface, the circuit board having a first arrangement region and a second arrangement region each provided in parallel with a gap on a front surface, and a groove portion formed in the gap in a length direction along the parallel direction; a first semiconductor chip provided in the first arrangement region via a first joining material; a second semiconductor chip provided in the second arrangement region via a second joining material; and a barrier member provided across the groove portion in the length direction in plan view.

[0012] Technical Effects

[0013] According to the disclosed technology, a semiconductor device that suppresses a decrease in reliability can be provided, which can suppress diffusion of a joining material between adjacent semiconductor chips, and can reliably prevent misalignment of semiconductor chips. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 FIG. 1 is a side view showing a semiconductor device of a first embodiment.

[0015] Figure 2 FIG. 2 is a plan view showing the semiconductor device of the first embodiment.

[0016] Figure 3 FIG. 3 is a diagram showing a flow of a manufacturing method of the semiconductor device of the first embodiment.

[0017] Figure 4 FIG. 4 is a plan view for explaining a ceramic circuit board used in the manufacturing method of the semiconductor device of the first embodiment.

[0018] Figure 5 FIG. 5 is a cross-sectional view for explaining the ceramic circuit board used in the manufacturing method of the semiconductor device of the first embodiment.

[0019] Figure 6 FIG. 6 is a plan view for explaining a wire bonding process for the ceramic circuit board in the manufacturing method of the semiconductor device of the first embodiment.

[0020] Figure 7 FIG. 7 is a plan view for explaining a process in which a substrate positioning tool mounts the ceramic circuit board in the manufacturing method of the semiconductor device of the first embodiment.

[0021] Figure 8 FIG. 6 is a sectional view of the step of mounting the ceramic circuit substrate in the substrate positioning tool for explaining the manufacturing method of the semiconductor device of the first embodiment.

[0022] Figure 9 FIG. 7 is a plan view of the step of mounting the component positioning tool for explaining the manufacturing method of the semiconductor device of the first embodiment.

[0023] Figure 10 FIG. 8 is a sectional view of the step of mounting the component positioning tool for explaining the manufacturing method of the semiconductor device of the first embodiment.

[0024] Figure 11 FIG. 9 is a plan view of the step of mounting the contact component by the component positioning tool for explaining the manufacturing method of the semiconductor device of the first embodiment.

[0025] Figure 12 FIG. 10 is a sectional view of the step of mounting the contact component by the component positioning tool for explaining the manufacturing method of the semiconductor device of the first embodiment.

[0026] Figure 13 FIG. 11 is a plan view of the step of mounting the pressing tool for explaining the manufacturing method of the semiconductor device of the first embodiment.

[0027] Figure 14 FIG. 12 is a sectional view of the step of mounting the pressing tool for explaining the manufacturing method of the semiconductor device of the first embodiment.

[0028] Figure 15 FIG. 13 is a plan view of a main part of the ceramic circuit substrate of the semiconductor device of the first embodiment.

[0029] Figure 16 FIG. 14 is a sectional view of a main part of the ceramic circuit substrate of the semiconductor device of the first embodiment.

[0030] Figure 17 FIG. 15 is a plan view of a main part of the ceramic circuit substrate of the semiconductor device of the reference example.

[0031] Figure 18 FIG. 16 is a plan view of a main part of the other ceramic circuit substrate of the semiconductor device of the first embodiment.

[0032] Figure 19 FIG. 17 is a plan view of a main part of the ceramic circuit substrate of the semiconductor device of the second embodiment.

[0033] Figure 20 FIG. 18 is a sectional view of a main part of the ceramic circuit substrate of the semiconductor device of the second embodiment.

[0034] Figure 21 is a plan view of a main portion of another ceramic circuit board of the semiconductor device of the second embodiment.

[0035] Figure 22 is a plan view of a main portion of a ceramic circuit board of the semiconductor device of the third embodiment.

[0036] Symbol explanation

[0037] 10 ceramic circuit board

[0038] 11 insulating plate

[0039] 12, 12a, 12b, 12c, 12d, 12e circuit board

[0040] 12b1 plating film

[0041] 13 metal plate

[0042] 14, 14a, 14b, 14c groove

[0043] 15a, 15b, 15c, 15d, 15e, 15f, 35 bonding wire

[0044] 20, 21 semiconductor chip

[0045] 20a, 21a arrangement region

[0046] 30 contact member

[0047] 31 solder

[0048] 40 external connection terminal

[0049] 45 sealing member

[0050] 50 semiconductor device

[0051] 60 board positioning tool

[0052] 61 housing

[0053] 62 guide post

[0054] 70 member positioning tool

[0055] 72, 82 guide hole

[0056] 73 element guide portion

[0057] 74 joint guide portion

[0058] 80 pressing tool

[0059] 81 flat plate portion

[0060] 81a main surface

[0061] 83 pressing portion DETAILED DESCRIPTION

[0062] Hereinafter, an embodiment will be described with reference to the drawings. Note that in the following description, "front surface" and "upper surface" mean surfaces facing upward in the semiconductor device 50. Similarly, "upper" means a direction upward in the semiconductor device 50. "Back surface" and "lower surface" mean surfaces facing downward in the semiconductor device 50. Similarly, "lower" means a direction downward in the semiconductor device 50. As needed, the same directionality is indicated in other drawings. "Front surface", "upper surface", "upper", "back surface", "lower surface", "lower", and "side surface" are merely convenient expressions to determine relative positional relationships and do not limit the technical idea of the present application. For example, "upper" and "lower" do not necessarily mean vertical directions with respect to a bottom surface. That is, the directions of "upper" and "lower" are not limited to the direction of gravity. Figure 1 Figure 1 [First Embodiment] Figure 1 Figure 1 The semiconductor device of the first embodiment will be described with reference to FIGS. 1A to 1C.

[0063] [First Embodiment]

[0064] The semiconductor device of the first embodiment will be described with reference to FIGS. 1A to 1C. Figure 1 Figure 2 is a side view illustrating the semiconductor device of the first embodiment, Figure 1 is a plan view illustrating the semiconductor device of the first embodiment. Note that a sealing member is indicated by a broken line, and in Figure 2 , illustration of the sealing member is omitted. In addition, the semiconductor device 50 omits description of a case that houses the ceramic circuit board 10 and the like. In addition, in the first embodiment, the same reference numerals are used to describe the plurality of circuit boards 12, the plurality of semiconductor chips 20, the plurality of semiconductor chips 21, the plurality of contact members 30, the plurality of bonding wires 35, and the plurality of external connection terminals 40 without distinguishing them. Note that the same reference numerals are used to describe the same components with respect to the components other than the above without distinguishing them. Figure 2

[0065] As Figure 1 Figure 2 As​​​​As shown, the semiconductor device 50 has a ceramic circuit substrate 10 (substrate), and semiconductor chips 20, 21 joined to the front surface of the ceramic circuit substrate 10. The semiconductor device 50 has a contact member 30 joined to the front surface of the ceramic circuit substrate 10. The semiconductor chips 20, 21 and the contact member 30 are joined to the front surface of the ceramic circuit substrate 10 via a joining material such as solder (omitted from the drawing). In addition, the semiconductor device 50 has a bonding wire 35 electrically connecting the front surface of the ceramic circuit substrate 10 and the main electrodes of the semiconductor chips 20, 21. In addition, an external connection terminal 40 is mounted by press-fitting the contact member 30. Further, the semiconductor device 50 is sealed by a sealing member 45 together with the semiconductor chips 20, 21 on the front surface of the ceramic circuit substrate 10 in a manner that the front end portion of the external connection terminal 40 mounted to the contact member 30 protrudes.

[0066] The ceramic circuit substrate 10 has an insulating plate 11, a plurality of circuit plates 12 formed on the front surface of the insulating plate 11, and a metal plate 13 formed on the back surface of the insulating plate 11. The insulating plate 11 is composed of a high-thermal-conductivity ceramic such as alumina, aluminum nitride, silicon nitride, or the like having excellent thermal conductivity. The plurality of circuit plates 12 (including circuit plates 12a to 12e) are composed of a material having excellent electrical conductivity. As such a material, for example, copper or a copper alloy, or the like is used. Further, in order to improve corrosion resistance, for example, the surface of the circuit plate 12 can be subjected to plating treatment using nickel or a nickel alloy, or the like. As the nickel alloy, a nickel-phosphorus alloy, a nickel-boron alloy, or the like is preferable. The metal plate 13 is composed of a metal such as aluminum, iron, silver, copper, or an alloy including at least one of these metals, or the like having excellent thermal conductivity. In addition, a heat dissipation plate and / or a cooler (omitted from the drawing) can be formed on the back surface of the metal plate 13. Note that the insulating plate 11 is rectangular, for example, in plan view. In addition, the metal plate 13 is rectangular in plan view, having an area smaller than that of the insulating plate 11 and a total area larger than that of the circuit plates 12. Thus, the ceramic circuit substrate 10 is rectangular, for example.

[0067] The circuit board 12 is appropriately formed with a groove portion 14. The groove portion 14 has a groove portion 14a formed so as to extend in the length direction parallel to the semiconductor chips 20, 21 (mounting regions) in the gap of the mounting region of the circuit board 12 on which the semiconductor chips 20, 21 are mounted. Further, the groove portion 14 has a groove portion 14b formed between the mounting region on which the semiconductor chips 20, 21 are mounted and a region on which a terminal such as the contact member 30 and / or an electronic component such as a capacitor, a resistor, and the like is mounted. Furthermore, the groove portion 14 has a groove portion 14c formed between the mounting region on which the semiconductor chips 20, 21 are mounted and a region to which the bonding wire 35 is bonded. Such a groove portion 14 (collectively referred to as the groove portions 14a, 14b, 14c) is formed independently in the plane of the circuit board 12 without contacting the end edge of the circuit board 12 in plan view. Further, the groove portion 14 is formed through the circuit board 12 in the thickness direction of the circuit board 12. The length in the width direction of such a groove portion 14 is, for example, 100 μm or more and 1.0 mm or less, and is preferably 400 μm or more and 500 μm or less. Note that the length in the length direction of the groove portion 14 is arbitrarily formed as needed. The groove portion 14 will be described in detail later.

[0068] Further, the groove portion 14 of the circuit board 12a to 12e is provided with the bonding wire 15a to 15f as a barrier member. The barrier member is provided in the groove portion 14a between the semiconductor chips 20, 21. Although the barrier member can be provided in the other groove portions 14b, 14c, it is preferable not to provide the barrier member. For example, if the barrier member is provided in the groove portion 14b, the soldering tool cannot be smoothly arranged when the contact member 30 is soldered. Further, if the barrier member is provided in the groove portion 14c, it can cause interference when the bonding wire 35 for electrically wiring is bonded, and can become an obstacle. Note that the case in which the barrier member is provided in the groove portion 14a between the two semiconductor chips 20, 21 is shown in the first embodiment. The barrier member can be provided in the groove portion between three or more semiconductor chips, and the barrier member can be provided in each groove portion as in the present embodiment, without being limited to this case.

[0069] Such bonding wires 15a to 15f are, for example, thin wires having a diameter of 125 μm or more and 400 μm or less. The bonding wires 15a to 15f are composed of, for example, aluminum, nickel, iron, or an alloy including at least one of these. In particular, the bonding wires 15a to 15f are preferably a metal having a lower solder wettability than the surfaces of the circuit boards 12a to 12e. For example, in the case where the surfaces of the circuit boards 12a to 12e are copper or a copper alloy, the bonding wires 15a to 15f can be composed of aluminum, nickel, iron, or an alloy including at least one of these. Also, for example, in the case where the surfaces of the circuit boards 12a to 12e are formed with nickel or a nickel alloy, the bonding wires 15a to 15f can be composed of, for example, aluminum or an aluminum alloy. Note that the bonding wires 15a to 15f will be described in detail later.

[0070] As the ceramic circuit board 10 having such a configuration, for example, a DCB (Direct Copper Bonding) substrate, an AMB (Active Metal Brazed) substrate, or the like can be used. Also, a cooler as described above (not shown) can be mounted to the metal plate 13 of the ceramic circuit board 10 via a thermally conductive paste such as silicon mixed with a filler of a metal oxide to improve the heat dissipation. The cooler in this case is composed of, for example, aluminum, iron, silver, copper, or an alloy including at least one of these, which has a high thermal conductivity. Also, as the cooler, a heat sink, a heat sink composed of a plurality of heat sinks, a cooling device using water cooling, or the like can be used.

[0071] The semiconductor chip 20 includes a switching element such as an IGBT, a power MOSFET, or the like, which is made of silicon or silicon carbide. Such a semiconductor chip 20 has, for example, a drain electrode (or a collector electrode) as a main electrode on the back surface, and a gate electrode and a source electrode (or an emitter electrode) as main electrodes on the front surface. In addition, the semiconductor chip 21 includes a diode such as an SBD (Schottky Barrier Diode), and an FWD (Free Wheeling Diode). Such a semiconductor chip 21 has a cathode electrode as a main electrode on the back surface, and an anode electrode as a main electrode on the front surface. The back surface side of the semiconductor chips 20 and 21 described above is bonded to a predetermined circuit board (omitted from the drawing). Note that the semiconductor chips 20 and 21 are bonded to the circuit board 12 via solder (omitted from the drawing). The solder will be described later. In addition, although omitted from the drawing, an RC (Reverse-Conducting)-IGBT that has both functions of an IGBT and an FWD can be used instead of the semiconductor chips 20 and 21. In addition, a lead frame, an external connection terminal (pin terminal, contact member, or the like), an electronic component (thermistor, current sensor), or the like can be provided as needed instead of the semiconductor chips 20 and 21. Note that the thickness of such a semiconductor chip 20 or 21 is, for example, 180 μm or more and 220 μm or less, and is about 200 μm on average.

[0072] The bonding wire 35 is appropriately electrically connected between the semiconductor chips 20 and 21 and the circuit board 12, or between a plurality of semiconductor chips 20 and 21. Such a bonding wire 35 is made of a material having excellent electrical conductivity. As such a material, for example, gold, silver, copper, aluminum, or an alloy including at least one of these is used. In addition, the diameter of the bonding wire 35 is, for example, 110 μm or more and 200 μm or less. The diameter of the other bonding wire 35 is, for example, 350 μm or more and 500 μm or less.

[0073] The sealing member 45 can be, for example, silicone. In addition, the sealing member 45 includes a thermosetting resin such as an epoxy resin, a phenol resin, a maleimide resin, or the like, and a filler material containing a thermosetting resin. As one example of such a sealing member 45, an epoxy resin, and a filler material such as silica, alumina, boron nitride, or aluminum nitride contained in the epoxy resin as a filler are included.

[0074] Next, a manufacturing method of such a semiconductor device 50 is described using a flowchart showing each process and each tool. Figures 4-14 , according to the flowchart shown in Figure 3 . Figure 3 is a drawing showing a flow of a manufacturing method of a semiconductor device according to the first embodiment. Figure 4is a plan view for explaining the ceramic circuit substrate used in the manufacturing method of the semiconductor device of the first embodiment. Figure 5 is a cross-sectional view for explaining the ceramic circuit substrate used in the manufacturing method of the semiconductor device of the first embodiment.

[0075] Figure 6 is a plan view for explaining the manufacturing method of the semiconductor device of the first embodiment, a wire bonding process for the ceramic circuit substrate. Figure 7 is a plan view for explaining the manufacturing method of the semiconductor device of the first embodiment, a process in which the substrate positioning tool mounts the ceramic circuit substrate. Figure 8 is a cross-sectional view for explaining the manufacturing method of the semiconductor device of the first embodiment, a process in which the substrate positioning tool mounts the ceramic circuit substrate.

[0076] Figure 9 is a plan view for explaining the manufacturing method of the semiconductor device of the first embodiment, a process in which the component positioning tool is mounted. Figure 10 is a cross-sectional view for explaining the manufacturing method of the semiconductor device of the first embodiment, a process in which the component positioning tool is mounted. Figure 11 is a plan view for explaining the manufacturing method of the semiconductor device of the first embodiment, a process in which the contact component is mounted using the component positioning tool. Figure 12 is a cross-sectional view for explaining the manufacturing method of the semiconductor device of the first embodiment, a process in which the contact component is mounted using the component positioning tool. Figure 13 is a plan view for explaining the manufacturing method of the semiconductor device of the first embodiment, a process in which the pressing tool is mounted. Figure 14 is a cross-sectional view for explaining the manufacturing method of the semiconductor device of the first embodiment, a process in which the pressing tool is mounted. Note that, Figure 5 , 8 , 10, 12, 14 are Figure 4 , 7 , 9, 11, 13.

[0077] The semiconductor device 50 is manufactured in accordance with the manufacturing process (flow) shown below. Each of the manufacturing processes below is executed artificially or by the manufacturing device as needed.

[0078] [Step S10] The semiconductor chips 20, 21, the ceramic circuit substrate 10, and the contact component 30 are prepared. Not limited to these components, components and the like required in the manufacturing of the semiconductor device 50 are prepared in advance. Note that, as Figure 4 and Figure 5As shown, the ceramic circuit substrate 10 includes an insulating plate 11, a plurality of circuit boards 12 formed on the front surface of the insulating plate 11, and a metal plate 13 formed on the back surface of the insulating plate 11. Figure 4 In the figure, the rectangular dashed lines drawn on the multiple circuit boards 12 indicate the placement areas for the semiconductor chips 20 and 21. Grooves 14 are formed for these placement areas. For example, on circuit boards 12a to 12d, a pair of placement areas 20a and 21a are defined, each separated by a gap and parallel to the gap. Grooves 14 are formed in these gaps, their longitudinal directions parallel to the gaps. Grooves 14 serve as alignment points when solder is later applied to placement areas 20a and 21a.

[0079] [Step S11] Figure 6 As shown in the top view, in circuit boards 12a through 12d of the ceramic circuit substrate 10, grooves 14 are formed in the gaps between arrangement areas 20a and 21a, and bonding wires 15a through 15d are provided across the length of grooves 14. As described above, bonding wires 15a through 15d are provided in grooves 14 between semiconductor chips 20 and 21. Furthermore, in circuit board 12e, groove 14a is also formed in the gap between arrangement area 20a of semiconductor chip 20, and bonding wires 15e and 15f are provided across the length of groove 14a. While bonding wires may be provided in grooves 14b and 14c, it is preferred that no bonding wires be provided.

[0080] [Step S12] Solder 31 is applied to the areas where the semiconductor chips 20, 21 and the contact members 30 are provided on the circuit board 12 of the ceramic circuit substrate 10 (see FIG. 1 ). Figure 7 ). It should be noted that the solder 31 of the circuit board 12 of such a ceramic circuit substrate 10 can be applied by, for example, a dispenser. Soldering pieces (not shown) can also be arranged in each setting area. It should be noted that Figure 7 The solder 31 shown is represented by a quadrangle to indicate the solder corresponding to the semiconductor chips 20 and 21 , and is represented by a circle to indicate the solder corresponding to the contact member 30 .

[0081] The solder 31 is made of lead-free solder, primarily composed of, for example, a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, or a tin-silver-indium-bismuth alloy. Furthermore, the solder 31 includes a flux that removes oxides from the circuit board 12. The flux may contain, for example, epoxy resin, carboxylic acid, rosin resin, an activator, and a solvent, and may contain other ingredients as needed. Furthermore, the solder 31 may include additives such as nickel, germanium, cobalt, or silicon.

[0082] The order of executing the steps S11 and S12 can be switched. If step S12 is performed first, the solder 31 can be applied to the bonding wires 15a to 15f without hindrance. The solder 31 can be applied by screen printing, for example.

[0083] [Step S13] Figure 7 and Figure 8 As shown, bonding wires 15a to 15f are arranged in this manner, and the ceramic circuit substrate 10 coated with solder 31 is mounted on a substrate positioning tool 60. The substrate positioning tool 60 is rectangular in plan view, with a central portion having a recessed housing 61 for accommodating the ceramic circuit substrate 10. Guide posts 62 are formed at each of the four corners of the upper surface of the substrate positioning tool 60. The substrate positioning tool 60 is made of a heat-resistant material such as a composite ceramic material or carbon. The ceramic circuit substrate 10 is placed on the housing 61 of the substrate positioning tool 60, with the circuit board 12 facing forward.

[0084] Moreover, if Figure 9 and Figure 10 As shown, a component positioning tool 70 is mounted on the substrate positioning tool 60. Furthermore, the component positioning tool 70 is also made of a material with excellent heat resistance, such as a composite ceramic material or carbon. The component positioning tool 70 is in the shape of a rectangular plate when viewed from above. Guide holes 72 are formed at each of the four corners of the component positioning tool 70. Each guide hole 72 is inserted through each guide post 62 of the substrate positioning tool 60, thereby mounting the component positioning tool 70 on the substrate positioning tool 60. Furthermore, the component positioning tool 70 is configured so that the component guide portion 73 and the connector guide portion 74 are open. As described above, when the component positioning tool 70 is mounted on the substrate positioning tool 60, the component guide portion 73 and the connector guide portion 74 are respectively opposed to the respective placement areas (applied solder 31) of the contact components 30 and semiconductor chips 20 and 21 of the ceramic circuit substrate 10. It should be noted that the component guide portion 73 and the connector guide portion 74 are formed to be slightly larger than the size of the semiconductor chips 20 and 21 and the contact components 30.

[0085] [Step S14] Figure 11 and Figure 12 As shown, the semiconductor chips 20 and 21 and the contact members 30 are mounted on the solder 31 applied in step S12 on the element guide portion 73 and the terminal guide portion 74 of the component positioning tool 70 by using a mounting device.

[0086] [Step S15] Figure 13 and Figure 14As shown, the pressing tool 80 is attached to the component positioning tool 70. In addition, the pressing tool 80 is also made of a material having excellent heat resistance, such as a composite ceramic material or carbon. The pressing tool 80 has a flat plate portion 81, guide holes 82, and a pressing portion 83. As shown, the flat plate portion 81 has a shape corresponding to the component positioning tool 70 in plan view. The guide holes 82 are formed at the four corners of the flat plate portion 81. The pressing portion 83 is formed on the main surface 81a of the flat plate portion 81 on the side of the component positioning tool 70 in a manner corresponding to the joint guide portion 74 of the component positioning tool 70. If the guide holes 82 are inserted through the guide posts 62 and the pressing tool 80 is attached to the component positioning tool 70, the pressing portion 83 enters the joint guide portion 74 of the component positioning tool 70 and abuts against the contact component 30. Figure 13

[0087] [Step S16] The ceramic circuit board 10, to which the pressing tool 80 is attached in the state of Step S15, is carried into a reflow furnace, and the inside of the furnace is depressurized and heated at a reflow processing temperature (reflow soldering process). The reflow processing temperature is, for example, 250°C or higher and 300°C or lower. As a result, the solders 31 each melt and electrically or mechanically connect the respective circuit boards 12 to the semiconductor chips 20 and 21 and the contact component 30. Then, by solidifying the molten solders 31, the semiconductor chips 20 and 21 and the contact component 30 are joined to the respective circuit boards 12. Note that the state of the semiconductor chips 20 and 21 and the solders 31 as thus joined to the ceramic circuit board 10 will be described later.

[0088] [Step S17] The pressing tool 80 and the component positioning tool 70 are sequentially detached, and the ceramic circuit board 10, to which the semiconductor chips 20 and 21 and the contact component 30 are joined to the respective circuit boards 12, is detached from the board positioning tool 60. Then, predetermined regions of the respective circuit boards 12 of the ceramic circuit board 10 are electrically connected to the semiconductor chips 20 and 21 by bonding wires using an ultrasonic bonding tool not shown. In addition, after the bonding wires 35 are thus connected, external connection terminals (not shown) are pressed into the respective contact components 30.

[0089] [Step S18] The ceramic circuit board 10, to which the semiconductor chips 20 and 21 and the contact component 30 are joined to the respective circuit boards 12 and which is electrically connected by the bonding wires 35, is attached to a housing and sealed by the sealing member 45. As a result, the semiconductor device 50 shown in Figure 1 and Figure 2 is manufactured.

[0090] Next, the semiconductor device 50 shown in Figure 15 and Figure 16 is manufactured.The step S16 of the manufacturing method of the semiconductor device 50 will be described. The reflow soldering is performed on the semiconductor chips 20, 21 and the solder 31 on the circuit board 12 of the ceramic circuit board 10. Figure 15 is a plan view of a main portion of the ceramic circuit board of the semiconductor device of the first embodiment, Figure 16 is a cross-sectional view of a main portion of the ceramic circuit board of the semiconductor device of the first embodiment. It should be noted that Figure 16 (A) of FIG. 10 shows Figure 15 a cross-sectional view of a single-dot chain line Y-Y of FIG. 10, Figure 16 (B) of FIG. 10 shows Figure 15 a cross-sectional view of a single-dot chain line X-X of FIG. 10. In addition, in Figure 15 and Figure 16 , the circuit boards 12a to 12d of the ceramic circuit board 10 and the periphery thereof are shown.

[0091] The reflow soldering is performed on the semiconductor chips 20, 21 and the solder 31 on the circuit board 12a to 12d via the solder 31 (step S16). Then, the solder 31 melts and starts to spread outside the arrangement region of the semiconductor chips 20, 21. For example, as shown in Figure 15 , in the circuit board 12b, the solder 31 in which the semiconductor chips 20, 21 are arranged melts and flows to the gap A side of the semiconductor chips 20, 21. At this time, the bonding wire 15b is provided in the gap A of the semiconductor chips 20, 21. Therefore, even if the solder 31 in which the semiconductor chips 20, 21 are arranged melts and flows to the gap A side of the semiconductor chips 20, 21, the flow is blocked by the bonding wire 15b. Specifically, as shown in Figure 16 , in the circuit board 12b in which the plating film 12b1 is formed, the molten solder 31 directly below the semiconductor chips 20, 21 at a position where the groove portion 14 is not formed is blocked by the bonding wire 15b. Therefore, the solder 31 of the semiconductor chips 20, 21 is prevented from being combined with each other. In addition, at this time, along with the combination of the solder 31 at the position where the groove portion 14 is not formed being thus suppressed, as shown in Figure 16 (B) of FIG. 10, the solder 31 flowing into the groove portion 14 can be suppressed. Of course, in the circuit boards 12a, 12c to 12d other than the circuit board 12b, the combination of the solder 31 and the like can be similarly suppressed by the bonding wires 15a, 15c, 15d. By solidifying the solder 31 thus melted, the semiconductor chips 20, 21 are respectively joined to the circuit boards 12a to 12d. It should be noted that the thickness of the solder 31 at this time is 100 μm or more and 200 μm or less.

[0092] In addition, in order to reliably block the diffusion of the solder 31 with the bonding wires 15a to 15d having a diameter of 125 μm or more and 400 μm or less in the width direction of the groove portion 14, it is preferable that the bonding wires 15a to 15d be positioned more downward than the front surface of the semiconductor chips 20, 21 and more upward than the front surface of the circuit boards 12a to 12d.

[0093] In the circuit boards 12a to 12d of the ceramic circuit substrate 10, the bonding wires 15a to 15d are provided across the groove portion 14 in the length direction of the groove portion 14 in the gap A of the semiconductor chips 20, 21. On the other hand, in the regions adjacent to the semiconductor chips 20, 21 of the circuit boards 12a to 12d, respectively, it is preferable that the outflow regions B (regions of the dotted lines in Figure 15 As described above, if the molten and diffused solder 31 is blocked by the bonding wires 15a to 15d, it diffuses to other regions where the bonding wires 15a to 15d are not provided. If the bonding wires are provided in four directions of the semiconductor chips 20, 21, it is assumed that all of the diffusion destinations of the molten solder 31 are blocked. Therefore, there is a possibility that the molten solder 31 passes over any one of the bonding wires provided in the four directions of the semiconductor chips 20, 21 and causes the joining of the solder 31. Therefore, it is necessary that the outflow regions B where the bonding wires 15a to 15d are not provided be provided in the regions adjacent to the semiconductor chips 20, 21 of the circuit boards 12a to 12d, respectively. Thus, the bonding wires 15a to 15d are members that block the diffusion of the molten solder 31. Therefore, other members such as a lead frame can be used instead of the bonding wires 15a to 15d as long as they are members that can block.

[0094] Here, the case where the bonding wires 15a to 15d are not provided will be described. Figure 17 Figure 17 is a plan view of a main portion of the ceramic circuit substrate of the semiconductor device of the reference example. It should be noted that the semiconductor device of the reference example is configured to be the same as the semiconductor device 50 except for the bonding wires 15a to 15d, the same symbols are attached, and the description thereof will be omitted. In addition, Figure 17 is a view corresponding to the case where the bonding wires 15a to 15d are not provided in Figure 15 According to Figure 17 Since the bonding wires 15a to 15d are not provided, if the solder 31 is molten and diffused, it is assumed that the molten solder 31 diffuses to the regions where the bonding wires 15a to 15d are not provided. Figure 3 ​During the reflow soldering (step S16), the solder 31 diffuses in four directions of the semiconductor chips 20 and 21. Therefore, for example, the semiconductor chip 20 (in the middle) of the circuit board 12a and the semiconductor chip 20 of the circuit board 12c are rotated or misaligned due to the diffused solder 31. A portion of the rotated semiconductor chip 20 is located on the groove 14 through the solder 31. When the solder 31 is filled in the groove 14, pores may be generated in the groove 14. If pores are generated in this way, the heat dissipation of the semiconductor chip 20 is reduced. In addition, on the circuit boards 12a (left and right sides) and 12b, the solder 31 is combined in the gap A. In such a case, poor conductivity will occur.

[0095] The semiconductor device 50 includes a ceramic circuit substrate 10 having circuit boards 12a to 12d with arrangement areas 20a and 21a defined on the front surface thereof, parallel to the gap A, across which a gap A is formed. A groove 14 is formed in the gap A in a direction parallel to the longitudinal direction of the gap A. An insulating plate 11 also includes circuit boards 12a to 12d formed on the front surface thereof. Furthermore, the semiconductor device 50 includes semiconductor chips 20 and 21 disposed in the arrangement areas 20a and 21a via solder 31. Bonding wires 15a to 15d are disposed across the longitudinal direction of the gap A in a plan view. These bonding wires 15a to 15d prevent the diffusion of molten solder 31 during reflow soldering during the manufacturing process of the semiconductor device 50 toward the gap A side of the arrangement areas 20a and 21a. This prevents the diffused solder 31 from joining in the gap A and suppresses positional displacement of the semiconductor chips 20 and 21. This suppresses a decrease in heat dissipation and electrical conductivity failure of the semiconductor chips 20 and 21 , thereby suppressing a decrease in the reliability of the semiconductor device 50 .

[0096] In the first embodiment, the case where two grooves 14 are formed with respect to the gap A between the configuration areas 20a and 21a is described as an example. The number of grooves 14 is not limited to two, but may be one, or three or more depending on the space of the gap A. Figure 18 , the case of forming one groove portion 14 will be described. Figure 18 FIG1 is a top view of the main part of another ceramic circuit substrate of the semiconductor device of the first embodiment. Figure 18 FIG. 5 shows a semiconductor device 50 in which only one groove 14 is provided along the length direction of the gap A in each of the configuration regions 20a and 21a. Figure 18 In FIG, the diffused solder 31 is omitted. Figure 18On the same circuit board 12a, the bonding wire 15a is provided across the three groove portions 14. Also, on the same circuit boards 12b to 12d, the bonding wires 15b to 15d are provided across the groove portions 14, respectively. In this case, the same effect as the semiconductor device 50 is obtained.

[0097] [Second Embodiment]

[0098] In the second embodiment, the other mounting of the bonding wires 15a to 15d of the first embodiment will be described. Figures 19-21 Figure 19 is a plan view of a main portion of a ceramic circuit substrate of a semiconductor device of the second embodiment. Figure 20 is a cross-sectional view of a main portion of a ceramic circuit substrate of a semiconductor device of the second embodiment. Figure 21 is a plan view of another main portion of a ceramic circuit substrate of a semiconductor device of the second embodiment. Note that, Figure 19 is a view of a portion corresponding to the semiconductor device 50 of the first embodiment Figure 15 indicated in FIG. 6. Figure 20 is a cross-sectional view of a single-dot chain line X-X in Figure 19 Figure 21 is a view of a portion corresponding to the semiconductor device 50 of the first embodiment Figure 18 indicated in FIG. 6. Also, in the semiconductor device of the second embodiment, the same symbols are attached to the same constituent elements as those of the semiconductor device 50 of the first embodiment, and the description thereof will be omitted.

[0099] As shown in Figure 19 and Figure 20 , in the semiconductor device of the second embodiment, the bonding wires 15a to 15d across the groove portions 14 are not one but two. Note that, depending on the space of the gap A, three or more can also be possible. Also, for example, as shown in Figure 20 , under plan view, the pair of bonding wires 15b disposed across the groove portion 14 of the circuit board 12b is the same as the boundary between the groove portion 14 and the circuit board 12b, or enters the circuit board 12b side from the boundary. At this time, the width of the entry is less than 50% of the diameter of the bonding wire 15b. By so disposing the plurality of bonding wires 15b across the groove portion 14, the diffusion of the molten solder 31 can be blocked more reliably. Also, as shown in Figure 21 , a plurality of (two in Figure 21 ) bonding wires 15b to 15d can also be used across one groove portion 14. In this case, the bonding wires 15b to 15d cross the groove portion 14 as in Figure 19 and Figure 20 , and the diffusion of the molten solder 31 can be blocked more reliably. Thus, it is not limited to Figure 15 and Figure 18 ​​In the case of Figure 19 In this way, a plurality of bonding wires 15a to 15d are used to span across a plurality of grooves 14. Alternatively, Figure 21 In this manner, the plurality of bonding wires 15 b to 15 d span across the respective grooves 14 .

[0100] [Third embodiment]

[0101] In a third embodiment, using Figure 22 Next, a description will be given of a case where the bonding wires 15 a to 15 d in the semiconductor device 50 according to the first embodiment are provided between the grooves 14 by automatic spot welding. Figure 22 1 is a top view of a main portion of a ceramic circuit substrate of a semiconductor device according to a third embodiment. Figure 22 This corresponds to the semiconductor device 50 of the first embodiment. Figure 15 In addition, Figure 22 In the figure, the diffused solder 31 is omitted. In the semiconductor device of the third embodiment, the same components as those of the semiconductor device 50 of the first embodiment are denoted by the same reference numerals, and their description is omitted.

[0102] like Figure 22 As shown, in the semiconductor device of the third embodiment, bonding wires 15a to 15d are automatically spot-welded between the plurality of grooves 14 on the circuit boards 12a to 12d, so as to be arranged across the grooves 14. By automatically spot-welding the bonding wires 15a to 15d between the plurality of grooves 14 so as to be arranged across the grooves 14, the spread of the molten solder 31 can be more reliably blocked.

Claims

1. A semiconductor device, characterized in that: have: A substrate having a circuit board and an insulating plate with the circuit board formed on a front surface, wherein the circuit board has a first arrangement area and a second arrangement area on the front surface thereof, respectively, with a gap therebetween and parallel to the gap, and a groove is formed in a portion of the gap such that a longitudinal direction thereof extends along the parallel direction; a first semiconductor chip disposed in the first arrangement region via a first bonding material; a second semiconductor chip disposed in the second arrangement region via a second bonding material; as well as The blocking member is a thin wire and is provided in the gap so as to straddle the groove portion in the longitudinal direction in a plan view.

2. The semiconductor device according to claim 1, wherein The length of the blocking member is longer than the length of the groove in the longitudinal direction.

3. The semiconductor device according to claim 2, wherein The blocking member has a width smaller than a width of the groove.

4. The semiconductor device according to any one of claims 1 to 3, wherein The blocking member is made of metal.

5. The semiconductor device according to claim 1, wherein The blocking member is bonded to the circuit board so as to span the longitudinal direction of the groove.

6. The semiconductor device according to claim 1, wherein The blocking member is provided so as to be located below the front surfaces of the first semiconductor chip and the second semiconductor chip and above the front surface of the circuit board.

7. The semiconductor device according to claim 1, wherein A plurality of the blocking members are provided across the groove.

8. The semiconductor device according to claim 1, wherein A plurality of the grooves are formed in a row such that the longitudinal directions are aligned with the parallel direction of the gap.

9. The semiconductor device according to claim 8, wherein The blocking member is provided on the circuit board so as to span the plurality of grooves in the parallel direction.

10. The semiconductor device according to claim 9, wherein The blocking member is bonded between the plurality of grooves and spans across the grooves.

11. The semiconductor device according to claim 1, wherein Outflow regions where the blocking member is not formed are provided in regions adjacent to the first semiconductor chip and the second semiconductor chip of the circuit board, respectively.

12. The semiconductor device according to claim 1, wherein The circuit board is made of copper or a copper alloy.

13. The semiconductor device according to claim 1, wherein The circuit board has a plating film formed on at least the first arrangement area and the second arrangement area.

14. The semiconductor device according to claim 13, wherein The plating film is made of nickel or a nickel alloy.

15. The semiconductor device according to claim 1, wherein The blocking member is formed of a metal having lower solder wettability than the circuit board.

16. The semiconductor device according to claim 12, wherein The blocking member is made of aluminum, nickel, iron, or an alloy including any of these metals.

17. The semiconductor device according to claim 15, wherein The blocking component is made of aluminum or an aluminum alloy.

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