Display device

Abstract

A display device is disclosed, and includes: a display panel including a plurality of pixels and configured to display an image; a drive controller including a timing controller and a driver controlled by the timing controller, the drive controller being configured to supply an electrical signal to the display panel; a memory being configured to receive still image data from the drive controller and store the still image data; and an interface being configured to connect the drive controller to the memory so as to transmit and receive the still image data, wherein the drive controller and the memory are independent separate components.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0114798, filed on September 18, 2019, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] Aspects of some exemplary embodiments of the present disclosure relate to display devices. Background Art

[0004] With the development of the information society, the demand for display devices for displaying images is growing in various forms. Recently, various types of flat panel display devices such as liquid crystal displays (LCDs), plasma display panels (PDPs), organic electroluminescent display devices (OELDs) (or organic light emitting diode (OLED) displays), and the like have been used.

[0005] Images displayed by a display device are largely categorized as either still (e.g., static) images or moving (e.g., video) images. Display devices typically display multiple frames of images per second. When multiple frames have identical image data, the display device displays an image that the viewer perceives as a still image. Conversely, when multiple frames have different image data, the display device displays an image that the viewer perceives as a moving image or video image.

[0006] Typically, even when a display panel displays a still image (not a moving image or video image), a display driver integrated circuit (IC) receives the same image data for each frame from a graphics processing device, which may cause excessive power to be consumed.

[0007] To reduce power consumption, a method can be used to add a frame memory as internal memory to a display driver IC to store image data for still images and supply the stored image data to the display panel while the still image is being displayed. This method can be classified as a panel self-refresh (PSR) method, and since image data does not need to be received from the graphics processing device while the still image is being displayed, the graphics processing device can be disabled, thereby reducing power consumption.

[0008] However, when a display device operates using the PSR method, the area added for the frame memory may increase, especially when the image resolution is high, which may lead to an increase in the size of the display driver IC. Accordingly, space and power consumption may increase.

[0009] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute prior art. Summary of the Invention

[0010] Aspects of some exemplary embodiments of the present disclosure include a display device in which a memory is located outside a display driver IC (eg, external to the display driver IC).

[0011] Features according to the embodiments of the present disclosure are not limited to the above-described features, and however, other features not described herein may be more clearly understood by those skilled in the art through the following description.

[0012] Aspects of some exemplary embodiments of the present disclosure may include a display device. The display device may include: a display portion including a plurality of pixels and configured to display an image; a drive controller including a timing controller and a driver, the driver being controlled by the timing controller and configured to supply an electrical signal to the display portion; a memory portion configured to receive and store still image data from the drive controller; and an interface configured to connect the drive controller to the memory portion for transmitting and receiving still image data. The drive controller and the memory portion may be implemented as separate components.

[0013] According to some example embodiments, the interface may transmit and receive still image data by using a differential signaling method.

[0014] According to some example embodiments, the interface may transmit and receive commands, addresses, and still image data by using a serial method.

[0015] According to some exemplary embodiments, the display part may display a high-quality image having a resolution of full high definition (FHD) or higher.

[0016] According to some example embodiments, the interface may include a first channel and a second channel, commands and addresses may be transmitted through the first channel during a first interval, still image data may be transmitted through the second channel during a second interval, and the second interval may be an interval subsequent to the first interval.

[0017] According to some exemplary embodiments, the number of pins of the interface may be twelve.

[0018] According to some example embodiments, the number of pins configured to transmit still image data may be eight.

[0019] According to some example embodiments, the resource of the memory portion may be 64 MB or less.

[0020] According to some example embodiments, the power consumption of the memory part may be 10 mW or less.

[0021] According to some exemplary embodiments, the memory part may include a frame memory configured to store image data when the image is in a still state and supply the stored image data to the driving controller while the display part displays the still image.

[0022] According to some example embodiments, the memory part may further include a first compensation memory storing stain compensation data and a second compensation memory storing afterimage compensation data including lifespan data of a plurality of pixels.

[0023] According to some example embodiments, the memory part may be outside the drive controller.

[0024] According to some example embodiments, an interface may couple the timing controller to the memory part.

[0025] Aspects of some exemplary embodiments of the present disclosure may include a display device. The display device may include: a display panel defining a display portion including a plurality of pixels configured to display an image, the display panel including a lower substrate including thin film transistors and an upper substrate configured to protect a plurality of components of the lower substrate; a flexible film attached to the lower substrate; a printed circuit board attached to the flexible film; a display driver integrated circuit (IC) configured to apply a data voltage and a scan signal to the display portion; and a first memory located outside the display driver IC and configured to receive data from the display driver IC and store the data.

[0026] According to some exemplary embodiments, the display driver IC may be mounted on the lower substrate in the form of a chip on glass (COG), and the first memory may be mounted on a flexible film or a printed circuit board.

[0027] According to some example embodiments, in a display device, the first memory is replaceable but is not replaced by the display driver IC.

[0028] According to some exemplary embodiments, stain compensation data may be stored in a first memory, and the display driver IC may include a second memory configured to store image data in a static state and supply the stored image data to the display driver IC while the display portion displays the static data.

[0029] According to some example embodiments, the second memory may be an internal memory of the display driver IC.

[0030] According to some example embodiments, the display device may further include a third memory located outside the display driver IC and configured to store lifespan data of the plurality of pixels.

[0031] According to some example embodiments, the first memory and the third memory may be separate components.

[0032] Further details of some exemplary embodiments according to the present disclosure are described and illustrated below in the detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a block diagram illustrating a display device according to some exemplary embodiments of the present disclosure.

[0034] Figure 2 is a perspective view schematically illustrating a display device according to some exemplary embodiments of the present disclosure.

[0035] Figures 3 to 5 It is shown based on Figure 2 1 and 2. Perspective views of further details of some exemplary embodiments of the exemplary features shown in FIG.

[0036] Figure 6 It is shown based on Figure 2 Perspective views of further details of some exemplary embodiments of the exemplary features shown in FIG.

[0037] Figure 7 is a circuit diagram illustrating a driving controller and a memory part of a display device according to some exemplary embodiments of the present disclosure.

[0038] Figure 8 is shown in more detail Figure 7 Circuit diagram of one channel.

[0039] Figure 9 is a timing diagram illustrating a data flow per interval between a driving controller and a memory section of a display device according to some exemplary embodiments of the present disclosure.

[0040] Figure 10 is a block diagram illustrating a display device according to some exemplary embodiments of the present disclosure.

[0041] Figure 11 is a block diagram illustrating a display device according to some exemplary embodiments of the present disclosure. DETAILED DESCRIPTION

[0042] With reference to the exemplary embodiments and drawings described in more detail below, the features and characteristics of some exemplary embodiments of the present disclosure and the methods for implementing them will become more clear. However, the embodiments of the present disclosure can be implemented in various forms and are not limited to the exemplary embodiments to be described below, and these exemplary embodiments are provided to make this disclosure more thorough and more complete, and to more fully convey the scope of the embodiments of the present disclosure to those skilled in the art. The embodiments of the present disclosure should be limited by the scope of the appended claims and their equivalents.

[0043] It will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or can be on the other element or layer with intervening elements or layers intervening therebetween. Throughout the specification, the same reference numerals are used to designate the same components.

[0044] Although the terms "first" and "second" are used to describe various components, it is obvious that those components are not limited by the terms. These terms are only used to distinguish one component from another. Therefore, it is obvious that the first component described below may also be the second component without departing from the technical spirit of the present disclosure. In the present disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0045] Hereinafter, some exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. Throughout the drawings, the same or similar reference numerals are used to designate the same components.

[0046] Figure 1 is a block diagram illustrating a display device 1 according to some exemplary embodiments of the present disclosure.

[0047] Reference Figure 1 The display device 1 includes a driving controller 10 , a display portion (or display panel) 20 , a memory portion (or memory or memory component) 30 and a main processor 40 .

[0048] The present embodiment relates to a display device 1 and is applicable to various types of electronic devices such as an organic electroluminescent display (or organic light emitting diode (OLED) display) device, a liquid crystal display device, a plasma display device, a field emission display device, an electrophoretic device, and the like.

[0049] According to some exemplary embodiments, the drive controller 10, the display portion 20, the memory portion 30, and the main processor 40 may be separate (e.g., independent and distinct) components within the display device 1. Accordingly, depending on the individual specifications required for the display device 1, each of the drive controller 10, the display portion 20, the memory portion 30, and the main processor 40 may be relatively easily replaced (and / or exchanged with other components having different specifications).

[0050] The main processor 40 may control the overall operation of the driving controller 10. For example, the main processor 40 may be implemented as a system on a chip, or may be an application processor (AP) provided in a mobile device.

[0051] The main processor 40 includes a first interface IF1 (e.g., a data communication channel or medium), and can transmit data to and receive data from the drive controller 10 using the first interface IF1, that is, directly transmit data to and receive data from the drive controller 10. According to some exemplary embodiments, the first interface IF1 may be a mobile industry processor interface (MIPI) and may comply with the MIPI Alliance specification for display serial interface and the MIPI Alliance specification for D-PHY. However, this is only an example, and the communication interface between the main processor 40 and the drive controller 10 is not limited thereto. For example, the first interface IF1 may be a high-speed serial interface for supporting nHD (n-high definition) or higher high-quality images.

[0052] The main processor 40 may output a data load command and output image data obtained by compensating the image data. According to some exemplary embodiments, the main processor 40 may supply a data load command for reading (loading) the compensation data from the memory unit 30 to the drive controller 10 via the first interface IF1. The drive controller 10 changes the packet structure of the data load command into a suitable format that the memory unit 30 can interpret and supplies it to the memory unit 30. That is, the main processor 40 may communicate indirectly with the memory unit 30 via the drive controller 10.

[0053] In addition, the main processor 40 can supply image data or compensated image data to the driving controller 10 through the first interface IF1. The driving controller 10 can change the image data or compensated image data into a data signal or data voltage suitable for image display and supply the data signal or data voltage to the display part 20.

[0054] According to some exemplary embodiments, the driving controller 10 may be implemented in the form of a display driver IC.

[0055] The driving controller 10 may include a timing controller 11 and a driver 12 controlled by the timing controller 11 .

[0056] The timing controller 11 may receive the processed image data through the first interface IF1 , thereby generating a data signal for image display, a gate control signal, and a data control signal.

[0057] The driver 12 may generate a data voltage based on a data signal and a data control signal. In addition, the driver 12 may generate a scan signal based on a scan control signal. According to some exemplary embodiments, the driver 12 may generate a data voltage and a scan signal based on a high-voltage analog signal.

[0058] The display portion 20 may be supplied with a data voltage and a scan signal from the driver 12. The display portion 20 may include a plurality of pixels 21 and display an image. Each of the plurality of pixels 21 may emit light based on the data voltage and the scan signal. According to some exemplary embodiments, the display portion 20 may display a high-quality image having a resolution of FHD (e.g., 1920×1080) or higher.

[0059] The display device 1 includes a second interface IF2 configured to connect the memory unit 30 to the driving controller 10, and can directly transmit and receive data to and from the driving controller 10 by using the second interface IF2. According to some exemplary embodiments, the second interface IF2 may be a T2M (Tconnect-to-memory) interface, and will be referred to below. Figure 3 A further description thereof will be given.

[0060] The memory unit 30 may be implemented in the form of an external memory located outside the display driver IC (or external to the display driver IC). For example, the memory unit 30 may be implemented in the form of a volatile memory or a non-volatile memory. Volatile memory may include dynamic random access memory (DRAM), mobile DRAM, static random access memory (SRAM), FRAM, MRAM, and the like, and non-volatile memory may include read-only memory (ROM), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), magnetic random access memory (MRAM), and the like.

[0061] According to some exemplary embodiments, the memory section 30 may include a frame memory 31, a first compensation memory 32 storing stain compensation data, a second compensation memory 33 storing afterimage compensation data including lifespan data of the plurality of pixels 21, and the like. The frame memory 31, the first compensation memory 32, and the second compensation memory 33 in the memory section 30 may be distinguished by blocks.

[0062] The frame memory 31 receives image data from the drive controller 10 and stores it, and the image data is input to the drive controller 10. For example, the frame memory 31 stores image data of a still image and can supply the stored image data to the drive controller 10 while displaying the still image.

[0063] When the display portion 20 displays a moving (e.g., video) image, the frame memory 31 may not be used. When the display portion 20 displays a still (or static) image, input image data is stored in the frame memory 31, and the image data stored in the frame memory 31 may be output to the display portion 20. The frame memory 31 may output the stored image data to the display portion 20 via the driving controller 10.

[0064] According to some exemplary embodiments, the frame memory 31 may include a driving frequency selector configured to select a first frequency when the display unit 20 displays a moving image, and select a second frequency when the display unit 20 displays a still image. When displaying a moving image, input image data is received from the drive controller 10 and output to the display unit 20 at the first frequency. When displaying a still image, stored image data is received from the frame memory 31 and output to the display unit 20 at the second frequency. Here, the second frequency may have a value lower than the first frequency.

[0065] For example, the first frequency may be 60 Hz (Hz), and this 60 Hz indicates that an image is displayed by playing (or displaying) 60 frames per second. In addition, the second frequency may be 10 Hz, and 10 Hz indicates that an image is displayed by playing (or displaying) 10 frames per second. In this case, when a still image is displayed, the power consumed can be reduced to about 1 / 6 of the power consumed when a moving image is displayed. Accordingly, when a still image is displayed, the frequency is set to a certain percentage equal to or less than the frequency set when a moving image is displayed, and thus, the amount of power consumption that can be reduced is greater than the amount of power consumed by increasing the frame memory 31.

[0066] When the frequency is set to low during the display of moving images, viewers may perceive the image motion as unnatural or degraded. However, when displaying still images, frames with the same image data are repeatedly displayed, so even if the frequency is set to low, viewers may not perceive any unnatural or degraded image quality. However, when the frequency is low, flicker may increase. Therefore, it is desirable to reduce the frequency only to a level where flicker is visually undetectable or imperceptible to the user.

[0067] In the first compensation memory 32, stain compensation data may be stored.

[0068] When the pixel 21 includes a light-emitting element such as an organic light-emitting diode, the pixel 21 may degrade over time depending on the driving time and the amount of driving current. When the pixel 21 degrades, the brightness of the pixel 21 may decrease, and thus, the display quality may be reduced or afterimages may appear. Stain compensation data for compensating for the degradation of the pixel 21 may be stored in the first compensation memory 32.

[0069] In the second compensation memory 33 , lifetime data for each pixel 21 may be stored.

[0070] When pixel 21 includes a light-emitting element such as an organic light-emitting diode, because multiple elements emit light independently, each of the multiple elements may use a different frequency, and thus, the lifespans of the multiple elements may differ from one another. Accordingly, even if an element outputs the same data as that output by another adjacent element, it emits light with lower brightness, and the different brightness may cause residual images on the screen. By compensating according to the lifespan of pixel 21, residual images can be slightly reduced. For compensation, the lifespan data of each pixel 21 can be stored in a second compensation memory 33.

[0071] The memory part 30 may have low resources because it is located outside the drive controller 10. For example, the resources of the memory part 30 may be equal to or less than about 64 MB.

[0072] Figure 2 is a perspective view schematically illustrating a display device 1 according to some exemplary embodiments of the present disclosure. Figures 3 to 5 It is shown based on Figure 2 1 and 2. Perspective views of further details of some exemplary embodiments of the exemplary features shown in FIG. Figure 6 It is shown based on Figure 2 Perspective views of further details of some exemplary embodiments of the exemplary features shown in FIG.

[0073] Reference Figure 2 The display device 1 includes a display panel 110, a flexible film 140, and a printed circuit board (PCB) 150, and a display portion 20 configured to display an image is defined in the display panel 110. Hereinafter, for the convenience of explanation, further details of the display device 1 will be described in the context of an organic electroluminescent (or OLED) display device, but as discussed above, the embodiments are not limited thereto. A person having ordinary skill in the art will recognize that various other display devices may be utilized without departing from the spirit and scope of the embodiments according to the present invention.

[0074] The display panel 110 includes a lower substrate 111 and an upper substrate 112. The lower substrate 111 may be a thin film transistor substrate formed of plastic or glass. The lower substrate 111 may include a light emitting element coupled to a thin film transistor.

[0075] The upper substrate 112 may be an encapsulation substrate or a window substrate formed of a plastic film, a glass substrate, or a protective film, and may protect the elements included in the lower substrate 111 from external moisture or air.

[0076] According to some exemplary embodiments, a display area configured to display an image and a non-display area surrounding the display area may be defined by a plurality of pixels 21 in the lower substrate 111. The display area is an area where the pixels 21 are provided to display an image. Scan lines to which scan signals are applied, data lines to which data voltages are applied, and lines to which power signals are applied may be located in the lower substrate 111.

[0077] The flexible film 140 may be provided using a chip-on-film (COF) method or a chip-on-plastic (COP) method. The chip-on-film may include a base film such as polyimide and a plurality of conductive leads provided on the base film. The flexible film 140 may be twisted or bent. The flexible film 140 may be attached to the lower substrate 111 of the display panel 110 and the printed circuit board 150.

[0078] According to some exemplary embodiments, the driver 12 in the form of the display driver IC 130 may be mounted on the flexible film 140. By using an anisotropic conductive film (ACF), the flexible film 140 may be attached to pads provided on the lower substrate 111 using a tape automated bonding (TAB) method. The pads are coupled to the scan lines and the data lines, and thus, the driver 12 may be electrically coupled to the scan lines and the data lines.

[0079] The printed circuit board 150 may be attached to the flexible film 140. The memory portion 30 in the form of an external memory 160 may be mounted on the printed circuit board 150. The printed circuit board 150 may be a flexible printed circuit board (FPCB).

[0080] However, the locations where the drive controller 10 and the memory section 30 are installed are not limited to those shown in the drawings. Figures 3 to 5 As shown in FIG, each of the driving controller 10 and the memory part 30 may be located on any one of the printed circuit board 150 and the flexible film 140 .

[0081] In addition, if Figure 6As shown in FIG, the drive controller 10 may be mounted on the lower substrate 111 by using a chip on glass (COG) method. For example, the lower substrate 111 may be formed of a flexible plastic material. For example, the lower substrate 111 may be formed of any one selected from a group including Kapton, polyethersulfone (PES), polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyacrylate (PAR), fiber reinforced plastic (FRP), and the like.

[0082] Next, the interface between the drive controller 10 and the memory section 30 will be described. This interface corresponds to the second interface ( Figure 1 IF2 in ).

[0083] Figure 7 is a circuit diagram illustrating a driving controller and a memory part of a display device according to some exemplary embodiments of the present disclosure. Figure 8 is shown in more detail Figure 7 Circuit diagram of one channel. Figure 9 is a timing diagram illustrating a data flow per interval between a driving controller and a memory section of a display device according to some exemplary embodiments of the present disclosure.

[0084] Reference Figures 7 to 9 The drive controller 10 and the memory unit 30 may transmit and receive data via the second interface IF2. For example, the timing controller 11 of the drive controller 10 may transmit and receive data to and from a plurality of storage devices in the memory unit 30. According to some exemplary embodiments, the data may include still image data transmitted and received between the frame memory 31 and the timing controller 11. The drive controller 10 and the memory unit 30 may implement a parallel link system in which they are connected via a plurality of channels via the second interface IF2.

[0085] Hereinafter, an example in which the drive controller 10 functions as a transmitter and the memory unit 30 functions as a receiver is described, but the memory unit 30 may function as a transmitter and the drive controller 10 may function as a receiver, or the memory unit 30 and the drive controller 10 may transmit and receive data therebetween. Therefore, the following description may be applied thereto.

[0086] The data transmitted from the drive controller 10 to the memory section 30 through the second interface IF2 may be a differential signal. When the signal transmitted from the drive controller 10 to the memory section 30 is a differential signal, the memory section 30 may receive a pair of transmission signals transmitted from the drive controller 10, sense a voltage difference between the pair of transmission signals, and operate in any one of a differential input mode and a pseudo differential input mode for restoring the received signal.

[0087] The second interface IF2 may include multiple channels CH1 to CHn. At least one of the multiple channels CH1 to CHn may be used to transmit differential signals. The second interface IF2 may include a first pin Pin1 for transmitting data signals and differential signals and a second pin Pin2 for transmitting single-ended signals. Here, the term "pin" refers to a terminal configuring one end of a channel CH. The pin for transmitting signals in differential input mode and pseudo-differential input mode may include two input terminals or output terminals. The pin for transmitting signals using a single-ended signaling method may include one input terminal or output terminal. Figure 8 The input resistance Rn shown in indicates an equivalent resistance of an input terminal to which the first pin Pin1 is coupled.

[0088] According to some exemplary embodiments, the second interface IF2 may include 12 pins. That is, the second interface IF2 may include 12 channels CH1 to CHn. For example, the number of first pins Pin1 may be 8, and the number of second pins Pin2 may be 4. However, the second interface IF2 has no limitation on the number of pins.

[0089] The first pin Pin1 can transmit a signal in either the differential input mode or the pseudo differential input mode as described above. The second pin Pin2 can transmit a signal based on a single-ended signaling method. The plurality of second pins Pin2 may include at least one pin configured to transmit an auxiliary signal AUX from the drive controller 10 to the memory unit 30 and at least one pin configured to transmit a clock CLK.

[0090] The operating mode of the memory unit 30 is set according to the signal transmission mode of the drive controller 10 connected to the memory unit 30. For example, when the drive controller 10 operates in a pseudo-differential signaling mode such as the third-generation double data rate synchronous DRAM (DDR3), the memory unit 30 is set to the differential mode, thereby operating in the pseudo-differential mode. When the drive controller 10 operates in a differential signaling mode (such as low-power double data rate synchronous DRAM (LPDDR), low-voltage differential signaling (LVDS), serial advanced technology attachment (S-ATA), or mobile industry processor interface (MIPI), the memory unit 30 can be set to the differential mode.

[0091] According to some exemplary embodiments, two input voltages can be simultaneously input to the first pin Pin 1. Information can be transmitted based on the voltage difference between the two input voltages. The first pin Pin 1 is used for high-speed differential signaling and has a bandwidth of a single unit set for a pair of transmission lines, and transmission lines can be added in parallel. For example, a single unit can have a bit rate in the range of approximately 0.90 Gbps to approximately 6.00 Gbps. However, the single unit according to embodiments of the present invention is not limited to the above bit rates.

[0092] In any unit interval 1 ui, any one input voltage may have the first logic level LL1 , and the other input voltage may have the second logic level LL2 .

[0093] According to some exemplary embodiments, the first logic level LL1 and the second logic level LL2 may represent different signals, while their amplitudes have the same absolute value but different signs. For example, the first logic level LL1 may correspond to a p-type signal, and the second logic level LL2 may correspond to an n-type signal.

[0094] One driving signal output part TX of the driving controller 10 that outputs a differential signal and one sensing signal input part RX of the memory part 30 that is supplied with a differential signal are coupled to each other through at least two lines.

[0095] One of the plurality of driving signal output parts TX1 to TXn and a corresponding one of the plurality of sensing signal input parts RX1 to RXn coupled to each other by paired lines may have the same input / output structure. Accordingly, bidirectional communication between the driving controller 10 and the memory part 30 is possible.

[0096] According to some exemplary embodiments, when transmitting and receiving differential signals, interference caused by external noise can be reduced, and long-distance signal transmission can be easier than when transmitting and receiving single-ended signals. In addition, the power consumed by the memory unit 30 can be reduced. For example, when transmitting and receiving differential signals, the power consumed by the memory unit 30 can be approximately 1 / 18 of the power consumed when transmitting and receiving single-ended signals, as shown in the following equation (1):

[0097]

[0098] Here, P1 represents the power consumption when transmitting and receiving differential signals, P2 represents the power consumption when transmitting and receiving single-ended signals, and α T Indicates the signal conversion rate (data switching rate), C L Represents line capacitance, V swing denotes the differential signal voltage level, and F denotes the frequency.

[0099] Since the voltage level when differential signals are used for transmission of still image data is about 1 / 6 of that when single-ended signals are used, power consumption can be reduced to about 1 / 18. For example, the power consumed by the second interface IF2 can be reduced to about 10 mW or less.

[0100] According to some exemplary embodiments, the second interface IF2 may transmit commands, addresses, and image data DATA using a serial method. For example, during a first interval T1, commands and addresses may be transmitted via the first channel CH1. After the commands and addresses are transmitted, the image data DATA may be transmitted via the second channel CH2 during a second interval T2. Here, the second interval T2 may be an interval after the first interval T1. Furthermore, the first interval T1 and the second interval T2 may be repeated. For ease of description, the first channel CH1 and the second channel CH2 are exemplary channels of the second interface IF2.

[0101] Meanwhile, when the image data DATA is transmitted using a serial method, the first interval T1 may be used as a delay time based on the second interval T2. However, when the packet size of the image data DATA is equal to or greater than a certain level, the delay time is almost equal to the delay time when the transmission is performed using a parallel method. When transmitting and receiving high-resolution image data DATA (for example, image data with FHD or higher resolution), even when the image data DATA is transmitted using a serial method, the delay time may be almost equal to the delay time when the data is transmitted using a parallel method.

[0102] Next, further details of the display device according to some exemplary embodiments will be described. Figures 1 to 9 The same components are described herein and the same or similar reference numerals will be used accordingly.

[0103] Figure 10 is a block diagram illustrating a display device 2 according to some exemplary embodiments of the present disclosure.

[0104] Reference Figure 10 The display device 2 according to this embodiment is different from the display device 2 according to Figure 1 The display device 1 of the embodiment is different in that the frame memory 31 is included in the drive controller 10_1 , not in the memory section 30_1 .

[0105] The memory part 30_1 may include a first compensation memory 32 and a second compensation memory 33. According to some exemplary embodiments, the frame memory 31 may be implemented in the form of an internal memory of the driving controller 10_1.

[0106] Figure 11 is a block diagram illustrating a display device 3 according to some exemplary embodiments of the present disclosure.

[0107] Reference Figure 11 The display device 3 according to this embodiment is different from the display device 3 according to Figure 10 The display device 2 of the embodiment of FIG. 1 differs in that the first compensation memory 32 and the second compensation memory 33 are implemented as separate components.

[0108] The display device 3 may include a first memory section 30_2 including a first compensation memory 32 and a second memory section 30_3 including a second compensation memory 33 , while the first memory section 30_2 and the second memory section 30_3 are implemented as separate components.

[0109] According to some exemplary embodiments of the present disclosure, since the display device is configured such that the memory is located outside the display driver IC (eg, external relative to the display driver IC), the size of the display driver IC may be reduced, thereby enabling a dead zone to be reduced.

[0110] Furthermore, according to some exemplary embodiments of the present disclosure, since the display device is configured such that the memory is located outside the display driver IC (eg, external with respect to the display driver IC), power consumption can be reduced.

[0111] Features according to exemplary embodiments of the present disclosure are not limited to the foregoing.

[0112] Although exemplary embodiments of the present disclosure have been disclosed, those skilled in the art will appreciate that the present disclosure may be implemented in other specific forms without departing from the technical spirit or scope of the present disclosure as disclosed in the appended claims and their equivalents. Therefore, it should be understood that the above embodiments are merely examples in all aspects and are not restrictive.

Claims

1. A display device comprising: a display panel including a plurality of pixels and configured to display an image; a driving controller comprising a timing controller and a driver controlled by the timing controller, the driving controller being configured to supply an electrical signal to the display panel; a memory configured to receive still image data from the drive controller and store the still image data; as well as an interface configured to couple the drive controller to the memory so as to transmit and receive commands, addresses, and the still image data by using a serial method, Wherein, the drive controller and the memory are independent separate components; in The interface includes a first channel and a second channel, the first channel being configured to transmit the command and the address during a first interval; the second channel being configured to transmit the still image data during a second interval; and The second interval is an interval subsequent to the first interval.

2. The display device according to claim 1, wherein The memory includes a frame memory configured to store image data when the image is in a still state and supply the stored image data to the driving controller while the display panel displays the still image.

3. The display device according to claim 2, wherein: The memory includes: a first compensation memory in which stain compensation data is stored; and A second compensation memory is provided in which afterimage compensation data including lifespan data of the plurality of pixels is stored.

4. The display device according to claim 1, wherein The memory is external to the drive controller.

5. The display device according to claim 1, wherein The interface couples the timing controller to the memory.

6. A display device comprising: A display panel comprising a plurality of pixels configured to display an image, the display panel comprising a lower substrate and an upper substrate configured to protect a plurality of components of the lower substrate, the lower substrate comprising thin film transistors; a flexible membrane attached to the lower substrate; a printed circuit board attached to the flexible membrane; a display driver integrated circuit configured to apply a data voltage and a scan signal to the display panel; as well as a memory external to the display driver integrated circuit and configured to receive data from the display driver integrated circuit and store the data; An interface configured to connect the display driver integrated circuit to the memory so as to transmit and receive commands, addresses and still image data by using a serial method; wherein, The interface includes a first channel and a second channel, the first channel being configured to transmit the command and the address during a first interval; the second channel being configured to transmit the still image data during a second interval; and The second interval is an interval subsequent to the first interval.

7. The display device according to claim 6, wherein: The memory is replaceable, but does not require replacement of the display driver integrated circuit.

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