Semiconductor memory device

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes a substrate having a memory cell region, a peripheral region, and a dam region between the memory cell region and the peripheral region, the memory cell region having a rectangular shape in a plan view, and the memory cell region having a plurality of active regions defined therein; a plurality of bit line structures extending on the substrate in the memory cell region to be parallel to each other in a first horizontal direction, and each including a bit line; a plurality of buried contacts filling lower portions of spaces between the plurality of bit line structures on the substrate; a plurality of bonding pads on the plurality of buried contacts; and a dam structure including a first dam structure and a second dam structure in the dam region, and being located at a same level as the plurality of bonding pads.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0114364, filed on September 17, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The inventive concept relates to a semiconductor memory device, and more specifically, to a semiconductor memory device comprising a dam structure between a memory cell region and a peripheral region. Background Technology

[0003] With the rapid development of the electronics industry and user demands, electronic devices are becoming lighter and more compact. Therefore, semiconductor memory devices used in electronic devices typically require high integration, leading to a reduction in design rules for semiconductor memory device components. Consequently, the pattern density difference between the memory cell region and the peripheral region in a semiconductor memory device has increased, resulting in increased manufacturing complexity and making it difficult to ensure structural reliability. Summary of the Invention

[0004] The inventive concept provides a semiconductor memory device for reducing the difficulty of manufacturing processes and ensuring structural reliability.

[0005] According to one aspect of the inventive concept, a semiconductor memory device is provided, the semiconductor memory device comprising: a substrate having a memory cell region, a peripheral region, and a dam region between the memory cell region and the peripheral region, the memory cell region having a rectangular shape according to a top view, and the memory cell region having a plurality of active regions defined therein; a plurality of bit line structures extending on the substrate in the memory cell region and being parallel to each other in a first horizontal direction, each bit line structure including a bit line; a plurality of buried contacts filling the lower portion of the space between the plurality of bit line structures on the substrate; a plurality of bonding pads located on the plurality of buried contacts; and a dam structure including a first dam structure and a second dam structure in the dam region and located at the same level as the plurality of bonding pads, the first dam structure having a linear shape extending in the first horizontal direction, the second dam structure being separate from the first dam structure and having a linear shape extending in a second horizontal direction perpendicular to the first horizontal direction, a first dam opening being provided between the first dam structure and the second dam structure.

[0006] According to another aspect of the inventive concept, a semiconductor memory device is provided, the semiconductor memory device comprising: a substrate having a memory cell region, a peripheral region, and a dam region between the memory cell region and the peripheral region, the memory cell region having a rectangular shape according to a top view, and the memory cell region having a plurality of active regions defined therein; a plurality of bit line structures extending on the substrate in the memory cell region to be parallel to each other in a first horizontal direction, each bit line structure including a bit line; a plurality of gate line structures located in the peripheral region, each of the plurality of gate line structures having a gate line pattern located at the same level as the bit line; buried contacts filling the lower portion of the space between the plurality of bit line structures on the substrate; bonding pads located on the buried contacts; and a dam structure arranged in the dam region along the edge of the rectangular shape of the memory cell region, wherein the edge of the top surface of the dam structure extends in a straight line, and the edge of the top surface faces the memory cell region.

[0007] According to another aspect of the inventive concept, a semiconductor memory device is provided, the semiconductor memory device comprising: a substrate having a memory cell region, a peripheral region, and a dam region between the memory cell region and the peripheral region, the memory cell region having a rectangular shape according to a top view, and the memory cell region having a plurality of active regions defined therein; a plurality of word lines extending across the plurality of active regions in the memory cell region in a first horizontal direction, the plurality of word lines being parallel to each other; a plurality of bit line structures extending on the substrate in the memory cell region to be parallel to each other in a second horizontal direction perpendicular to the first horizontal direction, each bit line structure including a bit line; a plurality of gate line structures located in the peripheral region, each of the plurality of gate line structures having a gate line pattern located at the same level as the bit line in a vertical direction; and a plurality of buried contacts filling the plurality of bit line junctions on the substrate. The space between the multiple bit line structures includes: a lower portion of the space between the multiple bit line structures; a plurality of bonding pads filling the upper portion of the space between the multiple bit line structures and extending above the multiple bit line structures; and a dam structure including a first dam structure and a second dam structure in a dam area and located at the same level as the multiple bonding pads in the vertical direction. The first dam structure has a linear shape extending in a first horizontal direction, and the second dam structure has a linear shape extending in a second horizontal direction. The first dam structure and the second dam structure are separated from each other at the corner of the rectangular shape of the memory cell area by a first dam opening. Each of the multiple bonding pads has a top surface having a disk shape. Opposite edges of the top surface of the first dam structure extend in a straight line in the first horizontal direction, and opposite edges of the top surface of the second dam structure extend in a straight line in the second horizontal direction. The opposite edges face the memory cell area and the peripheral area, respectively. Attached Figure Description

[0008] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figures 1 to 3 This is a schematic top view used to describe the dam structure of a semiconductor memory device according to an example embodiment;

[0010] Figure 4 This is a schematic planar layout used to describe the main components of a semiconductor memory device according to an example embodiment; and

[0011] Figures 5A to 5D , Figures 6A to 6D , Figures 7A to 7D , Figures 8A to 8D , Figures 9A to 9D and Figures 10A to 10D This is a cross-sectional view of a stage in a method for manufacturing a semiconductor memory device according to an example embodiment. Detailed Implementation

[0012] Figures 1 to 3 This is a schematic top view used to describe the dam structure of a semiconductor memory device according to an example embodiment.

[0013] Reference Figure 1 The semiconductor memory device 10 includes a memory cell region CR, a peripheral region PR, and a dam region DR between the memory cell region CR and the peripheral region PR. In some embodiments, the semiconductor memory device 10 may include a dynamic random access memory (DRAM) device. Figure 1 Multiple bonding pads LP in the memory cell region CR, electrically connected to multiple memory cells (e.g., DRAM cells) of the memory cell array, are shown, as are multiple gate line patterns GLP in the peripheral region PR, representing multiple logic transistors. A dam structure DM can be arranged in the dam region DR between the memory cell region CR and the peripheral region PR. The dam structure DM can reduce the fabrication complexity caused by the difference in pattern density between the memory cell region CR and the peripheral region PR, and can ensure structural reliability.

[0014] The top surface of the bonding pad LP can be at the same level as the top surface of the dam structure DM in the vertical direction (e.g., the Z direction). The top surface of the gate line pattern GLP can be at a lower level in the vertical direction (e.g., the Z direction) than the top surface of the bonding pad LP or the top surface of the dam structure DM.

[0015] According to the top view, the memory cell region CR can have a rectangular shape on the XY plane formed by a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction). The first horizontal direction (e.g., the X direction) and the second horizontal direction (e.g., the Y direction) can be orthogonal. For example, Figure 3The rectangular region within the dam structure DMb can be the memory cell region CR. In some embodiments, the bonding pad LP can be arranged in a zigzag pattern in a first horizontal direction (e.g., the X direction) or a second horizontal direction (Y direction).

[0016] The peripheral region PR can be referred to as the core circuit region and / or peripheral circuit region, and can be arranged around the memory cell region CR. Multiple circuits for driving the semiconductor memory device 10 or for reading and / or writing memory cells of the semiconductor memory device 10 can be arranged in the peripheral region PR. In some embodiments, decoders, sense amplifiers, input / output buffers, etc., can be arranged in the peripheral region PR.

[0017] The dam structure DM can extend in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction). The dam structure DM can be arranged along the edge of the memory cell region CR. According to the top view, the dam structure DM can have a linear shape extending along the sides of the rectangular shape of the memory cell region CR in the XY plane. The dam structure DM can have a linear shape with a longer axis in the first horizontal direction (e.g., the X direction) or the second horizontal direction (e.g., the Y direction). The length of the dam structure DM in the first horizontal direction (e.g., the X direction) or the second horizontal direction (e.g., the Y direction) can be similar to or smaller than the length of the sides of the rectangular shape of the memory cell region CR.

[0018] The top surface of the dam structure DM may have an edge facing the memory cell region CR and an edge facing the peripheral region PR, wherein each of the two edges may have a straight line shape extending in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction). For example, the edge of the top surface of the dam structure DM facing the memory cell region CR may have a straight line shape extending in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction), regardless of the shape of the top surface of the bonding pad LP adjacent to the dam structure DM.

[0019] The bonding pads LP and dam structures DM can be formed using extreme ultraviolet (EUV) lithography. In some embodiments, the bonding pads LP and dam structures DM can be formed without using techniques for increasing pattern density, such as dual patterning (DPT) or quadruple patterning (QPT). The edge of the top surface of each bonding pad LP can have a disk shape that is substantially circular rather than elliptical. The side surface of the dam structure DM facing the bonding pad LP (i.e., the side surface of the dam structure DM facing the memory cell region CR) can extend in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction), unaffected by the zigzag arrangement of the bonding pads LP in the first horizontal direction (e.g., the X direction) or the second horizontal direction (e.g., the Y direction).

[0020] In some embodiments, the semiconductor memory device 10 may include a plurality of dam structures DM. Each of the dam structures DM may have a line shape extending along one of the four sides of a rectangular shape of a memory cell region CR in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction). Dam openings DO may be present between the respective ends of pairs of dam structures DM. Dam openings DO may be located at corners of the rectangular shape of the memory cell region CR. For example, four dam structures DM between the memory cell region CR and the peripheral region PR may each extend along one of the four sides of the rectangular shape of the memory cell region CR and may be separated from each other at each corner of the rectangular shape.

[0021] The respective ends of the paired dam structures DM can be separated from each other by a first width D1. For example, the dam opening DO can have a first width D1. In some embodiments, the dam opening DO can be at each of the four corners of the rectangular shape of the memory cell area CR. In some embodiments, the first width D1 can be from about 1 μm to about 5 μm.

[0022] Reference Figure 2 The semiconductor memory device 10a includes a memory cell region CR and a peripheral region PR. A dam structure DMa may be disposed between the memory cell region CR and the peripheral region PR. The top surface of the bonding pad LP may be at the same level as the top surface of the dam structure DMa in the vertical direction (e.g., the Z direction). The top surface of the gate line pattern GLP may be at a lower level in the vertical direction (e.g., the Z direction) than the top surface of the bonding pad LP or the top surface of the dam structure DMa.

[0023] The dam structure DMa can extend in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction). The dam structure DMa can be arranged along the edge of the memory cell region CR. According to the top view, the dam structure DMa can have a linear shape extending along the sides of the rectangular shape of the memory cell region CR in the XY plane. The dam structure DMa can have a linear shape with a longer axis in the first horizontal direction (e.g., the X direction) or the second horizontal direction (e.g., the Y direction). The length of the dam structure DMa in the first horizontal direction (e.g., the X direction) or the second horizontal direction (e.g., the Y direction) can be smaller than the length of the sides of the rectangular shape of the memory cell region CR.

[0024] The top surface of the dam structure DMa may have an edge facing the memory cell region CR and an opposite edge facing the peripheral region PR, wherein each of the two edges may have a straight line shape extending in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction). For example, the edge of the top surface of the dam structure DMa facing the memory cell region CR may have a straight line shape extending in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction), regardless of the shape of the top surface of the bonding pad LP adjacent to the dam structure DMa.

[0025] The side surface of the dam structure DMa facing the bonding pad LP (i.e., the side surface of the dam structure DMa facing the memory cell region CR) can extend in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction), unaffected by the zigzag arrangement of the bonding pad LP in the first horizontal direction (e.g., the X direction) or the second horizontal direction (e.g., the Y direction).

[0026] In some embodiments, the semiconductor memory device 10a may include a plurality of dam structures DMa. Each of the dam structures DMa may have a line shape extending in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction) along one of the four sides of a rectangular shape of the memory cell region CR. At least two dam structures DMa may extend sequentially along at least one side of the rectangular shape of the memory cell region CR to be separated from each other. A dam opening DOa may exist between the respective ends of a pair of dam structures DMa. The dam opening DOa may include a first dam opening DOC and a second dam opening DOS. The first dam opening DOC may be located at a corner of the rectangular shape of the memory cell region CR. The second dam opening DOS may be located at a portion of a side of the rectangular shape of the memory cell region CR, wherein said portion of the side is away from the corner of the rectangular shape.

[0027] Despite Figure 2Eight dam structures DMa extend sequentially along the four sides of the rectangular shape of the memory cell region CR, and two dam structures DMa are separated from each other at each side of the rectangular shape, but the embodiment is not limited to this. For example, at least three dam structures DMa may extend sequentially along at least one side of the rectangular shape of the memory cell region CR to be separated from each other.

[0028] The first dam opening (DOC) may have a first width (D1). The second dam opening (DOS) may have a second width (D2). In some embodiments, the first width (D1) and the second width (D2) may be approximately 1 μm to approximately 5 μm. The first width (D1) may be equal to the second width (D2), but the embodiments are not limited thereto. In some embodiments, the first width (D1) may be larger than the second width (D2). In some embodiments, the first width (D1) may be smaller than the second width (D2).

[0029] Despite Figure 2 The diagram illustrates that the number of dam structures DMa extending sequentially along each of the two sides of the rectangular shape of the memory cell region CR in a first horizontal direction (e.g., the X direction) to be separated from each other is the same as the number of dam structures DMa extending sequentially along each of the two sides of the rectangular shape of the memory cell region CR in a second horizontal direction (e.g., the Y direction) to be separated from each other (where the number of dam structures DMa is 2), but the embodiment is not limited to this. For example, among the two sides of the rectangular shape of the memory cell region CR extending in the first horizontal direction (e.g., the X direction) and the two sides of the rectangular shape of the memory cell region CR extending in the second horizontal direction (e.g., the Y direction), the number of dam structures DMa extending sequentially along each of the two longer sides of the rectangular shape of the memory cell region CR to be separated from each other can be more than the number of dam structures DMa extending sequentially along each of the two shorter sides of the rectangular shape of the memory cell region CR to be separated from each other.

[0030] Although not shown, at least two dam structures DMa can extend sequentially along each of the two longer sides (e.g., the two sides extending in the second horizontal direction (e.g., the Y direction)) of the rectangular shape of the memory cell region CR to separate themselves from each other, and as shown... Figure 1 The dam structure DM shown can extend along each of the two shorter sides of the rectangular shape of the memory cell region CR (e.g., the two sides extending in the first horizontal direction (e.g., the X direction)).

[0031] Reference Figure 3The semiconductor memory device 10b includes a memory cell region CR and a peripheral region PR. A dam structure DMb may be disposed between the memory cell region CR and the peripheral region PR. The top surface of the bonding pad LP may be at the same level as the top surface of the dam structure DMb in the vertical direction (e.g., the Z direction). The top surface of the gate line pattern GLP may be at a lower level in the vertical direction (e.g., the Z direction) than the top surface of the bonding pad LP or the top surface of the dam structure DMb.

[0032] The dam structure DMb may have a portion extending in a first horizontal direction (e.g., the X direction) and a portion extending in a second horizontal direction (e.g., the Y direction), and may surround the memory cell region CR. According to the top view, the dam structure DMb may have a rectangular shape surrounding the memory cell region CR in the XY plane.

[0033] The top surface of the dam structure DMb may have an edge facing the memory cell region CR and an edge facing the peripheral region PR, wherein each of the two edges may have a straight line shape extending in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction). For example, the edge of the top surface of the dam structure DMb facing the memory cell region CR may have a straight line shape extending in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction), regardless of the shape of the top surface of the bonding pad LP adjacent to the dam structure DMb.

[0034] The side surface of the dam structure DMb facing the bonding pad LP (i.e., the side surface of the dam structure DMb facing the memory cell region CR) can extend in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction), unaffected by the zigzag arrangement of the bonding pad LP in the first horizontal direction (e.g., the X direction) or the second horizontal direction (e.g., the Y direction).

[0035] Figure 4 This is a schematic planar layout used to describe the main components of a semiconductor memory device according to an example embodiment.

[0036] Reference Figure 4 The semiconductor memory device 1 includes a memory cell region CR and a peripheral region PR. A dam structure DM can be arranged between the memory cell region CR and the peripheral region PR.

[0037] Although shown and described Figure 4 The semiconductor memory device 1 has Figure 1 The semiconductor memory device 10 has a dam structure DM, but the embodiments are not limited thereto. The semiconductor memory device 1 may have Figure 2 Dam structure DMa or Figure 3 The dam structure DMb, not Figure 1The dam structure DM in the middle.

[0038] In some embodiments, the semiconductor memory device 1 may include a plurality of dam structures DM. The dam structure DM may include: a first dam structure DMX having an elongated line shape with a side of a rectangular shape extending along the memory cell region CR in a first horizontal direction (e.g., the X direction); and a second dam structure DMY having an elongated line shape with a side of a rectangular shape extending along the memory cell region CR in a second horizontal direction (e.g., the Y direction).

[0039] When semiconductor memory device 1 has Figure 1 When the dam structure DM is in the middle, the first dam structure DMX can be separated from the second dam structure DMY. When the semiconductor memory device 1 has Figure 2 In the case of a dam structure DMa, multiple first dam structures DMX and multiple second dam structures DMY that are separable from each other can exist. When the semiconductor memory device 1 has Figure 3 When the dam structure DMb is in the middle, the first dam structure DMX can be connected to the second dam structure DMY.

[0040] The semiconductor memory device 1 may include a plurality of active regions ACT in the memory cell region CR. In some embodiments, the active regions ACT may be arranged to have a major axis in a diagonal direction in a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction).

[0041] Multiple word lines WL can extend parallel to each other in a first horizontal direction (e.g., the X direction) intersecting with the active region ACT within the memory cell region CR. Multiple bit lines BL can extend parallel to each other above the word lines WL in a second horizontal direction (e.g., the Y direction) intersecting with the first horizontal direction (e.g., the X direction).

[0042] Bit line BL can be connected to the active area ACT via direct contact DC.

[0043] In some embodiments, a plurality of buried contacts BC may be formed between two adjacent bit lines BL. In some embodiments, the buried contacts BC may be arranged in rows in a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction).

[0044] The buried contact element BC may include a plurality of first dummy buried contacts BCX and a plurality of second dummy buried contacts BCY. Here, each of the first dummy buried contacts BCX and the second dummy buried contacts BCY is a structure formed at the same level as each of the buried contacts BC (e.g., the top surface of the dummy buried contact is at the same level as the top surface of the buried contact) and adjacent to the buried contact BC. Within the buried contacts BC, some buried contacts adjacent to the first dam structure DMX may be first dummy buried contacts BCX, and some buried contacts adjacent to the second dam structure DMY may be second dummy buried contacts BCY. The first dummy buried contacts BCX may be arranged in one or at least two rows in a first horizontal direction (e.g., the X direction). The second dummy buried contacts BCY may be arranged in one or at least two rows in a second horizontal direction (e.g., the Y direction).

[0045] Multiple bonding pads LP may be formed above the buried contact BC. The bonding pads LP may at least partially overlap with the buried contact BC. In some embodiments, each of the bonding pads LP may extend over one of the two adjacent bit lines BL.

[0046] In some embodiments, the bonding pad LP may not be formed above the first dummy buried contacts BCX and the second dummy buried contacts BCY within the buried contacts BC. In some embodiments, the bonding pad LP may be formed above some of the first dummy buried contacts BCX and some of the second dummy buried contacts BCY, but not above the other first dummy buried contacts BCX and the other second dummy buried contacts BCY. For example, when the first dummy buried contacts BCX are arranged in at least two rows in a first horizontal direction (e.g., the X direction), the bonding pad LP may not be formed above some of the first dummy buried contacts BCX arranged in a row in the first horizontal direction (e.g., the X direction) adjacent to the first dam structure DMX, but may be formed above the other first dummy buried contacts BCX. Similarly, when the second dummy buried contacts BCY are arranged in at least two rows in the second horizontal direction (e.g., the Y direction), the joint pad LP may not be formed above some of the second dummy buried contacts BCY that are arranged in a row in the second horizontal direction (e.g., the Y direction) adjacent to the second dam structure DMY, but may be formed above other second dummy buried contacts BCY.

[0047] Multiple memory nodes (SNs) can be formed above the bonding pad LP. SNs can also be formed above the bit line BL. Each of the memory nodes (SNs) can be the lower electrode of a capacitor. SNs can be connected to the active region ACT via the bonding pad LP and the buried contact BC.

[0048] A dam structure DM may extend above some buried contacts BC in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction). In some embodiments, a first dam structure DMX may extend above at least some of the first dummy buried contacts BCX in the first horizontal direction (e.g., the X direction). For example, the first dam structure DMX may extend above some of the first dummy buried contacts BCX in the first horizontal direction (e.g., the X direction), wherein the first dummy buried contacts BCX are adjacent to the edge of the memory cell region CR and arranged in a row in the first horizontal direction (e.g., the X direction). In some embodiments, a second dam structure DMY may extend above at least some of the second dummy buried contacts BCY in the second horizontal direction (e.g., the Y direction). For example, the second dam structure DMY may extend above some of the second dummy buried contacts BCY in the second horizontal direction (e.g., the Y direction), wherein the second dummy buried contacts BCY are adjacent to the edge of the memory cell region CR and arranged in a row in the second horizontal direction (e.g., the Y direction).

[0049] The gate line pattern (GLP) can be arranged in the peripheral region (PR). For ease of illustration, other components besides the gate line pattern (GLP) are omitted from the peripheral region (PR). The gate line pattern (GLP) can extend away from the memory cell region (CR), but the embodiment is not limited thereto. Figure 4 The shape of the gate line pattern (GLP) in the example is merely an example, and the gate line pattern (GLP) can have various widths or curves, or can extend in various horizontal directions with variable widths.

[0050] The gate line pattern (GLP) may be formed at the same level as the bit line (BL). In some embodiments, the gate line pattern (GLP) and the bit line (BL) may comprise the same material or at least partially comprise the same material. For example, the process for forming all or part of the gate line pattern (GLP) may be the same as the process for forming the bit line (BL).

[0051] Figures 5A to 5D , Figures 6A to 6D , Figures 7A to 7D , Figures 8A to 8D , Figures 9A to 9D and Figures 10A to 10D This is a cross-sectional view of a stage in a method of manufacturing a semiconductor memory device according to an example embodiment. For example, Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A It is along Figure 4 A sectional view of the stage intercepted by line A-A' in the middle; Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B and Figure 10B It is along Figure 4 A sectional view of the stage intercepted by line B-B' in the middle; Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C and Figure 10C It is along Figure 4 A sectional view of the stage cut by line C-C'; and Figure 5D , Figure 6D , Figure 7D , Figure 8D , Figure 9D and Figure 10D It is along Figure 4 The sectional view of the stage cut by line D-D' in the middle.

[0052] Reference Figures 5A to 5D A substrate 110 is manufactured, comprising a memory cell region CR and a peripheral region PR. The substrate 110 may also include a dam region DR between the memory cell region CR and the peripheral region PR.

[0053] Although the memory cell region CR and the peripheral region PR are shown to be separated, and the area between the memory cell region CR and the peripheral region PR is represented as the dam region DR, the embodiments are not limited thereto. For example, the substrate 110 may include the memory cell region CR and the peripheral region PR that are demarcated and in contact with each other, and the dam region DR may be one of them. Figure 4 The dam structure DM is located along the boundary between the memory cell area CR and the peripheral area PR.

[0054] For example, substrate 110 may include silicon (Si) (e.g., crystalline Si, polycrystalline Si, or amorphous Si). Optionally, substrate 110 may include an elemental semiconductor (e.g., germanium (Ge)) or at least one compound semiconductor selected from silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Substrate 110 may have a silicon-on-insulator (SOI) structure. For example, substrate 110 may include a buried oxide (BOX) layer. Substrate 110 may include conductive regions (e.g., impurity-doped wells or impurity-doped structures).

[0055] Region isolation trenches 115T can be formed in the substrate 110, and region isolation films 115 can be formed to fill the region isolation trenches 115T. The region isolation films 115 can be arranged between the memory cell region CR and the peripheral region PR. The logic active region 117 can be defined in the peripheral region PR by the region isolation films 115.

[0056] Device isolation trenches 116T can be formed in the memory cell region CR of substrate 110, and a device isolation film 116 filling the device isolation trenches 116T can be formed. Multiple active regions 118 can be defined in the memory cell region CR of substrate 110 by means of the device isolation film 116. Figure 4 The active region ACT is the same as that in the active region 118, which can have a relatively long island shape with a short axis and a long axis.

[0057] In some embodiments, a region isolation film 115 and a device isolation film 116 can be formed simultaneously. For example, a region isolation trench 115T and a device isolation trench 116T can be formed simultaneously by etching in a substrate 110, and then a region isolation film 115 filling the region isolation trench 115T and a device isolation film 116 filling the device isolation trench 116T can be formed simultaneously by vapor deposition. In some embodiments, a region isolation trench 115T and a device isolation trench 116T can be formed separately by a separate etching process, and then a region isolation film 115 and a device isolation film 116 can be formed simultaneously by vapor deposition. In some embodiments, a region isolation trench 115T and a device isolation trench 116T can be formed separately by a separate etching process, and a region isolation film 115 and a device isolation film 116 can be formed separately by a separate vapor deposition process.

[0058] The area isolation film 115 and the device isolation film 116 may include a material comprising at least one selected from, for example, silicon oxide film, silicon nitride film and silicon oxynitride film.

[0059] In some embodiments, a logic device isolation film defining a logic active region 117 may be formed in the peripheral region PR of the substrate 110. In some embodiments, the logic device isolation film may be formed together with the region isolation film 115 and / or the device isolation film 116.

[0060] Multiple word line trenches 120T can be formed in the memory cell region CR of the substrate 110. The word line trenches 120T can have a line shape, extending parallel to each other in a first horizontal direction (e.g., the X direction) and arranged at equal intervals in a second horizontal direction (e.g., the Y direction) and spanning the active region 118. As shown in the cross-section taken along line B-B', steps can be present on the bottom surface of the word line trenches 120T.

[0061] After cleaning the resulting structure including the word line trench 120T, multiple gate dielectric films 122, multiple word lines 120, and multiple buried insulating films 124 can be sequentially formed in the word line trench 120T. The word lines 120 can be formed... Figure 4 The character line WL in the text.

[0062] The word lines 120 can fill the lower part of the interior of the word line groove 120T, and the buried insulating film 124 can cover the word lines 120 and fill the upper part of the interior of the word line groove 120T. Therefore, the word lines 120 can have a line shape extending parallel to each other in a first horizontal direction (e.g., the X direction) and arranged at equal intervals in a second horizontal direction (e.g., the Y direction) and spanning the active region 118. Similarly, the buried insulating film 124 can have a line shape extending parallel to each other in a first horizontal direction (e.g., the X direction) and arranged at equal intervals in a second horizontal direction (e.g., the Y direction) and spanning the active region 118.

[0063] For example, word line 120 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or combinations thereof.

[0064] The gate dielectric film 122 may include at least one selected from silicon oxide film, silicon nitride film, silicon oxynitride film, oxide / nitride / oxide (ONO) film, and high-k dielectric film having a higher dielectric constant than silicon oxide film. For example, the gate dielectric film 122 may have a dielectric constant of about 10 to about 25.

[0065] The top surface of the buried insulating film 124 may be substantially at the same level as the top surface of the substrate 110. The buried insulating film 124 may include a material film selected from silicon oxide films, silicon nitride films, silicon oxynitride films, and combinations thereof.

[0066] The top surface of word line 120 may be located at a lower level than the top surface of logic active region 117 in substrate 110. The bottom surface of word line 120 may have an uneven shape, and transistors with saddle fin structures (e.g., saddle fin field-effect transistors (FinFETs)) may be formed in active region 118.

[0067] In this specification, the term "horizontal" refers to the height of the substrate 110 from its main surface or top surface in a vertical direction (e.g., the Z direction). For example, "at the same level" or "at a certain level" means "at the same height from the main surface of the substrate 110 in a vertical direction (e.g., the Z direction)" or "at a certain location," and "at a low / high level" means "at a low / high location relative to the main surface of the substrate 110 in a vertical direction (e.g., the Z direction)." For example, the main surface or top surface of the substrate 110 may be located between the substrate 110 and the logic active region 117 or between the substrate 110 and the active region 118.

[0068] In some embodiments, before or after the word lines 120 are formed, impurity ions may be implanted into active regions 118 of the substrate 110 located on both sides of each of the word lines 120, thereby forming source and drain regions in the active regions 118.

[0069] Reference Figures 6A to 6D An insulating film pattern is formed to cover a substrate 110 having a region isolation film 115, a device isolation film 116, a logic active region 117, an active region 118, and a buried insulating film 124. For example, the insulating film pattern may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a metal dielectric film, or a combination thereof.

[0070] In some embodiments, an insulating film pattern can be formed by stacking a plurality of insulating films including a first insulating film pattern 112 and a second insulating film pattern 114. For example, the second insulating film pattern 114 may have a higher dielectric constant than the first insulating film pattern 112. In some embodiments, the first insulating film pattern 112 may include a silicon oxide film, and the second insulating film pattern 114 may include a silicon oxynitride film. In some embodiments, the first insulating film pattern 112 may include a non-metallic dielectric film, and the second insulating film pattern 114 may include a metallic dielectric film.

[0071] A direct contact hole 134H can be formed in the memory cell region CR to penetrate the first insulating film pattern 112 and the second insulating film pattern 114. The direct contact hole 134H can expose the source region in the active region 118. In some embodiments, the direct contact hole 134H can extend inside the active region 118 (i.e., the source region).

[0072] The first insulating film pattern 112 and the second insulating film pattern 114 covering the peripheral area PR can be removed at least partially, so that the logic active area 117 can be exposed without being covered by the first insulating film pattern 112 and the second insulating film pattern 114.

[0073] Reference Figures 7A to 7D A direct contact conductive layer is formed to fill the direct contact hole 134H and cover the first insulating film pattern 112 and the second insulating film pattern 114. The direct contact conductive layer may include, for example, an epitaxial silicon layer or doped polysilicon.

[0074] Subsequently, a metal conductive layer and an insulating capping layer are sequentially formed for forming the bit line structure 140 and the gate line structure 140P to cover the first insulating film pattern 112 and the second insulating film pattern 114, as well as the direct contact conductive layer. The metal conductive layer may have a stacked structure with the first metal conductive layer and the second metal conductive layer stacked on top of each other. The metal conductive layer may have a conductive layer stacked structure with a dual-layer structure, but this is only an example, and the embodiments are not limited thereto. For example, the metal conductive layer may include a single layer or a stacked structure containing at least three layers.

[0075] In some embodiments, the first metal conductive layer may include TiN or Ti-Si-N (TSN), and the second metal conductive layer may include tungsten (W) or W and tungsten silicide (WSi). x In some embodiments, the first metallic conductive layer may serve as a diffusion barrier layer. In some embodiments, the insulating capping layer may include a silicon nitride film.

[0076] A first conductive metal layer, a second conductive metal layer, and an insulating capping layer are etched to form multiple bit lines 147 with a line shape, including a first conductive metal pattern 145 and a second conductive metal pattern 146, in the memory cell region CR. Multiple gate lines 147P, including the first conductive metal pattern 145 and the second conductive metal pattern 146, are formed in the peripheral region PR. Multiple insulating capping lines 148 are formed in both the memory cell region CR and the peripheral region PR. The bit lines 147 in the memory cell region CR, including the first conductive metal pattern 145 and the second conductive metal pattern 146, can form multiple memory cells of a memory cell array. The gate lines 147P in the peripheral region PR, including the first conductive metal pattern 145 and the second conductive metal pattern 146, can form multiple logic transistors.

[0077] The bit line structure 140 in the memory cell region CR may include a bit line 147 and an insulating cover line 148 covering the bit line 147. The gate line structure 140P in the peripheral region PR may include a gate line 147P and an insulating cover line 148 covering the gate line 147P. A gate insulating film pattern 142 may be arranged between the gate line 147P and the logic active region 117.

[0078] In some embodiments, the bit line structure 140 may further include a conductive semiconductor pattern 132 between the insulating film pattern including the first insulating film pattern 112 and the second insulating film pattern 114 and the first metal conductive pattern 145, and the gate line structure 140P may further include a conductive semiconductor pattern 132 between the gate insulating film pattern 142 and the first metal conductive pattern 145. The conductive semiconductor pattern 132 may include doped polysilicon. In some embodiments, the conductive semiconductor pattern 132 may be omitted.

[0079] Multiple bit line structures 140, including bit line 147 and insulating cover line 148, may extend parallel to each other in a second horizontal direction (e.g., the Y direction) parallel to the main surface of the substrate 110.

[0080] Similar to bit line structure 140, a dummy bit line structure 140D, including bit line 147 and insulating cover line 148, may extend along the dam area DR in a second horizontal direction (e.g., the Y direction). In a first horizontal direction (e.g., the X direction), the width of the dummy bit line structure 140D may be larger than the width of each of the bit line structures 140, but embodiments are not limited thereto. In some embodiments, in the first horizontal direction (e.g., the X direction), the width of the dummy bit line structure 140D may be equal to the width of each bit line structure 140. Here, the dummy bit line structure 140D is a structure formed at the same level as the bit line structure 140 (e.g., the level of the top surface of the dummy bit line structure 140D is the same as the level of the top surface of each of the bit line structures 140) and adjacent to the bit line structure 140.

[0081] The dummy bit line structure 140D may include the same layers as those forming such a bit line structure 140 (e.g., bit line 147 and insulating cover line 148). In some examples, the dummy bit line structure 140D may be formed simultaneously with the bit line structure 140 using the same process as forming the metal conductive layer and insulating cover layer constituting the bit line structure 140. The dummy bit line structure 140D in the semiconductor memory device 1 is not used as an external terminal for transmitting signals to an external device (e.g., a memory controller (not shown)).

[0082] The dam area DR (i.e., extending only along the second horizontal direction (e.g., the Y direction) can be used only. Figure 4 A virtual datum structure 140D is formed in the dam area DR (where the second dam structure DMY is arranged), instead of extending along the first horizontal direction (e.g., the X direction) of the dam area DR (i.e., Figure 4 The dam area DR, which contains the first dam structure DMX, forms a virtual position line structure 140D.

[0083] Bit line 147 can be formed Figure 4 The bit line BL is shown in the diagram. Gate line 147P can be formed. Figure 4 The gate line pattern GLP is shown in the figure.

[0084] During the etching process for forming bit line 147, portions of the direct contact conductive layer that are not vertically superimposed on bit line 147 can also be etched, thereby forming multiple direct contact conductive patterns 134. At this time, the insulating film patterns (including the first insulating film pattern 112 and the second insulating film pattern 114) can be used as an etching stop layer during the etching process for forming bit line 147 and direct contact conductive patterns 134. The direct contact conductive patterns 134 can be formed... Figure 4 The DC direct contact shown is used. Bit line 147 can be electrically connected to multiple active regions 118 via direct contact conductive pattern 134.

[0085] In some embodiments, a conductive semiconductor pattern 132 may also be formed during the process of removing portions of the direct contact conductive layer to form the direct contact conductive pattern 134. For example, the conductive semiconductor pattern 132 may be a portion of the direct contact conductive layer that is vertically stacked with the bit line 147 but not vertically stacked with the direct contact hole 134H and located on an insulating film pattern (including the first insulating film pattern 112 and the second insulating film pattern 114), and the direct contact conductive pattern 134 may be a portion of the direct contact conductive layer that is vertically stacked with the direct contact hole 134H and contacts the active region 118.

[0086] The insulating spacer structure 150 may cover each of the opposing sidewalls of the bit line structure 140. The insulating spacer structure 150 may include a first insulating spacer 152, a second insulating spacer 154, and a third insulating spacer 156. The second insulating spacer 154 may include a material having a lower dielectric constant than the first insulating spacer 152 and the third insulating spacer 156. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may include a nitride film, and the second insulating spacer 154 may include an oxide film. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may include a nitride film, and the second insulating spacer 154 may include a material having etch selectivity relative to the first insulating spacer 152 and the third insulating spacer 156. For example, when the first insulating spacer 152 and the third insulating spacer 156 include a nitride film, the second insulating spacer 154 may include an oxide film and may be removed during a subsequent process to become an air spacer.

[0087] The sidewalls of the gate line structure 140P can be covered by a gate insulating spacer 150P. The gate insulating spacer 150P may include, for example, a nitride film. In some embodiments, the gate insulating spacer 150P may include a single layer, but is not limited thereto. The gate insulating spacer 150P may include a stacked structure comprising at least two layers.

[0088] A buried contact hole 170H can be formed between two adjacent bit lines 147. The internal space of the buried contact hole 170H can be defined by an insulating spacer structure 150 that covers the respective sidewalls of the two adjacent bit lines 147 and an active region 118 between the two adjacent bit lines 147.

[0089] Multiple buried contact holes 170H can be formed by using an insulating cover line 148 and multiple insulating spacer structures 150, each covering one of the opposing sidewalls of each bit line structure 140, as an etching mask to partially remove the insulating film pattern (including the first insulating film pattern 112 and the second insulating film pattern 114) and the active region 118 in the memory cell region CR. The buried contact holes 170H can also be formed by using an insulating cover line 148 and insulating spacer structures 150, each covering one of the opposing sidewalls of each bit line structure 140, as an etching mask to perform an anisotropic etching process that partially removes the insulating film pattern (including the first insulating film pattern 112 and the second insulating film pattern 114) and the active region 118, followed by an isotropic etching process that further removes a portion of each active region 118, thereby extending the space defined by the active region 118 of each buried contact hole 170H.

[0090] In some embodiments, such as Figure 7C As shown, the insulating film pattern (including the first insulating film pattern 112 and the second insulating film pattern 114) and a portion of the active region 118 may be retained in a portion of the memory cell region CR without being removed, wherein said portion of the memory cell region CR is adjacent to the dam region DR (more specifically, adjacent to the area where the dam region DR is located). Figure 4 The first dam structure DMX in the dam area DR is adjacent. For example, the covering and arrangement of the insulating film patterns (including the first insulating film pattern 112 and the second insulating film pattern 114) can be retained instead of removed. Figure 4 The active region 118 is a portion of the dam area DR between two adjacent buried insulating films 124 in the first dam structure DMX. For example, a mask layer can be formed to cover the peripheral region PR, the dam area DR, and a portion of the memory cell region CR adjacent to the dam area DR. The mask layer, insulating cover line 148, and insulating spacer structure 150 can then be used as an etching mask to partially remove the insulating film pattern (including the first insulating film pattern 112 and the second insulating film pattern 114) and the active region 118.

[0091] Reference Figures 8A to 8D A plurality of buried contacts 170 and a plurality of insulating fences 180 are formed in the space between insulating spacer structures 150 that respectively cover the sidewalls of the bit line structure 140 in the memory cell region CR. The plurality of buried contacts 170 and the plurality of insulating fences 180 may be arranged alternately in a second horizontal direction (e.g., the Y direction) between two adjacent insulating spacer structures 150 that respectively cover the sidewalls of the bit line structure 140.

[0092] For example, buried contact 170 may include polysilicon. For example, insulating fence 180 may include a nitride film.

[0093] In some embodiments, a plurality of buried contacts 170 may be arranged in a row in a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction). Each of the buried contacts 170 may extend from the active region 118 in a vertical direction (e.g., the Z direction) perpendicular to the substrate 110. The buried contacts 170 may be formed Figure 4 The buried contact BC is shown in the figure.

[0094] The buried contact 170 can be arranged in a space defined by an insulating fence 180 and an insulating spacer structure 150 that respectively covers the sidewalls of the position line structure 140.

[0095] The buried contact 170 can be formed by the following process: forming a preliminary buried contact material layer that fills the buried contact hole 170H, and removing the top portion of the preliminary buried contact material layer. For example, the preliminary buried contact material layer may include polysilicon.

[0096] The top surface of the buried contact 170 may be located at a lower level than the top surface of the insulating cover line 148. The top surface of the insulating fence 180 may be located at the same level as the top surface of the insulating cover line 148 in the vertical direction (e.g., the Z direction). Therefore, the top surface of the buried contact 170 may be located at a lower level than the top surface of the insulating fence 180.

[0097] The buried contact 170 may include a plurality of first dummy buried contacts 170X and a plurality of second dummy buried contacts 170Y. The first dummy buried contacts 170X can form... Figure 4 The first dummy buried contact BCX and the second dummy buried contact 170Y can form Figure 4 The second dummy buried contact BCY in the semiconductor memory device 1. The first dummy buried contact 170X and the second dummy buried contact 170Y include the same conductive layer (e.g., polysilicon) as the conductive layer forming such buried contact 170. For example, buried contact 170 and the first dummy buried contact 170X and the second dummy buried contact 170Y can be formed simultaneously using the same process as the process of depositing and patterning the conductive layer forming buried contact 170. Each of the first dummy buried contact 170X and the second dummy buried contact 170Y in the semiconductor memory device 1 is not used as an external terminal for transmitting signals to an external device (e.g., a memory controller (not shown)).

[0098] In some embodiments, a first dummy buried contact 170X may be formed on an insulating film pattern (including a first insulating film pattern 112 and a second insulating film pattern 114). For example, the first dummy buried contact 170X may be separated from the active region 118 using the insulating film pattern (including the first insulating film pattern 112 and the second insulating film pattern 114) between the first dummy buried contact 170X and the active region 118. The first dummy buried contact 170X may be electrically insulated (or separated) from the active region 118 by the insulating film pattern (including the first insulating film pattern 112 and the second insulating film pattern 114). In some embodiments, a second dummy buried contact 170Y may be formed on the active region 118. For example, the second dummy buried contact 170Y may contact the active region 118. The second dummy buried contact 170Y may be electrically connected to the active region 118.

[0099] A plurality of mating pad holes 190H can be defined by an insulating spacer structure 150 and an insulating fence 180. The buried contact 170 can be exposed at the bottom of the mating pad holes 190H.

[0100] In some embodiments, after the insulating fence 180 is formed, a preliminary buried contact material layer may be formed. In some embodiments, after the preliminary buried contact material layer is formed, the insulating fence 180 may be formed.

[0101] The buried contact 170 can fill the lower portion of the space between the insulating spacer structures 150 that respectively cover the sidewalls of the bit line structure 140. In some embodiments, the top surface of the buried contact 170 may be located at a lower level than the top surface of the bit line 147, but the embodiments are not limited thereto.

[0102] During the process of forming the buried contact 170 and the insulating fence 180, the first filler insulating layer 175 may cover the peripheral region PR. In the process of forming the buried contact 170 and the insulating fence 180, the upper portion of the first filler insulating layer 175 may be removed such that the top surface of the first filler insulating layer 175 is at the same level as the top surface of the gate line structure 140P. The first filler insulating layer 175 may include, for example, an oxide film.

[0103] In the process of forming the buried contact 170 and / or the insulating fence 180, the upper portion of the insulating cover line 148 included in each of the bit line structure 140, the dummy bit line structure 140D and the gate line structure 140P, as well as the upper portion of each insulating spacer structure 150, can be removed, thereby lowering the top surface of the bit line structure 140, the dummy bit line structure 140D and the gate line structure 140P.

[0104] Reference Figures 9A to 9DMultiple bonding pads 190 are formed that fill multiple bonding pad holes 190H and extend above the bit line structure 140, and a dam structure 190D that fills multiple bonding pad holes 190H and extends above the dummy bit line structure 140D can be formed.

[0105] Bonding pads 190 may be arranged on buried contacts 170 within the memory cell region CR and may extend over bit line 147. Bonding pads 190 may be individually arranged on and electrically connected to buried contacts 170. Each of the bonding pads 190 may be connected to the active region 118 via the buried contact 170. Bonding pads 190 may be formed... Figure 4 The bonding pad LP is shown in the figure. The top surface of each of the bonding pads 190 may have a disk shape that is substantially circular rather than elliptical.

[0106] An embedded contact 170 may be located between two adjacent bit line structures 140, and a bonding pad 190 may extend from between the two adjacent bit line structures 140 to above one of the two adjacent bit line structures 140, wherein the two adjacent bit line structures 140 have an embedded contact 170 between them. In other words, the bonding pad 190 may extend from between the two adjacent bit line structures 140 to above one of the two adjacent bit line structures 140, and is thereby electrically connected to the embedded contact 170 and vertically stacked with one bit line structure 140, wherein the two adjacent bit line structures 140 have an embedded contact 170 between them.

[0107] The bonding pad 190 can be formed by the following process: forming a bonding pad material layer that fills the bonding pad hole 190H and covers the insulating cover line 148 and the insulating fence 180, and then forming a groove 190R to separate the bonding pad material layer into multiple portions corresponding to the buried contact 170, respectively. The groove 190R between two adjacent bonding pads 190 can be used to separate two adjacent bonding pads 190 from each other. The groove 190R can expose the top end of the insulating spacer structure 150, the top end of the insulating cover line 148, and the top end of the insulating fence 180. In some embodiments, during the process of forming the groove 190R, the upper portion of the insulating spacer structure 150, the upper portion of the insulating cover line 148, and the upper portion of the insulating fence 180 can be removed.

[0108] In some embodiments, a metal silicide film may be formed on the buried contact 170 prior to forming the bonding pad 190. The metal silicide film may be disposed between the buried contact 170 and the bonding pad 190. The metal silicide film may include cobalt silicide (CoSi). x Nickel silicide (NiSi) x ) or manganese silicide (MnSi) x (but not limited to this).

[0109] In some embodiments, bonding pad 190 may include a conductive barrier film and a conductive pad material layer on the conductive barrier film. For example, the conductive barrier film may include a metal, a conductive metal nitride, or a combination thereof. In some embodiments, the conductive barrier film may include a Ti / TiN stacked structure. For example, the conductive pad material layer may include a metal. In some embodiments, the conductive pad material layer may include tungsten (W).

[0110] The dam structure 190D can be formed within the dam zone DR. The dam structure 190D can be formed by separating the portion of the bonding pad material layer that will be located within the dam zone DR. According to the top view, the dam structure 190D can have… Figures 1 to 3 The shape of the dam structure DM in the memory cell area. For example, the dam structure 190D can have a line shape extending along the side of a rectangular shape of the memory cell area CR.

[0111] The dam structure 190D may include a first dam structure DMX extending in a longer linear shape in a first horizontal direction (e.g., the X direction) and a second dam structure DMY extending in a longer linear shape in a second horizontal direction (e.g., the Y direction).

[0112] The bonding pad 190 and the dam structure 190D are formed of a bonding pad material layer and can therefore be located at the same level. The top surface of the dam structure 190D can be located at the same level as the top surface of the bonding pad 190, and the bottom surface of the dam structure 190D can be located at the same level as the bottom surface of the bonding pad 190.

[0113] The bonding pad 190 and the dam structure 190D can be formed simultaneously using the same process as that used to form the bonding pad 190 by filling the bonding pad hole 190H. The dam structure 190D in the semiconductor memory device 1 is not used as an external terminal for transmitting signals to an external device (e.g., a memory controller (not shown)).

[0114] The edge of the top surface of the dam structure 190D facing the memory cell region CR can have a straight line shape extending in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction), unaffected by the shape of the top surface of the bonding pad 190 adjacent to the dam structure 190D. Because there is a relatively wide gap between the dam structure 190D and the bonding pad 190, photoresist residues, etching byproducts, etc., can be easily removed.

[0115] In some embodiments, the dam structure 190D may have a linear shape extending along one of the four sides of a rectangle along the memory cell region CR in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction), such that the dam structure 190D has Figure 1 dam opening DO or Figure 2 The dam opening DOa in the middle. Photoresist residues, etching byproducts, etc., that may arise during the process of separating the bonding pad material layer into multiple parts to form the bonding pad 190 can be addressed through... Figure 1 dam opening DO or Figure 2 The dam opening DOa is used to discharge water.

[0116] In some embodiments, the dam structure 190D may extend in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction) and may have a rectangular shape surrounding the memory cell region CR.

[0117] In some embodiments, the dam structure 190D can be formed together with the bonding pad 190 by a process of forming a groove 190R by partially removing a layer of bonding pad material. For example, the groove 190R between the dam structure 190D and the bonding pad 190 can be used to separate the dam structure 190D from the bonding pad 190.

[0118] To form the groove 190R, a bonding pad mask pattern corresponding to the bonding pad 190 and a dam mask pattern corresponding to the dam structure 190D are formed on the bonding pad material layer. The bonding pad mask pattern and the dam mask pattern can be formed by, for example, EUV lithography. In some embodiments, the bonding pad mask pattern and the dam mask pattern can be formed without using techniques for increasing pattern density (such as DPT or QPT).

[0119] In some embodiments, the bonding pad mask pattern and the dam mask pattern can be formed simultaneously by EUV lithography. In some embodiments, the bonding pad mask pattern and the dam mask pattern can be formed separately by separate EUV lithography processes.

[0120] Subsequently, the bonding pad mask pattern and the dam mask pattern can be used as etching masks to partially remove the bonding pad material layer, thereby forming the bonding pad 190 and the dam structure 190D which is separated from the bonding pad 190 by the groove 190R between the dam structure 190D and the bonding pad 190.

[0121] Reference Figures 10A to 10DA semiconductor memory device 1 comprising multiple capacitor structures 200 can be formed by sequentially forming multiple lower electrodes 210, capacitor dielectric films 220, and upper electrodes 230 on bonding pads 190 in a memory cell region CR. The lower electrodes 210 can be electrically connected to the bonding pads 190 respectively. The capacitor dielectric films 220 can conformally cover the lower electrodes 210. The upper electrodes 230 can cover the capacitor dielectric films 220. The upper electrodes 230 can face the lower electrodes 210, and the capacitor dielectric films 220 are present between the upper electrodes 230 and the lower electrodes 210. Each of the capacitor dielectric films 220 and the upper electrodes 230 can be integrally formed to cover the lower electrodes 210 in a certain region (e.g., the memory cell region CR). The lower electrodes 210 can be formed into... Figure 4 The storage node SN is shown in the image.

[0122] Each of the lower electrodes 210 may have, but is not limited to, a solid cylindrical shape with a circular horizontal cross-section. In some embodiments, each of the lower electrodes 210 may have a cylindrical shape with a closed bottom. In some embodiments, the lower electrodes 210 may be arranged in a zigzag pattern in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction). In some embodiments, the lower electrodes 210 may be arranged in rows in a matrix pattern in a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction). The lower electrodes 210 may include, for example, impurity-doped silicon, a metal (such as tungsten or copper), or a conductive metal compound (such as titanium nitride). Although not shown, the semiconductor memory device 1 may also include at least one support pattern in contact with the sidewalls of the lower electrodes 210.

[0123] The capacitor dielectric film 220 may include, for example, TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST ((Ba,Sr)TiO), STO (SrTiO), BTO (BaTiO), PZT (Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)O, Sr(Zr,Ti)O, or combinations thereof.

[0124] The upper electrode 230 may include, for example, doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba,Sr)RuO), CRO (CaRuO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or combinations thereof.

[0125] Before forming the capacitor structure 200, an insulating structure 195 filling the groove 190R can be formed. In some embodiments, the insulating structure 195 may include an interlayer insulating layer and an etch stop layer. For example, the interlayer insulating layer may include an oxide film, and the etch stop layer may include a nitride film. Although in Figures 10A to 10C The top surface of the insulating structure 195 and the bottom surface of the lower electrode 210 are at the same level, but the embodiment is not limited to this. For example, the top surface of the insulating structure 195 may be at a higher level than the bottom surface of the lower electrode 210, and the lower electrode 210 may extend toward the substrate 110 inside the insulating structure 195.

[0126] The peripheral region PR and the dam region DR can be filled with a second filling insulating layer 250 flush with the capacitor structure 200. The second filling insulating layer 250 may include, for example, an oxide film or an ultra-low K (ULK) film. The oxide film may include films selected from borosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), undoped silicate glass (USG), tetraethyl orthosilicate (TEOS), and high-density plasma (HDP) films. The ULK film may include, for example, films selected from SiOC and SiCOH films, both having an ultra-low dielectric constant K of about 2.2 to about 2.4.

[0127] This specification shows that the peripheral region PR is filled with an insulating material other than the gate line structure 140P (e.g., a first filling insulating layer 175, an insulating structure 195, and a second filling insulating layer 250), but this is only an example. Conductive wiring electrically connected to the logic active region 117 and / or the gate line 147P, as well as many other components, can be formed in the peripheral region PR.

[0128] Reference Figures 1 to 4 and Figures 10A to 10D The semiconductor memory device 1 includes a peripheral region PR defining a logic active region 117, a memory cell region CR defining an active region 118, and a dam region DR between the memory cell region CR and the peripheral region PR.

[0129] The semiconductor memory device 1 may include: a gate dielectric film 122, word lines 120, and a buried insulating film 124, sequentially formed in word line trenches 120T in a memory cell region CR of a substrate 110; an insulating film pattern (including a first insulating film pattern 112 and a second insulating film pattern 114) covering a device isolation film 116, an active region 118, and the buried insulating film 124; a bit line structure 140 located on the insulating film pattern; a buried contact 170 filling the lower portion of a space defined by an insulating fence 180 and insulating spacer structures 150 respectively covering the sidewalls of the bit line structure 140, and connected to the active region 118; a bonding pad 190 filling the upper portion of the space defined by the insulating fence 180 and the insulating spacer structure 150, and extending above the bit line structure 140; and a capacitor structure 200 including a lower electrode 210, a capacitor dielectric film 220, and an upper electrode 230, the lower electrode 210 being connected to the bonding pad 190.

[0130] The buried contact 170 may include a first dummy buried contact 170X and a second dummy buried contact 170Y. The first dummy buried contact 170X may be arranged in at least one row adjacent to the peripheral area PR in a first horizontal direction (e.g., the X direction). The second dummy buried contact 170Y may be arranged in at least one row adjacent to the peripheral area PR in a second horizontal direction (e.g., the Y direction).

[0131] The insulating fence 180 can be arranged between two adjacent insulating spacer structures 150 that respectively cover the sidewalls of the wiring structure 140, and is separated from each other in a second horizontal direction (e.g., the Y direction). Each of the insulating fences 180 can extend from between two adjacent buried contacts 170 to between two adjacent mating pads 190.

[0132] The semiconductor memory device 1 includes a region isolation film 115 between the memory cell region CR and the peripheral region PR, and includes an insulating film pattern covering the logic active region 117 and the region isolation film 115 and a gate line structure 140P on the insulating film pattern in the peripheral region PR.

[0133] The semiconductor memory device 1 includes a dam structure 190D in the dam area DR. The dam structure 190D may include a first dam structure DMX extending in a longer linear shape in a first horizontal direction (e.g., the X direction) and a second dam structure DMY extending in a longer linear shape in a second horizontal direction (e.g., the Y direction).

[0134] In some embodiments, the dam structure 190D may be arranged on the dummy bit line structure 140D or the insulating fence 180. For example, a first dam structure DMX may be arranged adjacent to the peripheral area PR at the ends of the insulating fence 180 and bit line structure 140 alternating with each other along a first horizontal direction (e.g., the X direction). For example, a second dam structure DMY may be arranged on the dummy bit line structure 140D in a second horizontal direction (e.g., the Y direction) adjacent to the peripheral area PR. The second dam structure DMY may extend from the top surface of the second dummy buried contact 170Y to the top surface of the dummy bit line structure 140D.

[0135] The first dam structure DMX may extend in a first horizontal direction (e.g., the X direction) over one end of the first dummy buried contact 170X and the portion of the insulating cover line 148 located at one end of the position line structure 140, with the first dummy buried contact 170X and the position line structure 140 alternating with each other. The second dam structure DMY may extend in a second horizontal direction (e.g., the Y direction) over the second dummy buried contact 170Y and the insulating fence 180, which alternate with each other.

[0136] The top surface of dam structure 190D can be at the same level as the top surface of mating pad 190, and the bottom surface of dam structure 190D can be at the same level as the bottom surface of mating pad 190. The bottom surface of mating pad 190 contacts the top surface of buried contact 170. Similarly, the bottom surface of the first dam structure DMX can contact the top surface of the first dummy buried contact 170X, and the bottom surface of the second dam structure DMY can contact the top surface of the second dummy buried contact 170Y.

[0137] In some embodiments, with Figure 1 The dam structure DM is the same as that in dam structure 190D, and the first dam structure DMX and the second dam structure DMY can be separated from each other. In some embodiments, with Figure 2 The dam structure DMa is the same as that in dam structure 190D. Multiple first dam structures DMX and multiple second dam structures DMY can exist in dam structure 190D, and the first dam structures DMX and the second dam structures DMY can be separated from each other. In some embodiments, with... Figure 3 The dam structures DMb are identical, and the first dam structure DMX and the second dam structure DMY of dam structure 190D can be connected to each other.

[0138] Each of the top surfaces of the first dam structure DMX and the second dam structure DMY may have an edge facing the memory cell region CR and an edge facing the peripheral region PR, wherein the edges have a straight shape. The edge of the top surface of the first dam structure DMX may extend in a first horizontal direction (e.g., the X direction), and the edge of the top surface of the second dam structure DMY may extend in a second horizontal direction (e.g., the Y direction). For example, the edges of the top surfaces of the first dam structure DMX and the second dam structure DMY (the edges facing the memory cell region CR) may each have a straight shape extending in the first horizontal direction (e.g., the X direction) and the second horizontal direction (e.g., the Y direction), respectively, without being affected by the shape of the top surface of the bonding pad 190 adjacent to the first dam structure DMX and the second dam structure DMY. The upper portions of the sidewalls of the first dam structure DMX and the second dam structure DMY may extend in a vertical direction (e.g., the Z direction) and may extend in the first horizontal direction (e.g., the X direction) and the second horizontal direction (e.g., the Y direction) respectively without bending.

[0139] Semiconductor memory device 1 has a dam structure 190D between the memory cell region CR and the peripheral region PR, thereby reducing the manufacturing difficulty caused by the structural differences between the memory cell region CR and the peripheral region PR, and ensuring structural reliability. Furthermore, semiconductor memory device 1 has a relatively wide gap between the dam structure 190D and the bonding pad 190 in the memory cell region, and the dam structure 190D has… Figure 1 dam opening DO or Figure 2 The dam opening DOa in the structure allows for easy removal of photoresist residues, etching byproducts, etc., during the process of forming the bonding pad 190 and the dam structure 190D. As a result, the yield and quality of the semiconductor memory device 1 can be improved.

[0140] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the claims.

Claims

1. A semiconductor memory device comprising: a substrate having a memory cell region, a peripheral region, and a dam region between the memory cell region and the peripheral region, the memory cell region having a rectangular shape in a plan view, and the memory cell region having a plurality of active regions defined therein; a plurality of bit line structures extending on the substrate in the memory cell region to be parallel to each other in a first horizontal direction, each bit line structure including a bit line; a plurality of buried contacts filling a lower portion of a space between the plurality of bit line structures on the substrate; a plurality of bonding pads on the plurality of buried contacts; and a dam structure including a first dam structure and a second dam structure in the dam region and being located at a same level as the plurality of bonding pads, wherein the first dam structure has a linear shape extending in the first horizontal direction, wherein the second dam structure is separated from the first dam structure and has a linear shape extending in a second horizontal direction perpendicular to the first horizontal direction, the first dam structure and the second dam structure having a first dam opening therebetween, wherein the plurality of buried contacts include a plurality of first dummy buried contacts and a plurality of second dummy buried contacts, wherein each of the plurality of first dummy buried contacts has a top surface in contact with a bottom surface of the first dam structure, wherein each of the plurality of second dummy buried contacts has a top surface in contact with a bottom surface of the second dam structure, wherein the plurality of first dummy buried contacts are electrically separated from a corresponding active region of the plurality of active regions, and wherein the plurality of second dummy buried contacts are in contact with a corresponding active region of the plurality of active regions. opposite edges of a top surface of the first dam structure extend in a straight line in the first horizontal direction, and opposite edges of a top surface of the second dam structure extend in a straight line in the second horizontal direction, the opposite edges facing the memory cell region and the peripheral region, respectively.

2. The semiconductor memory device according to claim 1, wherein, each of the plurality of bonding pads has a top surface having a circular disc shape, and 3. The semiconductor memory device according to claim 1, wherein, wherein the plurality of bonding pads are arranged in a zigzag pattern in the first horizontal direction or the second horizontal direction in a honeycomb pattern. the first dam structure is arranged along an edge of the rectangular shape of the memory cell region extending in the first horizontal direction, and 4. The semiconductor memory device according to claim 1, wherein, wherein the second dam structure extends along an edge of the rectangular shape of the memory cell region extending in the second horizontal direction. each of the first dam structure and the second dam structure has a plurality of portions separated from each other by a second dam opening, 5. The semiconductor memory device of claim 4, wherein, wherein the plurality of portions of the first dam structure are sequentially arranged in the first horizontal direction, and wherein the plurality of portions of the second dam structure are sequentially arranged in the second horizontal direction. each of the first dam opening and the second dam opening has a width of 1 µm to 5 µm.

6. The semiconductor memory device of claim 5, wherein, 7.The semiconductor memory device of claim 1, further comprising: a dummy bit line structure extending on the substrate in the second horizontal direction, wherein the second dam structure extends from a top surface of the plurality of second dummy buried contacts to a top surface of the dummy bit line structure. ​ 8. The semiconductor memory device of claim 7, wherein, In the first horizontal direction, a width of the dummy bit line structure is greater than a width of each of the plurality of bit line structures.

9. The semiconductor memory device of claim 1, further comprising: a plurality of capacitor structures formed in the memory cell region, wherein the plurality of capacitor structures are formed of an upper electrode, a plurality of lower electrodes electrically connected to the plurality of bonding pads, and a capacitor dielectric film between the upper electrode and the plurality of lower electrodes, and wherein the dam structure is not electrically connected to the plurality of bonding pads.

10. A semiconductor memory device, comprising: a substrate having a memory cell region, a peripheral region, and a dam region between the memory cell region and the peripheral region, the memory cell region having a rectangular shape according to a top view, and the memory cell region having a plurality of active regions defined therein; a plurality of bit line structures extending on the substrate in the memory cell region to be parallel to each other in a first horizontal direction, each bit line structure including a bit line; a plurality of gate line structures located in the peripheral region, each gate line structure of the plurality of gate line structures having a gate line pattern at a same level as the bit line; a plurality of buried contacts filling lower portions of spaces between the plurality of bit line structures on the substrate; a bonding pad located on the buried contact; and a dam structure disposed along edges of the rectangular shape of the memory cell region in the dam region, wherein edges of a top surface of the dam structure extend in straight lines and face the memory cell region, wherein the dam structure includes a first dam structure and a second dam structure, wherein the plurality of buried contacts include a plurality of first dummy buried contacts and a plurality of second dummy buried contacts, wherein each first dummy buried contact of the plurality of first dummy buried contacts has a top surface in contact with a bottom surface of the first dam structure, wherein each second dummy buried contact of the plurality of second dummy buried contacts has a top surface in contact with a bottom surface of the second dam structure, wherein the plurality of first dummy buried contacts are electrically separated from respective active regions of the plurality of active regions, and wherein the plurality of second dummy buried contacts are in contact with respective active regions of the plurality of active regions.

11. The semiconductor memory device of claim 10, wherein, the top surface of the dam structure is at a same level as a top surface of the bonding pad, and wherein a bottom surface of the dam structure is at a same level as a bottom surface of the bonding pad.

12. The semiconductor memory device of claim 10, wherein, According to a top view, the dam structure has a rectangular shape surrounding the memory cell region.

13. The semiconductor memory device of claim 10, wherein, The dam structure extends along four edges of the rectangular shape of the memory cell region and is separated into a plurality of portions at each corner of the rectangular shape of the memory cell region.

14. The semiconductor memory device of claim 13, wherein, The dam structure includes at least two portions sequentially disposed and separated from each other along at least one edge of the four edges of the rectangular shape of the memory cell region.

15. The semiconductor memory device of claim 10, further comprising: a plurality of capacitor structures formed in the memory cell region, wherein the plurality of capacitor structures are formed of an upper electrode, a plurality of lower electrodes, and a capacitor dielectric film between the upper electrode and the plurality of lower electrodes, a corresponding lower electrode being electrically connected to the bonding pad, and wherein the dam structure is not electrically connected to the bonding pads.

16. The semiconductor memory device of claim 10, wherein, The bonding pads and the dam structure are formed of the same material.

17. A semiconductor memory device, the semiconductor memory device comprising: a substrate having a memory cell region, a peripheral region, and a dam region between the memory cell region and the peripheral region, the memory cell region having a rectangular shape in plan view, and the memory cell region having a plurality of active regions defined therein; a plurality of word lines extending in a first horizontal direction across the plurality of active regions in the memory cell region, the plurality of word lines being parallel to each other; a plurality of bit line structures extending on the substrate in the memory cell region to be parallel to each other in a second horizontal direction perpendicular to the first horizontal direction, each bit line structure including a bit line; a plurality of gate line structures located in the peripheral region, each of the plurality of gate line structures having a gate line pattern at a same level in a vertical direction as the bit lines; a plurality of buried contacts filling lower portions of spaces between the plurality of bit line structures on the substrate; a plurality of bonding pads filling upper portions of the spaces between the plurality of bit line structures and extending above the plurality of bit line structures; and a dam structure including a first dam structure and a second dam structure in the dam region and at a same level in the vertical direction as the plurality of bonding pads, wherein the first dam structure has a linear shape extending in the first horizontal direction, wherein the second dam structure has a linear shape extending in the second horizontal direction, wherein the first dam structure and the second dam structure are separated from each other by a first dam opening at a corner of the rectangular shape of the memory cell region, wherein each of the plurality of bonding pads has a top surface having a circular disc shape, wherein opposite sides of the top surface of the first dam structure extend in straight lines in the first horizontal direction, wherein opposite sides of the top surface of the second dam structure extend in straight lines in the second horizontal direction, wherein the opposite sides face the memory cell region and the peripheral region, respectively, wherein the plurality of buried contacts include a plurality of first buried contacts and a plurality of second buried contacts, wherein each of the plurality of first buried contacts has a top surface in contact with a bottom surface of the first dam structure, wherein each of the plurality of second buried contacts has a top surface in contact with a bottom surface of the second dam structure, wherein the plurality of first buried contacts are electrically separated from respective ones of the plurality of active regions, and wherein the plurality of second buried contacts are in contact with respective ones of the plurality of active regions. At least one selected from the first dam structure and the second dam structure includes a plurality of portions separated from each other by a second dam opening along at least one side of the rectangular shape of the memory cell region.

18. The semiconductor memory device of claim 17, wherein, There is a pattern of insulating films between the plurality of first buried contacts and respective ones of the plurality of active regions.

19. The semiconductor memory device of claim 17, wherein, ​

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