Display device with reduced dead zone

Abstract

The present invention discloses a display device with a reduced dead zone. The display device includes: a display area and a non-display area located around the display area and including a pad portion and a contact portion arranged between the display area and the pad portion; a first circuit portion, including an embedded circuit arranged in the display area, a first connection electrode arranged in the pad portion, and a second connection electrode arranged in the contact portion; and a second circuit portion, which is arranged on a different layer from the first circuit portion and includes a pixel arranged in the display area, a pad arranged in the pad portion, and a data line extending across the contact portion and the display area and electrically connected to the pixel. The pad is electrically connected to the embedded circuit through the first connection electrode. The data line is electrically connected to the embedded circuit through the second connection electrode.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2019-0114355 filed on September 17, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device, and more particularly, to a display device with a reduced dead zone. Background Art

[0003] With the development of multimedia technology, display devices are becoming more and more important. Various types of display devices such as liquid crystal display (LCD) devices and organic light emitting display (OLED) devices are currently used. Among these display devices, OLED devices including self-luminous organic light emitting elements show excellent contrast and wide viewing angle. OLED devices have attracted attention as next-generation display devices due to their advantages.

[0004] The display device may include a display area and a non-display area arranged around the display area. The pixel circuit may be arranged in the display area, and various drive circuits for driving the pixel circuit may be arranged in the non-display area as the dead zone of the display device. Recently, a display device with a wider display surface (e.g., with a narrower frame) in a limited size is favored. For this reason, research has been invested in the development of a method for reducing the dead zone. Unfortunately, as the resolution of the display device increases, the drive circuit becomes more complicated, and it is therefore more difficult to reduce the area where the drive circuit is arranged. Therefore, there is a limitation in reducing the width of the non-display area where the drive circuit is arranged. Summary of the invention

[0005] Exemplary embodiments of the present disclosure provide a display device having a reduced dead zone.

[0006] It should be noted that the purpose of the present disclosure is not limited to the exemplary embodiments disclosed herein; and other purposes of the present disclosure will be apparent to those skilled in the art from the following description.

[0007] According to an embodiment, a display device includes: a display area and a non-display area located around the display area, the non-display area including a pad portion and a contact portion arranged between the display area and the pad portion; a first circuit portion including an embedded circuit arranged in the display area, a first connection electrode arranged in the pad portion, and a second connection electrode arranged in the contact portion; and a second circuit portion arranged on a different layer from the first circuit portion and including a pixel arranged in the display area, a pad arranged in the pad portion, and a data line extending across the contact portion and the display area and electrically connected to the pixel. The pad is electrically connected to the embedded circuit through the first connection electrode. The data line is electrically connected to the embedded circuit through the second connection electrode.

[0008] The display device may further include: a first fan-out line connecting the first connecting electrode and the embedded circuit; and a second fan-out line connecting the embedded circuit and the second connecting electrode, wherein the first fan-out line may extend across the pad portion, the contact portion and the display area, and the second fan-out line may extend across the display area and the contact portion.

[0009] The first connection electrode and the second connection electrode may be disposed on the same first layer and include the same first material, and the pad and the data line may be disposed on the same second layer and may include the same second material.

[0010] The first fan-out line and the second fan-out line may be arranged on the same third layer and may include the same third material, and the third layer may be different from the first layer.

[0011] The pixel may include a pixel transistor and a light emitting element electrically connected to the pixel transistor, and the embedded circuit may include the embedded circuit transistor.

[0012] The pixel transistor may include a pixel semiconductor layer, and the embedded circuit transistor may include an embedded circuit semiconductor layer, and the pixel semiconductor layer and the embedded circuit semiconductor layer may include different materials.

[0013] One of the embedded circuit semiconductor layer and the pixel semiconductor layer may include an oxide semiconductor, and the other of the embedded circuit semiconductor layer and the pixel semiconductor layer may include polysilicon.

[0014] The pixel transistor may include a pixel semiconductor layer, a pixel gate electrode arranged on the pixel semiconductor layer, and a pixel source electrode and a pixel drain electrode arranged on the pixel gate electrode, and the pixel source electrode and the pixel drain electrode may be electrically connected to the pixel semiconductor layer, and the pixel source electrode and the pixel drain electrode are arranged on the same layer as the pad.

[0015] The embedded circuit transistor may include an embedded circuit semiconductor layer, an embedded circuit gate electrode arranged on the embedded circuit semiconductor layer, and an embedded circuit source electrode and an embedded circuit drain electrode arranged on the embedded circuit gate electrode, and the embedded circuit source electrode and the embedded circuit drain electrode may be arranged on the same layer as the first connecting electrode.

[0016] When viewed in a plan view from the top, the second connection electrode may be closer to the display area than the first connection electrode.

[0017] The display device may further include: an interlayer dielectric layer disposed between the first circuit portion and the second circuit portion.

[0018] The interlayer dielectric layer may be in direct contact with the first connection electrode and the second connection electrode.

[0019] According to an embodiment, a display device includes: a display area and a non-display area located around the display area, the non-display area including a pad portion and a contact portion arranged between the display area and the pad portion; a first circuit portion including a demultiplexer arranged in the display area, a first connecting electrode arranged in the pad portion, and a second connecting electrode arranged in the contact portion; and a second circuit portion, which is arranged on a different layer from the first circuit portion and includes pixels arranged in the display area, pads arranged in the pad portion, and at least one data line extending across the contact portion and the display area and electrically connected to the pixels, wherein the pad is electrically connected to the demultiplexer through the first connecting electrode and provides a data signal to the demultiplexer, wherein at least one data line is electrically connected to the demultiplexer through the second connecting electrode, and the demultiplexer generates a divided data signal by dividing the data signal received from the pad using time division multiplexing.

[0020] The at least one data line may include a first data line and a second data line respectively providing divided data signals.

[0021] The second connection electrode may include a 2-1 connection electrode connecting the demultiplexer and the first data line and a 2-2 connection electrode connecting the demultiplexer and the second data line.

[0022] The display device may further include: a first fan-out line connecting the first connection electrode and the demultiplexer; and a second fan-out line connecting the demultiplexer and the second connection electrode. The first fan-out line may extend across the pad portion, the contact portion, and the display area, and the second fan-out line may extend across the display area and the contact portion.

[0023] The second fan-out lines may include a 2-1 fan-out line connecting the demultiplexer and the 2-1 connection electrode and a 2-2 fan-out line connecting the demultiplexer and the 2-2 connection electrode.

[0024] At least one data line may extend in a first direction, and the first circuit portion may include a plurality of demultiplexers arranged in a second direction crossing the first direction.

[0025] The same demultiplexing select signal line can be connected to multiple demultiplexers.

[0026] At least one data line may extend in a first direction and include multiple data lines arranged along a second direction intersecting the first direction, the first circuit portion may include multiple demultiplexers, the multiple demultiplexers include a first demultiplexer and a second demultiplexer, and the first demultiplexer and the second demultiplexer may be connected to different data lines among the multiple data lines.

[0027] The first demultiplexer and the second demultiplexer may be connected to different demultiplexing selection signal lines.

[0028] The details of one or more exemplary embodiments of the disclosure are set forth in the accompanying drawings and the description below.

[0029] According to an exemplary embodiment of the present disclosure, an embedded circuit (eg, a demultiplexing driving circuit) is arranged in a display area to reduce a dead area of ​​a display device that may be occupied by the embedded circuit.

[0030] However, the features of the present disclosure are not limited to the features set forth herein. The above and other features of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present disclosure;

[0033] Figure 2 is a circuit diagram of a demultiplexer included in a demultiplexer circuit of a display device according to an exemplary embodiment of the present disclosure;

[0034] Figure 3 is an equivalent circuit diagram of a pixel of a display device according to an exemplary embodiment of the present disclosure;

[0035] Figure 4 is a plan view showing a layout of a display device according to an exemplary embodiment of the present disclosure;

[0036] Figure 5 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0037] Figure 6 yes Figure 4 An enlarged view of area A shown in;

[0038] Figure 7 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0039] Figure 8 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure;

[0040] Fig. 9 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure;

[0041] Fig.10 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure;

[0042] Fig.11 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure;

[0043] Fig.12 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure;

[0044] Fig.13 According to another exemplary embodiment of the present disclosure Figure 4 An enlarged view of area A shown in;

[0045] Fig.14 is a perspective view of a display device according to still another exemplary embodiment of the present disclosure;

[0046] Fig.15 is a plan view showing a display device according to still another exemplary embodiment of the present disclosure;

[0047] Fig.16 is along Fig.15 A cross-sectional view taken along the line XVI-XVI' shown in FIG.

[0048] Fig.17 is a plan view showing a layout of a display device according to still another exemplary embodiment of the present disclosure;

[0049] Fig.18 yes Fig.17 A schematic cross-sectional view of a display device shown in ;

[0050] Fig.19 yes Fig.17 an enlarged view of part B;

[0051] Fig. 20 is a perspective view of a display device according to still another exemplary embodiment of the present disclosure;

[0052] Fig.21 yes Fig. 20 An expanded view of a display device;

[0053] Fig. 22 yes Fig. 20 A schematic cross-sectional view of a display device of ; and

[0054] Fig.23 yes Fig.21 Magnified view of area C. DETAILED DESCRIPTION

[0055] The description of the exemplary embodiments of the present disclosure disclosed herein is for illustrative purposes only. Without departing from the spirit and salient features of the present disclosure, the present disclosure may be embodied in many different forms. Therefore, the embodiments of the present disclosure should not be interpreted as limiting the present disclosure.

[0056] It will be understood that when an element is referred to as being associated with another element, such as being "coupled" or "connected" to another element, the element may be directly coupled or connected to the other element, or one or more intermediate elements may be present between them. Conversely, it will be understood that when an element is referred to as being associated with another element, such as being "directly coupled" or "directly connected" to another element, there may be no intermediate elements. Other expressions that explain the relationship between elements, such as "between," "directly between," "adjacent," or "directly adjacent," should be interpreted in a similar manner.

[0057] Throughout the specification, the same reference numerals will refer to the same or similar elements and / or components.

[0058] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Therefore, without departing from the teachings of this article, the first element, first component, first region, first layer or first portion discussed below may be referred to as the second element, second component, second region, second layer or second portion.

[0059] The terms used herein are for the purpose of describing a particular embodiment and are not intended to be limiting. As used herein, "one", "the (described)" and "at least one" do not represent the limitation of quantity, and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". The phrase "at least one" is not interpreted as limiting "one". "Or" may mean "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the items listed in association. It will be further understood that the terms "include" and / or "comprising" used herein indicate the presence of stated features, regions, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their combinations.

[0060] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that relative terms are intended to include different orientations of the device containing the element other than the orientation depicted in the accompanying drawings. For example, if the device in one of the drawings is turned over, the element described as being on the "lower" side of the other elements will then be oriented to be on the "upper" side of the other elements. Therefore, depending on the specific orientation of the drawings, the exemplary term "lower" can include both "lower" and "upper" orientations. Similarly, if the device in one of the drawings is turned over, the element described as being "below" or "below" the other elements will then be oriented to be "above" the other elements. Therefore, depending on the specific orientation of the drawings, the exemplary term "lower" or "below" can include both "above" and "below" orientations.

[0061] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation from the stated value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0062] Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the content of the present disclosure, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined herein.

[0063] Herein, exemplary embodiments may be described with reference to cross-sectional illustrations, which are schematic illustrations of rationalized embodiments. Therefore, as a result of, for example, manufacturing techniques and / or tolerances, variations in the illustrated shapes may be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions illustrated in the accompanying drawings, but will include deviations in shapes that may be caused or resulting from manufacturing. For example, an area illustrated or described as flat may typically have rough and / or non-planar features. Moreover, the illustrated sharp corners may be rounded. Therefore, the areas illustrated in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the illustrated regions and are not intended to limit the scope of the present disclosure.

[0064] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0065] Figure 1 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present disclosure.

[0066] The display device 10 can be applied to various portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation systems, and ultra-portable mobile PCs (UMPCs), as well as various products such as televisions, notebooks, monitors, billboards, and Internet of Things (IoT) devices.

[0067] The display device 10 may display an image. Examples of the display device 10 include an organic light emitting display (OLED) device, a liquid crystal display (LCD) device, a plasma display (PDP) device, a field emission display (FED) device, an electrophoretic display (EPD) device, etc. Although the display device 10 is described as an organic light emitting display (OLED) device in the following description, it should be noted that the present disclosure is not limited thereto.

[0068] refer to Figure 1 , the display device 10 includes a plurality of pixels 1, a scan driver 20, a data driver 30, an emission control driver 40, a controller 50, and a demultiplexing circuit 60. In addition, the display device 10 may further include a plurality of scan lines SL1, SL2, and SL3, a plurality of data lines DL, and a plurality of emission control lines EL. In addition, the display device 10 may further include an initialization voltage supply line for supplying an initialization voltage VINT to each of the pixels 1 and a first supply voltage supply line for supplying a first supply voltage ELVDD to each of the pixels 1.

[0069] In the following description, the embedded circuit may refer to at least one of the scan driver 20 , the emission control driver 40 , and the demultiplexing circuit 60 .

[0070] The plurality of scan lines SL1, SL2, and SL3 may include first, second, and third scan lines SL1, SL2, and SL3. A first scan signal may be supplied to the first scan line SL1, a second scan signal may be supplied to the second scan line SL2, and a third scan signal may be supplied to the third scan line SL3.

[0071] In some exemplary embodiments, the first scan line SL1, the second scan line SL2, and the third scan line SL3 may extend in the first direction X. The first scan line SL1, the second scan line SL2, and the third scan line SL3 may be disposed in this order in a second direction Y crossing the first direction X. The first scan line SL1, the second scan line SL2, and the third scan line SL3 may form a group, and a plurality of such groups may be disposed along the second direction Y.

[0072] The data signal may be provided to the data line DL. In some exemplary embodiments, the data line DL may extend in the second direction Y and may be disposed along the first direction X.

[0073] The emission control signal may be provided to the emission control line EL. In some exemplary embodiments, the emission control line EL may extend in the first direction X, and may be disposed along the second direction Y.

[0074] Each of the pixels 1 may be connected to one of the data lines DL, one of the emission control lines EL, a group of the first scan line SL1, the second scan line SL2, and the third scan line SL3. In some exemplary embodiments, the pixels 1 may be arranged in a matrix, but not limited thereto. The pixels 1 may be arranged in a PenTile structure or in various other ways.

[0075] As will be described later, each of the pixels 1 may include an organic light emitting diode OLED (see Figure 3 ) or a light emitting element and at least one transistor electrically connected to the organic light emitting diode OLED. For example, the pixel 1 may include a plurality of transistors T1 to T7 (see Figure 3 The organic light emitting diode OLED may include an anode electrode ANO (see Figure 7 ), the cathode electrode CAT facing the anode electrode ANO (see Figure 7 ) and an organic layer OL disposed between the anode electrode ANO and the cathode electrode CAT (see Figure 7 ). In some exemplary embodiments, each of the pixels 1 may further include, but is not limited to, a storage capacitor Cst (see Figure 3 ).

[0076] The initialization voltage supply line may provide the initialization voltage VINT to each of the pixels 1. In some exemplary embodiments, a plurality of initialization voltage supply lines may extend in the first direction X and be disposed along the second direction Y. The initialization voltage supply line may be electrically connected to the pixels 1 to supply the initialization voltage VINT to the pixels 1.

[0077] A first supply voltage supply line for supplying the first supply voltage ELVDD to each of the pixels 1 may extend in the second direction Y, and a plurality of first supply voltage supply lines may be disposed along the first direction X. The first supply voltage supply line may be electrically connected to the pixels 1 to supply the first supply voltage ELVDD to the pixels 1 .

[0078] The second supply voltage supply line may be electrically connected to the cathode electrode CAT (see Figure 7 ) to supply the second supply voltage ELVSS to the cathode electrode CAT.

[0079] The scan driver 20 may generate three scan signals and transmit them to each of the pixels 1 through, for example, a plurality of scan lines SL1, SL2, and SL3. Specifically, the scan driver 20 provides a first scan signal to the first scan line SL1, a second scan signal to the second scan line SL2, and a third scan signal to the third scan line SL3.

[0080] The data driver 30 outputs a data signal. The data signal output from the data driver 30 is transmitted to the demultiplexing circuit 60.

[0081] The demultiplexing circuit 60 may be electrically connected to the data lines DL. The demultiplexing circuit 60 may generate data signals of the data lines DL according to the data signals provided by the data driver 30, and may provide them to the data lines DL.

[0082] The demultiplexing circuit 60 may include a plurality of demultiplexers DEMUX (see Figure 2 ). Each of the demultiplexers DEMUX may provide the received data signal to two or more data lines DL. For example, when two data lines DL are connected to one demultiplexer DEMUX, the data signal DATA (see Figure 2 ) can be transmitted to the demultiplexer DEMUX, and the demultiplexer DEMUX receiving the data signal DATA can divide the data signal DATA by time slot and transmit the divided data signals to the two data lines DL respectively. Figure 1 In the example shown in , the data driver 30 is electrically connected to the demultiplexing circuit 60 , and the demultiplexing circuit 60 is electrically connected to the data lines DL.

[0083] The data lines DL may include a first data line DLa and a second data line DLb (see Figure 2 ), each of the first data line DLa and the second data line DLb receives a data signal divided by using time division multiplexing. For example, the first data line DLa may refer to a data line DL that receives the divided data signal earlier, and the second data line DLb may refer to a data line DL that receives the divided data signal later. In another example, the second data line DLb may receive the divided data signal earlier, and the first data line DLa may receive the divided data signal later.

[0084] It is to be noted that the first data line DLa and the second data line DLb are designated to distinguish between them according to the order in which the data lines receive divided data signals, and not necessarily to describe a sequential or chronological order.

[0085] In some exemplary embodiments, the data driver 30 and the demultiplexing circuit 60 may be connected via a pad PAD (see Figure 7 ), a first connection electrode (eg, Figure 7 ) and a first fan-out line (eg, Figure 7 The demultiplexing circuit 60 can be electrically connected to each other through the second fan-out line (for example, Figure 7 ) and a second connecting electrode (eg, Figure 7 The second connection electrode 143 shown in FIG. 1 is electrically connected to the data line DL.

[0086] Reference Figure 2 The demultiplexer DEMUX is described in detail.

[0087] Figure 2 is a circuit diagram of a demultiplexer included in a demultiplexer circuit of a display device according to an exemplary embodiment of the present disclosure. Figure 2 In the example shown in , two data lines including a first data line DLa and a second data line DLb are connected to the demultiplexer DEMUX.

[0088] refer to Figure 2 , the demultiplexer DEMUX comprises a first demultiplexing transistor T DM1 and the second demultiplexing transistor T DM2 .exist Figure 2 In the example, the first demultiplexing transistor T DM1 and the second demultiplexing transistor T DM2 Both are shown as P-type metal oxide semiconductor (PMOS) transistors, but the present disclosure is not limited thereto. The first demultiplexing transistor T DM1 and the second demultiplexing transistor T DM2Each of the electrodes includes a first electrode, a second electrode, and a gate electrode.

[0089] from Figure 1 The data signal DATA output by the data driver 30 is provided to the first demultiplexing transistor T DM1 The first demultiplexing transistor T DM1 The second electrode of the transistor T may be electrically connected to the first data line DLa. The first demultiplexing selection signal CL1 may be provided to the first demultiplexing transistor T through the first demultiplexing selection signal line CLL1. DM1 When the first demultiplexing selection signal CL1 having a low level is applied to the first demultiplexing transistor T DM1 When the gate electrode of the first demultiplexing transistor T DM1 is turned on, so that the data signal DATA can be output to the first data line DLa.

[0090] from Figure 1 The data signal DATA output by the data driver 30 is also provided to the second demultiplexing transistor T DM2 The first electrode of the second demultiplexing transistor T DM2 The second electrode of the transistor may be electrically connected to the first demultiplexing transistor T DM1 The second demultiplexing selection signal CL2 may be provided to the second demultiplexing transistor T through the second demultiplexing selection signal line CLL2. DM2 When the second demultiplexing selection signal CL2 having a low level is applied to the second demultiplexing transistor T DM2 When the gate electrode of the second demultiplexing transistor T DM2 is turned on, so that the data signal DATA can be output to the second data line DLb.

[0091] With the first demultiplexing transistor T DM1 or the second demultiplexing transistor T DM2 In response to the first demultiplexing selection signal CL1 or the second demultiplexing selection signal CL2 being turned on, the data signal DATA may be selectively applied to the two data lines DLa and DLb. In some exemplary embodiments, when the first demultiplexing selection signal CL1 and the second demultiplexing selection signal CL2 have different timings, the data signal DATA may be transmitted in a time division multiplexing scheme.

[0092] According to the above exemplary embodiments, the demultiplexer DEMUX provides the data signal DATA received from the data driver 30 to the two data lines DLa and DLb. However, it should be understood that the data signal DATA may be provided to three or more data lines without departing from the scope of the present disclosure. When one demultiplexer DEMUX provides the data signal DATA to three or more data lines, the demultiplexer DEMUX may include three or more demultiplexing transistors corresponding to the number of data lines.

[0093] Return to reference Figure 1 , the emission control driver 40 generates an emission control signal and transmits the emission control signal to each of the pixels 1 through a plurality of emission control lines EL. The emission control signal controls the emission timing of the pixel 1. In some exemplary embodiments, the emission control driver 40 may be formed integrally with the scan driver 20, and the integrally formed driver may generate the emission control signal as well as the scan signal. Depending on the internal structure of the pixel 1, the emission control driver 40 may be omitted.

[0094] The controller 50 converts a plurality of image signals R, G, and B received from an external device into a plurality of image data signals DR, DG, and DB, and transmits them to the data driver 30. In addition, the controller 50 receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal MCLK, and generates various control signals for controlling the driving of the scan driver 20, the data driver 30, and the emission control driver 40, and transmits the control signals to the scan driver 20, the data driver 30, and the emission control driver 40. For example, the controller 50 generates a scan driving control signal SCS for controlling the scan driver 20, a data driving control signal DCS for controlling the data driver 30, and an emission driving control signal ECS for controlling the emission control driver 40, and transmits these control signals to the scan driver 20, the data driver 30, and the emission control driver 40, respectively. In addition, the controller 50 generates demultiplexing selection signals CL1 and CL2 for controlling the operation of the demultiplexer DEMUX, and transmits the demultiplexing selection signals CL1 and CL2 to the demultiplexing circuit 60.

[0095] Figure 3 is an equivalent circuit diagram of a pixel of a display device according to an exemplary embodiment of the present disclosure.

[0096] refer to Figure 3, the circuit of the pixel 1 of the display device 10 may include an organic light emitting diode OLED, a plurality of transistors T1 to T7, and a storage capacitor Cst. A data signal DATA, a first scan signal SGL1, a second scan signal SGL2, a third scan signal SGL3, an emission control signal EM, a first supply voltage ELVDD, a second supply voltage ELVSS, and an initialization voltage VINT are applied to the circuit of the pixel 1.

[0097] The storage capacitor Cst may include a first electrode and a second electrode.

[0098] Each of the transistors T1 to T7 includes a gate electrode, a first electrode, and a second electrode. One of the first electrode and the second electrode of each of the transistors T1 to T7 corresponds to a source electrode, and the other corresponds to a drain electrode.

[0099] Each of the transistors T1 to T7 may be a thin film transistor. Each of the transistors T1 to T7 may be a PMOS transistor or an N-type metal oxide semiconductor (NMOS) transistor. Figure 3 In the example of FIG. 1 , all transistors T1 to T7 of pixel 1 are shown as PMOS transistors, but the present disclosure is not limited thereto. For example, all transistors T1 to T7 may be NMOS transistors. Alternatively, some of the transistors T1 to T7 may be PMOS transistors, and the rest may be NMOS transistors.

[0100] The gate electrode of the first transistor T1 is connected to the first electrode of the storage capacitor Cst. The first electrode of the first transistor T1 is connected to the terminal from which the first supply voltage ELVDD is applied through the fifth transistor T5. The second electrode of the first transistor T1 is connected to the anode electrode ANO of the organic light emitting diode OLED through the sixth transistor T6. The first transistor T1 receives the data signal DATA according to the switching operation of the second transistor T2, and provides the driving current Id to the organic light emitting diode OLED.

[0101] The gate electrode of the second transistor T2 is connected to a terminal from which a first scan signal SGL1 is supplied. The first electrode of the second transistor T2 is connected to a terminal from which a data signal DATA is supplied. The second electrode of the second transistor T2 is connected to the first electrode of the first transistor T1, and is connected to a terminal from which a first supply voltage ELVDD is applied through a fifth transistor T5. The second transistor T2 is turned on in response to the first scan signal SGL1, and supplies the data signal DATA to the first electrode of the first transistor T1.

[0102] The gate electrode of the third transistor T3 is connected to the terminal from which the first scan signal SGL1 is provided. The first electrode of the third transistor T3 is connected to the second electrode of the first transistor T1, and is connected to the anode electrode ANO of the organic light emitting diode OLED through the sixth transistor T6. The second electrode of the third transistor T3 is connected to the first electrode of the storage capacitor Cst, the first electrode of the fourth transistor T4, and the gate electrode of the first transistor T1. When the third transistor T3 is turned on in response to the first scan signal SGL1, the gate electrode of the first transistor T1 is connected to the second electrode of the first transistor T1, so that the first transistor T1 is diode-connected. The threshold voltage of the first transistor T1 may cause a voltage difference between the first electrode and the gate electrode of the first transistor T1. The deviation of the threshold voltage of the first transistor T1 can be compensated by providing the data signal DATA compensated for the threshold voltage to the gate electrode of the first transistor T1.

[0103] The gate electrode of the fourth transistor T4 is connected to the terminal from which the second scan signal SGL2 is supplied. The second electrode of the fourth transistor T4 is connected to the terminal from which the initialization voltage VINT is supplied. The first electrode of the fourth transistor T4 is connected to the first electrode of the storage capacitor Cst, the second electrode of the third transistor T3, and the gate electrode of the first transistor T1. The fourth transistor T4 is turned on in response to the second scan signal SGL2, and supplies the initialization voltage VINT to the gate electrode of the first transistor T1 to initialize the voltage at the gate electrode of the first transistor T1.

[0104] The gate electrode of the fifth transistor T5 is connected to the terminal from which the emission control signal EM is supplied. The first electrode of the fifth transistor T5 is connected to the terminal from which the first supply voltage ELVDD is supplied. The second electrode of the fifth transistor T5 is connected to the first electrode of the first transistor T1 and the second electrode of the second transistor T2.

[0105] The gate electrode of the sixth transistor T6 is connected to the terminal from which the emission control signal EM is supplied. The first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1 and the first electrode of the third transistor T3. The second electrode of the sixth transistor T6 is connected to the anode electrode ANO of the organic light emitting diode OLED.

[0106] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to the emission control signal EM, so that the driving current Id flows through the organic light emitting diode OLED.

[0107] A gate electrode of the seventh transistor T7 is connected to a terminal from which a third scan signal SGL3 is supplied. A first electrode of the seventh transistor T7 is connected to an anode electrode ANO of the organic light emitting diode OLED. A second electrode of the seventh transistor T7 is connected to a terminal from which an initialization voltage VINT is supplied. The seventh transistor T7 is turned on according to the third scan signal SGL3 and initializes the anode electrode ANO of the organic light emitting diode OLED.

[0108] A second electrode of the storage capacitor Cst is connected to a terminal from which a first supply voltage ELVDD is applied. A first electrode of the storage capacitor Cst is connected to a gate electrode of the first transistor T1, a second electrode of the third transistor T3, and a first electrode of the fourth transistor T4. A cathode electrode CAT of the organic light emitting diode OLED is connected to a terminal from which a second supply voltage ELVSS is supplied. The organic light emitting diode OLED emits light corresponding to the driving current Id to display an image.

[0109] Hereinafter, the structure of the above-mentioned display device 10 will be described in more detail.

[0110] Figure 4 is a plan view illustrating a layout of a display device according to an exemplary embodiment of the present disclosure. Figure 5 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 6 yes Figure 4 Magnified view of area A shown in FIG. Figure 7 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure.

[0111] The display device 10 may include a flexible substrate including a flexible polymer material such as polyimide. Therefore, the display device 10 may be bent, curved, folded, or rolled.

[0112] The display device 10 may include a display area DA that displays an image and a non-display area NDA that does not display an image. Figure 4 As shown in FIG. 1 , when viewed in a plan view from the top, the display device 10 may include a display area DA and a non-display area NDA. The non-display area NDA may surround the display area DA.

[0113] The display area DA may include a plurality of pixels 1. Each of the pixels 1 may include an emission layer and a circuit layer for controlling the amount of light emitted from the emission layer. The circuit layer may include wires, electrodes, and at least one transistor. The emission layer may include an organic light-emitting material. The emission layer may be sealed by an encapsulation layer. The configuration of each of the pixels 1 will be described in detail later.

[0114] When viewed from the top, the display device 10 may include a flat area FA and a curved area BA connected to a lower side of the flat area FA in the second direction Y. The display device 10 may further include an auxiliary flat area SFA connected to a lower side of the curved area BA in the second direction Y and curved in a thickness direction Z (or a third direction) of the display device 10 to overlap with the flat area FA in the thickness direction Z.

[0115] The flat area FA may include the display area DA. The non-display area NDA may be placed at a peripheral area of ​​the display area DA.

[0116] When viewed from the top, the flat area FA may have a shape similar to the appearance of the display device 10. The flat area FA may correspond to a flat area on a plane. However, it should be understood that the present disclosure is not limited thereto. At least one of the edges (or sides) of the flat area FA (e.g., the edge (or side) connected to the curved area BA) may be curved to form a curved surface. Figure 5 , the edge connected to the bending area BA may be bent at a right angle.

[0117] When at least one of the edges (or sides) of the flat area FA is bent or curved, the display area DA may also be arranged on the bent or curved edge. However, it should be understood that the present disclosure is not limited thereto. The non-display area NDA that does not display an image may be arranged on the bent or curved edge, or the display area DA and the non-display area NDA may be arranged together on the bent or curved edge.

[0118] The non-display area NDA of the flat area FA may extend from an outer boundary of the display area DA to an edge of the display device 10 .

[0119] The curved area BA may be connected to one shorter side of the flat area FA. The width of the curved area BA in the first direction X may be narrower than the width of the shorter side of the flat area FA. A portion where the flat area FA intersects the curved area BA may be cut into an L shape to reduce the frame width.

[0120] In the bending area BA, the display device 10 may be bent with a curvature toward the opposite side of the display surface. As the display device 10 is bent in the bending area BA, the surface of the display device 10 may be reversed. Specifically, the upward-facing surface of the display device 10 may be bent so that it faces outward at the bending area BA and then faces downward.

[0121] The auxiliary flat area SFA may extend from the curved area BA. After the display device 10 has been curved, the auxiliary flat area SFA may extend in a direction parallel to the flat area FA. The auxiliary flat area SFA may overlap with the flat area FA in the thickness direction Z of the display device 10. The auxiliary flat area SFA may overlap with the non-display area NDA at the edge of the flat area FA. The width of the auxiliary flat area SFA may be, but is not limited to, equal to the width of the curved area BA.

[0122] As will be described below, the display device 10 may include a first circuit portion (eg, Figure 7 ), a first circuit portion CCP1 shown in FIG. 1 , and a second circuit portion (eg, Figure 7 ) and an interlayer dielectric layer (eg, Figure 7 The first circuit portion, the second circuit portion, and the interlayer dielectric layer 150 shown in FIG. 1 ). The first circuit portion, the second circuit portion, and the interlayer dielectric layer may be arranged in both the display area DA and the non-display area NDA.

[0123] In the display area DA, the pixels of the second circuit part and the embedded circuit of the first circuit part are arranged. In the non-display area NDA, the pad part PP and the contact part CP located between the pad part PP and the display area DA may be arranged. The embedded circuit of the first circuit part may be the same as that described above with reference to Figure 1 The display area DA, the pad portion PP, and the contact portion CP will be described in more detail later.

[0124] Since the embedded circuit is arranged in the display area DA, it is possible to reduce the non-display area NDA of the display device 10. Therefore, it is possible to reduce a space (eg, a dead space) where the circuit and the like are arranged.

[0125] The pad portion PP may be arranged in the auxiliary flat area SFA of the display device 10. A plurality of pads PAD may be arranged in the pad portion PP. An external device may be mounted (or attached) on the pad portion PP. An example of the external device may be the above-mentioned data driver 30. The pad portion PP may be arranged in the non-display area NDA.

[0126] One data driver 30 or a plurality of data drivers 30 may be installed in the auxiliary flat area SFA. Figure 4As shown in , the data driver 30 may be arranged in the auxiliary flat area SFA of the display device 10, and the drive substrate 80 may be attached to the end of the auxiliary flat area SFA. In this case, the pad portion PP may include a first pad portion connected to the data driver 30 and a second pad portion connected to the drive substrate 80.

[0127] The data driver 30 may be attached to the display device 10 through an anisotropic conductive film or through ultrasonic bonding.

[0128] The data driver 30 may include an integrated circuit for driving the display device 10. In an exemplary embodiment, the integrated circuit may be, but is not limited to, a data driving integrated circuit that generates and provides a data signal DATA. The data driver 30 is connected to a pad PAD arranged in a pad portion PP of the display device 10 to provide the data signal DATA to the pad PAD.

[0129] The contact portion CP may be disposed in the non-display area NDA of the flat area FA.

[0130] In some exemplary embodiments, the contact portion CP may be located in the bending area BA.

[0131] In the following, reference will be made to Figure 6 and Figure 7 The display area DA, the pad portion PP, and the contact portion CP are described in more detail.

[0132] refer to Figure 6 and Figure 7 , the display device 10 may include a plurality of demultiplexers DEMUX, a plurality of pixels 1, a plurality of pads PAD arranged in the pad portion PP, a first fan-out line 71, a second fan-out line 72, a first connection electrode 141, a second connection electrode 143, and a data line DL. The plurality of demultiplexers DEMUX may be arranged in the first direction X. A first demultiplexing selection signal line CLL1 providing a first demultiplexing selection signal CL1 and a second demultiplexing selection signal line CLL2 providing a second demultiplexing selection signal CL2 may pass through the above-mentioned reference numeral 140. Figure 1 and Figure 2 Describe the demultiplexer DEMUX.

[0133] The first demultiplexing selection signal line CLL1 and the second demultiplexing selection signal line CLL2 may extend in the first direction X.

[0134] Despite Figure 6 FIG. 4 shows that the first demultiplexing selection signal line CLL1 is located above the second demultiplexing selection signal line CLL2 in the second direction Y, but the present disclosure is not limited thereto.

[0135] When viewed from the top, the demultiplexer DEMUX may overlap with some neighboring pixels 1 and may not overlap with other pixels 1 .

[0136] The second fan-out line 72 may include a 2-1 fan-out line 72a and a 2-2 fan-out line 72b. It should be noted that, like the first data line DLa and the second data line DLb, the designation of the 2-1 fan-out line 72a and the 2-2 fan-out line 72b is also for distinguishing between them according to the order in which the two fan-out lines of the second fan-out line 72 receive the divided data signals from the demultiplexer DEMUX, and is not necessarily for describing a sequential or chronological order.

[0137] The second connection electrode 143 may include a 2-1 connection electrode 143a and a 2-2 connection electrode 143b. It should be noted that, like the first data line DLa and the second data line DLb, the designation of the 2-1 connection electrode 143a and the 2-2 connection electrode 143b is also for distinguishing between them according to the order in which the two connection electrodes of the second connection electrode 143 receive the divided data signals from the demultiplexer DEMUX, and is not necessarily for describing a sequential or chronological order.

[0138] The demultiplexer DEMUX of the demultiplexing circuit 60 and the pixel 1 may be arranged in the display area DA of the display device 10, the second connection electrode 143 including the 2-1 connection electrode 143a and the 2-2 connection electrode 143b may be arranged in the contact portion CP of the display device 10, and the first connection electrode 141 and the plurality of pads PAD may be arranged in the pad portion PP of the display device 10. The first fan-out line 71 may be arranged across the display area DA, the contact portion CP, and the pad portion PP of the display device 10, and the second fan-out line 72 including the 2-1 fan-out line 72a and the 2-2 fan-out line 72b and the data line DL including the first data line DLa and the second data line DLb may be arranged across the display area DA and the contact portion CP of the display device 10.

[0139] The first fan-out line 71 and the second fan-out line 72 including the 2-1 fan-out line 72a and the 2-2 fan-out line 72b may be electrically connected to the embedded circuit transistor included in the embedded circuit. In some exemplary embodiments, the embedded circuit transistor may correspond to the demultiplexing transistor included in the demultiplexer DEMUX. The first fan-out line 71 and the second fan-out line 72 including the 2-1 fan-out line 72a and the 2-2 fan-out line 72b may be electrically connected to the demultiplexing transistor included in the demultiplexer DEMUX. Figure 7 , each of the demultiplexing transistors of the demultiplexing circuit 60 may include a gate electrode GE1 , a source electrode 145 , and a drain electrode 147 disposed on the embedded circuit semiconductor layer 105 .

[0140] As referenced above Figure 2 As described, the demultiplexing transistor may include a first demultiplexing transistor T DM1 and the second demultiplexing transistor T DM2 The first fan-out line 71 may be connected to the first demultiplexing transistor T DM1 and the second demultiplexing transistor T DM2 Each of the 2-1 fan-out lines 72a can be connected to the first demultiplexing transistor T DM1 , and the 2-2 fan-out line 72b can be connected to the second demultiplexing transistor T DM2 However, it should be understood that the present disclosure is not limited thereto. 2-1 The fan-out line 72a may be connected to the second demultiplexing transistor T DM2 , and the 2-2 fan-out line 72b can be connected to the first demultiplexing transistor T DM1 .

[0141] The pads PAD may be spaced apart from each other in a first direction X crossing a second direction Y from the pad portion PP to the contact portion CP. The data driver 30 may be attached to the pads PAD as described above.

[0142] The data driver 30 may provide a data signal DATA to the pad PAD. The data signal DATA provided from the data driver 30 to the pad PAD may be provided to the first fan-out line 71 through the first connection electrode 141. That is, the pad PAD may be electrically connected to the first fan-out line 71 through the first connection electrode 141. In some exemplary embodiments, the first fan-out line 71 may extend to the demultiplexer DEMUX and may be electrically connected to the demultiplexer DEMUX.

[0143] The second fan-out line 72 may electrically connect the demultiplexing circuit 60 with the data line DL. Specifically, the 2-1 fan-out line 72a may be electrically connected to the demultiplexer DEMUX and the first data line DLa, and the 2-2 fan-out line 72b may be electrically connected to the demultiplexer DEMUX and the second data line DLb.

[0144] In some exemplary embodiments, the second connection electrode 143 may be disposed closer to the display area DA than the first connection electrode 141 .

[0145] The data line DL may be electrically connected to the second connection electrode 143 and the pixel 1. Specifically, the first data line DLa may be electrically connected to the 2-1 connection electrode 143a and the pixel 1, and the second data line DLb may be electrically connected to the 2-2 connection electrode 143b and the pixel 1.

[0146] When viewed in a plan view from the top, the first data line DLa may be located on one side of the first fan-out line 71 in the first direction X, and the second data line DLb may be located on the other side of the first fan-out line 71 in the first direction X. The 2-1 fan-out line 72a may be located closer to one side of the first fan-out line 71 than the first data line DLa in the first direction X, and the 2-2 fan-out line 72b may be located closer to the other side of the first fan-out line 71 than the second data line DLb in the first direction X. However, it should be understood that the arrangement of the first data line DLa, the second data line DLb, the 2-1 fan-out line 72a, and the 2-2 fan-out line 72b is not limited thereto but may be modified in various ways.

[0147] In some exemplary embodiments, the demultiplexer DEMUX may be arranged in the display area DA. In some exemplary embodiments, the demultiplexer DEMUX may overlap with at least some of the pixels 1. For example, the demultiplexing transistor included in the demultiplexer DEMUX may overlap with at least one of the transistors (e.g., transistors T1 to T7) included in the pixel 1. However, it should be understood that the present disclosure is not limited to this. Both the demultiplexer DEMUX and the pixel 1 may be arranged in the display area DA so that they do not overlap each other when viewed in a plan view from the top.

[0148] The stacking structure of the display device 10 will be described. Figure 7 , the display device 10 may include a first circuit portion CCP1, a second circuit portion CCP2, and an interlayer dielectric layer 150 disposed between the first circuit portion CCP1 and the second circuit portion CCP2. Figure 7 Only the second fan-out line 72, the data line DL, the second connection electrode 143, the 2-1 contact hole CNT21, and the 2-2 contact hole CNT22 are shown for illustration, but it should be understood that the stacked structure may include the 2-1 fan-out line 72a, the first data line DLa, the 2-1 connection electrode 143a, the 2-1-1 contact hole CNT21a, and the 2-2-1 contact hole CNT22a (see Figure 6 ), or 2-2 fan-out line 72b, second data line DLb, 2-2 connection electrode 143b, 2-1-2 contact hole CNT21b and 2-2-2 contact hole CNT22b (see Figure 6 ).

[0149] The first circuit portion CCP1, the second circuit portion CCP2 and the interlayer dielectric layer 150 may be arranged in the display area DA and the non-display area NDA. The first circuit portion CCP1, the second circuit portion CCP2 and the interlayer dielectric layer 150 may be arranged on the entire surface of the pad portion PP, the contact portion CP and the display area DA.

[0150] First, the first circuit portion CCP1 will be described. The first circuit portion CCP1 may include at least one embedded circuit. The embedded circuit may include the demultiplexing circuit 60 as described above. Figure 7 , as an example of an embedded circuit, only one demultiplexing transistor included in the demultiplexing circuit 60 is shown. However, it should be noted that the present disclosure is not limited thereto. The first circuit portion CCP1 includes a base substrate 101, a plurality of conductive layers arranged on the base substrate 101, and a plurality of insulating layers arranged between the plurality of conductive layers. In addition, the first circuit portion CCP1 may include the base substrate 101 and a transistor of at least one embedded circuit arranged on the base substrate 101.

[0151] The base substrate 101 surrounds the pad portion PP, the contact portion CP, and the display area DA. The base substrate 101 may support various elements disposed thereon. In some exemplary embodiments, the base substrate 101 may be a flexible substrate including a flexible material such as polyimide (PI).

[0152] The buffer layer 102 may be disposed on the base substrate 101. The buffer layer 102 may be used to prevent moisture and oxygen from penetrating from the outside through the base substrate 101. In some exemplary embodiments, the buffer layer 102 may include silicon nitride (SiN x ), silicon oxide (SiO 2 ) and silicon oxynitride (SiO x N y )

[0153] The embedded circuit semiconductor layer 105 may be disposed on the buffer layer 102. The embedded circuit semiconductor layer 105 forms a semiconductor layer included in the demultiplexer DEMUX (see Figure 2 ) in the channel of the demultiplexing transistor. The embedded circuit semiconductor layer 105 may be arranged in the display area DA. The embedded circuit semiconductor layer 105 may include a source region, a drain region, and an active region.

[0154] The embedded circuit semiconductor layer 105 may include polycrystalline silicon. Polycrystalline silicon may be formed by crystallizing amorphous silicon. Examples of crystallization techniques may include, but are not limited to, rapid thermal annealing (RTA), solid phase crystallization (SPC), excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), continuous lateral solidification (SLS), etc. The portion of the embedded circuit semiconductor layer 105 connected to the source / drain electrode of each transistor in the transistor (i.e., the source / drain region) may be doped with impurity ions (p-type impurity ions in the case of a PMOS transistor). A trivalent dopant such as boron (B) may be used as the p-type impurity ion.

[0155] According to another exemplary embodiment, the embedded circuit semiconductor layer 105 may include single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor. The oxide semiconductor may include, for example, a binary compound (AB) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB x C y ) and quaternary compounds (AB x C y D z ).

[0156] exist Figure 7 In the exemplary embodiment shown in FIG. 1 , the embedded circuit semiconductor layer 105 may include indium tin zinc oxide (ITZO) or indium gallium zinc oxide (IGZO) as an oxide semiconductor.

[0157] The first insulating layer 111 may be disposed on the embedded circuit semiconductor layer 105. In some exemplary embodiments, the first insulating layer 111 may be disposed on the entire surface of the base substrate 101. The first insulating layer 111 may be used as a gate insulator. The first insulating layer 111 may include a silicon compound, a metal oxide, or the like. For example, the first insulating layer 111 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. They may be used alone or in any combination to form the first insulating layer 111.

[0158] The first conductive layer 120 may be disposed on the first insulating layer 111. The first conductive layer 120 may include a gate electrode GE1 of a demultiplexing transistor of an embedded circuit disposed in the display area DA, a first fan-out line 71, and a second fan-out line 72.

[0159] The first conductive layer 120 may include at least one metal selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 120 may include a single layer or multiple layers of the materials listed above.

[0160] The second insulating layer 112 may be disposed on the first conductive layer 120. The second insulating layer 112 may be disposed on the entire surface of the base substrate 101. The second insulating layer 112 may be selected from the materials of the first insulating layer 111 listed above.

[0161] The second conductive layer 140 may be disposed on the second insulating layer 112. In some exemplary embodiments, the second insulating layer 112 may insulate the first conductive layer 120 from the second conductive layer 140. The second conductive layer 140 may include a first connection electrode 141 disposed in the pad portion PP, a second connection electrode 143 disposed in the contact portion CP, and a source electrode 145 and a drain electrode 147 disposed in the display area DA.

[0162] The first connection electrode 141 may be electrically connected to the first fan-out line 71 through a 1-1 contact hole CNT11 penetrating the second insulating layer 112 in the thickness direction Z. The second connection electrode 143 may be electrically connected to the second fan-out line 72 through a 2-1 contact hole CNT21 penetrating the second insulating layer 112 in the thickness direction Z.

[0163] The source electrode 145 and the drain electrode 147 may penetrate the second insulating layer 112 and the first insulating layer 111 in the thickness direction Z to be connected to the source region and the drain region of the embedded circuit semiconductor layer 105 , respectively.

[0164] The gate electrode GE1 , the source electrode 145 , and the drain electrode 147 of the embedded circuit semiconductor layer 105 may form an embedded circuit transistor (eg, a demultiplexing transistor).

[0165] The second conductive layer 140 may include at least one selected from the group consisting of molybdenum (Mo), aluminum (Al), germanium (Ge), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu). The second conductive layer 140 may be composed of a single layer of one of the materials listed above. However, it should be understood that the present disclosure is not limited thereto. The second conductive layer 140 may include a stack of multiple layers. For example, the second conductive layer 140 may have a stack structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc.

[0166] The interlayer dielectric layer 150 may be disposed on the first circuit portion CCP1. In some exemplary embodiments, the interlayer dielectric layer 150 may be disposed directly on the second conductive layer 140 and cover the second conductive layer 140. The interlayer dielectric layer 150 may be used to insulate the conductive layers and semiconductor layers of the first circuit portion CCP1 and the second circuit portion CCP2 from each other. In addition, the interlayer dielectric layer 150 may support a plurality of elements of the second circuit portion CCP2 disposed thereon.

[0167] The interlayer dielectric layer 150 may include a plurality of layers. For example, the insulating material contained in the interlayer dielectric layer 150 may include an inorganic insulating material or an organic insulating material. The inorganic insulating material may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These inorganic insulating materials may be used alone or in combination. The organic insulating material may include at least one of the following: polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB), etc.

[0168] refer to Figure 7 For convenience of explanation, the interlayer dielectric layer 150 shown includes an organic insulating material. The interlayer dielectric layer 150 including the organic insulating material may be used as a planarization layer for providing a planar upper surface.

[0169] Hereinafter, the second circuit portion CCP2 will be described. The second circuit portion CCP2 may include a pixel 1 (see Figure 7 That is, the second circuit portion CCP2 may include the above reference Figure 3 A transistor and an organic light emitting diode OLED of a pixel 1 are described.

[0170] The stack structure of the second circuit portion CCP2 will be described. The second circuit portion CCP2 includes a plurality of conductive layers disposed on the interlayer dielectric layer 150 and a plurality of insulating layers disposed between the plurality of conductive layers.

[0171] The pixel semiconductor layer 155 may be disposed on the interlayer dielectric layer 150. The pixel semiconductor layer 155 may form the first transistor T1 to the seventh transistor T7 of the pixel 1 (see Figure 3 ) channel. For ease of explanation, Figure 7 Only one of the transistors included in the pixel 1 is illustrated as an example.

[0172] The pixel semiconductor layer 155 may be arranged in each of the pixels 1 in the display area DA. The pixel semiconductor layer 155 may include a source region, a drain region, and an active region. The pixel semiconductor layer 155 may include polycrystalline silicon. According to another exemplary embodiment, the pixel semiconductor layer 155 may include single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor.

[0173] In some exemplary embodiments, the pixel semiconductor layer 155 may overlap the embedded circuit semiconductor layer 105 in the thickness direction Z.

[0174] In some exemplary embodiments, the embedded circuit semiconductor layer 105 and the pixel semiconductor layer 155 may include the same material. For example, the embedded circuit semiconductor layer 105 and the pixel semiconductor layer 155 may include the same polysilicon. Alternatively, in some exemplary embodiments, the embedded circuit semiconductor layer 105 and the pixel semiconductor layer 155 may include different materials. For example, the embedded circuit semiconductor layer 105 may include an oxide semiconductor, and the pixel semiconductor layer 155 may include polysilicon. In another exemplary embodiment, the embedded circuit semiconductor layer 105 may include polysilicon, and the pixel semiconductor layer 155 may include an oxide semiconductor.

[0175] The third insulating layer 161 may be disposed on the pixel semiconductor layer 155. The third insulating layer 161 may be disposed on the entire surface of the interlayer dielectric layer 150. The third insulating layer 161 may serve as a gate insulator. In some exemplary embodiments, the third insulating layer 161 may include the same material as the first insulating layer 111, or may include one of the inorganic insulating materials listed above as examples of the first insulating layer 111.

[0176] The third conductive layer 170 may be disposed on the third insulating layer 161. The third conductive layer 170 may include gate electrodes of the first to seventh transistors T1 to T7 of the pixels 1 disposed in the display area DA and a storage capacitor Cst (see Figure 3 )'s first electrode CE1. Figure 7 1, one gate electrode GE2 among the gate electrodes of the first transistor T1 to the seventh transistor T7 of the pixel 1 is illustrated as an example. In some exemplary embodiments, the gate electrode GE2 may be, but is not limited to, the seventh transistor T7 of the pixel 1 (see Figure 3 ) of the gate electrode.

[0177] The third conductive layer 170 may include at least one metal selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer 170 may include a single layer or multiple layers of the materials listed above.

[0178] The fourth insulating layer 162 may be disposed on the third conductive layer 170. The fourth insulating layer 162 may be disposed on the entire surface of the interlayer dielectric layer 150. The fourth insulating layer 162 may be selected from the materials of the third insulating layer 161 listed above.

[0179] The fourth conductive layer 180 may be disposed on the fourth insulating layer 162. The fourth insulating layer 162 may insulate the third conductive layer 170 from the fourth conductive layer 180. The fourth conductive layer 180 may include a storage capacitor Cst (see Figure 3 The fourth conductive layer 180 may be selected from the materials of the third conductive layer 170 listed above.

[0180] The fifth insulating layer 163 may be disposed on the fourth conductive layer 180. The fifth insulating layer 163 may include at least one of the above-listed materials of the third insulating layer 161. In some exemplary embodiments, the fifth insulating layer 163 may include an organic insulating material.

[0181] The fifth conductive layer 190 may be disposed on the fifth insulating layer 163. The fifth conductive layer 190 may include a data line DL, a pixel source electrode 191, a pixel drain electrode 193, and a pad PAD disposed in the pad portion PP. The 1-2 contact hole CNT12 and the 2-2 contact hole CNT22 may be formed to penetrate the interlayer dielectric layer 150, the third insulating layer 161, the fourth insulating layer 162, and the fifth insulating layer 163 in the thickness direction Z in the pad portion PP and in the contact portion CP, respectively.

[0182] The pad PAD may overlap the first connection electrode 141 of the above-mentioned first circuit portion CCP1 in the thickness direction Z, and may be connected to the first connection electrode 141 through the 1-2 contact hole CNT12. The data line DL may overlap the second connection electrode 143 of the first circuit portion CCP1 in the thickness direction Z, and may be connected to the second connection electrode 143 through the 2-2 contact hole CNT22. In addition, the data line DL may be electrically connected to the pixel source electrode 191, and the pixel source electrode 191 is connected to the source region of the pixel semiconductor layer 155. In some exemplary embodiments, the data line DL and the pixel source electrode 191 may not be directly connected to each other, but may be electrically connected to each other through a separate line or a separate transistor. The pixel drain electrode 193 may be connected to the drain region of the pixel semiconductor layer 155.

[0183] The gate electrode GE2, the pixel semiconductor layer 155, the pixel source electrode 191, and the pixel drain electrode 193 may form a thin film transistor. The thin film transistor may be included in the above reference Figure 3 The thin film transistor may correspond to one of the transistors T1, T2, T3, T4, T5, T6 and T7 in the pixel 1 described above. For example, the thin film transistor may be Figure 3 The seventh transistor T7 or the sixth transistor T6 shown in FIG. 1 is connected to the anode electrode ANO of the organic light emitting diode OLED.

[0184] The fifth conductive layer 190 may include at least one selected from the group consisting of molybdenum (Mo), aluminum (Al), germanium (Ge), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu). The fifth conductive layer 190 may include a single layer of one of the materials listed above. However, it should be understood that the present disclosure is not limited thereto. The fifth conductive layer 190 may include a stack of multiple layers. For example, the fifth conductive layer 190 may have a stack structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc.

[0185] The sixth insulating layer 164 may be disposed on the fifth conductive layer 190. The sixth insulating layer 164 may include an organic insulating material.

[0186] The anode electrode ANO is disposed on the sixth insulating layer 164 in the display area DA. The anode electrode ANO may pass through the sixth insulating layer 164 to be electrically connected to the pixel drain electrode 193.

[0187] The bank layer BANK may be arranged on the anode electrode ANO. In some exemplary embodiments, the bank layer BANK may be arranged in the display area DA and may be further arranged in the contact portion CP. The bank layer BANK may include an opening through which the anode electrode ANO is exposed. The bank layer BANK may include an organic insulating material. For example, the bank layer BANK may include at least one of a photoresist, a polyimide resin, an acrylic resin, a polyacrylic resin, and the like.

[0188] The organic layer OL may be disposed on the upper surface of the anode electrode ANO and the opening of the bank layer BANK. The organic layer OL may include an organic light emitting layer and may emit light of a specific color. For example, the light emitted by the organic layer OL may be one of red light, green light, and blue light.

[0189] The cathode electrode CAT is disposed on the organic layer OL and the bank layer BANK. The cathode electrode CAT may be a common electrode disposed across a plurality of pixels 1 .

[0190] The anode electrode ANO, the organic layer OL, and the cathode electrode CAT may form an organic light emitting diode OLED.

[0191] The thin film encapsulation layer TFE is arranged on the cathode electrode CAT. The thin film encapsulation layer TFE may be arranged across the display area DA and the contact portion CP. The thin film encapsulation layer TFE may cover the organic layer OL. The thin film encapsulation layer TFE may include a stacked layer including one or more inorganic layers and one or more organic layers alternately stacked on each other. For example, the thin film encapsulation layer TFE may include a first inorganic encapsulation film TFE1, an organic encapsulation film TFE2, and a second inorganic encapsulation film TFE3 stacked on each other in sequence. In some exemplary embodiments, the organic encapsulation film TFE2 may be disposed closer to the organic light emitting diode OLED than the second inorganic encapsulation film TFE3, and the second inorganic encapsulation film TFE3 covers the side surface of the organic encapsulation film TFE2 and may be in direct contact with the upper surface of the first inorganic encapsulation film TFE1, such as Figure 7 The stacked structure of the thin film encapsulation layer TFE prevents the organic encapsulation film TFE2 from flowing to the outside.

[0192] In some exemplary embodiments, the thin film encapsulation layer TFE may not be disposed in the pad portion PP.

[0193] In the display device 10 according to the above exemplary embodiment, the embedded circuit or demultiplexing circuit 60 (see Figure 1 and Figure 7 ) and pixel 1 (see Figure 1 and Figure 7 ) may be arranged in the display area DA. That is, the embedded circuit may be included in the first circuit portion CCP1 arranged on a different layer from the second circuit portion CCP2. In this way, the dead zone of the display device 10 may be reduced. In some exemplary embodiments, the embedded circuit may overlap with the pixel 1. For example, the demultiplexing transistor included in the demultiplexing circuit 60 may overlap with the transistor included in the pixel 1 (see Figure 7 ). In this case, the integration degree of the display device 10 can be improved while reducing the dead area.

[0194] Hereinafter, a display device according to other exemplary embodiments of the present disclosure will be described. In the following description, the same or similar elements will be denoted by the same or similar reference numerals, and redundant descriptions will be omitted or briefly described.

[0195] Figure 8 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure.

[0196] Figure 8 The display device 10_1 shown in FIG. 1 is substantially the same as the display device 10 according to the above exemplary embodiment, except that the interlayer dielectric layer 150_1 includes multiple layers. Therefore, redundant descriptions will be omitted, and the description will focus on the differences between the interlayer dielectric layer 150_1 and the interlayer dielectric layer 150.

[0197] More specifically, the interlayer dielectric layer 150_1 of the display device 10_1 may include a first interlayer dielectric layer 150a and a second interlayer dielectric layer 150b disposed on the first interlayer dielectric layer 150a. The first interlayer dielectric layer 150a may be an inorganic interlayer dielectric layer having a polished surface, and the second interlayer dielectric layer 150b may be an organic interlayer dielectric layer including an organic material. The first interlayer dielectric layer 150a may be disposed on the second conductive layer 140, and may be in direct contact with a plurality of electrodes of the second conductive layer 140 and a portion of the second insulating layer 112 exposed by the plurality of electrodes of the second conductive layer 140.

[0198] The 1-2 contact hole CNT12 and the 2-2 contact hole CNT22 may penetrate the first interlayer dielectric layer 150 a , the second interlayer dielectric layer 150 b , the third insulating layer 161 , the fourth insulating layer 162 , and the fifth insulating layer 163 in the thickness direction Z.

[0199] Since the interlayer dielectric layer 150_1 of the display device 10_1 includes the first and second interlayer dielectric layers 150a and 150b including different materials, the upper surface of the interlayer dielectric layer 150_1 may become flatter. As a result, the elements of the second circuit part CCP2 may be more stably formed on the interlayer dielectric layer 150_1.

[0200] Fig. 9 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure.

[0201] Fig. 9 The display device 10_2 shown in FIG. Figure 8 The display device 10_1 shown in FIG. 1 is substantially the same except that the positions of the first interlayer dielectric layer 150 a and the second interlayer dielectric layer 150 b of the interlayer dielectric layer 150_2 are reversed.

[0202] More specifically, the second interlayer dielectric layer 150b including an organic insulating material may be disposed on the second conductive layer 140 and may be in direct contact with the plurality of electrodes of the second conductive layer 140 and portions of the second insulating layer 112 exposed by the plurality of electrodes of the second conductive layer 140. The first interlayer dielectric layer 150a including an inorganic insulating material may be disposed on the second interlayer dielectric layer 150b, and the second circuit portion CCP2 may be disposed on the first interlayer dielectric layer 150a.

[0203] Other components are the same as above Figure 7 The other elements described are the same; and therefore, redundant descriptions will be omitted.

[0204] Fig.10is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure.

[0205] Fig.10 The display device 10_3 shown in FIG. Figure 7 The display device 10 shown in FIG. 1 is substantially the same except that the embedded circuit of the first circuit portion CCP1_1 has a bottom gate structure.

[0206] More specifically, in the display device 10_3 , transistors (eg, demultiplexing transistors) included in the embedded circuit of the first circuit portion CCP1_1 may be bottom gate type. That is, a first conductive layer 120_1 including a gate electrode GE1_1 , a first fan-out line 71_1 , and a second fan-out line 72_1 may be disposed on the buffer layer 102 .

[0207] The first insulating layer 111 may be disposed on the first conductive layer 120_1, and the embedded circuit semiconductor layer 105_1 may be disposed on the first insulating layer 111. A 1-1 contact hole CNT11 exposing the first fan-out line 71_1 and a 2-1 contact hole CNT21 exposing the second fan-out line 72_1 may be formed penetrating the first insulating layer 111.

[0208] The second conductive layer 140 may be disposed on the embedded circuit semiconductor layer 105_1. As described above, the second conductive layer 140 may include a first connection electrode 141, a second connection electrode 143, a source electrode 145, and a drain electrode 147. The first connection electrode 141 is connected to the first fan-out line 71_1 through the 1-1 contact hole CNT11, and the second connection electrode 143 is connected to the second fan-out line 72_1 through the 2-1 contact hole CNT21. The source electrode 145 and the drain electrode 147 may contact the embedded circuit semiconductor layer 105_1.

[0209] The interlayer dielectric layer 150 may be disposed on the second conductive layer 140. A 1-2 contact hole CNT12 exposing the first connection electrode 141 and a 2-2 contact hole CNT22 exposing the second connection electrode 143 may be formed to penetrate the interlayer dielectric layer 150.

[0210] The second circuit part CCP2 may be disposed on the interlayer dielectric layer 150. The pad PAD may be connected to the first connection electrode 141 through the 1-2 contact hole CNT12, and the data line DL may be connected to the second connection electrode 143 through the 2-2 contact hole CNT22.

[0211] Other components are the same as above Figure 7 The other elements described are the same; and therefore, redundant descriptions will be omitted.

[0212] Fig.11is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure.

[0213] Fig.11 The display device 10_4 shown in FIG. Figure 7 The display device 10 shown in FIG. 1 is substantially the same, except that the second circuit portion CCP2_1 includes transistors of the bottom-gate type.

[0214] More specifically, the third conductive layer 170_1 including the gate electrode GE2_1 may be disposed on the interlayer dielectric layer 150. As described above, the gate electrode GE2_1 may be a gate electrode of one of the transistors included in the pixel 1.

[0215] The third insulating layer 161 may be disposed on the third conductive layer 170_1 , and the pixel semiconductor layer 155_1 may be disposed on the third insulating layer 161 .

[0216] A fourth conductive layer 190 including a pad PAD, a data line DL, a pixel source electrode 191 , and a pixel drain electrode 193 may be disposed on the pixel semiconductor layer 155_1 and the third insulating layer 161 , and a sixth insulating layer 164 may be disposed on the fourth conductive layer 190 .

[0217] The 1-2 contact hole CNT12 and the 2-2 contact hole CNT22 may be formed to penetrate the interlayer dielectric layer 150 and the third insulating layer 161 .

[0218] Other components are the same as above Figure 7 The other elements described are the same; and therefore, redundant descriptions will be omitted.

[0219] Fig.12 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure.

[0220] Fig.12 The display device 10_5 shown in FIG. Figure 7 The display device 10 shown in FIG. 1 is substantially the same except that the first circuit portion CCP1_1 and the second circuit portion CCP2_1 include transistors of the bottom-gate type.

[0221] The first circuit part CCP1_1 is similar to the above reference Fig.10 The first circuit portion CCP1_1 described above is identical to the first circuit portion CCP1_1 described above, and the second circuit portion CCP2_1 is identical to the first circuit portion CCP1_1 described above. Fig.11 The second circuit portion CCP2_1 described is identical. Therefore, a redundant description will be omitted.

[0222] Fig.13 According to another exemplary embodiment of the present disclosure Figure 4 Magnified view of area A shown in FIG.

[0223] Fig.13 The display device shown in Figure 6 The display device shown in is substantially the same as that shown in , except that the former further includes a demultiplexer DEMUXa in addition to the demultiplexer DEMUX.

[0224] like Fig.13 As shown in , the demultiplexer DEMUXa may not be aligned with the demultiplexer DEMUX in the first direction X, but may be arranged close to the upper side in the second direction Y. However, it should be understood that the present disclosure is not limited thereto. Fig.13 Unlike the exemplary embodiment shown in , the demultiplexer DEMUXa may be disposed closer to the lower side in the second direction Y than the demultiplexer DEMUX.

[0225] When the demultiplexer DEMUX is connected to the first demultiplexing selection signal line CLL1 and the second demultiplexing selection signal line CLL2, the demultiplexer DEMUXa may not be connected to the first demultiplexing selection signal line CLL1 and the second demultiplexing selection signal line CLL2, but may be connected to different demultiplexing selection signal lines including the first demultiplexing selection signal line CLL1a and the second demultiplexing selection signal line CLL2a.

[0226] For example, the first and second demultiplexing selection signal lines CLL1 a and CLL2 a may be disposed in the second direction Y above the first and second demultiplexing selection signal lines CLL1 and CLL2 .

[0227] Fig.14 is a perspective view of a display device according to still another exemplary embodiment of the present disclosure. Fig.15 is a plan view illustrating a layout of a display device according to still another exemplary embodiment of the present disclosure. Fig.16 is along Fig.15 A cross-sectional view taken along line XVI-XVI' shown in FIG.

[0228] according to Figures 14 to 16 The display device 10_6 of the exemplary embodiment shown in FIG. 1 is substantially the same as the display device 10 according to the above exemplary embodiment, except that a rigid substrate is adopted in the display device 10_6 .

[0229] More specifically, the display device 10_6 may include a display unit DU, a touch unit TDU, and a sealing member SEAL for sealing side surfaces of the display unit DU and the touch unit TDU.

[0230] The display unit DU may include a first circuit portion CCP1_2 and a second circuit portion CCP2 (the first circuit portion CCP1_2 and the second circuit portion CCP2 include a rigid substrate including rigid glass or quartz) and an interlayer dielectric layer 150 disposed between the first circuit portion CCP1_2 and the second circuit portion CCP2. The first circuit portion CCP1_2 has substantially the same configuration as the first circuit portion CCP1 described above, except that Figure 7 The base substrate 101 shown in FIG. 1 may include materials other than the rigid material; and thus, a redundant description will be omitted.

[0231] The touch unit TDU may include a touch base substrate TSUB disposed on the display unit DU and a touch sensor layer TSL disposed on the touch base substrate TSUB. The touch sensor layer TSL may include at least one touch conductive layer and at least one touch insulating layer. The touch conductive layer may include touch electrodes and touch wires.

[0232] In some exemplary embodiments, the touch base substrate TSUB may be a package substrate of the display device 10_6.

[0233] When viewed from the top, the sealing member SEAL may be used to seal the edge between the rigid substrate of the first circuit part CCP1_2 and the touch base substrate TSUB. According to some exemplary embodiments, the sealing member SEAL may include glass frit, etc.

[0234] Like the display device 10 according to the above exemplary embodiment, the display device 10_6 may include a display area DA displaying an image and a non-display area NDA located around the display area DA. A sealing member SEAL may be disposed in the non-display area NDA of the display device 10_6.

[0235] In the display device 10_6, the embedded circuit and the pixel may be arranged in the display area DA. Specifically, the embedded circuit may be included in the first circuit portion CCP1_2 and arranged on a different layer from the second circuit portion CCP2 including the pixel, and the embedded circuit and the pixel may overlap each other in the display area DA. In this way, the border width of the display device 10_6 may be reduced.

[0236] Embedded circuits and pixels are similar to those referenced above Figures 1 to 7 The described embedded circuits and pixels are the same; and therefore, redundant descriptions will be omitted.

[0237] Fig.17 is a plan view illustrating a layout of a display device according to another exemplary embodiment of the present disclosure. Fig.18 yes Fig.17 Schematic cross-sectional view of a display device shown in . Fig.19 yes Fig.17 An enlarged view of part B.

[0238] according to Figures 17 to 19 The display device 10_7 of the exemplary embodiment shown in FIG. 1 is substantially the same as the display device 10 according to the above exemplary embodiment, except that Figure 4 and Figure 5 The data driver 30 shown in FIG. 8 is not mounted on the second circuit portion CCP2 but is mounted outside the printed circuit board 80_1.

[0239] More specifically, the data driver 30 according to this exemplary embodiment may be used as a chip mounted on a film on the printed circuit board 80_1 .

[0240] refer to Fig.17 and Fig.18 , the pad portion PP_1 may refer to an area where the printed circuit board 80_1 is attached to the non-display area NDA of the display device 10_7.

[0241] The pad part PP_1 is the same as the reference above Figures 5 to 7 The pad portion PP of the display device 10 described is substantially the same except that a printed circuit board 80_1 is attached instead of the data driver 30 .

[0242] Fig. 20 is a perspective view of a display device according to still another exemplary embodiment of the present disclosure. Fig.21 yes Fig. 20 An expanded view of the display device. Fig. 22 yes Fig. 20 Schematic cross-sectional view of a display device. Fig.23 yes Fig.21 Magnified view of area C.

[0243] according to Figure 20 to Figure 23 In the display device 10_8 of the exemplary embodiment shown in , the display area DA may include a main display area DA0 and first to fourth auxiliary display areas DA1 to DA4. The main display area DA0 may correspond to the flat area FA of the display device 10_8, and the first auxiliary display area DA1, the second auxiliary display area DA2, the third auxiliary display area DA3 and the fourth auxiliary display area DA4 may be located on the side area SA of the display device 10_8. The side area SA may be located substantially in the same plane, but may be located on a plane different from the plane of the flat area FA. The side area SA may be bent from the flat area FA in a downward direction or in a third direction Z intersecting the first direction X and the second direction Y in the accompanying drawings. As shown Fig. 20As shown in , although the flat area FA and the side area SA are shown as being substantially orthogonal to each other, there may be an acute angle or an obtuse angle between the flat area FA and the side area SA. In addition, in some exemplary embodiments, the flat area FA may partially include a curved surface. In addition, the side area SA may partially include a curved surface, or the entire side area SA may include a curved surface.

[0244] The first auxiliary display area DA1 may be connected to the main display area DA0. Similarly, each of the second auxiliary display area DA2, the third auxiliary display area DA3, and the fourth auxiliary display area DA4 may be connected to the main display area DA0. In some exemplary embodiments, Fig. 20 and Fig.21 As shown in the figure, the first auxiliary display area DA1 can be located on the left side of the main display area DA0, the second auxiliary display area DA2 can be located on the right side of the main display area DA0, the third auxiliary display area DA3 can be located on the upper side of the main display area DA0, and the fourth auxiliary display area DA4 can be located on the lower side of the main display area DA0.

[0245] The non-display area NDA may include a first non-display area NDA1, a second non-display area NDA2, a third non-display area NDA3, and a fourth non-display area NDA4. In some exemplary embodiments, Fig. 20 and Fig.21 As shown in , when viewed from the top, the first non-display area NDA1 may be located on the left side of the first auxiliary display area DA1. That is, in the case where the first auxiliary display area DA1 is located therebetween, the first non-display area NDA1 may be located on the opposite side of the main display area DA0. When viewed from the top, the second non-display area NDA2 may be located on the right side of the second auxiliary display area DA2. That is, in the case where the second auxiliary display area DA2 is located therebetween, the second non-display area NDA2 may be arranged on the opposite side of the main display area DA0. When viewed from the top, the third non-display area NDA3 may be located on the upper side of the third auxiliary display area DA3. That is, in the case where the third auxiliary display area DA3 is located therebetween, the third non-display area NDA3 may be located on the opposite side of the main display area DA0. When viewed from the top, the fourth non-display area NDA4 may be located on the lower side of the fourth auxiliary display area DA4. That is, in the case where the fourth auxiliary display area DA4 is located therebetween, the fourth non-display area NDA4 may be located on the opposite side of the main display area DA0. The fourth non-display area NDA4 may include a pad portion PP.

[0246] Despite Fig.21The pad portion PP is shown as being arranged only in the fourth non-display area NDA4, but the present disclosure is not limited thereto. For example, the pad portion PP may be arranged in one of the first non-display area NDA1, the second non-display area NDA2, and the third non-display area NDA3, may be arranged in each of the fourth non-display area NDA4 and the third non-display area NDA3, may be arranged in each of the first non-display area NDA1 and the second non-display area NDA2, may be arranged in three of the first non-display area NDA1, the second non-display area NDA2, the third non-display area NDA3, and the fourth non-display area NDA4, or may be arranged in each of the first non-display area NDA1, the second non-display area NDA2, the third non-display area NDA3, and the fourth non-display area NDA4.

[0247] According to an exemplary embodiment of the present disclosure, the non-display area NDA may further include a fifth non-display area NDA5 , a sixth non-display area NDA6 , a seventh non-display area NDA7 , and an eighth non-display area NDA8 .

[0248] The fifth non-display area NDA5, the sixth non-display area NDA6, the seventh non-display area NDA7 and the eighth non-display area NDA8 may be located at the corners of the display device 10_8, respectively. The fifth non-display area NDA5 may be located between the first auxiliary display area DA1 and the third auxiliary display area DA3 and / or between the first non-display area NDA1 and the third non-display area NDA3. The sixth non-display area NDA6 may be located between the second auxiliary display area DA2 and the third auxiliary display area DA3 and / or between the second non-display area NDA2 and the third non-display area NDA3. The seventh non-display area NDA7 may be located between the first auxiliary display area DA1 and the fourth auxiliary display area DA4 and / or between the first non-display area NDA1 and the fourth non-display area NDA4. The eighth non-display area NDA8 may be located between the second auxiliary display area DA2 and the fourth auxiliary display area DA4 and / or between the second non-display area NDA2 and the fourth non-display area NDA4.

[0249] The fifth non-display area NDA5, the sixth non-display area NDA6, the seventh non-display area NDA7, and the eighth non-display area NDA8 may be folded toward the inside (i.e., toward the inner space or the center of gravity of the display device 10_8). In this case, the fifth non-display area NDA5, the sixth non-display area NDA6, the seventh non-display area NDA7, and the eighth non-display area NDA8 may be bent along corresponding bending lines among the plurality of bending lines CL, respectively.

[0250] At least one of the sides of the display device 10_8 may be curved. Figure 20 to Figure 22As shown in , the display area DA of the display device 10_8 may be arranged in some of the side areas SA and the flat area FA, the contact portion CP may be arranged in at least one of the side areas SA, and the pad portion PP may be arranged in the auxiliary flat area SFA. The auxiliary flat area SFA may extend from the side area SA in which the contact portion CP is arranged to face the flat area FA, and may be located in a plane different from that of the flat area FA.

[0251] refer to Fig. 22 and Fig.23 , the contact portion CP may be disposed in a portion of the fourth non-display area NDA4 adjacent to the fourth auxiliary display area DA4, and the pad portion PP may be disposed in another portion of the fourth non-display area NDA4.

[0252] In some exemplary embodiments, Fig. 22 and Fig.23 Unlike shown in FIG. 2 , the pad portion PP may be disposed on a portion of the side area SA.

[0253] Although exemplary embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure as disclosed in the accompanying claims.

Claims

1. A display device, comprising: a display area and a non-display area located around the display area, the non-display area including a pad portion and a contact portion arranged between the display area and the pad portion, a first circuit portion including an embedded circuit arranged in the display area, a first connection electrode arranged in the pad portion, and a second connection electrode arranged in the contact portion; as well as a second circuit portion, arranged on a different layer from the first circuit portion, and comprising pixels arranged in the display area, pads arranged in the pad portion, and data lines extending across the contact portion and the display area and electrically connected to the pixels, wherein the pad is electrically connected to the embedded circuit through the first connecting electrode, and The data line is electrically connected to the embedded circuit through the second connecting electrode.

2. The display device according to claim 1, further comprising: A first fan-out line connecting the first connection electrode and the embedded circuit; and a second fan-out line connecting the embedded circuit and the second connection electrode, wherein the first fan-out line extends across the pad portion, the contact portion, and the display area, and the second fan-out line extends across the display area and the contact portion.

3. The display device according to claim 2, wherein: The first connection electrode and the second connection electrode are disposed on the same first layer and include the same first material, and wherein the pad and the data line are disposed on the same second layer and include the same second material.

4. The display device according to claim 3, wherein: The first fan-out line and the second fan-out line are arranged on a same third layer and include a same third material, and wherein the third layer is different from the first layer.

5. The display device according to claim 4, wherein: The pixel includes a pixel transistor and a light emitting element electrically connected to the pixel transistor, and wherein the embedded circuit includes an embedded circuit transistor.

6. The display device according to claim 5, wherein: The pixel transistor includes a pixel semiconductor layer, and the embedded circuit transistor includes an embedded circuit semiconductor layer, and wherein the pixel semiconductor layer and the embedded circuit semiconductor layer include different materials.

7. The display device according to claim 6, wherein: One of the embedded circuit semiconductor layer and the pixel semiconductor layer includes an oxide semiconductor, and the other of the embedded circuit semiconductor layer and the pixel semiconductor layer includes polysilicon.

8. The display device according to claim 5, wherein: The pixel transistor includes a pixel semiconductor layer, a pixel gate electrode arranged on the pixel semiconductor layer, and a pixel source electrode and a pixel drain electrode arranged on the pixel gate electrode, wherein the pixel source electrode and the pixel drain electrode are electrically connected to the pixel semiconductor layer, and the pixel source electrode and the pixel drain electrode are arranged on the same layer as the pad.

9. The display device according to claim 8, wherein: The embedded circuit transistor includes an embedded circuit semiconductor layer, an embedded circuit gate electrode arranged on the embedded circuit semiconductor layer, and an embedded circuit source electrode and an embedded circuit drain electrode arranged on the embedded circuit gate electrode, and wherein the embedded circuit source electrode and the embedded circuit drain electrode are arranged on the same layer as the first connecting electrode.

10. The display device according to claim 1, wherein: When viewed in a plan view from the top, the second connection electrode is closer to the display area than the first connection electrode.

11. The display device according to claim 1, further comprising: An interlayer dielectric layer is disposed between the first circuit portion and the second circuit portion.

12. The display device according to claim 11, wherein: The interlayer dielectric layer is in direct contact with the first connection electrode and the second connection electrode.

13. A display device comprising: a display area and a non-display area located around the display area, the non-display area including a pad portion and a contact portion arranged between the display area and the pad portion, a first circuit portion including a demultiplexer arranged in the display area, a first connection electrode arranged in the pad portion, and a second connection electrode arranged in the contact portion; as well as a second circuit portion, arranged on a different layer from the first circuit portion, and comprising pixels arranged in the display area, pads arranged in the pad portion, and at least one data line extending across the contact portion and the display area and electrically connected to the pixels, wherein the pad is electrically connected to the demultiplexer through the first connection electrode and provides a data signal to the demultiplexer, wherein the at least one data line is electrically connected to the demultiplexer via the second connection electrode, and The demultiplexer generates divided data signals by dividing the data signal received from the pad using time division multiplexing.

14. The display device according to claim 13, wherein: The at least one data line includes a first data line and a second data line that respectively provide the divided data signals.

15. The display device according to claim 14, wherein: The second connection electrodes include a 2-1 connection electrode connecting the demultiplexer and the first data line and a 2-2 connection electrode connecting the demultiplexer and the second data line.

16. The display device according to claim 15, further comprising: connecting the first connection electrode and a first fan-out line of the demultiplexer; and a second fan-out line connecting the demultiplexer and the second connection electrode, wherein the first fan-out line extends across the pad portion, the contact portion, and the display region, and the second fan-out line extends across the display region and the contact portion.

17. The display device according to claim 16, wherein: The second fan-out lines include a 2-1 fan-out line connecting the demultiplexer and the 2-1 connection electrode and a 2-2 fan-out line connecting the demultiplexer and the 2-2 connection electrode.

18. The display device according to claim 13, wherein: The at least one data line extends in a first direction, and wherein the first circuit portion includes a plurality of demultiplexers arranged along a second direction crossing the first direction.

19. The display device according to claim 18, wherein: The same demultiplexing selection signal line is connected to the plurality of demultiplexers.

20. The display device according to claim 13, wherein: The at least one data line extends in a first direction and includes a plurality of data lines arranged along a second direction intersecting the first direction, wherein the first circuit portion includes a plurality of demultiplexers, the plurality of demultiplexers include a first demultiplexer and a second demultiplexer, and wherein the first demultiplexer and the second demultiplexer are connected to different data lines among the plurality of data lines.

21. The display device according to claim 20, wherein: The first demultiplexer and the second demultiplexer are connected to different demultiplexing selection signal lines.

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