Apparatus and method for generating time resolution for electronic devices

Abstract

An apparatus for generating temporal resolution for an electronic device. The apparatus receives input from a sub-gate delay resolution arrangement and has processing circuitry configured to selectively invert a set of bits in a sampling matrix sampled at a sampling instance based on a first predefined reference node of the sub-gate delay resolution arrangement to provide a unary code. The unary code is then compressed and a mapping is expanded based on the compressed unary code using the values ​​of the selected bits. The apparatus then provides an output based on the expansion. Thus, the arrangement makes it possible to use sub-gate delays for a number of different applications.

Description

Technical Field

[0001] The following description relates generally to the field of electronic devices and, more particularly, to apparatus and methods for generating temporal resolution for electronic devices that is resilient to mismatch-induced sampling errors. Background Art

[0002] High-resolution timing is a crucial aspect of many modern integrated circuit applications. One example of an application requiring high-resolution timing is modern data communications networks. These networks use high-speed and high-resolution analog-to-digital converters and time-to-digital converters. An example of such a modern data communications network is 5G, where high bandwidth and latency requirements necessitate high-resolution timing.

[0003] Designing an analog-to-digital converter using time-domain circuit techniques involves converting the analog input signal into a time-domain signal using a voltage-to-time converter. The resulting time-domain signal is then sampled and quantized into a digital signal using a time-to-digital converter. The resolution of a time-domain analog-to-digital converter is determined by the gain of the voltage-to-time conversion and the resolution of the time-to-digital conversion.

[0004] Traditionally, time resolution has been determined by the delay of the inverters used in the converter. Therefore, the delay is at least partially technology-dependent. To further improve time resolution, inverter delay solutions have been introduced, such as vernier time-to-digital converters and pulse-squeezing converters.

[0005] However, with the continuing demand for higher bandwidth and shorter latency, there is a need for improved apparatus and methods for generating improved temporal resolution.

[0006] One solution to this problem is to use a grid arrangement, such as a ring-coupled ring oscillator (RCRO). A RCO refers to an arrangement in which multiple ring oscillators (M) are coupled in a ring-shaped fashion, thereby forming a ring. When properly designed, the individual ring oscillators establish a phase relationship with each other such that 2×N×M phase steps uniformly distributed between 0 and 2π can be extracted from the structure. The resulting time step between temporally adjacent phase steps is approximately 1 / M of the inverter delay. Thus, sub-gate delay resolution is achieved. When this arrangement is used in a ring oscillator TDC architecture instead of a conventional ring oscillator, arbitrarily small time steps can be achieved without sacrificing conversion time, regardless of technology.

[0007] Grid arrangements, such as those in ring-coupled ring oscillators, enable arbitrarily small phase quantization steps of sub-gate delays. When data converters based on ring-coupled ring oscillators are implemented in deeply scaled semiconductor technologies, phase quantization steps approach picoseconds or even shorter. It is well known that in highly scaled semiconductor technologies, wire delays dominate gate delays. Therefore, even in carefully laid-out designs, wiring delay mismatches can easily exceed the phase quantization step size of the ring-coupled ring oscillator. This leads to erroneous sampling of the phase signal. A range of non-ideal circuit conditions can arise that cause delay mismatches in the phase signal, which can lead to erroneous sampling. These include mismatches in: propagation delay from low to high versus propagation delay from high to low, rise delay versus fall delay, low drive strength versus high drive strength, drive strength between ring-coupled ring oscillator nodes, loading between ring-coupled ring oscillator nodes, wiring delays between nodes, and clock skew between flip-flops in registers. The net effect of these mismatches can be modeled by delay mismatches between nodes in the phase signal. When the amount of mismatch approaches the phase quantization step size of the RCO, which is very likely to happen when designing RCO-based converters in deep scaling techniques, errors may appear in the sampled phase signal. These errors will cause larger errors at the converter output, thus degrading performance. Summary of the Invention

[0008] A device and method for encoding a sampled phase signal. The device receives input from a sub-gate delay resolution arrangement and has processing circuitry, wherein the processing circuitry is configured to selectively invert a set of bits in a sampling matrix sampled in a sampling instance based on a first predefined reference node of the sub-gate delay resolution arrangement to provide a unary code. A unary code is a code in which each bit in the code has an equal weight. The unary code is then compressed and mapped based on the compressed unary code using the values ​​of the selected bits. The device then provides an output based on the expansion. Thus, the arrangement makes it possible to use sub-gate delays for several different applications.

[0009] In one aspect, an apparatus for encoding a sampled phase signal is disclosed. The apparatus includes a sampling instance for receiving an input from a sub-gate delay resolution arrangement. The apparatus also includes processing circuitry for selectively inverting a set of bits in a sampling matrix sampled in the sampling instance based on a first predefined reference node of the sub-gate delay resolution arrangement to provide a unary code; compressing the unary code; and expanding a mapping based on the compressed unary code using values ​​of selected bits. The apparatus also includes an output for providing an output based on the expansion.

[0010] In particular, the device may include a cyclic coupled ring oscillator (CCRO).

[0011] The sampling matrix may be a matrix obtained by sampling the logic values ​​at the nodes of the CCRO in the sampling instance. The processing circuit may be configured to selectively invert a set of bits in the matrix based on a predefined reference node arranged according to the sub-gate delay resolution. According to one implementation, this inversion operation provides a unary code with a redundant, non-unique mapping to the phase of the CCRO. In other words, for example, a code for a phase ranging from 0 to 180 degrees may also be used for a phase ranging from 180 to 360 degrees. The unary code may be compressed by calculating the sum of the non-zero bits in the code. The resulting sum may be viewed as an example of the mapping mentioned in the preceding paragraph and may be expanded using the values ​​of selected bits to obtain a non-redundant, unique mapping between the code and the phase of the CCRO. The expansion is performed by considering the sum of the non-zero bits or the inverse of the sum according to the reference bit values. Here, the inverse of the sum refers to the difference between the sum and the maximum possible value of the sum.

[0012] The advantages of the arrangement are that it encodes the sampling phase of a ring-coupled ring oscillator in a flexible manner, thereby eliminating or reducing the effects of sampling errors due to delay mismatches between the phase taps of the oscillator, thereby achieving the goal of improving the performance of data converters using CCROs as quantizers. In addition, it helps to design high-performance, high-bandwidth data converters with technology-independent sub-gate delay resolution in highly scaled semiconductor technologies where line delay mismatches dominate gate delay mismatches. The present invention also provides an error-resilient encoding method for the sampling phase of a ring-coupled ring oscillator, so that delay mismatches inherent to the design during deep scaling do not significantly degrade the performance of the converter. In addition, the encoder is fully digital and can be designed entirely using CAD tools that can be used for digital design, thereby shortening design time, reducing costs, and improving design portability.

[0013] In one implementation, the processing circuit is further configured to: count the number of ones in the unary code when compressing the unary code; a counter counts the sum of all ones in the output and provides the sum for error mitigation, wherein the sum can be used for selection of the selected bit.

[0014] In one implementation, the value of the selected bit is selected from the result of counting the number of ones in the unary code.In error mitigation, it is beneficial to use the sum counted by a counter.

[0015] In one implementation, the apparatus includes a second processing circuit and a second output, wherein the second processing circuit and the second output perform the same tasks as the first processing circuit and the first output in parallel with at least two different predefined reference nodes to provide at least two outputs from a single input. Calculating two different values ​​is advantageous so that a better representative value can be selected from the calculation based on two different taps.

[0016] In one implementation, the apparatus is configured to select a second predefined reference, wherein the second predefined reference is non-adjacent to the first predefined reference, such that a temporal distance between transitions at the first reference node and the second reference node is maximized in the sub-gate delay resolution arrangement. In particular, the first and second references may be spaced apart, i.e., the second reference may be positioned at a predetermined temporal distance from the first reference in the sub-gate delay resolution arrangement. When the references are spaced apart in the oscillator arrangement, the accuracy of the arrangement is improved.

[0017] In one implementation, the first processing circuit and the second processing circuit are configured to estimate a temporal position of a transition phase tap in the sampling instance. The estimation of the temporal position of the transition phase tap in the sampling instance facilitates selection of a correct tap.

[0018] In one implementation, the first processing circuit and the second processing circuit are configured to select a correct output from the at least two outputs based on the estimation. When there are two options to choose from, the accuracy of the arrangement can be improved because an inaccurate option may be discarded.

[0019] In one implementation, the apparatus further includes logic for providing the logic with a histogram of the output and detecting whether an appropriate reversal pattern specific to the oscillation pattern has been applied. Utilizing the histogram and logic to select the appropriate reversal pattern improves the accuracy of the arrangement by facilitating the selection of the appropriate reversal pattern.

[0020] In one implementation, the apparatus is further configured to select a suitable inversion pattern by detecting the oscillation pattern. Utilizing the oscillation pattern when selecting a suitable inversion pattern improves the accuracy of the arrangement by facilitating the selection of a suitable inversion pattern.

[0021] In one aspect, a method for encoding a sampled phase signal is disclosed. The method includes: receiving an input from a sub-gate delay resolution arrangement in a sampling instance; selectively inverting a set of bits in a sampling matrix sampled in the sampling instance based on a first predefined reference node of the sub-gate delay resolution arrangement to provide a unary code; compressing the unary code; unpacking a mapping based on the compressed unary code using the value of the selected bit; and providing an output based on the unpacking. The advantages of the method are that the method encodes the sampling phase of a ring-coupled ring oscillator in a resilient manner, thereby eliminating or reducing the impact of sampling errors caused by delay mismatches between the phase taps of the oscillator; and achieving the goal of improving the performance of a data converter using a CCRO as a quantizer. In addition, it facilitates the design of high-performance, high-bandwidth data converters with technology-independent sub-gate delay resolution in highly scaled semiconductor technologies, in which line delay mismatches dominate gate delay mismatches. The present invention also provides an error-resilient encoding method for the sampling phase of a ring-coupled ring oscillator, so that delay mismatches inherent to the design during deep scaling do not significantly degrade the performance of the converter. Furthermore, the encoder is fully digital and can be designed entirely using CAD tools available for digital design, thereby achieving reduced design time, reduced costs, and improved design portability.

[0022] In one implementation, compressing the unary code includes counting the number of ones in the unary code. A counter counts the sum of all ones in the output and provides the sum for error mitigation, wherein the sum can be used for selection of the selected bit.

[0023] In one implementation, the value of the selected bit is selected from the result of counting the number of ones in the unary code.In error mitigation, it is beneficial to use the sum counted by a counter.

[0024] In one implementation, the method is performed at least twice in parallel with at least two different predefined reference nodes to provide at least two outputs from one input. Calculating two different values ​​is beneficial so that a better representative value can be selected from the calculation based on two different taps.

[0025] In one implementation, the method further comprises selecting a second predefined reference so as to be spaced apart in the sub-gate delay resolution arrangement. When the references are spaced apart in the oscillator arrangement, the accuracy of the arrangement is improved.

[0026] In one implementation, the method further comprises estimating a time position of a transition phase tap in the sampling instance. The estimation of the time position of the transition phase tap in the sampling instance facilitates selection of a correct tap.

[0027] In one implementation, the correct output is selected from the at least two outputs based on the estimation.When there are two options to choose from, the accuracy of the arrangement can be improved because it is possible to discard an inaccurate option.

[0028] In one implementation, the method includes providing logic with a histogram of the output and detecting whether an appropriate inversion pattern specific to the oscillation mode is applied. Using the histogram and logic to select the appropriate inversion pattern improves the accuracy of the arrangement by facilitating the selection of the appropriate inversion pattern.

[0029] In one implementation, the method further comprises selecting a suitable inversion pattern by detecting the oscillation pattern.Utilizing the oscillation pattern in selecting the suitable inversion pattern improves the accuracy of the arrangement by facilitating the selection of the suitable inversion pattern.

[0030] In one implementation, the method further comprises selecting an inversion mode. It is advantageous to select the oscillation mode so that the intended application and overall configuration are taken into account.

[0031] In one aspect, a computer program comprising computer program code is disclosed. The computer program code is configured to, when executed on a computing device, cause the method described above to be performed. It is advantageous to implement the method for arranging as an executable computer program so that parameters can be easily changed when necessary.

[0032] The aforementioned and other objects are achieved by the subject matter of the independent claims. Further implementations are apparent from the dependent claims, the description and the drawings.

[0033] The principles discussed in this specification can be implemented in hardware and / or software. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Other exemplary embodiments will be described with reference to the following drawings, in which:

[0035] Figure 1 An example of a schematic diagram illustrating an analog-to-digital converter is shown;

[0036] Figure 2 An example of a conventional ring oscillator 200 is shown;

[0037] Figure 3 An example of a ring-coupled ring oscillator is shown;

[0038] Figure 4 An example of a TDC using a ring-coupled ring oscillator is shown;

[0039] Figure 5shows the sources of delay mismatch associated with sampling of the phase signal;

[0040] Figure 6 shows an example of error caused by delay mismatch in the sampled phase signal;

[0041] Figure 7 An example is shown, in which the state of 5×3CCRO for the mode with ψ=120° is shown;

[0042] Figure 8 An example of a sampling method is shown;

[0043] Figure 9 An example of an inverted style is shown;

[0044] Figure 10 shows an example of the state after the inversion is applied;

[0045] Figure 11 An example of a coding arrangement is shown;

[0046] Figure 12 The error suppression capability of the proposed scheme is shown;

[0047] In the various figures, the same reference numerals are used for identical or at least functionally equivalent features. DETAILED DESCRIPTION

[0048] The following description is made with reference to the accompanying drawings, which form a part hereof and illustrate, by way of illustration, specific aspects of the apparatus and method of the present invention. It should be understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the claims. Therefore, the following detailed description should not be construed as limiting.

[0049] For example, it should be understood that the disclosures in connection with a described method may also apply to a corresponding device or system for performing the method, and vice versa. For example, if a specific method step is described, a corresponding device may include a unit for performing the described method step, even if the unit is not specifically illustrated or described in the figure. Furthermore, it should be understood that the features of the various exemplary aspects described herein may be combined with each other unless otherwise specifically noted.

[0050] In the following description, a ring-coupled ring oscillator is used and explained as an example, however, the arrangement and method that are resilient to mismatch-induced sampling errors can also be used for other grid-like arrangements.

[0051] Figure 1A basic implementation of an analog-to-digital converter is shown. The exemplary analog-to-digital converter can serve as a basis for embodiments of the described arrangement, in particular the device for generating a time resolution, ie the device for performing data conversion with a predefined time resolution. Figure 1 The analog-to-digital converter of the present invention receives an analog input 100 at a voltage-to-time converter 101. The received analog input (typically a voltage-representing signal) 100 is then converted into a time-domain signal 102 using the voltage-to-time converter (VTC) 101. The resulting time-domain signal 102 is then sampled and quantized into a digital signal using a time-to-digital converter (TDC) 103 to provide a digital output 104. The resolution of the time-domain ADC is determined by the gain of the voltage-to-time conversion and the resolution of the time-to-digital conversion. The arrangement described in detail below helps to improve the resolution of the time-to-digital conversion, and thus also helps to improve the resolution of the analog-to-digital conversion.

[0052] Figure 2 An example of a conventional ring oscillator 200 is shown. A conventional ring oscillator divides its phase into 2N steps, where N is the number of inverters in the ring. Therefore, the time resolution created is still in the steps of the inverter delay. Conventional ring oscillator 200 is a conventional ring oscillator with 5 inverters, and the resulting phase interpolation is shown below the ring oscillator 200 in the figure. Assuming that the minimum inverter delay under certain load conditions is t inv-min It should be noted that the minimum possible time step t in the circuit min With t inv-min same.

[0053] Figure 3 An example of a ring-coupled ring oscillator is shown. The number of ring oscillators and inverters in each ring is for illustration only. However, the present invention can be implemented using a ring oscillator arrangement having any number of stages and any number of inverters in each stage. Furthermore, the number of coupled inverters is not limited to the number shown in this embodiment. In the example shown, the number of coupled inverters is the same as the number of inverters in the ring-coupled ring oscillator; however, as mentioned above, this is only one possible example. The ring-coupled ring oscillator includes three conventional five-stage ring oscillators 300-302. Each conventional ring oscillator has five inverters 303, with N=5 and M=3. The newly introduced coupled inverters 305 are labeled c. The coupled inverters are arranged in a ring 304 to couple the conventional ring oscillators 300-302 to each other. Compared to the conventional inverters 303, the coupled inverters 305 are typically designed to have relatively weaker drive strength.

[0054] The five-level oscillators 300-302 are coupled to the coupled inverters in a ring form, thereby forming a set of vertical ring oscillators. When the coupled oscillators oscillate in a desired oscillation mode, each possible mode corresponds to a certain obvious phase relationship between the five-level horizontal oscillators, achieving the following: Figure 3 The desired phase interpolation is shown below in the ring coupled ring oscillator. There are usually several different modes that provide the desired phase interpolation, so it is easy to design the structure to ensure the desired mode oscillation. Figure 3 It can be seen that the minimum time step t in the circuit min Now it is 1 / M, which is less than the minimum inverter delay t inv-min Thus, the desired sub-gate delay resolution is achieved.

[0055] Figure 4 An example of a TDC using a ring-coupled ring oscillator 400 is shown. The ring-coupled ring oscillator 400 enables arbitrarily small sub-gate delay phase quantization steps. When a data converter (TDC or ADC) based on a ring-coupled ring oscillator is implemented in deeply scaled semiconductor technology, the phase quantization step size approaches picoseconds or even shorter. Figure 4 As shown, the phase output of the ring-coupled ring oscillator is sampled via registers 402 and 403. The sampled phase of the oscillator is then digitally encoded within digital signal processor block 404 to generate digital output samples. It should be noted that in highly scaled semiconductor technologies, wiring delays dominate gate delays. Therefore, even in a carefully laid-out design, wiring delay mismatch can easily exceed the phase quantization step size of the ring-coupled ring oscillator. Figure 4 The example further shows a counter 401 which can be used to count integer cycles of the ring-coupled ring oscillator.

[0056] Figure 5 The source of delay mismatch associated with sampling of the phase signal is shown. When the delay mismatch exceeds the phase quantization step size of the ring-coupled ring oscillator, the sampling of the phase signal will be erroneous. Figure 5A set of non-ideal circuit conditions are shown that result in delay mismatches in the phase signal, which can lead to incorrect sampling. This includes mismatches in: propagation delay from low to high versus propagation delay from high to low, rise delay versus fall delay, low drive strength versus high drive strength, drive strength between ring-coupled ring oscillator nodes, loading between ring-coupled ring oscillator nodes, wiring delays between nodes, and clock skew between register flip-flops. The net effect of the mismatch can be modeled by delay mismatches between nodes in the phase signal. When the amount of mismatch approaches the phase quantization step size of the ring-coupled ring oscillator, which is particularly likely when designing ring-coupled ring oscillator-based converters in deep scaling techniques, errors in the sampled phase signal can occur. These errors cause larger errors at the converter output, thereby degrading performance.

[0057] Figure 6 An example of the error caused by delay mismatch in the sampled phase signal is shown. This example shows the error of the reordering of transitions in the ring as seen by the sampling register. Figure 6 In the example, r2 to r0 are nodes in the ring-coupled ring oscillator with temporally adjacent phase increments. In addition, in this case, the number of nodes is set to 3 for illustration purposes. However, it should be clear that the number of nodes can be arbitrary. The nodes in the ring-coupled ring oscillator with temporally adjacent phase transitions are generally not spatially adjacent. Figure 6 As shown, due to the delay mismatch in the phase signals, the time sequence of the transitions in the multiphase output of the ring coupled ring oscillator can be seen in a different order through the register input. In other words, due to the delay mismatch, the time when the transitions occur in the multiphase output of the ring coupled ring oscillator (CCRO) can have a different time sequence in the register. For example, in this example, the time sequence of the transitions in the multiphase output of the CCRO is t r2 <t r1 <t r0 , while the time sequence of the same transition seen through the register is t' r2 <t' r0 <t' r1 This reordering can lead to errors in the sampling phase, resulting in large conversion errors. The number of temporally adjacent nodes (phase taps) over which the reordering extends and the complexity of the reordering pattern depend on the degree of delay mismatch relative to the phase step size of the ring-coupled ring oscillator and the complexity of the delay mismatch pattern.

[0058] For finite N and M, if the drive strength of the coupled inverters is assumed to be weaker than that of the main inverter, then under locked conditions, the phases at multiple nodes in the CCRO can be related in a finite number of ways. The oscillation of each horizontal ring oscillator is similar to that of a conventional ring oscillator. When the oscillator is locked, the constant phase difference between adjacent nodes in the horizontal oscillator can be expressed as

[0059] θ=π+π / N

[0060] The phase difference between adjacent vertical nodes is given by:

[0061] ψ=n(2π / M), where 0<n<M.

[0062] Each value of n corresponds to a specific oscillation mode. Because ψ has M-1 solutions, theoretically, there are M-1 unique oscillation modes. However, in practical designs, there are a small number of stable modes, some of which have maximum phase resolution, with 2×N×M different phase steps. By selecting appropriate values ​​of N, M, and the ratio of the drive strengths of the main inverter and the coupled inverter, the CCRO can be designed to oscillate in a stable mode with maximum phase resolution.

[0063] By adding a node (such as n 11 ) is set to zero, and this node is then considered the reference node. The relative phase at each node of the ring-coupled ring oscillator can then be calculated using θ and ψ for any desired pattern. Thus, the possible states of the ring-coupled ring oscillator can be predicted for all patterns, with each state defined by the set of Boolean states of all nodes in the ring-coupled ring oscillator.

[0064] Figure 7 An example is shown, where the states of a 5×3 CCRO are shown for a pattern with ψ=120°. There are 2×N×M=30 possible different states, corresponding to the different phase steps indicated. Each square represents the state of a node in the CCRO, where a black square indicates a logic low and a white square indicates a logic high. Obviously, the way of indicating the logic states is purely conventional. Accordingly, a logic low can also be represented by a white square and a logic high can also be represented by a black square. In general, any mapping that can represent a binary state pattern can be used instead of Figure 7 The circled squares highlight the defining nodes of the corresponding states, i.e., the nodes that switch compared to the previous state. It can be observed that temporally adjacent transitions in CCROs generally do not occur at spatially adjacent nodes, unlike conventional ring oscillators.

[0065] When the signals within the multiphase outputs of the CCRO are delayed unevenly, causing a temporal reordering of the transitions seen by the sampling registers, the sampled outputs deviate from the finite set of valid patterns. Note that there is a large amount of redundancy in the CCRO code (2×N×M vs.2 N×M Possible modes), these redundancies can be used for error correction. An advantageous feature of the present invention is that the state is mapped into a form that facilitates error correction, as described below.

[0066] Figure 8 The encoding scheme is shown, along with CCRO 800 and sampling register 801. The sampled phase output of CCRO 800 is processed by a selective inversion block 802, which inverts a set of bits in a sampling matrix, resulting in a cyclic unary code for a set of valid CCRO 800 states. Specifically, the sampling matrix can be a matrix obtained by sampling the logical values ​​at the nodes of the CCRO during a sampling instance or sampling phase. The device (i.e., the TDC in this example) includes processing circuitry configured to selectively invert a set of bits in the matrix based on predefined reference nodes arranged at the sub-gate delay resolution. According to one implementation, this inversion operation provides a unary code with a redundant, non-unique mapping to the CCRO phase. In other words, for example, a code for phases in the range of 0 to 180 degrees can also be used for phases in the range of 180 to 360 degrees. The unary code can be compressed by summing the non-zero bits in the code. The resulting sum can be considered as an example of the mapping mentioned in the previous paragraph, which can be expanded using the values ​​of the selected bits to obtain a non-redundant unique mapping between the code and the phase of the CCRO. The expansion is performed by considering the sum of the non-zero bits or the inverse of the sum according to the reference bit value. In this context, the inverse of the sum refers to the difference between the sum and the maximum possible value of the sum.

[0067] The unary code is then compressed by a counter block 803 which calculates the sum of all ones in the output. However, the output of a counter 803 does not provide a unique mapping for the CCRO 800 stage. This can be alleviated by expanding 804 the mapping using the values ​​of selected bits from the output of a counter. The details of the mapping are explained below with the following example: For a pattern with ψ = 120°, Figure 3 5×3CCRO.

[0068] The inversion pattern to be applied to the sampled CCRO output to obtain the cyclic unary code depends on the oscillation mode. The pattern can be shown as a cascade of a checkerboard pattern followed by a pattern-dependent inversion pattern ( Figure 9 ). Although Figure 9An example of possible options for a checkerboard pattern is shown, but any checkerboard pattern seen at the CCRO output (which can correspond to any arbitrary phase) can be used as a reference pattern. The mode-dependent inversion pattern is defined based on the oscillation pattern of the CCRO. For example, Figure 10 The example shown in corresponds to the pattern with ψ = 120° as described above. When the pattern-dependent pattern is applied to the checkerboard pattern, the white cells in the pattern-dependent inversion pattern cause the cells in the checkerboard to change state. (i.e., in Figure 7 in the example, from white / high to black / low). Figure 9 This general concept is shown. Figure 10 shows that by applying this inversion style to Figure 7 The unary code obtained by the CCRO phase is shown. White cells represent inversions, and black cells represent non-inversions. This type of pattern can be calculated for any CCRO pattern using the values ​​of θ and ψ.

[0069] Figure 10 Shows that Figure 9 The inversion style shown is applied to Figure 6 Following the state shown, the output of block 802 is reversed. As can be seen, a counter operating on the pattern produces a non-unique mapping that can be expanded based on the value of a predetermined reference bit.

[0070] Figure 11 The coding arrangement is disclosed. Figure 8 Similar principle for a simplified example. Figure 8 A CCRO 1100 and sampling register 1101 are shown. For different taps, the sampled phase output of CCRO 1100 is processed by selective inversion blocks 1102a and 1102b, respectively. These selective inversion blocks 1102a and 1102b invert a set of bits in the sampling matrix, resulting in a cyclic unary code for a set of valid CCRO 1100 states. The unary code is then compressed by counter blocks 1103a and 1103b, which calculate the sum of all ones in the output. However, the outputs of counters 1103a and 1103b do not provide a unique mapping of the CCRO 1100 phase according to the corresponding tap. This can be mitigated by expanding the mappings 1104a and 1104b using the values ​​of selected bits from the output of the corresponding counter.

[0071] The expansion operations 1104a and 1104b focus on the accuracy of sampling a selected phase tap, which can reduce the error suppression capability of the above-mentioned encoding. That is, when the phase tap of the CCRO converted in the sampling instance is near the (time) of the reference tap, there may be a large error. This can be solved by using two such encoders with two different reference phase taps, which are positioned as far away from each other (in time) as possible so that the output of one of the encoders is always error-free. The correct output can be selected 1106 based on a rough estimate 1105 of the (time) position of the converted phase tap in the sampling instance. The selected output is then provided to register 1107.

[0072] Furthermore, by observing the histogram 1108 of the encoder output, it is possible to detect whether the appropriate inversion pattern specific to the oscillation pattern is being applied. If the inversion is correct, for a uniformly distributed phase input, the output covers all possible output codes with approximately equal probability, while other patterns from the superset of all CCRO inversion patterns result in outputs covering only a few codes. This property can be used to implement an adaptive system 1109 that automatically detects the oscillation pattern of the CCRO by observing the encoder output without any calibration signal (blind detection), thereby selecting the appropriate inversion pattern.

[0073] Figure 12 The error suppression capability of the proposed scheme is shown. Figure 12 The maximum error of the coding is plotted as a function of U (the number of phase taps randomly reordered) for 7×5 CCRO. It can be seen that the proposed scheme maintains a very low maximum error for the coding over a wide range of U compared to the case without error correction.

[0074] The arrangement disclosed above reduces the performance dependency of data converters and delay measurement circuits employing CCRO as a time-domain sub-gate delay quantizer on component and layout accuracy. Thus, the arrangement enables the design of high-performance, high-bandwidth data converters in deeply scaled semiconductor technologies, where delay mismatch due to layout inaccuracies is difficult to control.

[0075] The above arrangement can be used in several different applications, some examples of which are given below. These examples are provided to better understand the wide range of applications in which these arrangements can be used.

[0076] The arrangement disclosed above can be used for high-performance time-domain ADCs. The arrangement helps to realize high-resolution and high-bandwidth time-domain ADCs by supporting fast and high-resolution time-to-digital conversion.

[0077] One approach to implementing a 5G receiver front-end employs an RF digitization approach using high-performance ADCs. A time-interleaved architecture is proposed to achieve the required converters with very high bandwidth and high resolution, where each converter is implemented using a time-domain approach to exploit the superior temporal resolution of advanced processes. This arrangement facilitates the implementation of such converters, avoiding the limitations of previous solutions.

[0078] All-digital phase-locked loops (ADPLLs) are gaining popularity as an attractive architecture for implementing frequency synthesizers and similar applications in highly scalable semiconductor technologies. The resolution and conversion speed of the TDC block in an ADPLL are crucial in determining the circuit's performance and bandwidth. The arrangement disclosed above can alleviate the performance limitations of ADPLLs and frequency synthesizers designed in modern semiconductor technologies by enabling fast and high-resolution time-to-digital conversion. Phase-locked loops and frequency synthesizers are widely used in radio transceivers and high-speed serial communication transceivers.

[0079] The arrangement can also be used to achieve the high-precision time measurements required by time-of-flight (ToF) sensors, which are used in a wide range of radar applications, including automotive radar and other consumer radar applications.

[0080] As explained above, the arrangement for encoding the sampled phase signal as described above can be implemented in hardware such as a mobile phone, tablet computer, computer, telecommunication network base station, or any other network-connected device, or as a method. The method can be implemented as a computer program. The computer program is then executed in a computing device.

[0081] The apparatus, such as an apparatus for transmitting signals in a communications network, is configured to perform one of the methods described above. The apparatus includes necessary hardware components. These hardware components may include at least one processor, at least one memory, at least one network connection, a bus, etc. For example, instead of dedicated hardware components, the memory or processor may be shared with other components or accessed from a cloud service, a centralized computing unit, or other resource accessible via a network connection.

[0082] Apparatus and corresponding methods for transmitting signals in a communication network have been described herein in conjunction with various embodiments. However, based on a study of the drawings, the present invention and the appended claims, those skilled in the art will be able to understand and implement other variations of the disclosed embodiments when practicing the claimed invention. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit may fulfil the functions of several items described in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not mean that a combination of these measures cannot be effectively used. The computer program may be stored or distributed on a suitable medium, such as an optical storage medium or solid-state medium provided together with or as part of other hardware, and may also be distributed in other forms such as via the Internet or other wired or wireless telecommunications systems.

Claims

1. A device for generating a time resolution for an electronic device, characterized in that include: a sampling instance for receiving input from a sub-gate delay resolution arrangement; Processing circuitry for: inverting a set of bits in a sampling matrix sampled in a sampling instance based on a first predefined reference node arranged at the sub-gate delay resolution to provide a unary code; compressing the unary code; unfolding a map based on the compressed unary code using the value of the selected bit; output, for providing output based on the expansion; The processing circuit is further configured to: count the number of ones in the unary code when compressing the unary code; and the value of the selected bit is selected from a result of counting the number of ones in the unary code.

2. The device according to claim 1, characterized in that The apparatus comprises a second processing circuit and a second output, wherein the second processing circuit and the second output are configured to perform the same tasks as the processing circuit and the output in parallel with at least two different predefined reference nodes to provide at least two outputs from one input.

3. The device according to claim 2, characterized in that The apparatus is configured to select a second predefined reference, wherein the second predefined reference is not adjacent to the first predefined reference in the sub-gate delay resolution arrangement.

4. The device according to claim 2, characterized in that The processing circuit and the second processing circuit are configured to estimate a time position of a transition phase tap in the sampling instance.

5. The device according to claim 4, characterized in that The processing circuit and the second processing circuit are configured to select a correct output from the at least two outputs based on the estimation.

6. Device according to any one of the preceding claims 1 to 5, characterized in that The apparatus also includes logic further configured to provide the logic with a histogram of the output and detect whether an appropriate reversal pattern specific to an oscillation mode is applied; the oscillation mode being an oscillation mode of the oscillator.

7. The device according to claim 6, characterized in that The device is further configured to select a suitable reversal pattern by detecting the oscillation pattern.

8. A method for generating time resolution for an electronic device, characterized in that include: receiving input from a sub-gate delay resolution arrangement in a sampling example; selectively inverting a set of bits in a sampling matrix sampled in a sampling instance based on a first predefined reference node arranged at the sub-gate delay resolution to provide a unary code; compressing the unary code; unfolding a map based on the compressed unary code using the value of the selected bit; providing output based on the expansion; Said compressing said unary code comprises counting a number of ones in said unary code; said value of said selected bit being selected from a result of counting the number of ones in said unary code.

9. The method according to claim 8, characterized in that The method is performed at least twice in parallel with at least two different predefined reference nodes to provide at least two outputs from one input.

10. The method according to claim 9, characterized in that The method further includes selecting a second predefined reference so as to be separately positioned in the sub-gate delay resolution arrangement.

11. The method according to claim 9, characterized in that The method also includes estimating a time location of a transition phase tap in the sampling instance.

12. The method according to claim 11, characterized in that The method also includes selecting a correct output from the at least two outputs based on the estimation.

13. Method according to any one of the preceding claims 8 to 12, characterized in that The method also includes providing logic with a histogram of the output and detecting whether an appropriate reversal pattern specific to an oscillation mode is applied; the oscillation mode being an oscillation mode of the oscillator.

14. The method according to claim 13, characterized in that The method further includes selecting a suitable reversal pattern by detecting the oscillation pattern.

15. The method according to any one of the preceding claims 8 to 12 and 14, characterized in that The method also includes selecting an oscillation mode.

16. A product comprising a computer program comprising computer program code, characterized in that The computer program code is configured to cause the method according to any one of claims 8 to 15 to be performed when the computer program code is executed in a computing device.

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