Image sensing device

Abstract

An image sensing device includes: a pixel array, which includes a plurality of pixels arranged in rows and columns and is configured to output a plurality of pixel signals; and a plurality of readout circuits, which are connected to the pixel array and are configured to compensate for readout deviations between the plurality of pixel signals when reading out the plurality of pixel signals.

Description

Technical Field

[0001] Various embodiments of the present invention relate to semiconductor design technology, and more particularly, to an image sensing device. Background Art

[0002] Image sensing devices utilize the light-sensitive properties of semiconductors to capture images. Image sensing devices can be broadly classified into charge coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors. CMOS image sensors are widely used in the industry because they allow both analog control circuits and digital control circuits to be implemented directly on a single integrated circuit (IC). Summary of the invention

[0003] Various embodiments of the present invention are directed to an image sensing device for reducing degradation of characteristics occurring when a pixel signal is read out.

[0004] According to an embodiment, an image sensing device may include: a pixel array, which includes a plurality of pixels arranged in rows and columns and is configured to output a plurality of pixel signals; and a plurality of readout circuits, which are connected to the pixel array and are configured to compensate for readout deviations between the plurality of pixel signals when reading out the plurality of pixel signals.

[0005] The plurality of readout circuits may positively compensate or inversely compensate for readout deviations between the plurality of pixel signals by applying corresponding predetermined resistance values ​​in a plurality of readout lines that read out the plurality of pixel signals.

[0006] The plurality of readout circuits may reduce the readout variation between the plurality of pixel signals when compensating for the readout variation between the plurality of pixel signals.

[0007] When compensating for the readout variation between the plurality of pixel signals, the plurality of readout circuits may increase the readout variation between the plurality of pixel signals.

[0008] According to an embodiment, an image sensing device may include: a pixel array, which includes a plurality of pixels arranged in rows and columns and is configured to output a plurality of pixel signals to a plurality of column lines; a plurality of detectors, which are connected to the plurality of column lines and are configured to output a plurality of detection signals corresponding to corresponding voltage levels of the pixel signals to a plurality of readout lines; a plurality of counters, which are connected to the plurality of readout lines and are configured to count the plurality of detection signals respectively; and a plurality of compensators, which are connected to the plurality of readout lines and are configured to apply corresponding predetermined resistance values ​​in the plurality of readout lines, wherein a different predetermined resistance value is applied in each of the plurality of readout lines.

[0009] The corresponding predetermined resistance value may be set according to the readout deviation between the plurality of pixel signals.

[0010] The respective predetermined resistance values ​​may be set to reduce readout deviations between the plurality of pixel signals.

[0011] The respective predetermined resistance values ​​may be set to increase a readout deviation between the plurality of pixel signals.

[0012] Each compensator may include a load, and the load may include a non-salicide polysilicon resistor.

[0013] Each compensator may include a load, and the load may include a metal resistor.

[0014] According to an embodiment, an image sensing device may include: a pixel array, which includes a plurality of pixels arranged in rows and columns and is configured to output a plurality of pixel signals to a plurality of column lines; a plurality of detectors, which are connected to the plurality of column lines and are configured to output a plurality of detection signals corresponding to respective voltage levels of the pixel signals to a plurality of readout lines; a plurality of counters, which are connected to the plurality of readout lines and are configured to count the plurality of detection signals respectively; and a plurality of compensators, which are connected to the plurality of readout lines and are configured to selectively apply one of two or more resistance values ​​in each readout line under the control of two or more common control signals.

[0015] The plurality of compensators may apply different resistance values ​​in two or more readout lines.

[0016] The two or more resistance values ​​may include a first resistance value that may be set to reduce a readout deviation between the plurality of pixel signals and a second resistance value that may be set to increase a readout deviation between the plurality of pixel signals.

[0017] Each compensator may include: a first load; a second load; a first switch, which is configured to selectively connect the first load to each readout line under the control of a first common control signal in the common control signal; and a second switch, which is configured to selectively connect the second load to each readout line under the control of a second common control signal in the common control signal.

[0018] Each of the first load and the second load may include a non-salicide polysilicon resistor.

[0019] Each of the first load and the second load may include a metal resistor.

[0020] Each compensator may include: a plurality of loads; and a plurality of switches configured to selectively couple one or more of the plurality of loads to a respective sense line under control of a common control signal.

[0021] The plurality of loads may have the same resistance value.

[0022] Each load may include a non-salicide polysilicon resistor.

[0023] Each load may include a metallic resistor.

[0024] These and other features and advantages of the present invention will become apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a block diagram illustrating an image sensing device according to various embodiments of the present invention.

[0026] Figure 2 It is a diagram showing various embodiments according to the present invention. Figure 1 A block diagram of multiple readout circuits of an image sensing device.

[0027] Figure 3A and Figure 3B Showing various embodiments according to the present invention Figure 2 An example of a first compensator for multiple readout circuits.

[0028] Figure 4 It is a diagram showing various embodiments according to the present invention. Figure 1 FIG. 5 is a graph showing a positive compensation operation of an image sensing device.

[0029] Figure 5A and Figure 5B Showing various embodiments according to the present invention Figure 3A and Figure 3B Various implementations of the first compensator.

[0030] Figure 6 is a block diagram illustrating an image sensing device according to various embodiments of the present invention.

[0031] Figure 7 It is a diagram showing various embodiments according to the present invention. Figure 6 A block diagram of multiple readout circuits of an image sensing device.

[0032] Fig. 8A and Figure 8B Showing various embodiments according to the present invention Figure 7 An example of a first compensator for multiple readout circuits.

[0033] Fig. 9 It is a diagram showing various embodiments according to the present invention. Figure 6 FIG. 5 is a graph showing an inverse compensation operation of an image sensing device.

[0034] Fig. 10A and Fig. 10B Showing various embodiments according to the present invention Fig. 8A and Figure 8B Various implementations of the first compensator.

[0035] Fig.11 is a block diagram illustrating an image sensing device according to various embodiments of the present invention.

[0036] Fig.12 It is a diagram showing various embodiments according to the present invention. Fig.11 A block diagram of multiple readout circuits of an image sensing device.

[0037] Fig.13 It is a diagram showing various embodiments according to the present invention. Fig.12 Circuit diagram of multiple compensators of multiple readout circuits.

[0038] Fig.14A and Fig. 14B Showing various embodiments according to the present invention Fig.13 Example of a first load of multiple compensators.

[0039] Fig.15 It is a diagram showing various embodiments according to the present invention. Fig.11 FIG. 5 is a graph showing a positive compensation operation of an image sensing device.

[0040] Fig.16 It is a diagram showing various embodiments according to the present invention. Fig.11 FIG. 5 is a graph showing an inverse compensation operation of an image sensing device.

[0041] Fig.17 is a block diagram illustrating an image sensing device according to various embodiments of the present invention.

[0042] Fig.18 It is a diagram showing various embodiments according to the present invention. Fig.17 A block diagram of multiple readout circuits of an image sensing device.

[0043] Fig.19 It is a diagram showing various embodiments according to the present invention. Fig.18 Circuit diagram of multiple compensators of multiple readout circuits.

[0044] Fig. 20A and Fig. 20B Showing various embodiments according to the present invention Fig.19Example of a first load of multiple compensators.

[0045] Fig.21 It is a diagram showing various embodiments according to the present invention. Fig.17 FIG. 5 is a graph showing a positive compensation operation of an image sensing device.

[0046] Fig. 22 It is a diagram showing various embodiments according to the present invention. Fig.17 FIG. 5 is a graph showing an inverse compensation operation of an image sensing device. DETAILED DESCRIPTION

[0047] Various embodiments are described in more detail below with reference to the accompanying drawings. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0048] It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, it may be directly on, connected to, or coupled to another element, or one or more intermediate elements may be present. In addition, it will also be understood that the terms "comprises" and "comprising" when used in this specification specify the presence of the element, and do not exclude the presence or addition of one or more other elements. As used herein, unless the context clearly indicates otherwise, the singular may also include the plural, and vice versa. Unless otherwise indicated or clearly pointed to the singular from the context, the article "a" as used in this application and the appended claims should generally be interpreted as "one or more".

[0049] Figure 1 is a block diagram illustrating an image sensing device 100 according to various embodiments of the present invention.

[0050] Reference Figure 1 , the image sensing device 100 may include a pixel region 110 , a readout region 120 , and a power supply region.

[0051] The pixel area 110 may include a pixel array. The pixel array may include a plurality of pixels PX00 to PXxy (where x and y are natural numbers) arranged along rows and columns. For example, the plurality of pixels PX00 to PXxy may be arranged in a first row ROW0 to a (x+1)th row ROWx and a first column COL0 to a (y+1)th column COLy. The pixel array may output a plurality of pixel signals PS0 to PSy to a plurality of column lines CL0 to CLy. For example, the first pixel PX00 to the (y+1)th pixel PX0y arranged in the first row ROW0 may output the first pixel signal PS0 to the (y+1)th pixel signal PSy to the first column line CL0 to the (y+1)th column line CLy during the first single row time period, and the first pixel PXx0 to the (y+1)th pixel PXxy arranged in the (x+1)th row ROWx may output the first pixel signal PS0 to the (y+1)th pixel signal PSy to the first column line CL0 to the (y+1)th column line CLy during the (x+1) single row time period.

[0052] The readout region 120 may include a plurality of readout circuits RD0 to RDy. The plurality of readout circuits RD0 to RDy may be connected to the pixel array through a plurality of column lines CL0 to CLy, and read out a plurality of pixel signals PS0 to PSy. For example, the first readout circuit RD0 to the (y+1)th readout circuit RDy may be connected to the first column line CL0 to the (y+1)th column line Cly to read out the first pixel signal PS0 to the (y+1)th pixel signal Psy from the first column line CL0 to the (y+1)th column line CLy, and then output them as the first count signal CNT0 to the (y+1)th count signal CNTy.

[0053] When multiple pixel signals PS0 to PSy are read out by multiple readout circuits RD0 to RDy, they may be subjected to time delays (hereinafter referred to as readout time delays). For each of the multiple pixel signals PS0 to PSy, the readout time delays caused by the multiple readout circuits RD0 to RDy may be different. Herein, the term readout deviation will be used to refer to the difference between the readout time delays of the multiple pixel signals PS0 to PSy. In an embodiment of the present invention, when the pixel signals PS0 to PSy are read out, the multiple readout circuits RD0 to RDy may compensate for the readout deviation between the multiple pixel signals PS0 to PSy. For example, the multiple readout circuits RD0 to RDy may compensate for the readout deviation between the multiple pixel signals PS0 to PSy by applying corresponding predetermined resistance values ​​in each path within the multiple readout circuits RD0 to RDy, and each path executes the corresponding pixel signal in the multiple pixel signals PS0 to Psy, thereby positively compensating for the readout deviation between the multiple pixel signals PS0 to PSy. Positively compensating for the readout deviation refers to reducing the readout deviation between the multiple pixel signals PS0 to PSy. For this reason, the resistance values ​​in the respective paths within the plurality of readout circuits RD0 to RDy may be set so that the readout deviation between the plurality of pixel signals PS0 to PSy may be reduced.

[0054] The power supply region may include power supply circuits 130 and 140, respectively. The power supply circuits 130 and 140 may generate power required by the readout region 120 and supply the power to the readout region 120. For example, the power supply circuits 130 and 140 may jointly supply power to the plurality of readout circuits RD0 to RDy included in the readout region 120. The power supply circuit 130 may be disposed closest to the first readout circuit RD0 among the plurality of readout circuits RD0 to RDy, and the power supply circuit 140 may be disposed closest to the (y+1)th readout circuit RDy among the plurality of readout circuits RD0 to RDy.

[0055] Figure 2 It is a diagram showing various embodiments according to the present invention. Figure 1 Block diagram of multiple readout circuits RD0 to RDy.

[0056] Reference Figure 2 , the first readout circuit RD0 may include a first detector 121_0 , a first compensator 123_0 , and a first counter 125_0 .

[0057] The first detector 121_0 may be coupled to the first column line CL0 , and may receive the first pixel signal PS0 through the first column line CL0 , and output a first detection signal DS0 corresponding to the voltage level of the first pixel signal PS0 to a first readout line RL0 (hereinafter referred to as a “first initial readout line”).

[0058] The first compensator 123_0 may be connected to the first initial readout line RL0. The first compensator 123_0 may apply a predetermined resistance value in the first initial readout line RL0. For example, when detected by the first detector 121_0, the first detection signal DS0 on the first readout line RL0 has a readout time delay. The amount of the readout time delay of the first detection signal DS0 may be different from the amount of the readout time delay of each of the second detection signal DS1 to the (y+1)th detection signal DSy on the second readout line RL1 to the (y+1)th readout line RLy. For positive compensation according to various embodiments of the present invention, by using a load (not shown) having a predetermined resistance value as the first compensator 123_0 to apply a predetermined resistance value in the first initial readout line RL0, the first compensator 123_0 may adjust the readout time delay of the first detection signal DS0 so that the difference between the readout time delay of the first detection signal DS0 and the readout time delay of the second detection signal DS1 to the (y+1)th detection signal DSy may be reduced (as described below in FIG. 3A to FIG. 5B The first compensator 123_0 may output the positively compensated first detection signal DS0 as a delayed first detection signal DS0' to a first readout line RL0' (hereinafter referred to as a "first last readout line").

[0059] The first counter 125_0 may be coupled to the first last readout line RL0 ′. The first counter 125_0 may count the delayed first detection signal DS0 ′ and output a first counting signal CNT0 .

[0060] Since the second readout circuit RD1 to the (y+1)th readout circuit RDy may be configured similarly to the first readout circuit RD0, a description thereof will be omitted for clarity. However, a resistance value set in at least one of the second compensator 123_1 to the (y+1)th compensator 123_y may be different from a resistance value set in the first compensator 123_0. In other words, the plurality of compensators 123_0 to 123_y included in the plurality of readout circuits RD0 to RDy may apply different resistance values ​​in two or more of the plurality of readout lines RL0 to RLy.

[0061] Figure 3A and Figure 3B Various embodiments according to the present invention are shown. Figure 2 An example of the first compensator 123_0.

[0062] Reference Figure 3A, the first compensator 123_0 may include a first load. The first load may be a non-salicide poly resistor. The non-salicide poly resistor may include a salicide region A and a non-salicide region B. The salicide region A may have a relatively small resistance value, and the non-salicide region B may have a relatively large resistance value. The resistance value of the non-salicide poly resistor may be set by adjusting the size of each of the salicide region A and the non-salicide region B. For example, as the size of the non-salicide region B increases, the resistance value of the non-salicide poly resistor may increase, and as the size of the non-salicide region B decreases, the resistance value of the non-salicide poly resistor may decrease.

[0063] Each of the second to (y+1)th compensators 123_1 to 123_y may include a non-self-aligned silicide polysilicon resistor similar to the first compensator 123_0. However, the size of the non-self-aligned silicide region included in at least one of the second to (y+1)th compensators 123_1 to 123_y may be different from the size of the non-self-aligned silicide region B included in the first compensator 123_0.

[0064] Then, refer to Figure 3B , the first compensator 123_0 may include a second load. The second load may be a metal resistor. The metal resistor may include a metal wire. The resistance value of the metal resistor may be set by adjusting the length of the metal wire. For example, as the length of the metal wire increases, the resistance value of the metal resistor may increase, and as the length of the metal wire decreases, the resistance value of the metal resistor may decrease.

[0065] Each of the second to (y+1)th compensators 123_1 to 123_y may include a metal resistor similar to the first compensator 123_0. However, the length of the metal line included in at least one of the second to (y+1)th compensators 123_1 to 123_y may be different from the length of the metal line included in the first compensator 123_0.

[0066] Below, we will refer to Figure 4 , Figure 5A and Figure 5B The operation of the image sensing device 100 having the above-described configuration according to various embodiments of the present invention is described.

[0067] Figure 4 It is a diagram showing various embodiments according to the present invention. Figure 1 FIG. 1 is a graph showing the operation of the image sensing device 100 .

[0068] Reference Figure 4 , a readout deviation T may occur between the plurality of pixel signals PS0 to PSy. More specifically, a readout deviation T may occur between the plurality of detection signals DS0 to DSy. Figure 4 , since the power supply circuits 130 and 140 for commonly supplying power to the plurality of readout circuits RD0 to RDy are respectively disposed closest to the first readout circuit RD0 and the (y+1)th readout circuit RDy, a graph representing the readout deviation T is shown in a convex shape at the center of the column axis. Therefore, the plurality of detection signals DS0 to DSy may be output with different readout time delays according to different distances from the power supply circuit to the corresponding readout circuit, so that the readout deviation T may occur between the plurality of detection signals DS0 to DSy. Herein, the distance between the power supply circuit and the readout circuit may indicate a supply duration or a physical length of a path for supplying power from the power supply circuit to the readout circuit.

[0069] A corresponding resistance value suitable for realizing positive compensation may be preset in the plurality of compensators 123_0 to 123_y according to the readout deviation T. For example, when the distance between the corresponding readout circuit and the power supply circuit decreases, the resistance value set in the compensators 123_0 to 123_y may be larger, and when the distance between the corresponding readout circuit and the power supply circuit increases, the resistance value set in the compensators 123_0 to 123_y may be smaller. The plurality of compensators 123_0 to 123_y may positively compensate for the readout deviation T between the plurality of detection signals DS0 to DSy by applying a corresponding predetermined resistance value in the plurality of readout lines RL0 to RLy based on the distance between the corresponding readout circuit and the power supply circuit. For example, the plurality of compensators 123_0 to 123_y may reduce the readout deviation T between the plurality of detection signals DS0 to DSy to facilitate positive compensation of the readout deviation T. Therefore, the plurality of delayed detection signals DS0 ′ to DSy′ output from the plurality of compensators 123_0 to 123_y may have the same readout time delay.

[0070] The plurality of counters 125_0 to 125_y may output a plurality of counting signals CNT0 to CNTy corresponding to the plurality of delayed detection signals DS0 ′ to DSy′, respectively.

[0071] Figure 5A and Figure 5B Various embodiments according to the present invention are shown. Figure 3A and Figure 3B Various implementations of compensators 123_0 to 123_y. Figure 5A and Figure 5B , for convenience of description, the compensators 123_0 to 123_y are shown as the first to eighth compensators, ie, y=7.

[0072] Reference Figure 5A and Figure 5B , the fourth and fifth compensators disposed in the center of the first to eighth compensators may be set to have relatively small resistance values, and the first to third compensators and the sixth to eighth compensators may be set to have relatively large resistance values ​​toward both ends thereof.

[0073] According to an embodiment, a readout deviation between a plurality of pixel signals may be positively compensated and thereby mitigated.

[0074] Figure 6 is a block diagram illustrating an image sensing device 200 according to various embodiments of the present invention.

[0075] Reference Figure 6 , the image sensing device 200 may include a pixel region 210, a readout region 220, and a power supply region.

[0076] The pixel area 210 may include a pixel array. The pixel array may include a plurality of pixels PX00 to PXxy (where x and y are natural numbers) arranged along rows and columns. For example, the plurality of pixels PX00 to PXxy may be arranged in a first row ROW0 to a (x+1)th row ROWx and a first column COL0 to a (y+1)th column COLy. The pixel array may output a plurality of pixel signals PS0 to PSy to a plurality of column lines CL0 to CLy. For example, the first pixel PX00 to the (y+1)th pixel PX0y arranged in the first row ROW0 may output the first pixel signal PS0 to the (y+1)th pixel signal PSy to the first column line CL0 to the (y+1)th column line CLy during the first single row time period, and the first pixel PXx0 to the (y+1)th pixel PXxy arranged in the (x+1)th row ROWx may output the first pixel signal PS0 to the (y+1)th pixel signal PSy to the first column line CL0 to the (y+1)th column line CLy during the (x+1) single row time period.

[0077] The readout region 220 may include a plurality of readout circuits RD0 to RDy. The plurality of readout circuits RD0 to RDy may be connected to the pixel array through a plurality of column lines CL0 to CLy, and read out a plurality of pixel signals PS0 to PSy. For example, the first readout circuit RD0 to the (y+1)th readout circuit RDy may be connected to the first column line CL0 to the (y+1)th column line CLy, and read out the first pixel signal PS0 to the (y+1)th pixel signal PSy from the first column line CL0 to the (y+1)th column line CLy, and then output the signals as the first count signal CNT0 to the (y+1)th count signal CNTy.

[0078] When reading out the pixel signals PS0 to PSy, the plurality of readout circuits RD0 to RDy may compensate for the readout deviation between the plurality of pixel signals PS0 to PSy. For example, the plurality of readout circuits RD0 to RDy may compensate for the readout deviation between the plurality of pixel signals PS0 to PSy by applying a corresponding predetermined resistance value in each path within the plurality of readout circuits RD0 to RDy, each path executing a corresponding pixel signal in the plurality of pixel signals PS0 to PSy, thereby inversely compensating for the readout deviation between the plurality of pixel signals PS0 to PSy. Inversely compensating for the readout deviation refers to increasing the readout deviation between the plurality of pixel signals PS0 to PSy. To this end, the resistance value in each path within the plurality of readout circuits RD0 to RDy may be set so that the readout deviation between the plurality of pixel signals PS0 to PSy may be increased.

[0079] The power supply region may include power supply circuits 230 and 250, respectively. The power supply circuits 230 and 250 may generate power required by the readout region 220 and supply the power to the readout region 220. For example, the power supply circuits 230 and 250 may jointly supply power to the plurality of readout circuits RD0 to RDy included in the readout region 220. The power supply circuit 230 may be disposed closest to the first readout circuit RD0 among the plurality of readout circuits RD0 to RDy, and the power supply circuit 250 may be disposed closest to the (y+1)th readout circuit RDy among the plurality of readout circuits RD0 to RDy.

[0080] Figure 7 It is a diagram showing various embodiments according to the present invention. Figure 6 Block diagram of multiple readout circuits RD0 to RDy.

[0081] Reference Figure 7 , the first readout circuit RD0 may include a first detector 221_0 , a first compensator 223_0 , and a first counter 225_0 .

[0082] The first detector 221_0 may be coupled to the first column line CL0 , and may receive the first pixel signal PS0 through the first column line CL0 , and output a first detection signal DS0 corresponding to the voltage level of the first pixel signal PS0 to a first readout line RL0 (hereinafter referred to as a “first initial readout line”).

[0083] The first compensator 223_0 may be connected to the first initial readout line RL0. The first compensator 223_0 may apply a predetermined resistance value in the first initial readout line RL0. For example, when detected by the first detector 221_0, the first detection signal DS0 on the first readout line RL0 has a readout time delay. The amount of the readout time delay of the first detection signal DS0 may be different from the amount of the readout time delay of each of the second detection signal DS1 to the (y+1)th detection signal DSy on the second readout line RL1 to the (y+1)th readout line RLy. For inverse compensation according to various embodiments of the present invention, by using a load (not shown) having a predetermined resistance value as the first compensator 223_0 to apply a predetermined resistance value in the first initial readout line RL0, the first compensator 223_0 may adjust the readout time delay of the first detection signal DS0 so that the difference between the readout time delay of the first detection signal DS0 and the readout time delay of the second to (y+1)th detection signals DS1 to DSy may be increased (as shown below in FIG. 8A to FIG. 10B The first compensator 223_0 may output the inverse-compensated first detection signal DS0 as a delayed first detection signal DS0′ to a first readout line RL0′ (hereinafter referred to as “first last readout line”).

[0084] The first counter 225_0 may be coupled to the first last readout line RL0 ′. The first counter 225_0 may count the delayed first detection signal DS0 ′ and output a first counting signal CNT0 .

[0085] Since the second readout circuit RD1 to the (y+1)th readout circuit RDy may be configured similarly to the first readout circuit RD0, a description thereof will be omitted for clarity. However, a resistance value set in at least one of the second compensator 223_1 to the (y+1)th compensator 223_y may be different from a resistance value set in the first compensator 223_0. That is, the plurality of compensators 223_0 to 223_y included in the plurality of readout circuits RD0 to RDy may apply different resistance values ​​in two or more of the plurality of readout lines RL0 to RLy.

[0086] Fig. 8A and Figure 8B Various embodiments according to the present invention are shown. Figure 7 An example of the first compensator 223_0.

[0087] Reference Fig. 8A, the first compensator 223_0 may include a first load. The first load may be a non-self-aligned silicide polysilicon resistor. The non-self-aligned silicide polysilicon resistor may include a silicide region A and a non-self-aligned silicide region B. The silicide region A may have a relatively small resistance value, and the non-self-aligned silicide region B may have a relatively large resistance value. The resistance value of the non-self-aligned silicide polysilicon resistor may be set by adjusting the size of each of the silicide region A and the non-self-aligned silicide B. For example, as the size of the non-self-aligned silicide region B increases, the resistance value of the non-self-aligned silicide polysilicon resistor may increase, and as the size of the non-self-aligned silicide region B decreases, the resistance value of the non-self-aligned silicide polysilicon resistor may decrease.

[0088] Each of the second to (y+1)th compensators 223_1 to 223_y may include a non-self-aligned silicide polysilicon resistor similar to the first compensator 223_0. However, the size of the non-self-aligned silicide region included in at least one of the second to (y+1)th compensators 223_1 to 223_y may be different from the size of the non-self-aligned silicide region B included in the first compensator 223_0.

[0089] Then, refer to Figure 8B , the first compensator 223_0 may include a second load. The second load may be a metal resistor. The metal resistor may include a metal wire. The resistance value of the metal resistor may be set by adjusting the length of the metal wire. For example, as the length of the metal wire increases, the resistance value of the metal resistor may increase, and as the length of the metal wire decreases, the resistance value of the metal resistor may decrease.

[0090] Each of the second to (y+1)th compensators 223_1 to 223_y may include a metal resistor similar to the first compensator 223_0. However, the length of the metal line included in at least one of the second to (y+1)th compensators 223_1 to 223_y may be different from the length of the metal line included in the first compensator 223_0.

[0091] Below, we will refer to Fig. 9 , Fig. 10A and Fig. 10B The operation of the image sensing device 200 having the above-described configuration according to various embodiments of the present invention is described.

[0092] Fig. 9 It is a diagram showing various embodiments according to the present invention. Figure 6 FIG. 2 is a graph showing the operation of the image sensing device 200 .

[0093] Reference Fig. 9, a readout deviation T may occur between the plurality of pixel signals PS0 to PSy. Specifically, a readout deviation T may occur between the plurality of detection signals DS0 to DSy. Fig. 9 In FIG. 1 , since the power supply circuits 230 and 250 for commonly supplying power to the plurality of readout circuits RD0 to RDy are disposed closest to the first readout circuit RD0 and the (y+1)th readout circuit RDy, a graph representing the readout deviation T is shown in a convex shape at the center of the column axis. Therefore, the plurality of detection signals DS0 to DSy may be output with different readout time delays according to different distances from the power supply circuit to the corresponding readout circuit, so that the readout deviation T may occur between the plurality of detection signals DS0 to DSy.

[0094] A corresponding resistance value suitable for realizing inverse compensation may be preset in the plurality of compensators 223_0 to 223_y according to the readout deviation T. For example, when the distance between the corresponding readout circuit and the power supply circuit increases, the resistance value set in the compensators 223_0 to 223_y may be larger, and when the distance between the corresponding readout circuit and the power supply circuit decreases, the resistance value set in the compensators 223_0 to 223_y may be smaller. The plurality of compensators 223_0 to 223_y may inversely compensate for the readout deviation T between the plurality of detection signals DS0 to DSy by applying the corresponding resistance value in the plurality of readout lines RL0 to RLy based on the distance between the corresponding readout circuit and the power supply circuit. Therefore, the difference in readout time delay between the plurality of delayed detection signals DS0' to DSy' output from the plurality of compensators 223_0 to 223_y may be further increased. In other words, the readout deviation T' between the plurality of delayed detection signals DS0' to DSy' may increase more than the readout deviation T between the plurality of detection signals DS0 to DSy.

[0095] The plurality of counters 225_0 to 225_y may respectively output a plurality of count signals CNT0 to CNTy corresponding to the plurality of delayed detection signals DS0' to DSy'. When the plurality of counters 225_0 to 225_y operate at similar timing, peak noise due to the plurality of counters 225_0 to 225_y may occur. However, since there is a readout deviation T' between the plurality of delayed detection signals DS0' to DSy', the peak noise due to the plurality of counters 225_0 to 225_y may be dispersed.

[0096] Fig. 10A and Fig. 10B Various embodiments according to the present invention are shown. Fig. 8A and Figure 8B Various implementations of compensators 223_0 to 223_y. Fig. 10A and Fig. 10B, for convenience of description, the compensators 223_0 to 223_y are shown as the first to eighth compensators, ie, y=7.

[0097] Reference Fig. 10A and Fig. 10B , the fourth and fifth compensators disposed in the center of the first to eighth compensators may be set to have relatively large resistance values, and the first to third compensators and the sixth to eighth compensators may be set to have relatively small resistance values ​​toward both ends thereof.

[0098] According to an embodiment, a readout deviation between a plurality of pixel signals may be inversely compensated, thereby dispersing peak noise caused by a plurality of counters.

[0099] Fig.11 is a block diagram illustrating an image sensing device 300 according to various embodiments of the present invention.

[0100] Reference Fig.11 , the image sensing device 300 may include a pixel region 310 , a readout region 320 , and a power supply region.

[0101] The pixel area 310 may include a pixel array. The pixel array may include a plurality of pixels PX00 to PXxy (where x and y are natural numbers) arranged along rows and columns. For example, the plurality of pixels PX00 to PXxy may be arranged in a first row ROW0 to a (x+1)th row ROWx and a first column COL0 to a (y+1)th column COLy. The pixel array may output a plurality of pixel signals PS0 to PSy to a plurality of column lines CL0 to CLy. For example, the first pixel PX00 to the (y+1)th pixel PX0y arranged in the first row ROW0 may output the first pixel signal PS0 to the (y+1)th pixel signal PSy to the first column line CL0 to the (y+1)th column line CLy during the first single row time period, and the first pixel PXx0 to the (y+1)th pixel PXxy arranged in the (x+1)th row ROWx may output the first pixel signal PS0 to the (y+1)th pixel signal PSy to the first column line CL0 to the (y+1)th column line CLy during the (x+1) single row time period.

[0102] The readout region 320 may include a plurality of readout circuits RD0 to RDy. The plurality of readout circuits RD0 to RDy may be connected to the pixel array through a plurality of column lines CL0 to CLy, and read out a plurality of pixel signals PS0 to PSy. For example, the first readout circuit RD0 to the (y+1)th readout circuit RDy may be connected to the first column line CL0 to the (y+1)th column line CLy, and read out the first pixel signal PS0 to the (y+1)th pixel signal PSy from the first column line CL0 to the (y+1)th column line CLy, and then output the signals as the first count signal CNT0 to the (y+1)th count signal CNTy.

[0103] When reading out the pixel signals PS0 to PSy, the plurality of readout circuits RD0 to RDy may compensate for the readout deviations between the plurality of pixel signals PS0 to PSy based on the plurality of control signals CTRL<0:n> (where n is a natural number). For example, the plurality of readout circuits RD0 to RDy may compensate for the readout deviations between the plurality of pixel signals PS0 to PSy by applying one of a plurality of predetermined resistance values ​​in each path within the plurality of readout circuits RD0 to RDy, each path performing a corresponding pixel signal among the plurality of pixel signals PS0 to PSy, thereby compensating for the readout deviations between the plurality of pixel signals PS0 to PSy. Specifically, each of the plurality of readout circuits RD0 to RDy may adjust the resistance values ​​to be applied in each path within the plurality of readout circuits RD0 to RDy respectively under the control of the control signal CTRL<0:n>, thereby determining one of the resistance values. In addition, each of the plurality of readout circuits RD0 to RDy may flexibly adjust the resistance values ​​to be applied in each path within the plurality of readout circuits RD0 to RDy respectively under the control of the control signal CTRL<0:n> according to the changes in process, voltage and temperature (PVT).

[0104] Compensation may include positive compensation and inverse compensation. Positive compensation refers to reducing the readout deviation between multiple pixel signals PS0 to PSy. To this end, the resistance value to be applied in each path within the multiple readout circuits RD0 to RDy may be set so that the readout deviation between the multiple pixel signals PS0 to PSy can be reduced. Inverse compensation refers to increasing the readout deviation between the multiple pixel signals PS0 to PSy. To this end, the resistance value to be applied in each path within the multiple readout circuits RD0 to RDy may be set so that the readout deviation between the multiple pixel signals PS0 to PSy can be increased.

[0105] The power supply region may include power supply circuits 330 and 340, respectively. The power supply circuits 330 and 340 may generate power required by the readout region 320 and supply the power to the readout region 320. For example, the power supply circuits 330 and 340 may jointly supply power to the plurality of readout circuits RD0 to RDy included in the readout region 320. The power supply circuit 330 may be disposed closest to the first readout circuit RD0 among the plurality of readout circuits RD0 to RDy, and the power supply circuit 340 may be disposed closest to the (y+1)th readout circuit RDy among the plurality of readout circuits RD0 to RDy.

[0106] Fig.12 It is a diagram showing various embodiments according to the present invention. Fig.11 Block diagram of multiple readout circuits RD0 to RDy.

[0107] Reference Fig.12, the first readout circuit RD0 may include a first detector 321_0 , a first compensator 323_0 , and a first counter 325_0 .

[0108] The first detector 321_0 may be coupled to the first column line CL0 , and may receive the first pixel signal PS0 through the first column line CL0 , and output a first detection signal DS0 corresponding to the voltage level of the first pixel signal PS0 to a first readout line RL0 (hereinafter referred to as a “first initial readout line”).

[0109] The first compensator 323_0 may be coupled to the first initial readout line RL0. The first compensator 323_0 may selectively apply one of a plurality of resistance values ​​in the first initial readout line RL0 under the control of a plurality of control signals CTRL<0:n>. For positive compensation according to various embodiments of the present invention, by applying one of a plurality of first resistance values ​​in the first initial readout line RL0 using a plurality of loads (not shown) each having one of a plurality of first resistance values ​​under the control of the control signal CTRL<0:n>, the first compensator 323_0 may adjust the readout time delay of the first detection signal DS0 so that a difference between the readout time delay of the first detection signal DS0 and the readout time delay of the second detection signal DS1 to the (y+1)th detection signal DSy may be reduced (as described below in Figures 13 to 15 For inverse compensation according to various embodiments of the present invention, by applying one of a plurality of second resistance values ​​in the first initial readout line RL0 using a plurality of loads (not shown) each having one of a plurality of second resistance values ​​under the control of the control signal CTRL<0:n>, the first compensator 323_0 may adjust the readout time delay of the first detection signal DS0 so that the difference between the readout time delay of the first detection signal DS0 and the readout time delay of the second detection signal DS1 to the (y+1)th detection signal DSy may be increased (as described below in Fig.13 , Fig.14A , Fig. 14B and Fig.16 The first compensator 323_0 may output the positively compensated or inversely compensated first detection signal DS0 as a delayed first detection signal DS0′ to a first readout line RL0′ (hereinafter referred to as “first last readout line”).

[0110] The first counter 325_0 may be coupled to the first last readout line RL0 ′. The first counter 325_0 may count the delayed first detection signal DS0 ′ and output a first counting signal CNT0 .

[0111] Since the second readout circuit RD1 to the (y+1)th readout circuit RDy may be configured similarly to the first readout circuit RD0, a description thereof will be omitted for clarity. However, the plurality of resistance values ​​set in at least one of the second compensator 123_1 to the (y+1)th compensator 123_y may be different from the plurality of resistance values ​​set in the first compensator 323_0.

[0112] Fig.13 It is a diagram showing various embodiments according to the present invention. Fig.12 1 to 2. Circuit diagram of the first to (y+1)th compensator 323_0 to 323_y.

[0113] Reference Fig.13 , the first compensator 323_0 may include a plurality of first switches SW00 to SW0n and a plurality of first loads R00 to R0n.

[0114] The plurality of first switches SW00 to SW0n may be connected in parallel between the first initial readout line RL0 to which the first detection signal DS0 is input and the plurality of first loads R00 to R0n. Under the control of the plurality of control signals CTRL<0:n>, the plurality of first switches SW00 to SW0n may connect one or more of the first loads R00 to R0n to the first initial readout line RL0.

[0115] The plurality of first loads R00 to R0n may be connected in parallel between the first last readout line RL0' outputting the delayed first detection signal DS0' and the plurality of first switches SW00 to SW0n. The plurality of first loads R00 to R0n may have the same resistance value.

[0116] The first compensator 323_0 having the above-described configuration may have one of a plurality of resistance values ​​according to a combination of a plurality of first loads R00 to R0n determined by a plurality of first switches SW00 to SW0n.

[0117] Since the second compensator 323_1 to the (y+1)th compensator 323_y may be configured similarly to the first compensator 323_0, their description will be omitted for clarity. However, the plurality of resistance values ​​set in at least one of the second compensator 323_1 to the (y+1)th compensator 323_y may be different from the plurality of resistance values ​​set in the first compensator 323_0. For example, the plurality of second loads R10 to R1n included in the second compensator 323_1 have the same resistance value, but may have a resistance value different from the plurality of first loads R00 to R0n included in the first compensator 323_0.

[0118] Fig.14A and Fig. 14B Various embodiments according to the present invention are shown. Fig.13An example of a first load R00 among a plurality of first loads R00 to R0n.

[0119] Reference Fig.14A , the first load R00 may be a non-self-aligned silicide polysilicon resistor. The non-self-aligned silicide polysilicon resistor may include a silicide region A and a non-self-aligned silicide region B. The silicide region A may have a relatively small resistance value, and the non-self-aligned silicide region B may have a relatively large resistance value. The resistance value of the non-self-aligned silicide polysilicon resistor may be set by adjusting the size of each of the silicide region A and the non-self-aligned silicide region B. For example, as the size of the non-self-aligned silicide region B increases, the resistance value of the non-self-aligned silicide polysilicon resistor may increase, and as the size of the non-self-aligned silicide region B decreases, the resistance value of the non-self-aligned silicide polysilicon resistor may decrease.

[0120] Each of the first loads R01 and R0n among the plurality of first loads R00 to R0n may include a non-self-aligned silicide polysilicon resistor in the same manner as the first load R00. Since the plurality of first loads R00 to R0n have the same resistance value, the self-aligned silicide region A and the non-self-aligned silicide region B may be designed to be the same size as each other.

[0121] The corresponding loads included in the second compensator 323_1 to the (y+1)th compensator 323_y may include a non-self-aligned salicide polysilicon resistor in the same manner as the first load R00. However, since the plurality of loads included in at least one of the second compensators 323_1 to the (y+1)th compensator 323_y have a resistance value different from that of the first load R00, the salicide region A and the non-self-aligned salicide region B of each of the plurality of loads included in at least one of the second compensators 323_1 to the (y+1)th compensator 323_y may be designed to be different in size from that of the first load R00. For example, the salicide region A and the non-self-aligned salicide region B of each of the plurality of second loads R10 to R1n included in the second compensator 323_1 may be designed to be different in size from that of the first load R00.

[0122] Then, refer to Fig. 14B , the first load R00 may be a metal resistor. The metal resistor may include a metal wire. The resistance value of the metal resistor may be set by adjusting the length of the metal wire. For example, as the length of the metal wire increases, the resistance value of the metal resistor may increase, and as the length of the metal wire decreases, the resistance value of the metal resistor may decrease.

[0123] Each of the first loads R01 and R0n among the plurality of first loads R00 to R0n may include a metal resistor in the same manner as the first load R00. Since the plurality of first loads R00 to R0n have the same resistance value, metal lines included in the metal resistors of the first loads R01 and R0n may be designed to have the same length.

[0124] Each load included in the second compensator 323_1 to the (y+1)th compensator 323_y may include a metal resistor in the same manner as the first load R00. However, since the plurality of loads included in at least one of the second compensators 323_1 to the (y+1)th compensator 323_y have a resistance value different from that of the first load R00, the metal lines of the plurality of loads included in at least one of the second compensators 323_1 to the (y+1)th compensator 323_y may be designed to have a length different from that of the metal line of the first load R00. For example, the metal lines of the plurality of second loads R10 to R1n included in the second compensator 323_1 may be designed to have a length different from that of the metal line of the first load R00.

[0125] Below, we will refer to Fig.15 and Fig.16 The operation of the image sensing device 300 having the above-described configuration according to various embodiments of the present invention is described.

[0126] Fig.15 It is a diagram showing various embodiments according to the present invention. Fig.11 FIG. 5 is a graph of a positive compensation operation of the image sensing device 300 .

[0127] Reference Fig.15 , a readout deviation T may occur between the plurality of pixel signals PS0 to PSy. Specifically, a readout deviation T may occur between the plurality of detection signals DS0 to DSy. Fig.15 In FIG. 1 , since the power supply circuits 330 and 340 for commonly supplying power to the plurality of readout circuits RD0 to RDy are respectively disposed closest to the first readout circuit RD0 and the (y+1)th readout circuit RDy, a graph representing the readout deviation T is shown in a convex shape at the center of the column axis. Therefore, the plurality of detection signals DS0 to DSy may be output with different readout time delays according to different distances from the power supply circuit to the corresponding readout circuit, so that the readout deviation T may occur between the plurality of detection signals DS0 to DSy.

[0128] A corresponding resistance value suitable for realizing positive compensation may be preset in a plurality of compensators 323_0 to 323_y according to the readout deviation T. For example, when the distance between the corresponding readout circuit and the power supply circuit decreases, the resistance value set in the compensators 323_0 to 323_y may be larger, and when the distance between the corresponding readout circuit and the power supply circuit increases, the resistance value set in the compensators 323_0 to 323_y may be smaller. The plurality of compensators 323_0 to 323_y may finely adjust the corresponding resistance value under the control of the plurality of control signals CTRL<0:n>. The plurality of compensators 323_0 to 323_y may positively compensate for the readout deviation T between the plurality of detection signals DS0 to DSy by applying the corresponding resistance value in the plurality of readout lines RL0 to RLy based on the distance between the corresponding readout circuit and the power supply circuit. For example, the plurality of compensators 323_0 to 323_y may reduce the readout deviation T between the plurality of detection signals DS0 to DSy to facilitate positive compensation of the readout deviation T. Therefore, the plurality of delayed detection signals DS0 ′ to DSy′ output from the plurality of compensators 323_0 to 323 — y may have the same readout time delay.

[0129] The plurality of counters 325_0 to 325_y may output a plurality of counting signals CNT0 to CNTy corresponding to the plurality of delayed detection signals DS0 ′ to DSy′, respectively.

[0130] Fig.16 It is a diagram showing some embodiments according to the present invention. Fig.11 FIG. 5 is a graph showing an inverse compensation operation of the image sensing device 300 .

[0131] Reference Fig.16 , a readout deviation T may occur between the plurality of pixel signals PS0 to PSy. Specifically, a readout deviation T may occur between the plurality of detection signals DS0 to DSy. Fig.16 In FIG. 1 , since the power supply circuits 330 and 340 for commonly supplying power to the plurality of readout circuits RD0 to RDy are respectively disposed closest to the first readout circuit RD0 and the (y+1)th readout circuit RDy, a graph representing the readout deviation T is shown in a convex shape at the center of the column axis. Therefore, the plurality of detection signals DS0 to DSy may be output with different readout time delays according to different distances from the power supply circuit to the corresponding readout circuit, so that the readout deviation T may occur between the plurality of detection signals DS0 to DSy.

[0132] A corresponding resistance value suitable for implementing inverse compensation may be preset in a plurality of compensators 323_0 to 323_y according to the readout deviation T. For example, when the distance between the corresponding readout circuit and the power supply circuit increases, the resistance value set in the compensator may be larger, and when the distance between the corresponding readout circuit and the power supply circuit decreases, the resistance value set in the compensator 323_0 to 323_y may be smaller. The plurality of compensators 323_0 to 323_y may finely adjust the corresponding resistance value under the control of the plurality of control signals CTRL<0:n>. The plurality of compensators 323_0 to 323_y may inversely compensate for the readout deviation T between the plurality of detection signals DS0 to DSy by applying a corresponding predetermined resistance value in the plurality of readout lines RL0 to RLy based on the distance between the corresponding readout circuit and the power supply circuit. Therefore, the difference in readout time delay between the plurality of delayed detection signals DS0' to DSy' output from the plurality of compensators 323_0 to 323_y may be further increased. In other words, the readout deviation T′ between the plurality of delayed detection signals DS0 ′ to DSy′ may increase over the readout deviation T between the plurality of detection signals DS0 to DSy.

[0133] The plurality of counters 325_0 to 325_y may respectively output a plurality of count signals CNT0 to CNTy corresponding to the plurality of delayed detection signals DS0' to DSy'. When the plurality of counters 325_0 to 325_y operate at similar timing, peak noise due to the plurality of counters 325_0 to 325_y may occur. However, since there is a readout deviation T' between the plurality of delayed detection signals DS0' to DSy', the peak noise due to the plurality of counters 325_0 to 325_y may be dispersed.

[0134] According to various embodiments of the present invention, the resistance value required to compensate for the readout deviation between multiple pixel signals can be finely adjusted, and the resistance value can be adjusted according to the change of process, voltage and temperature (PVT). In addition, the readout deviation between multiple pixel signals can be mitigated by positively compensating the readout deviation between multiple pixel signals, or the peak noise caused by multiple counters can be dispersed by inversely compensating the readout deviation between multiple pixel signals.

[0135] Fig.17 is a block diagram illustrating an image sensing device 400 according to various embodiments of the present invention.

[0136] Reference Fig.17 , the image sensing device 400 may include a pixel region 410 , a readout region 420 , and a power supply region.

[0137] The pixel area 410 may include a pixel array. The pixel array may include a plurality of pixels PX00 to PXxy (where x and y are natural numbers) arranged along rows and columns. For example, the plurality of pixels PX00 to PXxy may be arranged in a first row ROW0 to a (x+1)th row ROWx and a first column COL0 to a (y+1)th column COLy. The pixel array may output a plurality of pixel signals PS0 to PSy to a plurality of column lines CL0 to CLy. For example, the first pixel PX00 to the (y+1)th pixel PX0y arranged in the first row ROW0 may output the first pixel signal PS0 to the (y+1)th pixel signal PSy to the first column line CL0 to the (y+1)th column line CLy during the first single row time period, and the first pixel PXx0 to the (y+1)th pixel PXxy arranged in the (x+1)th row ROWx may output the first pixel signal PS0 to the (y+1)th pixel signal PSy to the first column line CL0 to the (y+1)th column line CLy during the (x+1) single row time period.

[0138] The readout region 420 may include a plurality of readout circuits RD0 to RDy. The plurality of readout circuits RD0 to RDy may be connected to the pixel array through a plurality of column lines CL0 to CLy, and may read out a plurality of pixel signals PS0 to PSy. For example, the first readout circuit RD0 to the (y+1)th readout circuit RDy may be connected to the first column line CL0 to the (y+1)th column line CLy, and read out the first pixel signal PS0 to the (y+1)th pixel signal PSy from the first column line CL0 to the (y+1)th column line CLy, and then output the signals as the first count signal CNT0 to the (y+1)th count signal CNTy.

[0139] When reading out the pixel signals PS0 to PSy, the plurality of readout circuits RD0 to RDy may be configured to generate the pixel signals PS0 to PSy in response to the first and second control signals CTRL <a:b>Under the control of , the readout deviation between the multiple pixel signals PS0 to PSy is compensated. For example, the multiple readout circuits RD0 to RDy can compensate for the readout deviation between the multiple pixel signals PS0 to PSy by applying one of the predetermined first resistance value and the second resistance value in each path within the multiple readout circuits RD0 to RDy, and each path executes the corresponding pixel signal in the multiple pixel signals PS0 to PSy, thereby compensating the readout deviation between the multiple pixel signals PS0 to PSy. Compensating the readout deviation may include positive compensation and inverse compensation. Positive compensation refers to reducing the readout deviation between the multiple pixel signals PS0 to PSy. To this end, the first resistance value to be applied in each path within the multiple readout circuits RD0 to RDy can be set so that the readout deviation between the multiple pixel signals PS0 to PSy can be reduced. Inverse compensation refers to increasing the readout deviation between the multiple pixel signals PS0 to PSy. To this end, the second resistance value to be applied in each path within the multiple readout circuits RD0 to RDy can be set so that the readout deviation between the multiple pixel signals PS0 to PSy can be increased.

[0140] The power supply region may include power supply circuits 430 and 440, respectively. The power supply circuits 430 and 440 may generate power required by the readout region 420 and supply the power to the readout region 420. For example, the power supply circuits 430 and 440 may jointly supply power to the plurality of readout circuits RD0 to RDy included in the readout region 420. The power supply circuit 430 may be disposed closest to the first readout circuit RD0 among the plurality of readout circuits RD0 to RDy, and the power supply circuit 440 may be disposed closest to the (y+1)th readout circuit RDy among the plurality of readout circuits RD0 to RDy.

[0141] Fig.18 It is a diagram showing various embodiments according to the present invention. Fig.17 Block diagram of multiple readout circuits RD0 to RDy.

[0142] Reference Fig.18 , the first readout circuit RD0 may include a first detector 421_0 , a first compensator 423_0 , and a first counter 425_0 .

[0143] The first detector 421_0 may be coupled to the first column line CL0. The first detector 421_0 may receive the first pixel signal PS0 through the first column line CL0 and output a first detection signal DS0 corresponding to the voltage level of the first pixel signal PS0 to the first readout line RL0 (hereinafter referred to as "first initial readout line").

[0144] The first compensator 423_0 may be coupled to the first initial readout line RL0. The first compensator 423_0 may be coupled to the first initial readout line RL0. <a:b>Under the control of , one of the predetermined first resistance value and the second resistance value is applied to the first initial read line RL0. For positive compensation, when the first and second control signals CTRL <a:b>The first control signal CTRL When enabled, the first compensator 423_0 can be activated by the first control signal CTRL On the other hand, for reverse compensation, when the first and second control signals CTRL <a:b>The second control signal CTRL When enabled, the first compensator 423_0 can be activated by the enabled second control signal CTRL The first compensator 423_0 may output the positively compensated or inversely compensated first detection signal DS0 as a delayed first detection signal DS0' to the first readout line RL0' (hereinafter referred to as "the first final readout line").

[0145] The first counter 425_0 may be coupled to the first last readout line RL0 ′. The first counter 425_0 may count the delayed first detection signal DS0 ′ and output a first counting signal CNT0 .

[0146] Since the second readout circuit RD1 to the (y+1)th readout circuit RDy may be configured similarly to the first readout circuit RD0, a description thereof will be omitted for clarity. However, the first resistance value and the second resistance value set in at least one of the second compensator 423_1 to the (y+1)th compensator 423_y may be different from the first resistance value and the second resistance value set in the first compensator 423_0.

[0147] < / a:b> Fig.19 It is a diagram showing various embodiments according to the present invention. Fig.18 1 to 2. Circuit diagram of the first to (y+1)th compensator 423_0 to 423_y.

[0148] Reference Fig.19 , the first compensator 423_0 may include first switches SW00 and SW01 , and first loads R00 and R01 .

[0149] The first switch SW00 may be coupled between the first initial readout line RL0 to which the first detection signal DS0 is input and the first load R00. The first switch SW00 may be switched on at the first control signal CTRL The first initial readout line RL0 is selectively coupled to the first load R00 under the control of .

[0150] The first switch SW01 may be coupled between the first initial readout line RL0 to which the first detection signal DS0 is input and the first load R01. The first switch SW01 may be coupled between the first initial readout line RL0 to which the first detection signal DS0 is input and the first load R01. The first initial readout line RL0 is selectively coupled to the first load R01 under the control of .

[0151] The first load R00 may be coupled between the first last readout line RL0' outputting the delayed first detection signal DS0' and the first switch SW00. The first load R00 may have a first resistance value for positive compensation.

[0152] The first load R01 may be coupled between the first last readout line RL0' outputting the delayed first detection signal DS0' and the first switch SW01. The first load R01 may have a second resistance value for reverse compensation. The second resistance value may be different from the first resistance value.

[0153] Since the second compensator 423_1 to the (y+1)th compensator 423_y may be configured similarly to the first compensator 423_0, a description thereof will be omitted for clarity. However, the first resistance value and the second resistance value set in at least one of the second compensator 423_1 to the (y+1)th compensator 423_y may be different from the first resistance value and the second resistance value set in the first compensator 423_0.

[0154] Fig. 20A and Fig. 20B Showing various embodiments according to the present invention Fig.19 An example of the first loads R00 and R01.

[0155] Reference Fig. 20A , each of the first loads R00 and R01 may be a non-self-aligned silicide polysilicon resistor. The non-self-aligned silicide polysilicon resistor may include a silicide region A and a non-self-aligned silicide region B. The silicide region A may have a relatively small resistance value, and the non-self-aligned silicide region B may have a relatively large resistance value. The resistance value of the non-self-aligned silicide polysilicon resistor may be set by adjusting the size of each of the silicide region A and the non-self-aligned silicide region B. For example, as the size of the non-self-aligned silicide region B increases, the resistance value of the non-self-aligned silicide polysilicon resistor may increase, and as the size of the non-self-aligned silicide region B decreases, the resistance value of the non-self-aligned silicide polysilicon resistor may decrease.

[0156] The loads included in each of the second compensators 423_1 to the (y+1)th compensators 423_y may include non-self-aligned salicide polysilicon resistors in the same manner as the first loads R00 and R01, respectively. However, since each of the loads included in at least one of the second compensators 423_1 to the (y+1)th compensators 423_y has a resistance value different from that of the first loads R00 and R01, the loads included in at least one of the second compensators 423_1 to the (y+1)th compensators 423_y may be designed to have a size different from that of the first loads R00 and R01. For example, the salicide region A and the non-salicide region B of the second load R10 included in the second compensator 423_1 may be designed to have a size different from that of the first load R00, and the salicide region A and the non-salicide region B of the second load R11 included in the second compensator 423_1 may be designed to have a size different from that of the first load R01.

[0157] Reference Fig. 20B , each of the first loads R00 and R01 may be a metal resistor. The metal resistor may include a metal wire. The resistance value of the metal resistor may be set by adjusting the length of the metal wire. For example, as the length of the metal wire increases, the resistance value of the metal resistor may increase, and as the length of the metal wire decreases, the resistance value of the metal resistor may decrease.

[0158] The loads included in each of the second compensators 423_1 to the (y+1)th compensators 423_y may include metal resistors in the same manner as the first loads R00 and R01, respectively. However, since each of the loads included in at least one of the second compensators 423_1 to the (y+1)th compensators 423_y has a resistance value different from that of the first loads R00 and R01 included in the first compensator 423_0, the length of the metal line of the load included in at least one of the second compensators 423_1 to the (y+1)th compensators 423_y may be designed to have a length different from that of the first loads R00 and R01 included in the first compensator 423_0. For example, the metal line of the second load R10 included in the second compensator 423_1 may be designed to have a different length from the first load R00 included in the first compensator 423_0, and the metal line of the second load R11 included in the second compensator 423_1 may be designed to have a different length from the first load R01 included in the first compensator 423_0.

[0159] Below, we will refer to Fig.21 and Fig. 22 The operation of the image sensing device 400 having the above-described configuration according to various embodiments of the present invention is described.

[0160] Fig.21 It is a diagram showing various embodiments according to the present invention. Fig.17 FIG. 4 is a graph of a positive compensation operation of the image sensing device 400 .

[0161] Reference Fig.21 , when the first and second control signals CTRL <a:b>The first control signal CTRL When enabled, operations related to positive compensation can be performed.

[0162] A readout deviation T may occur between the plurality of pixel signals PS0 to PSy. Specifically, a readout deviation T may occur between the plurality of detection signals DS0 to DSy. Fig.21 In FIG. 1 , since the power supply circuits 430 and 440 for commonly supplying power to the plurality of readout circuits RD0 to RDy are respectively disposed closest to the first readout circuit RD0 and the (y+1)th readout circuit RDy, a graph representing the readout deviation T is shown in a convex shape at the center of the column axis. Therefore, the plurality of detection signals DS0 to DSy may be output with different readout time delays according to different distances from the power supply circuit to the corresponding readout circuit, so that the readout deviation T may occur between the plurality of detection signals DS0 to DSy.

[0163] The corresponding first resistance values ​​suitable for realizing positive compensation may be preset in the plurality of compensators 423_0 to 423_y according to the readout deviation T. For example, when the distance between the corresponding readout circuit and the power supply circuit decreases, the first resistance value set in the compensators 423_0 to 423_y may be larger, and when the distance between the corresponding readout circuit and the power supply circuit increases, the first resistance value set in the compensators 423_0 to 423_y may be smaller. The plurality of compensators 423_0 to 423_y may be enabled at the first control signal CTRL The plurality of compensators 423_0 to 423_y may positively compensate for the readout deviation T between the plurality of detection signals DS0 to DSy by applying the corresponding first resistance value in the plurality of readout lines RL0 to RLy under the control of . For example, when positively compensating for the readout deviation T, the plurality of compensators 423_0 to 423_y may reduce the readout deviation T between the plurality of detection signals DS0 to DSy. Therefore, the plurality of delayed detection signals DS0' to DSy' output from the plurality of compensators 423_0 to 423_y may have the same readout time delay.

[0164] The plurality of counters 425_0 to 425_y may output a plurality of counting signals CNT0 to CNTy corresponding to the plurality of delayed detection signals DS0 ′ to DSy′.

[0165] Fig. 22 It is a diagram showing various embodiments according to the present invention. Fig.17 FIG. 4 is a graph showing an inverse compensation operation of the image sensing device 400 .

[0166] Reference Fig. 22 , when the first and second control signals CTRL <a:b>The second control signal CTRL When enabled, operations related to inverse compensation can be performed.

[0167] A readout deviation T may occur between the plurality of pixel signals PS0 to PSy. Specifically, a readout deviation T may occur between the plurality of detection signals DS0 to DSy. Since the power supply circuits 430 and 440 for commonly supplying power to the plurality of readout circuits RD0 to RDy are respectively disposed closest to the first readout circuit RD0 and the (y+1)th readout circuit RDy, a graph representing the readout deviation T is shown in a convex shape at the center of the column axis. Therefore, the plurality of detection signals DS0 to DSy may be output with different readout time delays according to different distances between the corresponding readout circuits and the power supply circuit, so that a readout deviation T may occur between the plurality of detection signals DS0 to DSy.

[0168] The corresponding second resistance values ​​suitable for implementing the inverse compensation may be preset in the plurality of compensators 423_0 to 423_y according to the readout deviation T. For example, when the distance between the corresponding readout circuit and the power supply circuit increases, the second resistance value set in the compensators 423_0 to 423_y may be larger, and when the distance between the corresponding readout circuit and the power supply circuit decreases, the second resistance value set in the compensators 423_0 to 423_y may be smaller. The plurality of compensators 423_0 to 423_y may be enabled when the second control signal CTRL Under the control of the plurality of compensators 423_0 to 423_y, the readout deviation T between the plurality of detection signals DS0 to DSy is inversely compensated by applying the corresponding second resistance value in the plurality of readout lines RL0 to RLy. Therefore, the difference in readout time delay between the plurality of delayed detection signals DS0' to DSy' output from the plurality of compensators 423_0 to 423_y can be further increased. In other words, the readout deviation T' between the plurality of delayed detection signals DS0' to DSy' can be increased by more than the readout deviation T between the plurality of detection signals DS0 to DSy.

[0169] The plurality of counters 425_0 to 425_y may output a plurality of count signals CNT0 to CNTy corresponding to the plurality of delayed detection signals DS0' to DSy'. When the plurality of counters 425_0 to 425_y operate at similar timing, peak noise due to the plurality of counters 425_0 to 425_y may occur. However, since there is a readout deviation T' between the plurality of delayed detection signals DS0' to DSy', the peak noise due to the plurality of counters 425_0 to 425_y may be dispersed.

[0170] According to various embodiments of the present invention, a first resistance value required for positive compensation of a readout deviation between a plurality of pixel signals and a second resistance value required for inverse compensation of a readout deviation between a plurality of pixel signals are configured to flexibly perform positive compensation and inverse compensation. In addition, the readout deviation between a plurality of pixel signals can be mitigated by positive compensation of the readout deviation, and the peak noise caused by a plurality of counters can be dispersed by inverse compensation of the readout deviation between a plurality of pixel signals.

[0171] According to an embodiment, degradation of characteristics caused when a plurality of pixel signals are read out is compensated, thereby improving operational reliability.

[0172] Although the present invention is shown and described with respect to specific embodiments, the disclosed embodiments are not intended to be limiting. In addition, it should be noted that those skilled in the art will recognize from this disclosure that the present invention may be implemented in various ways by substitution, change and modification without departing from the spirit and / or scope of the present disclosure. The present invention is intended to cover all such substitutions, changes and modifications that fall within the scope of the following claims.

[0173] CROSS-REFERENCE TO RELATED APPLICATIONS

[0174] This application claims priority to Korean Patent Application No. 10-2019-0114099, filed on September 17, 2019, the disclosure of which is incorporated herein by reference in its entirety. < / a:b> < / a:b> < / a:b> < / a:b> < / a:b>

Claims

1. An image sensing device, comprising: a pixel array including a plurality of pixels arranged in rows and columns and configured to output a plurality of pixel signals to a plurality of column lines; as well as A plurality of readout circuits are coupled to the pixel array via the plurality of column lines and configured to compensate for readout deviations between the plurality of pixel signals by applying corresponding predetermined resistance values ​​in the plurality of readout lines that read out the plurality of pixel signals when reading out the plurality of pixel signals, wherein the readout deviations refer to differences between readout time delays of the plurality of pixel signals.

2. The image sensing device according to claim 1, wherein The plurality of readout circuits positively compensate or inversely compensate the readout deviation between the plurality of pixel signals.

3. The image sensing device according to claim 1, wherein The plurality of readout circuits reduce the readout variation between the plurality of pixel signals when compensating for the readout variation between the plurality of pixel signals.

4. The image sensing device according to claim 1, wherein When compensating for the readout variation between the plurality of pixel signals, the plurality of readout circuits increase the readout variation between the plurality of pixel signals.

5. An image sensing device, comprising: a pixel array including a plurality of pixels arranged in rows and columns and configured to output a plurality of pixel signals to a plurality of column lines; a plurality of detectors coupled to the plurality of column lines and configured to output a plurality of detection signals to a plurality of readout lines, the plurality of detection signals corresponding to voltage levels of the respective pixel signals; a plurality of counters coupled to the plurality of readout lines and configured to count the plurality of detection signals respectively; as well as a plurality of compensators coupled to the plurality of sense lines and configured to apply respective predetermined resistance values ​​in the plurality of sense lines, Wherein, a different predetermined resistance value is applied to each of the plurality of readout lines.

6. The image sensing device according to claim 5, wherein: The corresponding predetermined resistance values ​​are set according to differences between readout time delays of the plurality of pixel signals.

7. The image sensing device according to claim 5, wherein: The respective predetermined resistance values ​​are set to reduce differences between readout time delays of the plurality of pixel signals.

8. The image sensing device according to claim 5, wherein: The respective predetermined resistance values ​​are set to increase a difference between readout time delays of the plurality of pixel signals.

9. The image sensing device according to claim 5, wherein: Each of the compensators includes a load, and the load includes a non-salicide polysilicon resistor.

10. The image sensing device according to claim 5, wherein: Each of the compensators includes a load, and the load includes a metal resistor.

11. An image sensing device, comprising: a pixel array including a plurality of pixels arranged in rows and columns and configured to output a plurality of pixel signals to a plurality of column lines; a plurality of detectors coupled to the plurality of column lines and configured to output a plurality of detection signals to a plurality of readout lines, the plurality of detection signals corresponding to voltage levels of the respective pixel signals; a plurality of counters coupled to the plurality of readout lines and configured to count the plurality of detection signals respectively; as well as A plurality of compensators are coupled to the plurality of readout lines and configured to selectively apply one of two or more resistance values ​​in each of the readout lines under the control of two or more common control signals.

12. The image sensing device according to claim 11, wherein The plurality of compensators apply different resistance values ​​in two or more of the plurality of readout lines.

13. The image sensing device according to claim 11, wherein The two or more resistance values ​​include a first resistance value and a second resistance value, wherein the first resistance value is set to reduce the readout deviation between the multiple pixel signals, and the second resistance value is set to increase the readout deviation between the multiple pixel signals, wherein the readout deviation refers to the difference between the readout time delays of the multiple pixel signals.

14. The image sensing device according to claim 11, wherein Each of the compensators comprises: First load; Second load; a first switch configured to selectively couple the first load to each of the readout lines under control of a first common control signal among the common control signals; and a second switch configured to selectively couple the second load to each of the readout lines under control of a second common control signal among the common control signals.

15. The image sensing device according to claim 14, wherein: Each of the first load and the second load includes a non-salicide polysilicon resistor.

16. The image sensing device according to claim 14, wherein: Each of the first load and the second load includes a metal resistor.

17. The image sensing device according to claim 11, wherein Each of the compensators comprises: Multiple loads; and A plurality of switches are configured to selectively couple one or more of the plurality of loads to each of the readout lines under control of the common control signal.

18. The image sensing device according to claim 17, wherein: The plurality of loads have the same resistance value.

19. The image sensing device according to claim 17, wherein: Each of the loads includes a non-salicide polysilicon resistor.

20. The image sensing device according to claim 17, wherein Each of the loads includes a metal resistor.

Images