Integrated communication link testing

Abstract

A test and measurement device includes: an input configured to receive an analog signal from a device under test (DUT); an analog-to-digital converter (ADC) coupled to the input and configured to convert the analog signal into a digital signal; a receiver implemented in a first field programmable gate array (FPGA) and configured to accept a digital signal and perform signal analysis on the digital signal; a transmitter implemented in a second FPGA and configured to generate a digital output signal; and a digital-to-analog converter (DAC) coupled to the transmitter and configured to convert the digital output signal from the transmitter into an analog signal and configured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high-speed data link, on which data about a current test environment can be shared.

Description

Technical Field

[0001] The present disclosure relates to test and measurement devices, and more particularly to systems and methods for testing communication links or devices using a high precision signal output generator that may also work in close coordination with a high precision signal receiver. Background Art

[0002] Accurate testing of modern electronic devices currently requires a collection of expensive equipment that is not necessarily designed to operate in coordination. Today's equipment requirements for performing accurate or high-frequency signal analysis on a communication link or device typically include a bit error rate tester (BERT), an arbitrary waveform generator (AWG), possibly a programmable pattern generator (PPG), an oscilloscope, a computer that integrates the functionality of the device, software operating on the computer, and multiple cables connecting all of the devices to each other and to the device under test (DUT). Using such a collection of different instruments and equipment to perform testing encounters many problems in addition to the obvious problem of the expense of purchasing, managing, and maintaining multiple test components in a test assembly.

[0003] One of the problems in the case of using such a collection of instruments relates to the non-repeatability of the measurement. In the case of precise testing, small differences within the system often produce large differences in specific measurements. For example, using cables of different lengths may have an impact on the output impedance of the AWG, or have an impact on the propagation time of the signal received by the oscilloscope. Therefore, even when the same main component is used in two different test assemblies, the measurement may also be different from one assembly to another based on the length of the connecting cable. Often, since precise test equipment is very expensive, even the main components are not the same in various test assemblies. For example, one test assembly may be using the second version of the AWG, while another test assembly is using the first version, which may have a restricted set of features. In such a case, due to the restricted function of the AWG assembly alone, the second test assembly may be prevented from running the same test as the first assembly. Further, some differences that affect the measurement may not even be detectable externally. For example, the impedance of the connecting cable may change over time, or the cable end may be experiencing wear and tear inside the cable, and is therefore invisible to the user. Furthermore, high precision instruments are typically calibrated either at the factory or periodically, or both, and it is virtually impossible to determine whether a difference in calibration (even a small difference) will have an effect on the overall test system. Thus, even in the best case with multiple test assemblies - when identical copies of the equipment are configured in the same way, using identical cables that appear to be identical outwardly - it may still not always be possible to have repeatable measurements from one test assembly to the next.

[0004] Another problem in the case of using multi-component devices in a test assembly is the lack of timing coordination between the various components. High-precision testing typically involves very high operating clock rates, and the devices in the test assembly generally need to work simultaneously to ensure test integrity. Even when the clock signal comes from a common source, it is difficult or impossible to fully synchronize the clock signal across the separate components of the device because of variations in the time it takes for each component of the device to receive and process the clock signal or because of cable impedance differences as described above or for other reasons.

[0005] Yet another problem in the case of using multi-component equipment in a test assembly is the excess power used to power each device individually. The power requirements for devices such as AWGs are generally set to allow for adequate operation when the device draws peak energy, plus an additional amount of power margin. Therefore, in a test assembly, because each separate component includes a power supply of maximum size, the components themselves generally draw more power than is required to operate the entire assembly. In addition to excessive energy consumption, using excess power may also generate excess heat, which may also negatively affect measurement results or prevent them from being repeatable due to various operating conditions.

[0006] Yet another problem with using multiple instruments in a test assembly is that it typically requires an incoherent and self-organizing software environment to create a complete test setup. For example, one test assembly may include a BERT from a first manufacturer using a first set of control signals, while another test assembly includes a BERT from a second manufacturer utilizing a second set of control signals. The control software for each of these test assemblies must therefore be customized so that it generates the appropriate control signals to operate the two different BERTs, which adds complexity, delay, and expense. This further exacerbates the problems described above with creating reproducible results.

[0007] Embodiments of the present disclosure address these and other deficiencies of the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The aspects, features and advantages of the embodiments of the present disclosure will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 is a functional block diagram of a single channel communication link tester including a receiving part and a transmitting part according to some embodiments of the present disclosure.

[0010] Figure 2 is based on Figure 1 Functional block diagram of the multi-channel version of the communication link tester.

[0011] Figure 3According to an embodiment of the present invention Figure 1 Functional block diagram of the receiver component of a communications link tester.

[0012] Figure 4 According to an embodiment of the present invention Figure 1 Functional block diagram of the digital components of the transmitter assembly of a communications link tester.

[0013] Figure 5 According to an embodiment of the present invention Figure 1 Functional block diagram of the analog components of the transmitter assembly of a communications link tester. DETAILED DESCRIPTION

[0014] Figure 1 is a functional block diagram of a single channel communication link tester 100 including a receiving part and a transmitting part according to some embodiments of the present disclosure. Figure 1 The diagram shows a single channel in which a single device under test (DUT) 110 is connected to the signal data channel of the transmitter and the receiver, but embodiments of the present invention may also include multiple channels, such as referring to Figure 2 Example DUTs may include: components or products that send and receive signals at very high rates, such as high-speed data communications and telecommunications networking equipment, such as switches and routers; fiber optic systems including components, links, and / or channels; cables and chip-to-chip communication links, such as serializer-deserializers (SERDES).

[0015] In general, the communication link tester 100 generates test signals and then sends them to the input of the DUT. The DUT operates on the test signals and sends output signals back to the communication link tester 100. The communication link tester 100 then receives and analyzes the output signals sent from the DUT. In this way, the communication link tester 100 can test the operation and functionality of the DUT in a very controlled environment. The communication link tester 100 can be used during the development or manufacture of the DUT, or can be used to troubleshoot problems that may occur with a finished DUT product.

[0016] The output signal sent from the DUT 110 is the data input signal to the communication link tester 100. The communication link tester 100 can also perform analysis on these data input signals in real time. In many existing test assemblies, such as assemblies including oscilloscopes, the link tester is "blind" or "offline" for most of the time when receiving the input signal due to the long processing time to analyze the input signal. For example, previous devices will collect a large number of samples, such as having tens of millions or hundreds of millions of data samples, but then stop accepting additional input data when analyzing the sampled data. If it is an error that occurs very rarely compared to the number of samples, there is a high probability that the error may have occurred when the test equipment has stopped accepting samples to analyze the samples that have been accepted. Therefore, discovering rare errors sometimes comes down to the luck of accepting data in which an error happens to have occurred. The "offline" period also reduces the accuracy of statistical measurements such as jitter, bit error rate (BER) or eye diagram tolerance, for example. In contrast, using embodiments of the present invention, the communication link tester 100 can perform analysis and sampling on the data as it is received from the DUT in real time, without stopping to accept new samples when analyzing previous samples.

[0017] Figure 1 The communication link tester 100 includes a receiver part and a transmitter part. Figure 1 , the receiver portion is generally indicated as receiver 120, which is connectable to DUT 110 via input signal conditioner 130. Input signal conditioner 130 may include one or more programmable amplifiers and may be capable of performing some input signal pre-conditioning, such as described below with reference to Figure 3 The input signal conditioner 130 may be housed in a remote head (not separately shown) that is physically attached to the DUT 110 for receiving input signals from the DUT and is electrically (or optically) and physically connected between the DUT and the receiver 120. In some embodiments, the input signal conditioner 130 may be considered to be part of the receiver 120, although in Figure 1 For clarity, it is illustrated as being separated from the receiver. In some embodiments, the input signal conditioner 130 can operate in a bypass mode in which no signal conditioning of the input signal from the DUT needs to occur within the input signal conditioner. Although generally described herein as receiving electrical signals, embodiments of the present invention may additionally or alternatively receive optical signals. In such embodiments, the input signal conditioner 130 may also include an optical receiver for receiving the optical signal and a converter for converting the received optical signal into an electrical signal for processing and / or analysis.

[0018] Receiver 120 includes an analog-to-digital converter (ADC) 122 that converts analog signals from input signal conditioner 130 or directly from the DUT into digital signals. In some embodiments, ADC 122 is a high-precision converter capable of generating high-precision or high-resolution digital output signals. In some embodiments, ADC 122 includes one or more n-bit converters that can encode analog signals into 2 n One of discrete levels. For example, if ADC 122 includes an 8-bit converter, the input signal can be encoded into one of 256 separate and discrete levels. In general, ADC 122 is oversampled or highly oversampled compared to the bit input rate of the input signal received from the DUT. The digital signal output from ADC 122 is then provided to digital processor 126 for processing, as described below. The digital signal and other related signals can be stored in memory 128 before or after being processed by processor 126. In some embodiments, digital processor 126 can process the signal both before and after the signal is stored in memory 128, and can actually store signals or other data multiple times between processing functions.

[0019] Receiver 120 can perform various functions on digital signals, such as clock and data recovery, edge detection, extraction, digital equalization, down conversion, digital signal processing, channel estimation, triggering, error checking, protocol-specific processing, bit error rate (BER) calculation and other functions, as described in detail below. Receiver 120 can be embodied in a field programmable gate array (FPGA), which enables the functions and operations of receiver 120 to be easily updated or modified. FPGA can also be controlled by embedded or external software. In other embodiments, receiver 120 can be embodied by a general or dedicated processor, which is controlled by a specific software program and runs the specific software program, although it may be more difficult to update and modify receiver 120 in those embodiments compared to FPGA embodiments. Other embodiments can operate on retargetable or reconfigurable commercial logic devices and / or custom logic devices. For example, example FPGAs that can be used as platforms on which receiver 120 is implemented include various versions of FPGAs produced by INTEL or XILINX.

[0020] Figure 1The communication link tester 100 of 100 also includes a transmitter portion 150 that is connectable to the DUT 110 via an output signal conditioner 160. The output signal conditioner 160 may be capable of performing some output signal conditioning, such as cable compensation or other conditioning, before the signal is output from the communication link tester 100. The output signal conditioner 160 may be housed in a remote head (not separately illustrated) that is physically attached to the DUT 110 for providing signals to the DUT and is electrically (or optically) and physically connected between the DUT 110 and the transmitter 150. In some embodiments, the output signal conditioner 160 may be considered to be part of the transmitter 150, although in Figure 1 10 is illustrated as being separate from the transmitter for clarity. In some embodiments, the output signal conditioner 160 can operate in a bypass mode in which signal conditioning of the output signal from the transmitter 150 need not occur before the output signal from the transmitter 150 is provided to the DUT 110. Similar to the receiver 120 above, the transmitter 150 can generate an optical output signal in addition to or in lieu of an electrical output signal. In such embodiments, the output signal conditioner 160 can also include an electrical-to-optical converter or generator to produce the optical output signal.

[0021] The transmitter 150 includes a digital processor 156 associated with a memory 158. The primary function of the digital processor 156 is to generate signals that are output from the communication link tester 100 to the DUT 110. The signals generated by the transmitter 150 may include test signals, such as various protocols and patterned signals as described in detail below. In some embodiments, the memory 158 may store the final signal before it is transmitted out of the processor 156. In other embodiments, the memory 158 includes data or programs used by the processor 156 to generate the final test signal. The test signal may be modified from a standard form to stress test the DUT 110, such as by modifying the amplitude, duration, timing or other characteristics of the signal, such as jitter and impairments, as described in detail below. The transmitter 150 may also include a filter to shape and modify the signal generated by the digital processor 156 before transmitting the modified signal to a digital to analog converter (DAC) 152. The DAC 152 converts the digital signals generated by the digital processor 158 into analog signals before passing them to the output signal conditioner 160 (if used) before sending the analog signals out of the communication link tester 100 to the DUT 110 .

[0022] The digital processor 156 may also include one or more provisions for controlling the DAC 152, such as pre-distortion, linearity testing (by introducing non-linearity into the output signal), rising and falling edge control, and voltage swing control, among other things. These provisions modify the digital signal before it is sent to the DAC 152 to help the DAC produce a properly constructed signal for output of the communication link tester 100 to the DUT 110.

[0023] The transmitter 150 may be embodied in an FPGA, which enables the functionality and operation of the transmitter 150 to be easily updated or modified. In some embodiments, a single FPGA may enable the functionality and operation of both the transmitter 150 and the receiver 120. Similar to the receiver 120, the FPGA embodying the transmitter 150 may also be controlled by embedded or external software. In other embodiments, the transmitter 150 may be embodied by a general or dedicated processor that is controlled by and runs a specific software program, although it may be more difficult to update and modify the transmitter 150 in those embodiments compared to the FPGA embodiments. In some embodiments, the receiver 120 and the transmitter 150 may be implemented on a single FPGA.

[0024] The link user interface 140 is coupled to the receiver 120 and the transmitter 150, and although not shown, may also be coupled to other components of the communication link tester 100. The user interface 140 may include a keyboard, a mouse, a trackball, a touch screen, switches, a rotary switch, buttons, a menu selector, and / or any other control that a user may employ to interact with the communication link tester 100. The user interface 140 may also include or be coupled to a graphical user interface (GUI), which may include a digital screen, a display, or any other monitor. The GUI may be used, for example, to control the operation of the communication link tester 100, display test or measurement results, time stamps, captured waveforms, packet data, and display output or other results to a user, as discussed herein. Further, the GUI may be used by an operator to control functions of the communication link tester 100, such as selecting a particular test to be run, modifying parameters, setting trigger conditions, selecting which inputs and outputs to use, and the like. In other embodiments, a user may interact with the communication link tester through a programming user interface rather than a graphical user interface. A programming user interface is an interface that does not have graphical capabilities. Computer programs such as test, setup, or calibration programs may be stored in a test application storage 142 within or accessible by the user interface 140. These applications 142 may be selected by a user using the interface 140 for operation on the communication link tester 100. In some embodiments, particular applications 142 may be available to some users and unavailable to other users. For example, a particular set of applications 142 may be made available to users who purchase additional functionality provided by the particular applications. Although the user interface 140 is depicted as being integrated within the communication link tester 100, one of ordinary skill in the art will appreciate that any of these components may be external to the communication link tester and may be coupled to the link tester in any conventional manner (e.g., by using wired and / or wireless communication media and / or mechanisms).

[0025] As in Figure 11, the communication link tester 100 may be coupled to a computer 170, which may have one or more computer applications 172 running thereon. The computer 170 may control the operation of the communication link tester 100, or may operate in conjunction with the link user interface 140 to control the functions of the tester 100. For example, the computer application 172 running on the computer 170 may be operable to cause the communication link tester 100 to run a particular protocol system analysis or other test sequence for the connected DUT 110. The communication link tester 100 may also send data or other information directly to the computer 170. Such information may include data received by the receiver 120 from the DUT 110, or may include information about the communication link tester 100 sent to the DUT, or other information. In some embodiments, the computer 170 may be used as a scheduler, i.e., causing the communication link tester 100 to automatically or periodically perform certain tests on the DUT 110 or to perform internal tests such as calibration within the link tester itself.

[0026] The communication link tester 100 may include a local output 112 and a local input 114. Each of the local output 112 and the local input 114 may include multiple data channels. The local output 112 may be used for data logging, or for receiving data generated by the communication link tester 100. The local input 114 may be used to provide data, such as test data, to the communication link tester 100. In some embodiments, the local output 112 and the local input 114 are not necessarily separate ports into the communication link tester 100, but are included in the connection between the link tester and the computer 170. Further, the communication link tester 100 may have the ability to send outputs such as output data or data received from the DUT 110 to a cloud output 116. Additionally, the communication link tester 100 may be coupled to a cloud input 118 and receive data and / or instructions from the cloud input 118. The cloud output 116 can stream data from the communication link tester 100 and store it in a cloud-based network, such as via the Internet, where the data can be available for viewing by multiple people in distributed geographical locations. For example, a user can log into the computer 170 via the Internet (not shown), cause the communication link tester 100 to run a specific program or test on the DUT 110, and then instruct the link tester 100 to store specific and desired data in the cloud via the cloud output 116. Similarly, the communication link tester 100 can receive data or instructions from the cloud input 118, where the data can be directly accessed by the link tester 100 without having to access the data through a separate computer. In some embodiments, the cloud output 116 and the cloud input 118 are housed in the same physical device. Such cloud access allows a user of the communication link tester 100 to access data used by the link tester or data generated by the link tester directly to and from a cloud data network (a cloud data network is a data network such as the Internet or other privately accessible data network) without being in the same physical location as the communication link tester 100 or having to access data from the communication link tester 100 through a computer 170. In yet another embodiment, the cloud output 116 and cloud input 118 can be used to support coordinated and aggregated testing, measurement, and analysis across multiple distributed link testers 100 that may be separated from each other by large distances. For example, the transmitter 150 of a first link tester 100 can be coupled to a long-distance fiber optic network, while the receiver 120 of a second link tester 100 can be coupled to the other end of the fiber optic network. The two link testers can also be coupled to each other through their respective cloud outputs 116 and cloud inputs 118. In this manner, the fiber optic network represents the DUT 110, which is coupled between the first and second link testers 100, and each link tester 100 is also coupled together through their cloud output 116 and cloud input 118, respectively. Figure 1 The cloud input 118 is illustrated as being directly coupled to the transmitter 150, but it may also be coupled to the receiver 120 or elsewhere in the link tester 100. Similarly, while the cloud output 116 is illustrated as being directly coupled to the receiver 120, it may also be coupled to the transmitter 150 or elsewhere in the link tester 100. In other words, any portion of the communication link tester 100 may send and receive signals directly from the cloud or a communication network such as the Internet.

[0027] In some embodiments, Figure 1 All functional blocks of the communication link tester 100 illustrated in FIG. 1 may be integrated into a single physical unit that may be stand-alone or mounted in a test bench. The communication link tester 100 includes a power supply 180 that provides power to both the receiver 120, the transmitter 150, and the Figure 1 The communication link tester 100 of the present invention is used to power all circuits of the physical unit in accordance with other components illustrated in the communication link tester 100. Additionally, the receiver 120 and the transmitter 150 are coupled to each other by a high-speed parallel bus 182, which is used to carry data, communications, instructions, control information, etc. between the receiver 120 and the transmitter 150. Although not shown separately, the parallel bus 182 may also carry one or more clock signals generated by the receiver 120 or the transmitter 150 or elsewhere in the communication link tester 100 and sent to other components within the communication link tester 100. In other embodiments, the communication link tester 100 may be physically assembled in multiple components. For example, the transmitter 150 may be housed in a first component and the receiver 120 may be housed in a physically separate component.

[0028] Although Figure 1 A single transmitter and receiver coupled to a single DUT is shown, but a communication link tester according to an embodiment of the present invention may include multiple channels. Figure 2 The communication link tester 200 illustrated in FIG. 2 may include a plurality of channels. Figure 2 The communication link tester 200 includes at least four channels, labeled as Channel 1, Channel 2, Channel 3, and Channel N. Depending on the implementation, there may be any number of channels included in the communication link tester 200. Figure 2 , each DUT is illustrated as being coupled to a particular channel, however, it is possible that any particular channel may receive a signal from any of the DUTs connected to the communication link tester 200. The channel may be within the communication link tester 200 and as shown in FIG. Figure 2210. Thus, it is possible that DUT 3 232 is coupled to channel 1 210. Additionally, for example, the transmitter of channel 1 210 may generate a signal for DUT 3 232, and the receiver of channel 1 210 may receive a signal from DUT 3 232. Further, the test channels may be synchronized and aligned, meaning that the output signals from DUTs 1 to N are synchronized and aligned in waveform timing, and possibly in channel packet data, and may be received by any or all of the receivers of any or all of the channels 1 to N. The synchronization and alignment may be performed by the input signal conditioner 130 and / or the receiver 120 ( Figure 1 ) controlled. Input signal conditioner 130 may accept single-ended or differential signals from any or all of DUTs 1 to N and may be AC ​​or DC coupled. In some embodiments, through its input signal conditioner 130, receiver 120 may accept samples exceeding 0.5-500 Gigasamples / second (GS / s) and may accept input signal bandwidths up to 100-200 GHz on all channels 1 to N simultaneously.

[0029] The synchronization of the signals from the input signal conditioner 130 may be performed by a synchronous time interleaving (STI) function that may be present within the input signal conditioner 130 or as a separate component. Figure 2 The STI allows single or multiple differential input channels from DUTs 1 to N to be grouped and synchronously interleaved for analysis by the receiver 120 of any channel within the communication link tester 200. The STI function may be programmable and / or selectable, which may be controlled by a user through the user link interface 140, the computer 170, an application 172 running on the computer 170 or elsewhere, an application 142 running on the link interface 140, or by any other control method. The communication link tester 200 may also have the ability to synchronize and align multiple input and output channels in a timely manner by using signal processing functions in the receiver 120 and the transmitter 150. Such synchronization and alignment may also involve synchronizing the ADC 122 ( Figure 1 ) and adjustments in DAC 152.

[0030] Grouping the inputs from multiple DUTs through the input signal conditioner 130 enables testing of standards that stream data over multiple stripes in separate channels, where specific striped data is sent to and / or received from any or all of the DUTs 1 through N. Coupling multiple DUTs to various channels in the communication link tester 200 also allows for testing and implementation of the overall protocol stack outlined by a specific communication or test standard.

[0031] The receiver 120 may receive input signals from the DUTs 1 to N through its input signal conditioner 130 with an input signal dynamic range of, for example, between 0 and 20 V. In some embodiments, the input signal dynamic range may be between 50 mV and 4.5 V or greater. The input signal conditioner 130 may include an attenuator and a number of programmable amplifiers to condition the signal for analysis by the receiver 120.

[0032] As mentioned above, the input signal conditioner 130 may include a CTLE executed in the analog domain, such as described in U.S. Patent Application 15 / 395,416, filed on December 30, 2016, entitled "NOISE REDUCTION IN DIGITIZING SYSTEMS" and assigned to the assignee of the present invention (which is incorporated herein by reference). The use of a CTLE allows the input signal conditioner 130 to increase bandwidth by boosting the frequency to optimize the frequency response and noise performance of the entire signal path, thereby providing a signal path bandwidth of more than 100 GHz. Analog CTLE equalization can also be used to boost the frequency to de-embed the input channel in the DUT 110. In some embodiments, the boost frequency is a function of the baud rate, so the analog CTLE has the ability to support boost frequencies over a large frequency band, which allows the communication link tester 100 to be used to test a large number of varying communication standards, such as IEEE 802.3bs, IEEE 802.3bj, OIF CEI-56G and CEI-112G, OIF CEI-11G, OIF CEI-6G, PCI-e, and other high-speed data communication standards. Including the analog CTLE function in the input signal conditioner 130 allows for frequency response shaping of the input signal to increase the signal-to-noise ratio (SNR) performance of the input signal conditioner 130 and the receiver 120. Imperfections in the frequency shaping of the input signal can be compensated in the input signal conditioner 130 by using the analog CTLE. The analog CTLE functionality of the input signal conditioner 130 may be programmable and / or selectable, which may be controlled by a user via the user link interface 140, an application 142 running on the link interface, a computer 170, an application 172 running on the computer 170 or elsewhere, or via any other control method.

[0033] Still like Figure 2 As shown in FIG. 1 , a set of optical inputs and outputs 211, 221, 231, and 241 can be coupled between the communication link tester 200 and any or all of the DUTs 1 to N. The optical inputs and outputs 211, 221, 231, and 241 allow the communication link tester 200 to communicate with the DUT using optical signals rather than electrical signals. This increases the functionality of the communication link tester 200. The inclusion of such optical inputs and outputs 211, 221, 231, and 241 further allows the communication link tester 200 to test coherent optical standards, such as QAM, at rates up to or exceeding 64 Gigabaud / second (GBd / s).

[0034] Figure 3 According to an embodiment of the present invention Figure 1Functional block diagram of the receiver component of a communications link tester. Figure 3 The receiver 300 shown in FIG. Figure 1 Receiver 300 is an example or embodiment of a digital processor 126 and may perform the functions described above with reference to digital processor 126 of receiver 120. Also as described above, receiver 300 may be embodied in an FPGA, which allows receiver 300 to be quickly upgraded and enhanced by reprogramming the FPGA itself.

[0035] The receiver accepts one or more input signals at a programmable amplifier 302, which may function as described above with reference to the input signal conditioner 130. Further, the programmable amplifier 302 may include a programmable analog CTLE function that performs equalization on the input signal before the input signal is provided to the ADC 306, or the analog CTLE block 304 may be separate from the programmable amplifier 302, as in Figure 3 304. The CTLE implemented in the analog CTLE block 304 is an analog CTLE, meaning that it performs equalization on analog signals received from one or more DUTs. The analog CTLE 304 shapes the frequency response of the input signal and helps reduce noise and enhance SNR (signal-to-noise ratio) before transmitting the equalized input signal to the ADC 306. The ADC 306 can be embodied by multiple separate ADCs that can interleave the input signal received from the pre-sampler in the input signal conditioner 130, which samples the input signal at a very high sampling rate in the analog domain and distributes the interleaved phase waveform to multiple ADCs at a lower sampling rate. After the input signal is processed by the programmable amplifier 302, the analog CTLE 304, and the ADC 306, it is provided to the receiver 300 in digital form. The ADC 306 has the ability to operate at a high sampling rate compared to the baud rate of the input data signal. As described above, the ADC 306 can be, for example, an 8, 10, or 12-bit converter that can effectively generate a digital capture of the analog input waveform. ADC 306 need not be an even number of bits, and thus may alternatively have, for example, 7, 9, 11, or 13 bits. Embodiments of the present invention are not limited to any particular resolution, and ADC 306 may include any number of bits. Figure 3 , the programmable amplifier 302 and the ADC 306 operate in the analog domain, while the remaining components within the receiver block 300 operate in the digital domain.

[0036] After the analog input signal is received and digitized by ADC 306, it is transmitted to receiver 300 for processing in the digital domain. Figure 3The various functional blocks of the receiver 300 illustrated in FIG. 3 work together to process the input signal. As described above, although illustrated as separate processing blocks, Figure 3 The various functional blocks illustrated in the figure may be functions programmed into one or more custom logic devices (such as FPGA or (multiple) other digital processors). Those skilled in the art will recognize that Figure 3 300 is a functional block diagram illustrating the functionality of the receiver 300 and does not necessarily align with physical boundaries or identify discrete components. Further, although some functional blocks are illustrated as being connected to each other, those skilled in the art will appreciate that Figure 3 The output of any functional block can be accessed by any other block. By enabling the receiver 120 to be implemented using a high speed ADC coupled to one or more FPGAs, the algorithms and functions of the receiver can be run in real time relative to the input data signal received by the communication link tester 100. This combined functionality, along with the benefits of tight integration of components within the communication link tester 100, can replace the need to use a combination of BERTs, sampling scopes, and / or real-time scopes to perform only a limited set of functions. In contrast, using methods that physically integrate the receiver 120 and transmitter 150 into a single instrument or actually utilize tightly coupled receiver and / or transmitting instruments, many more functions are available to the user to test the DUT or link channel more accurately, more efficiently, and at a lower cost than previous test assemblies.

[0037] After the digitized input signal is received at the receiver 300, it can be digitally down-converted by a digital down-converter (DDC) 310 to select a specific frequency band of interest. Including the DDC 310 in the receiver 300 allows the user of the communication link tester 100 to perform spectrum testing and analysis of RF (radio frequency) signals. In some embodiments, the DDC 310 uses a numerically controlled oscillator (NCO) to select the center frequency of interest from the input signal before extracting the data to a reduced sampling rate. The DDC 310 can accept real input data from a single ADC, or if the RF local oscillator (LO) stage, mixer stage, and filter stage are used for analog down-conversion in the input signal conditioner 130 and then the resulting intermediate frequency (IF) I and Q waveform components are sampled using separate ADCs, then complex in-phase / quadrature (I / Q) data is accepted from two ADCs. The DDC 310 can be used to select an accurate frequency window of interest using a reduced sampling rate, allowing a longer time span to be acquired for a fixed memory size and making it easier to implement downstream measurement and analysis functions.

[0038] Similarly, the decimator 312 may include a decimation filter to resample the digital input signal to a lower sampling rate signal for use by the link tester 100. The specific frequencies, output sampling rates, and filter coefficients of the DDC 310 and decimator 312 may be controlled by a user through the link user interface 140, the application 142, or by the external computer 170 or an application 172 running on the computer, as described above.

[0039] The output from DDC 310 and decimator 312 may be sent to acquisition memory 314, which stores the input signal after down conversion or decimation. Additionally, the output from DDC 310 and decimator 312 may be sent to livestream data output 316, which may be Figure 1 314, 324, and / or 374, or to a real-time streaming data output 316. Further, the real-time streaming data output 316 may also be a local output 112 of the embodiment of the ... Figure 1 In some embodiments, the real-time streaming data output 316 may be a local port 112 on the link tester 100 and have a cloud output 116 component that can be selected by the user so that data streamed from the physical local port 112 is additionally or alternatively streamed to the cloud through the cloud storage port 116.

[0040] The data generated by the ADC 306 and provided to the receiver 300 may also be subjected to additional CTLE equalization processing performed by the digital CTLE processor 308. The digital CTLE processor 308 is different from the CTLE function or processing performed in the analog CTLE block 304 described above. In general, the CTLE processing performed in the analog CTLE block 304 is an analog processing, which is performed in the analog domain, while the CTLE equalization processing performed by the digital CTLE processor 308 is performed in the digital domain. That is, the digital CTLE processor 308 provides equalization to the input signal after the input signal has been converted to a digital signal by the ADC 306. The digital CTLE processor 308 performs equalization of the digital input signal as described above, and also with reference to the incorporated '416 application. In general, the digital CTLE processor 308 uses various techniques to modify the digital input signal to reduce noise and improve the SNR of the input signal, as well as to compensate for the input analog signal path. The digital CTLE processor 308 may be used in conjunction with the analog CTLE function 304 , which may be within the input signal conditioner 130 .

[0041] The channel estimation block 320 receives the digital input signal from the ADC 306 and is used to estimate the noise, frequency response, or other channel conditions of the communication channel between the DUT and the receiver 300. As described below, once the noise and other channel conditions are known, they can be sent to the transmitter 150 so that they can be taken into account when the transmitter sends information to the DUT on the communication channel. The channel estimation block 320 can be used to initially characterize the communication channel and cause the transmitter 150 and / or DUT 110 to take the channel characterization into account during initial transmitter setup, or the channel estimation block can be used continuously so that the communication channel is constantly monitored and the results are sent to the transmitter so that the transmitter can change its transmission parameters in response to changing channel conditions or be used to change parameters within the DUT. The channel estimation characteristics determined by the channel estimation block 320 can also be used to increase the efficacy of equalization, generation of stress impairments, and clock and data recovery, as described below. The channel estimation block 320 can cooperate with the transmitter 150 to transmit specific data or signals (such as a sine wave) at various frequencies and measure the effect that the communication channel coupled to or within the DUT has on the signal transmitted thereto. As with reference to the DDC 310 and the decimator 312 above, the output of the channel estimation block 320 can be sent to the acquisition memory 324 or other memory within the receiver 300 so that the instantaneous channel information can be stored and accessed later.

[0042] After the input signal has been modified by the digital CTLE processor 308, the timing and clock recovery processor 330 receives the input signal. As described in detail below, the clock recovery processor 330 performs a clock data recovery (CDR) process to generate a clock signal from the received input signal. Generally speaking, the clock recovery processor 330 uses one or more phase detectors on the received input signal, which operate at a clock rate that is oversampled relative to the input waveform to generate a clock signal that is a very accurate estimate of the clock signal used by the DUT to generate the input data waveform. Since the ADC 306 oversamples the input waveform relative to the baud rate of the input waveform, the timing and clock recovery processor 330 can use an interpolated clock and data recovery method. The clock recovery processor 330 can initially recover or generate a data waveform clock based on the input symbol period, and then resample the input signal from the sampling rate of the ADC 306 to the recovered baud rate clock. The clock recovery processor 330 determines the baud rate based on the input signal analysis. In general, the clock recovery processor 330 internally reduces the sample rate and determines the actual baud rate by operating in conjunction with the decision feedback equalizer (DFE) 334 discussed below to determine which phase and symbol clock rate relative to the input samples provides the best margin relative to the eye diagram. However, not all embodiments require DFE. The clock recovery processor evaluates multiple possible symbol clock rates and determines the optimal symbol clock rate for tracking the input waveform. The loop filter in the clock recovery processor 330 can have adjustability in bandwidth and other filter characteristics to track clock changes and support changing standards and test requirements. The clock recovery processor 330 may include a phase detector that uses, for example, known techniques such as Bang Bang, Mueller-Muller, Gardner, and minimum mean square error.

[0043] The equalizer 332 may perform further equalization on the recovered clock signal in conjunction with the adaptation engine 340 described further below. The equalizer 332 may be a feed-forward equalizer that may be adapted to automatically help the receiver 300 adapt to changing conditions (such as temperature) that may affect the accuracy of the receiver. A user of the link tester 100 may be able to modify the receiver 300 through the user interface 140 ( Figure 1) to control or set parameters for the operation of the equalizer 332. The equalizer generally performs equalization at the baud rate (i.e., the rate at which the sampled data groups are taken), although fractionally spaced equalization may also be implemented using the described architecture. This equalization may be different from the equalization performed by the CTLE 308 described above, which instead operates at a certain multiple of the rate of the input samples from the ADC 306 or the symbol baud rate, for example, for an equalization filter with fractional UI resolution. The filter may also be used to de-embed cables, package models, or other interconnects between the instrument and the DUT. Additionally, filters may be used to embed models of interconnects and packages that are not in the physical measurement.

[0044] The output from the equalizer 332 and the clock recovery processor 330 can be used in conjunction with the decision feedback equalizer 334 to generate a visual data output referred to as an eye diagram 336, which can take the form of a histogram. The eye diagram output itself can be displayed on the user interface 140 ( Figure 1 ), stored in memory 320 for later analysis, stored elsewhere on the link tester 100, stored in the cloud via real-time streaming data output 316, or stored in an attached computer 170. In general, an eye diagram is a graphical illustration of an input waveform used in test and measurement applications for many high-speed data communication standards to evaluate link performance. One problem with previous test equipment for testing input signals is that previous test equipment is unable to process the input signal and generate the eye diagram in real time due to the large amount of computer processing taken to generate the eye diagram from the received signal. The eye diagram analysis function may include real-time jitter and noise analysis and measurement capabilities or more complex link performance metrics such as TDECQ (transmitter dispersion eye closure) and COM. In contrast, embodiments of the present invention are able to operate continuously at such a high sampling rate relative to the input waveform baud rate that the eye diagram 336 is generated in real time using the clock recovery processor 330, the equalizer 332, and the decision feedback equalizer 334. Further, these functional blocks of the clock recovery processor 330, the equalizer 332, and the decision feedback equalizer 334 may be used to accurately perform clock data recovery, as described in detail below.

[0045] Adaptation engine 340 can work independently or through link user interface 140 ( Figure 1 ) and work with user input. The adaptation engine 340 can accept specific filter coefficients, or can automatically calculate or select them using pre-stored values. The adaptation engine 340 can also communicate with the transmitter 150 ( Figure 1). Thus, when the transmitter 150 sends a known signal to the DUT, the adaptation engine 340 can use the known values ​​to modify the filter coefficients or other coefficients within the adaptation engine to maximize the integrity of the received signal. In other modes, the adaptation engine 340 can be used to emulate the behavior of a specific known receiver. For example, if a user of the communication link tester 100 wishes to view the signal received from the DUT 110 ( Figure 1 ) input signals (as they will be presented to three different known receivers), the adaptation engine can pre-store specific coefficients to emulate the known receivers. The user can then select various receivers to simulate and analyze how the characteristics of the recovered waveform will change as if the input signal were being received by one of the known receivers.

[0046] The adaptation engine 340 can operate in various modes. For example, a user can select a fixed mode in which a specific receiver is simulated as described above. In another mode, the adaptation engine 340 can operate in an automatic mode in which specific coefficients and settings are automatically changed and the effects of such changes are tested internally to determine the optimal or best set of settings for a particular purpose.

[0047] One of the main functions of a receiver in a test and measurement system such as an embodiment of the present invention is the ability to capture input data only after a specific event or situation has occurred. This concept is called triggering and works as described below. In general, and as described above, the amount of information sent by the DUT to the receiver 120 may be large. Sometimes only during special conditions, such as when the input signal exceeds a threshold value or when two signals are received too quickly in succession, that is, when there is a timing error, is the test information searched. The trigger system allows the receiver 300 to capture data only when the trigger condition is met, and allows the data that does not meet the trigger to be discarded or overwritten. In these embodiments, the receiver stores the input data only when the trigger condition is met. Triggers can be related to the input data itself, such as those described above, they can be related to timing (such as capturing the first data after a reset condition), can be based on anomalies detected in the input waveform or based on the detection of a specific pattern or pattern set in the protocol encoded in the input waveform. Two characteristics that define triggers include trigger flexibility, how the trigger can be defined, and trigger dead time, which describes how long the receiver must perform between acquisitions. In other words, in some conventional test equipment (such as oscilloscopes), there are time periods that are "invisible" to the receiver because its data cannot be simultaneously evaluated against the trigger and stored when the trigger conditions are met. Embodiments of the present invention solve both of these problems. First, the trigger is extremely flexible and allows precise control and combination, as described below. Second, embodiments of the present invention analyze the input data in real time, and decisions can be made based on the input data itself as well as the trigger conditions. Unlike previous receivers, there is no dead time between acquisitions because the receiver 300 operates continuously at an extremely high sampling rate and is able to store data in real time while it continues to analyze and process continuously received data. Therefore, using embodiments of the present invention, there are no missed triggers and there is no "acquisition dead time."

[0048] Figure 3 Several different types of triggers are shown, which may be pre-set into the communication link tester 100, or may be triggered by a user through, for example, the link interface 140 or an attached computer 170 ( Figure 1) is set. A pseudo-random binary sequence (PRBS) is a generated sequence of binary values ​​that exhibits statistical behavior similar to a truly random sequence. They are widely used in telecommunications and other high-speed data communication industries, and are particularly used to test communication standards. An embodiment of the present invention includes a pseudo-random binary sequence (PRBS) pattern generator 352, which allows a user to select or generate various PRBS patterns used in bit error rate (BER) analysis. In operation, a user selects a PRBS pattern, and a receiver receives input data. The PRBS pattern generator 352 is synchronized with the recovered input waveform to align its phase. Once aligned in phase, the recovered input data can be checked against the PRBS pattern using an error checker 360 processor to detect bit errors. Once a bit error is detected, the error checker 360 processor can cause a trigger to occur, and then the receiver 300 will automatically store the input data within a predefined time before and after the bit error occurs.

[0049] The error checker 360 processor can also accept other waveforms to compare the input waveforms in contrast, for error checking, such as the pattern generator 354 or custom waveform pattern memory 356 for common pattern types. The custom waveform pattern memory 356 allows the user to specify any waveform to use in error checking or for triggering. The waveform used in triggering can be digital or analog. Generally speaking, the pattern generators 352, 254 and 356 are synchronized with the input data and compared. The trigger is satisfied when a match occurs or in some cases when a match does not occur.

[0050] The pattern generators 352, 354, 356 may be selected by a multiplexer 358 which selects one of the pattern generators to operate. The receiver 300 performs error checking by an error checker 360 and bit error rate (BER) calculations in a processor 362. These are explained in further detail below.

[0051] In addition to the error checking and BER calculation and related triggering capabilities by blocks 360, 362, other general triggers are also possible, as illustrated in block 364. For example, an external trigger can be set to cause the receiver 300 to store input data, or perform additional functions when an external trigger is met. The trigger in block 364 can also include a protocol-based trigger (based on the protocol recovered in block 370), a forced trigger, and a trigger on the sampled input data similar to the capabilities in a traditional oscilloscope. Further, the trigger block 364 can be set to trigger by error, in which case the receiver 300 stores the input data after the error occurs. When the data input to the receiver 300 does not match the input data expected from the pattern generator 352, 254, 356-this is a sign that an error has occurred-an error may occur. In some embodiments, the input data is received at a circular memory buffer, and when an error occurs, some input data from before the error occurs is also stored to provide an increased tool for analysis. More details about error triggering are provided below.

[0052] When the input signal conforms to a specific protocol, the protocol-specific processing block 370 allows the receiver 300 to perform a specific test. The protocol can be automatically identified by the receiver 300. For example, the receiver 300 can continuously compare the input from the ADC 306 to trigger based on the pattern, as described above. Then, when the trigger condition is met, that is, when the receiver 300 is receiving data that matches the predefined data, the receiver 300 changes the state to reflect that a specific protocol is being received. Then, the protocol-specific processing block 370 can perform a specific function on the data based on the protocol being received. Examples of specific protocols include, for example, various forms of Ethernet, peripheral component interconnect (PCI), peripheral component interconnect fast (PCI-e), high-definition multimedia interface (HDMI), serial front panel data port (FPDP) and coherent optical standards. In some embodiments, the communication link tester 100 can be used, for example, to evaluate or test network protocols, bus protocols, wireless protocols or hardware for Internet protocols and other protocols or hardware.

[0053] As with the other components, the protocol-specific processing block 370 may output data to the acquisition memory 374 and / or the real-time streaming data output 316. For example, the protocol-specific processing block 370 may pass incoming data to the acquisition memory 374 and / or the real-time streaming data output 316 only when the receiver 300 is receiving Ethernet-based frames (or a subset of frame protocols), and ignore idle periods in the incoming waveform.

[0054] Although in Figure 3In the figure, three separate acquisition memories 314, 324 and 374 are shown, but it is understood by those skilled in the art that the memory can be embodied by a single memory, separate memories or any combination thereof. Further, the memory stored in the acquisition memories 314, 324 and 374 can be capable of being stored in Figure 3 Further, while not specifically illustrated in all cases for spatial limitations, any component within the receiver 300 that stores data to any of the acquisition memories 314, 324, and 374 may also stream data out of the real-time streaming data output 316. Figure 3 300. The memory and controller 344 may be used in place of or in conjunction with the acquisition memory. For example, specific settings or coefficients may be stored in the memory and controller 344. These memories need not necessarily be classified as "acquisition" memories, and are therefore illustrated separately. Those skilled in the art will understand how to use various memories associated with specific components or how to use various memories for the receiver 300 in general.

[0055] Figure 4 According to an embodiment of the present invention Figure 1 Functional block diagram of the transmitter component of a communications link tester. Figure 4 The transmitter 400 shown in FIG. 4 may be Figure 1 150 and can perform the functions described above with reference to the digital processor 156 of the transmitter 150. Also as described above, the transmitter 400 can be embodied in one or more FPGAs, which allows the transmitter 400 to be quickly upgraded and enhanced by reprogramming the FPGA itself. The architecture enables the generation of data waveforms and added impairment stress tests as defined by each specific standard via digital signal processing (DSP) techniques in addition to various analog methods. Further, since the transmitter includes a high-speed DAC, many different types of waveforms can be generated similar to the AWG. Embodiments of the present invention can also replace the need to use a BERT as a signal source, as is true in existing test equipment settings for some test and measurement applications. Further, tightly coupling the DSP function to the high-speed DAC enables the communication link tester 100 to support standards from low baud rate to high baud rate states in the technology standard without having to explicitly change the DAC sampling rate. Alternatively, DSP techniques can be used in the transmitter 400 to resample the lower baud rate data waveform to a higher sampling rate DAC.

[0056] The waveform triggering, alignment and synchronization block 410 prepares the transmitter 400 to generate waveforms that can be modified and ultimately sent to the DAC 440 ( Figure 5 ) for sending to DUT 110 ( Figure 1 ) waveform. The primary function of the waveform triggering, alignment and synchronization block 410 is to calibrate and align one or more channels so that they are tightly aligned in time for generating a final output waveform from the transmitter 400. The waveform triggering, alignment and synchronization block 410 also supports external triggering for timing synchronization and mode control. The waveform triggering, alignment and synchronization block 410 can receive a trigger signal from the receiver 300, which causes the transmitter to initiate waveform generation in response to a function in the receiver 300. Note also that, as described above with reference to the receiver 300, the trigger signal can be an external trigger, i.e., a trigger sent from an external source to the communication link tester 100. The waveform triggering, alignment and synchronization block 410 can also receive synchronization signals to allow the transmitter 400 to tightly align its output signal to any expected input for the receiver 300, and also allow the output signal of the transmitter 400 to be tightly aligned across multiple output channels, as described above with reference to Figure 2 Just as described.

[0057] A set of generators 420, 422, 424, 426, and 428 are responsible for generating the specific desired waveforms and impairments to be output by the transmitter 400. The digital marker waveform generator 420 is used to generate one or more digital marker waveforms that are related to and synchronized with the output analog signal. For example, a trigger can be used to start the generation of a long, complex pattern for the output analog signal. A digital marker can be used at the end of a waveform to indicate to the DUT or elsewhere within the communication link tester 100 to synchronize the processing of the waveform, or to indicate that a specific process should be triggered at a specific time. Figure 5 , note that the output(s) from the digital marker waveform generator 420 becomes one of the final outputs of the transmitter 400. The digital marker output(s) from the digital marker waveform generator 420 can also be used to mark specific portions of interest of the output signal. Using this functionality provides a channel separate from the final analog signal to describe portions of the analog signal that may be of interest to an operator, or can allow specific portions of the output signal to be labeled.

[0058] The amplitude noise impairment waveform generator 422 generates specific impairments that can be added to an existing waveform or can generate an impaired waveform entirely. The waveform impairments generated by the amplitude noise impairment waveform generator 422 are particularly useful in stress testing of the DUT 110, for example, such as providing a signal to the DUT that is not perfectly formed to simulate real-world usage conditions for the DUT 110. In this way, the transmitter 400 may generate an imperfect waveform to test how well the DUT 110 performs when the input to the DUT 110 is not perfectly formed. In some embodiments, the amplitude noise waveform generator 422 functions to add amplitude noise to the output waveform, which is particularly helpful for stress testing devices while they are being developed or tested. Another advantage of separately generating noise impairments for waveforms is that compared to only including the noise addition functionality in the Figure 5 The noise can have a different scale and resolution in the dynamic range compared to the DAC 440 discussed in . In other words, the amplitude noise impairment waveform generator 422 can generate a small amount of noise compared to the output signal or generate a large amount of noise, and the generation of the noise is completely independent of the other parts of the output waveform generation.

[0059] The waveform pattern generator 424 generates a waveform that matches a specific waveform pattern that is expected to be output from the transmitter 400. In practice, the user can select the waveform pattern through the link user interface 140 ( Figure 1 ) selects any desired waveform or waveform pattern, which is generated in the waveform pattern generator 424. It is particularly noted that in some embodiments, the waveform pattern generator 424 can be oversampled relative to the output baud rate of the waveform. Such oversampling allows for increased time resolution for adding timing-related impairments such as jitter to the output waveform, giving greater control over the impairment of the output waveform for stress testing. Inputs to the waveform pattern generator 424 can include input waveform patterns from real-time streaming data received from the receiver 300 or external to the communication link tester 100, data output alignment controls from the waveform triggering, alignment and synchronization block 410, and clock and output waveform timing controls from the clock generator / PLL 432.

[0060] A digital up-converter and interpolation function 430 may be connected after the waveform pattern generator 424. The digital up-converter and interpolation function 430 interpolates the waveform generated by the waveform pattern generator 424 to a higher output sampling rate used downstream by the DAC 440, and may also optionally modulate the input waveform received from the waveform pattern generator 424 to shift the waveform from a lower output frequency range to a higher output frequency range. When digital up-conversion is used, the waveform pattern generator may generate a real or complex baseband waveform type, which is then modulated to a higher frequency in the digital up-converter and interpolation function 430.

[0061] The clock generator / PLL 432 may generate a basic clock using a phase locked loop (PLL) or other oscillator. The clock generator / PLL 432 may synthesize a digital representation of a clock waveform to emulate a conventional analog PLL. The clock generator / PLL 432 may also receive a clock signal from the communication link tester 100 (eg, via the local input 114). Figure 1 ) or receive an external reference clock from outside the tester itself. Clock generator / PLL 432 can be configured to support the generation of stressed (including clock impairments simulated by transmitter 400) or unstressed (without clock impairments simulated by transmitter 400) clock outputs that can be synchronized to the baud rate / symbol period of the generated waveform pattern, which can be used to synchronize with other instruments. The clock output generated by clock generator / PLL 432 can be at the output baud rate or divided down at a given ratio.

[0062] The jitter impairment generator 426 is coupled to the clock generator / PLL 432 to cause the clock generator to generate a waveform that varies in a controllable manner from its original clock. As with the impairments generated by the amplitude noise impairment waveform generator 422, providing the DUT 110 with a clock rate that is subject to moderate or excessive amounts of jitter and other timing-related impairments can be useful for testing how well the DUT 110 reacts to such imperfect inputs.

[0063] Jitter insertion driven by the jitter impairment generator 426 is one aspect of stress testing used with communication standards. The types of jitter range from low frequency to high frequency jitter in the form of periodic or non-periodic jitter. In addition, random jitter, bounded uncorrelated jitter, and spread spectrum clock are all examples of types of clock edge modulation that the transmitter discussed herein can be configured to support.

[0064] Some serial or other high-speed data standards (such as PCI-e) use spread spectrum clocks. Spread spectrum generator 428 is used to modulate the phase of clock generator 432 described in detail below internally. Spread spectrum generator 428 shifts the phase of the clock by a controllable amount. One benefit of clock offset is a reduction in electromagnetic interference (EMI) because it allows the spectrum energy to be spread over more frequencies to reduce the magnitude of EMI for the entire system.

[0065] The jitter and spread spectrum clocks from the jitter reduction generator 426 and the spread spectrum generator 428 can be inserted into embodiments of the present invention by several possible methods. For example, the jitter insertion from the jitter reduction generator 426 can be performed in conjunction with the resampling process described above. This can be accomplished by using a jitter waveform to modulate the phase of each symbol transition in time. In another example, the jitter reduction generator can pass the signal through a continuously variable fractional delay filter. In this case, the resampled signal is delayed in time by different amounts, thereby producing the effect of jitter. In other embodiments, jitter can be inserted by moving the DAC 440 ( Figure 5 ) in the DAC sampling clock. The analog PI can rotate throughout the entire DAC sampling period range without rollover glitch. The jitter waveform will be used to modulate the phase of the analog PI in the DAC 440. Further, the jitter impairment generator 426 can also insert low frequency jitter into the waveform by adding phase modulation to the reference clock used to generate the sampling clock in the DAC 440.

[0066] The clock generator / PLL 432 uses the clock impairments from the jitter impairment generator 426 and the spread spectrum generator 428 as control inputs to precisely control the edges of the clock.

[0067] After the waveform has been generated by the waveform pattern generator 424 using the clock generated by the clock generator / PLL 432, the transmitter 400 may further modify the waveform depending on various factors. For example, the feedforward equalizer 434 may provide pre-emphasis equalization to the waveform based on channel conditions or operating conditions of the transmitter 400 or even the receiver 300. The feedforward equalizer 434 may receive a dynamic equalization control signal from the receiver 300 or from an external source. In some embodiments, equalization need not be performed by the feedforward equalizer 434.

[0068] Further impairments can be inserted into the waveform by impairment and channel simulation block 436, which can be used to generate inter-symbol interference (ISI) and modify the waveform to match a specific selected communication channel. For example, if a specific reference channel is subject to high frequency roll-off, it is possible that the ISI and channel simulation block 436 can simulate this by performing the same amount of roll-off. In this way, the transmitter 400 can simulate a specific type of test channel without requiring the waveform to be actually sent on the impaired channel. Similarly, the channel nonlinear simulation block 438 can modify the waveform by the nonlinear effects experienced in some specific types of components and channels. Including simulation blocks 436 and 438 allows the user of the communication link tester to replace the necessity of using a fixed board to simulate a specific channel impairment by allowing the use of digital signal processing to accurately and controllably simulate specific channel impairments.

[0069] Figure 4 The functions of the specific blocks illustrated in the figure are performed in the digital domain using DSP technology. Further, as described above, Figure 4 The blocks shown in the figure can be fully implemented in an FPGA. Figure 4 A memory and controller 444 are included. Those skilled in the art will recognize that many parameters, controls, example waveforms, modes, etc. can be stored in the memory and controller 444 for use by the Figure 4 Any components shown in the figure are used. Additionally, Figure 4 Each individual block function illustrated in may include its own separate memory for its own purposes.

[0070] Figure 5 The transmitter 150 ( Figure 1 ) embodiment, where all functions after DAC 440 are performed in the analog domain. It should be noted that in different embodiments, any functions within the analog transmitter portion 402 may be implemented in the digital domain, in which case they will appear in the Figure 4 The embodiments of the present invention provide great flexibility in this regard.

[0071] DAC 440 receives the signal from transmitter 400 ( Figure 4 ) and converts it into an analog waveform signal. As described above, DAC 440 can be oversampled compared to the output waveform. According to an embodiment of the present invention, oversampling provides overhead for clock jitter, spread spectrum control and other features. DAC 440 can have a resolution of 8 bits or higher.

[0072] The analog transmitter portion 402 of the transmitter 400 can then be used to send the analog waveform signal out of the transmitter 150 ( Figure 1 ) before performing additional modifications to the analog waveform signal. In some aspects, Figure 5 The analog transmitter portion 402 shown in FIG. 4 may be Figure 1 Implementation of the output signal conditioner 160.

[0073] First, the variable gain / attenuation transmitter amplifier 450 sets the output gain for the waveform that is ultimately output from the transmitter portion of the communication link tester 100. By using the variable gain / attenuation transmitter amplifier 450, the user can increase or decrease the strength or amplitude of the output signal.

[0074] Next, the signal combiner 452 may combine Figure 4 The amplitude noise reduction waveform generator 422 generates a selectable amount of impairment. In this way, the selectable level of impairment generated by the amplitude noise reduction waveform generator 422 can be added to the output waveform. Although the amplitude noise reduction waveform generator 422 is Figure 4 400, but the noise and other impairments may also be generated using analog circuits and will then be represented in the analog transmitter portion 402 of the transmitter 400. In the analog case, the controllable amplifier ( Figure 5 ) may be provided as an input to the signal combiner 452 to controllably mix in how much impairment is desired.

[0075] The impairment simulator 454 can add controllable amounts of differential skew and common-mode impairments to the output waveform. Adding differential skew allows the user to add additional delay on the output path with respect to any of the differential output signals. Such delays can be added by relaying, forcing the output signal for a particular differential output to pass through a longer or shorter trace length path. The common-mode impairment portion of the impairment simulator 454 generates noise for the common mode of the differential signal. For example, the common-mode voltage can be varied by this portion of the impairment simulator to test how well the receiver reacts to differential signals that do not sum exactly to 0 volts or how well the receiver rejects common-mode noise from the input differential signal.

[0076] The crosstalk simulation block 456 can be sent to the DUT 110 ( Figure 1 ) before adding the synthesized crosstalk to the output waveform. This block 456 simulates the effect of generating adjacent or other channels in addition to the output waveform. Figure 2, recall that embodiments of the present invention can work with multiple channels, which is common in electrical devices. The crosstalk simulation block 456 allows such crosstalk to be synthesized or simulated when only a single channel is actually generated. Generally speaking, the crosstalk simulation block 456 mixes a small portion of the final waveform from an adjacent channel into the main output waveform. The amount of amplitude from the adjacent channel can be controlled in the crosstalk simulation block 456. Sometimes adjacent channels are referred to as interfering channels. The crosstalk simulation block 456 mixes a certain amount of interfering channels into the final waveform. The final result is that the main output waveform from the transmitter 400 contains a small percentage of the interfering channel crosstalk. This can be used in a test mode to determine how much crosstalk a DUT coupled to the transmitter 400 can accept before an error occurs. Embodiments of the present invention are not limited to a single interfering channel for crosstalk. On the contrary, many channels can be mixed, each channel being in a controllable amount. The output of the crosstalk simulation block 456 is the main output waveform generated by the transmitter 400.

[0077] The output clock synthesizer 460 accepts the output from the clock generator / PLL 432 as input to generate the final clock signal to be output by the transmitter 400. In some embodiments, the clock output from the transmitter 400 is a DSP synthesized clock. The output clock synthesizer 460 accepts a stream of counts, values, and other data from the clock generator / PLL 432 and creates a physical clock output signal at a specified rate. The output clock synthesizer 460 can be formed by one or more DACs operating at the output rate of the output waveform. The DAC within the output clock synthesizer 460 does not need to have the same accuracy as the DAC 440, and can instead be a one-bit or two-bit DAC.

[0078] Reference Figure 1 By including the receiver 120 and the transmitter 150 in the same unit, and by including a high-speed parallel data bus 182 between the receiver and the transmitter, the tight integration of the components within the communication link tester 100 enables the link tester 100 to perform various operations in a more efficient and much more accurate manner than the previous different test assembly systems described above. The high-speed parallel data bus 182 provides excellent and high-speed communication between the receiver 120 and the transmitter 150. The link user interface 140 and the test application 142 provide a complete single system for controlled operation of the communication link tester 100, rather than ad hoc software assembled to control existing systems. All components within the communication link tester 100 are controllable and precisely specified so that their capabilities precisely match the needs of the combined unit. Because the components of the communication link tester 100 share a common power supply 180, power usage is minimized. Additionally, the shared power supply means that if the power supply deviates from the optimal output, all components of the communication link tester 100 are equally affected.

[0079] In other embodiments, the receiver 120 and the transmitter 150 can be housed in separate physical units, but are tightly coupled and communicate through a high-speed parallel data bus 182 between the receiver and the transmitter or through other communication components (such as other electrical, optical or wireless connections). Further, many receivers 120 and many transmitters 150 can be coupled to each other through multiple high-speed parallel buses 182 or other communication components. This coupling can occur across multiple physical components. The number of receivers and the number of transmitters do not need to be the same for each system. Although described above as a parallel bus 182, the communication path 182 can actually be a serial bus, an optical connection, a wireless connection or any other type of communication path.

[0080] Another benefit of the integrated communication link tester 100 is that it can perform functions that are not possible in existing test assemblies. Once such functions involve bit error testing, they utilize high-speed receivers that can effectively capture input signals and process the input signals in real time, with high-speed transmitters that can purposefully generate stressed impairments and other conditions to trigger bit errors.

[0081] The receiver 120 in the communication link tester 100 can be configured to trigger on a given pattern or error criteria. For example, the receiver 120 can be configured to compare the input stream accepted from the DUT 110 with the output stream sent to the DUT by the transmitter 150. If any of the bits received by the receiver 120 from the DUT 110 do not match those sent by the transmitter 150, a bit error trigger is generated, which causes the receiver to immediately store the data. After receiving the bit error trigger, the receiver 150 can combine, aggregate, and store patterns and events across multiple input channels. In some embodiments, reference is made to Figure 3, after receiving the bit error trigger, the input data from the DUT 110 may be stored in any one of the acquisition memories 314, 324, 374 and / or 344, or may be sent to the real-time streaming data output 316. The example waveform may be stored from the output of the ADC 306, which is prior to clock data recovery performed by the clock recovery processor 330. Alternatively or additionally, the input data may be stored as waveform symbols after being processed by the clock recovery processor 330, which may also be stored in any one of the acquisition memories 314, 324, 374 and / or 344, or may be sent to the real-time streaming data output 316. The eye diagram 336 may also be stored and linked to the input waveform. Additionally, the transmitter 150 may store the exact output waveform signal that caused the bit error event to occur. Further, the transmitter may store the conditions applied to the output waveform signal when a bit error occurs. For example, if when the output waveform signal is generated by the crosstalk emulator 456 ( Figure 5 ) applies a crosstalk interference exceeding a threshold amount, the settings that caused the crosstalk interference can be stored together with the input waveform and data described above. Additionally, the communication link tester 100 can store the state of any or all adaptations of any or all component parts of the receiver 120 and / or the transmitter 150. For example, referring to Figure 3 The states of the clock recovery processor 330, the equalizer 332, the adaptation engine 340, the DFE 334, the protocol specific processor 370, any of the trigger pattern generators 352, 354, 356, and any of the triggers 364 may be combined with Figure 4 4, the transmitter 400 is shown in the figure, and any state data associated with it is stored together, such as data from the following: waveform triggering, alignment and synchronization block 410, any of the impairment generators 422, 426, 428, the waveform pattern generator 424, the digital marker waveform generator 420, the clock generator / PLL 432, the equalizer settings from the feedforward equalizer 434, and the simulation settings from the simulators 436 and 438. In short, any setting or waveform data from anywhere in the communication link tester 100 can be captured at a certain time before the time when the bit error occurs and at a certain time after that to help the user understand how and why the bit error occurs. The captured data can be output to the user in real time, stored in any of the acquisition memories 314, 324, 374 and / or 344, or can be sent to the real-time streaming data output 316.

[0082] Further, all settings and waveforms can be time-aligned into a comprehensive graph or graph collection or other visual output, so that the user can visually identify those conditions that cause bit errors and their results. In other embodiments, the test or debug program can be an example of an application 142, 172 that works on the user link interface 140 or the external computer 170, respectively. These test and debug programs can automatically perform analysis on the data stored around the bit error event to try to determine the cause of the bit error. Such a program can include threshold values ​​and other combinations of threshold levels for specific types of stored data. For example, the application 142, 172 can be programmed or learned to identify the specific sensitivity of the DUT to a specific type of clock jitter or added impairment. Then, after a bit error, the user can run the analysis program 142, 172 to help identify the source of the specific error that occurred. In other embodiments, the test or debug program or data provided to or sent from the communication link tester 100 can be transmitted through the cloud input 118 and the cloud output 116, thereby remotely accessing the communication link tester 100. Further, the cloud output 116 and the cloud input 118 may be used to synchronize multiple coupled communication link testers 100, or may be used to send and receive data between one or more communication link testers.

[0083] In addition to bit error testing, Figure 2 The receiver 120 may also be configured to be triggered by specific data generated by the ADC 122. In such an embodiment, the pattern is stored and the output of the ADC 122 is compared to the pattern. When the output from the ADC matches the trigger pattern, all waveforms and other control data as described above may be stored for later analysis. In some embodiments, a trigger may be set for a specific situation and for a specific data protocol. The trigger may be set in or in conjunction with the protocol-specific processing block 370. In operation, when data is received by the receiver 300 ( Figure 3 ) is received and the data is analyzed. Protocol-specific processing block 370 can be set to generate a trigger when specific data is received by the receiver and the input data matches the specific data protocol of interest. When two events occur simultaneously, that is, when protocol-specific processing block 370 identifies the receipt of data matching a specific protocol and when the input data received by receiver 300 matches the desired pattern, the protocol-specific processing block or other components in receiver 300 can generate a trigger. In such an embodiment, receiver 120 effectively gates the link protocol state machine transition and the transition can be used as a trigger event. Generating a trigger then causes any or all of the input and / or output data described above with reference to the bit error to be stored for analysis immediately or later.

[0084] The ease of assembling a measurement setup is facilitated by an integrated solution combining the receiver 120 and the transmitter 150 in the same device, and any need for debugging can be made simpler and faster. Less time can therefore be spent on functional testing and more time can be spent on specialized tests (such as those that depend on and are related to a specific communication standard). Further examples of benefits associated with the architecture outlined above are the ability to modify firmware for customization and the reduction in latency, which is not possible with software-based solutions assembled for testing combining different types of instruments.

[0085] Given that both transmitter and receiver are fully integrated, the integrated solution may also enable measurements to be easily performed to directly characterize the communication channel or loopback testing.

[0086] The integrated solution also opens the door to other types of testing applications, such as intentionally adding errors to any data stream recovered in the receiver 120 and sending the resulting waveform to the transmitter 150. It will be appreciated that the above benefits are merely illustrative of the benefits that the system may provide, and that one of ordinary skill in the art utilizing the disclosed integrated solution or aspects thereof will readily recognize additional benefits.

[0087] A further benefit of the integrated communication link tester 100 is that it can perform loopback testing with precision never before possible. Loopback testing is a method for testing the viability of a communication link. The integrated communication link tester 100 enables real-time testing with low latency because data can be received by the receiver 120 just as it is placed on the channel by the transmitter 150. Further, the receiver 120 can know exactly what data the transmitter 150 is sending through the high-speed data connection 182.

[0088] Another variation of loopback testing may be supported in the integrated communication link tester 100, where the receiver captures an arbitrary waveform from the user and then rebroadcasts the waveform pattern using an integrated transmitter with data errors and / or other signal impairments such as jitter, noise, etc. In such a loopback test, the receiver 120 is configured to receive a waveform from the DUT 110, which itself may be a data channel of a certain type. First, the receiver 120 receives an arbitrary waveform from the data channel. The captured waveform is then sent to the transmitter 150, which applies controlled impairments to the data, such as jitter, crosstalk, or reference. Figure 4 and Figure 5The transmitter applies the desired impairments to the waveform sent by the receiver 120 and then sends the impaired waveform back to the data channel.

[0089] Aspects of the present disclosure may work on specifically created hardware, firmware, digital signal processors, or on a specially programmed computer including a processor that works according to programming instructions. The term controller or processor as used herein is intended to include a microprocessor, a microcomputer, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), and a dedicated hardware controller. One or more aspects of the present disclosure may be embodied in computer-usable data and computer-executable instructions, such as embodied in one or more program modules, executed by one or more computers (including monitoring modules) or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc., which perform specific tasks or implement specific abstract data types when executed by a processor in a computer or other device. Computer executable instructions may be stored on a computer-readable storage medium, such as a hard disk, an optical disk, a removable storage medium, a solid-state memory, a random access memory (RAM), etc. As will be appreciated by those skilled in the art, the functions of the program modules may be combined or distributed in various aspects as desired. In addition, the functions may be fully or partially embodied in firmware or hardware equivalents (such as integrated circuits, FPGAs, etc.). Certain data structures may be used to more efficiently implement one or more aspects of the present disclosure, and such data structures are contemplated to be within the scope of the computer-executable instructions and computer-usable data described herein.

[0090] In some cases, the disclosed aspects may be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by one or more computer-readable storage media or instructions stored on one or more computer-readable storage media, which may be read and executed by one or more processors. Such instructions may be referred to as computer program products. As discussed herein, computer-readable media means any medium that may be accessed by a computing device. By way of example and not limitation, computer-readable media may include computer storage media and communication media.

[0091] Computer storage media means any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital video disk (DVD) or other optical disk storage, cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, and any other volatile or non-volatile, removable or non-removable media implemented using any technology. Computer storage media excludes the signal itself and the transient form of signal transmission.

[0092] Communication media means any medium that can be used for communication of computer-readable information. By way of example and not limitation, communication media can include coaxial cables, fiber optic cables, air, or any other medium suitable for communication of electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals.

[0093] Example

[0094] Illustrative examples of the technology disclosed herein are provided below. Embodiments of the technology may include any one or more of the examples described below and any combination thereof.

[0095] Example 1 is a test and measurement device comprising: an input configured to receive an analog signal from a device under test (DUT); an analog-to-digital converter (ADC) coupled to the input and constructed to convert the analog signal into a digital signal; a receiver constructed to accept the digital signal and perform signal conditioning, symbol recovery, and analysis on the digital signal using a first digital signal processor; a transmitter constructed to generate a digital output signal using a second digital signal processor; a digital-to-analog converter (DAC) coupled to the transmitter and constructed to convert the digital output signal from the transmitter into an analog signal, and constructed to send the analog signal to the DUT; and a communication path between the receiver and the transmitter, the communication path not passing through the DUT.

[0096] Example 2 is the test and measurement device of Example 1, wherein at least a portion of the first digital processor is physically embodied in a reconfigurable processor.

[0097] Example 3 is the test and measurement device of Example 1, wherein at least a portion of the first digital processor is physically embodied in a field programmable gate array.

[0098] Example 4 is the test and measurement device of any of Examples 1 to 3, wherein at least a portion of the second digital processor is physically embodied in a reconfigurable processor.

[0099] Example 5 is the test and measurement device of any of Examples 1 to 4, wherein at least a portion of the second digital processor is physically embodied in a field programmable gate array.

[0100] Example 6 is the test and measurement device of any of Examples 1 to 5, wherein at least portions of the first digital processor and the second digital processor are physically embodied in a field programmable gate array.

[0101] Example 7 is the test and measurement device of any of Examples 1 to 6, wherein the transmitter and the receiver are housed in the same physical device.

[0102] Example 8 is the test and measurement device of any of Examples 1 to 7, wherein the transmitter and the receiver are housed in separate physical devices, and wherein the communication path between the receiver and the transmitter is a wired connection.

[0103] Example 9 is the test and measurement device of any of Examples 1 to 8, wherein the transmitter and the receiver are housed in separate physical devices, and wherein the communication path between the receiver and the transmitter is a wireless connection.

[0104] Example 10 is the test and measurement apparatus of any of Examples 1 to 9, wherein the DUT is a communication channel.

[0105] Example 11 is a test and measurement device comprising: an input configured to receive an analog signal from a device under test (DUT); an analog-to-digital converter (ADC) coupled to the input and constructed to convert the analog signal into a digital signal; a receiver constructed to accept a digital signal and perform signal conditioning, symbol recovery, and analysis on the digital signal using a first digital signal processor at a rate that is the same as or greater than the rate at which the analog signal is received from the DUT to continuously process the analog signal from the DUT.

[0106] Example 12 is the test and measurement apparatus of Example 11, wherein the analog signal is converted to a digital signal at a rate exceeding 500M samples / second.

[0107] Example 13 is the test and measurement apparatus of Examples 11-12, wherein the receiver includes an eye pattern generator configured to continuously generate an eye pattern for the digital signal without stopping receiving the analog signal from the DUT.

[0108] Example 14 is the test and measurement apparatus of Examples 11-13, wherein the receiver includes a second input to receive a second analog signal from a second device under test (DUT).

[0109] Example 15 is the test and measurement apparatus of Examples 11 to 14, wherein the analog signal and the second analog signal are synchronized with each other.

[0110] Example 16 is the test and measurement apparatus of Examples 11 to 15, wherein the analog signal and the second analog signal carry the first portion and the second portion of the signal according to a specific protocol, respectively.

[0111] Example 17 is the test and measurement apparatus of Examples 11 to 16, wherein the receiver is configured to recover a protocol signal according to a specific protocol from a combination of the analog signal and the second analog signal.

[0112] Example 18 is a transmitter portion of a test and measurement device, comprising: a signal generator coupled to a digital signal processor and constructed to generate a basic output signal; a digital signal processor constructed to add one or more impairments to the basic output signal to form a combined output signal; and a digital-to-analog converter (DAC) coupled and constructed to convert the combined output signal into an analog signal and send the analog signal to a device for testing.

[0113] Example 19 is a transmitter portion of the test and measurement device of Example 18, further comprising a second signal generator to generate a second output signal.

[0114] Example 20 is a transmitter portion of the test and measurement apparatus of Examples 18-19, wherein each of the primary output signal and the secondary output signal carries a portion of the protocol signal.

[0115] Example 21 is a transmitter portion of the test and measurement apparatus of Examples 18 to 20, further comprising a differential deviation generator, and wherein the generated differential deviation is added to the analog signal before the analog signal is output to the apparatus for testing.

[0116] Example 22 is the transmitter portion of the test and measurement apparatus of Examples 18 to 21, further comprising a common mode impairment simulator, and wherein the generated common mode impairments are added to the analog signal before the analog signal is output to the apparatus for testing.

[0117] Example 23 is a transmitter portion of the test and measurement apparatus of Examples 18 to 22, wherein one of the one or more impairments includes inter-symbol interference generated by an inter-symbol interference emulator.

[0118] Example 24 is a transmitter portion of the test and measurement apparatus of Examples 18 to 23, wherein one of the one or more impairments includes a crosstalk emulation generated by a crosstalk emulator.

[0119] Example 25 is a transmitter portion of the test and measurement device according to Examples 18 to 24, further comprising a clock generator, and wherein the transmitter portion of the test and measurement device is configured to transmit a clock signal generated by the clock generator to the device.

[0120] Example 26 is a transmitter portion of the test and measurement device according to Examples 18 to 25, further comprising a clock stress generator configured to modify the clock signal before the clock signal is sent to the device.

[0121] Example 27 is a transmitter portion of the test and measurement apparatus of Examples 18 to 26, wherein the clock stress generator is a jitter impairment generator.

[0122] Example 28 is a transmitter portion of the test and measurement device according to Examples 18 to 27, wherein the clock pressure generator is configured to generate a clock offset.

[0123] Example 29 is a transmitter portion of a test and measurement device according to Examples 18 to 28, further comprising a digital marker waveform generator, and wherein the transmitter portion of the test and measurement device is configured to transmit a digital marker signal generated by the digital marker waveform generator to the device.

[0124] Example 30 is a transmitter portion of the test and measurement device according to Examples 18 to 29, wherein the digital marker signal is related to the analog signal.

[0125] Example 31 is a transmitter portion of the test and measurement device according to Examples 18 to 30, wherein the digital marker signal is synchronized with the analog signal.

[0126] Example 32 is a transmitter portion of a test and measurement apparatus according to Examples 18 to 31, further comprising a noise impairment waveform generator, and wherein the generated noise impairment is added to the analog signal before the analog signal is output to the apparatus for testing.

[0127] Example 33 is a test and measurement device comprising: a signal receiver constructed to receive one or more input signals and generate an input data stream therefrom; a bit error trigger generator configured to generate a bit error based on a comparison of a static trigger pattern with a portion of the input data stream; and a memory storage configured to store the one or more input signals and at least one of associated data and measurements in a memory after the bit error trigger is generated, the memory including a portion of the stored signal as the signal existed before the bit error trigger was generated.

[0128] Example 34 is a test and measurement device according to Example 33, wherein the static trigger mode is specified by a user of the test and measurement device.

[0129] Example 35 is a test and measurement apparatus according to Examples 33 to 34, wherein the static trigger mode is an analog signal.

[0130] Example 36 is a test and measurement device according to Examples 33 to 35, wherein the signal receiver is configured to perform a first test before a bit error is triggered, and wherein the signal receiver is configured to perform a second test after the bit error is triggered.

[0131] Example 37 is a test and measurement device according to Examples 33 to 36, wherein the one or more input signals are received from a device or a communication link, and the test and measurement device further includes an impairment generator and transmitter coupled to the device or the communication link.

[0132] Example 38 is a test and measurement apparatus according to Examples 33 to 37, wherein the impairment generator is configured to generate a first set of impairments before a bit error is triggered, and wherein the impairment generator is configured to generate a first set of impairments after the bit error is triggered.

[0133] The foregoing described versions of the disclosed subject matter have many advantages that have been described or will be apparent to one of ordinary skill in the art. Even so, these advantages or features are not required in all versions of the disclosed devices, systems or methods.

[0134] Additionally, this written description refers to specific features. It is to be understood that the disclosure in this specification includes all possible combinations of those specific features. Where a specific feature is disclosed in the context of a specific aspect or example, the feature may also be used in the context of other aspects and examples to the extent possible.

[0135] Additionally, when the present application refers to a method having two or more defined steps or operations, the defined steps or operations may be performed in any order or simultaneously, unless the context excludes those possibilities.

[0136] Although specific examples of the present invention have been shown and described for purposes of illustration, it will be appreciated that various modifications may be made without departing from the spirit and scope of the present invention.Accordingly, the present invention should not be limited except as by the appended claims.

Claims

1. A test and measurement device, include: an input configured to receive an analog signal from a device under test (DUT); an analog-to-digital converter (ADC) coupled to the input and configured to convert the analog signal into a digital signal; a receiver configured to accept a digital signal and perform signal conditioning, symbol recovery, and analysis on the digital signal using a first digital signal processor; a transmitter configured to generate a digital output signal using a second digital signal processor; a digital-to-analog converter (DAC) coupled to the transmitter and configured to convert a digital output signal from the transmitter into an analog signal and configured to send the analog signal to the DUT; as well as A communication path between a receiver and a transmitter that does not pass through the DUT.

2. The test and measurement device according to claim 1, in, At least a portion of the first digital processor is physically embodied in a reconfigurable processor.

3. The test and measurement device according to claim 1, in, At least part of the first digital processor is physically embodied in a field programmable gate array.

4. The test and measurement device according to claim 1, in, At least a portion of the second digital processor is physically embodied in the reconfigurable processor.

5. The test and measurement device according to claim 1, in, At least a portion of the second digital processor is physically embodied in a field programmable gate array.

6. The test and measurement device according to claim 1, in, At least portions of the first digital processor and the second digital processor are physically embodied in a field programmable gate array.

7. The test and measurement device according to claim 1, in, The transmitter and receiver are housed in the same physical device.

8. The test and measurement device according to claim 1, in, The transmitter and receiver are housed in separate physical devices, and wherein the communication path between the receiver and the transmitter is a wired connection.

9. The test and measurement device according to claim 1, in, The transmitter and receiver are housed in separate physical devices, and wherein the communication path between the receiver and the transmitter is a wireless connection.

10. The test and measurement device according to claim 1, in, The DUT is the communication channel.

11. A test and measurement device, include: an input configured to receive an analog signal from a device under test (DUT); an analog-to-digital converter (ADC) coupled to the input and configured to convert the analog signal into a digital signal; A receiver configured to accept a digital signal and to perform signal conditioning, symbol recovery, and analysis on the digital signal using a first digital signal processor at a rate that is the same as or exceeds a rate at which the analog signal is received from the DUT to continuously process the analog signal from the DUT.

12. The test and measurement device according to claim 11, in, Analog signals are converted to digital signals at a rate of more than 500M samples / second.

13. The test and measurement device according to claim 12, in, The receiver includes an eye pattern generator configured to continuously generate an eye pattern for the digital signal without stopping receiving the analog signal from the DUT.

14. The test and measurement device according to claim 13, in, The receiver includes a second input for receiving a second analog signal from a second device under test (DUT).

15. The test and measurement device according to claim 13, in, The analog signal and the second analog signal are synchronized with each other.

16. The test and measurement device according to claim 15, in, The analog signal and the second analog signal carry a first portion and a second portion of a signal according to a specific protocol, respectively.

17. The test and measurement device according to claim 15, in, The receiver is configured to recover a protocol signal according to a particular protocol from a combination of the analog signal and the second analog signal.

18. A transmitter portion of a test and measurement device, include: a signal generator configured to generate a primary output signal; a digital signal processor configured to add one or more impairments to a base output signal to form a combined output signal; a digital-to-analog converter (DAC) coupled to the digital signal processor and configured to convert the combined output signal into an analog signal and send the analog signal to a device for testing; as well as A common mode impairment simulator is provided, and wherein the generated common mode impairments are added to the analog signal before the analog signal is output to the device for testing.

19. The transmitter portion of the test and measurement device of claim 18, further comprising a second signal generator to generate a second output signal.

20. The transmitter portion of the test and measurement device according to claim 19, in, Each of the primary output signal and the secondary output signal carries a portion of the protocol signal.

21. The transmitter portion of the test and measurement apparatus of claim 18, further comprising a differential deviation generator, and wherein the generated differential deviation is added to the analog signal before the analog signal is output to the apparatus for testing.

22. The transmitter portion of the test and measurement apparatus of claim 18, wherein one of the one or more impairments comprises inter-symbol interference generated by an inter-symbol interference emulator.

23. The transmitter portion of the test and measurement apparatus of claim 18, wherein one of the one or more impairments comprises a crosstalk emulation generated by a crosstalk emulator.

24. The transmitter portion of the test and measurement device of claim 18, further comprising a clock generator, and wherein the transmitter portion of the test and measurement device is configured to transmit a clock signal generated by the clock generator to the device.

25. The transmitter portion of the test and measurement device of claim 18, further comprising a clock stress generator configured to modify the clock signal before the clock signal is sent to the device.

26. The transmitter portion of the test and measurement apparatus of claim 25, wherein the clock stress generator is a jitter impairment generator.

27. The transmitter portion of the test and measurement device of claim 25, wherein the clock stress generator is configured to generate a clock offset.

28. The transmitter portion of the test and measurement device of claim 18, further comprising a digital marker waveform generator, and wherein the transmitter portion of the test and measurement device is configured to transmit the digital marker signal generated by the digital marker waveform generator to the device.

29. The transmitter portion of the test and measurement device of claim 28, wherein the digital marker signal is related to the analog signal.

30. The transmitter portion of the test and measurement device of claim 29, wherein the digital marker signal is synchronized with the analog signal.

31. The transmitter portion of the test and measurement apparatus of claim 18, further comprising a noise impairment waveform generator, and wherein the generated noise impairment is added to the analog signal before the analog signal is output to the apparatus for testing.

32. A test and measurement device, include: a signal receiver configured to receive one or more input signals and generate an input digital data stream therefrom; a bit error trigger generator configured to generate a bit error trigger based on a comparison of a static trigger pattern and a portion of an input digital data stream; a memory storage configured to store the one or more input signals and at least one of the associated data and measurements in a memory after a bit error trigger is generated, the memory comprising a portion of the stored signal as the signal existed before the bit error trigger was generated, wherein the one or more input signals are received from a device or a communication link, and the test and measurement device further comprises an impairment generator and a transmitter coupled to the device or the communication link, and Wherein the impairment generator is configured to generate a first set of impairments before the bit error is triggered, and wherein the impairment generator is configured to generate a first set of impairments after the bit error is triggered.

33. The test and measurement device of claim 32, wherein the static trigger mode is specified by a user of the test and measurement device.

34. The test and measurement device according to claim 32, in, The static trigger mode is an analog signal.

35. The test and measurement device according to claim 32, in, Wherein the signal receiver is configured to perform a first test before a bit error is triggered, and wherein the signal receiver is configured to perform a second test after the bit error is triggered.

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