Semiconductor device and method for manufacturing the same

Abstract

An embodiment of the present invention provides a semiconductor device and a method for manufacturing the same, wherein the semiconductor device includes a first system-on-chip device bonded to a first memory device, a second system-on-chip device bonded to the first memory device, a first sealant surrounding the first system-on-chip device and the second system-on-chip device, a second sealant surrounding the first system-on-chip device, the second system-on-chip device and the first memory device, and a through hole extending from a first side of the second sealant to a second side of the first sealant, the through hole being located outside the first sealant.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density comes from the continuous reduction in the minimum component size (e.g., semiconductor process node shrinking to sub-20nm nodes), which allows more components to be integrated into a given area. With the recent growth in demand for miniaturization, higher speed and greater bandwidth, as well as lower power consumption and latency, there is an increasing demand for smaller and more creative packaging technologies for semiconductor dies.

[0003] As semiconductor technology has further developed, stacked and bonded semiconductor devices have become an effective option to further reduce the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic circuits, memory circuits, processor circuits, etc. are at least partially manufactured on separate substrates and then physically and electrically bonded together to form functional devices. Such bonding processes utilize complex techniques and are expected to be improved. Summary of the invention

[0004] An embodiment of the present invention provides a semiconductor device, comprising: a first system-on-chip device, bonded to a first memory device; a second system-on-chip device, bonded to the first memory device; a first sealant, surrounding the first system-on-chip device and the second system-on-chip device; a second sealant, surrounding the first system-on-chip device, the second system-on-chip device and the first memory device; and a through hole, extending from a first side of the second sealant to a second side of the first sealant, the through hole being located outside the first sealant.

[0005] An embodiment of the present invention further provides a semiconductor device, comprising: a first package electrically connected to a through hole; a first redistribution layer electrically connected to the through hole; a first system-on-chip device electrically connected to the first redistribution layer; a second system-on-chip device electrically connected to the first redistribution layer; a memory device bonded to the first system-on-chip device and the second system-on-chip device; a first sealant surrounding the first system-on-chip device and the second system-on-chip device; and a second sealant surrounding the through hole, the first system-on-chip device, the second system-on-chip device, the memory device, and the first sealant. An embodiment of the present invention further provides a method for manufacturing a semiconductor device, the method comprising: providing a memory device; bonding the first system-on-chip device to the memory device; bonding the second system-on-chip device to the memory device; sealing the first system-on-chip device and the second system-on-chip device with a first sealant; after sealing, bonding the first system-on-chip device and the second system-on-chip device to the redistribution layer, the redistribution layer electrically connected to the through hole; and sealing the through hole, the first system-on-chip device, and the second system-on-chip device with a second sealant. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A to Figure 1B A semiconductor wafer having a first semiconductor device is shown in accordance with some embodiments.

[0008] FIG. 2A to FIG. 2B A reconstituted wafer of a first semiconductor device is shown in accordance with some embodiments.

[0009] FIG. 3A to FIG. 3B Bonding of a second semiconductor device to a first semiconductor device is shown in accordance with some embodiments.

[0010] Figure 4 Sealing of a second semiconductor device is shown in accordance with some embodiments.

[0011] Figure 5 A cutting process according to some embodiments is shown.

[0012] Figure 6 An integrated fan-out process is shown in accordance with some embodiments.

[0013] Figure 7 A second package is shown in accordance with some embodiments.

[0014] Figure 8A back-to-back engagement configuration is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0017] Embodiments will now be described with respect to a specific embodiment that integrates a first system-on-chip device, a second system-on-chip device, and a wide I / O memory device with a system-on-integrated circuit and integrated fan-out technology to achieve a high-performance and low-cost structure. However, the embodiments described herein may be applied to a variety of structures and methods, and all such structures and methods are fully intended to be included within the scope of the embodiments.

[0018] Reference now Figure 1A to Figure 1B , showing a semiconductor wafer 100 having a plurality of first semiconductor devices 101 formed together with the semiconductor wafer 100 and the plurality of first semiconductor devices 101 formed above the semiconductor wafer 100 ( Figure 1B Shows Figure 1ACross-sectional view along line AA). In a particular embodiment, the first semiconductor device 101 may be a memory device, such as a wide I / O dynamic random access memory (DRAM) device having a large number of I / O interfaces (such as greater than 256 interfaces), thereby enabling large data bandwidth even at a low clock speed. However, the first semiconductor device 101 may also be any other suitable type of memory device with a high data transfer rate, such as an LPDDRn memory device with a high data transfer rate, or may be any other suitable type of device, such as a logic die, a central processing unit (CPU) die, an input / output die, a combination of these, etc. In addition, the semiconductor wafer 100 may be received by the manufacturer from a third-party manufacturer, or may be manufactured internally.

[0019] In one embodiment, the first semiconductor device 101 may include a first substrate 103, a first active device, a first metallization layer 105, a first wafer bonding layer 109, and a first conductive wafer bonding material 107. The first substrate 103 may include a doped or undoped bulk silicon, or an active layer of a silicon-on-insulator (SOI) substrate. Typically, an SOI substrate includes a layer of semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0020] The first active devices include a variety of active and passive devices such as capacitors, resistors, inductors, etc. that can be used to generate the desired structural and functional requirements of the design of the first semiconductor device 101. The first active devices can be formed in or on the first substrate 103 using any suitable method.

[0021] The first metallization layer 105 is formed over the first substrate 103 and the first active device and is designed to connect the various active devices to form a functional circuit. In one embodiment, the first metallization layer 105 is formed of alternating layers of dielectric material and conductive material and can be formed by any suitable process such as deposition, damascene, dual damascene, etc. In one embodiment, four metallization layers can be separated from the first substrate 103 by at least one interlayer dielectric layer (ILD), but the exact number of first metallization layers 105 depends on the design of the first semiconductor device 101.

[0022] The first wafer bonding layer 109 may be formed over the first metallization layer 105 on the first substrate 103. The first wafer bonding layer 109 may be used for hybrid bonding or fusion bonding (also referred to as oxide-to-oxide bonding). According to some embodiments, the first wafer bonding layer 109 is formed of a silicon-containing dielectric material such as silicon oxide, silicon nitride, etc. The first wafer bonding layer 109 may be deposited to a thickness of about 1 nm to about 1000 nm, such as about 5 nm, using any suitable method such as atomic layer deposition (ALD), CVD, high density plasma chemical vapor deposition (HDPCVD), PVD, etc. However, any suitable material, process, and thickness may be used.

[0023] Once the first wafer bonding layer 109 has been formed, a bonding opening can be formed in the first wafer bonding layer 109 to prepare for forming the first conductive wafer bonding material 107. In one embodiment, the bonding opening can be formed by first applying and patterning a photoresist over the top surface of the first wafer bonding layer 109. Then, to form the opening, the first wafer bonding layer 109 is etched using the photoresist. The first wafer bonding layer 109 can be etched by dry etching (e.g., reactive ion etching (RIE) or neutral beam etching (NBE)), wet etching, etc. According to some embodiments of the present disclosure, etching stops on the first metallization layer 105 so that the first metallization layer 105 is exposed through the opening in the first wafer bonding layer 109.

[0024] Once the first metallization layer 105 is exposed, the first conductive wafer bonding material 107 can be formed to be in physical and electrical contact with the first metallization layer 105. In one embodiment, the first conductive wafer bonding material 107 may include a barrier layer, a seed layer, a filler metal, or a combination thereof (not shown separately). For example, the barrier layer may be blanket deposited over the first metallization layer 105. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The seed layer may be a conductive material such as copper, and may be blanket deposited over the barrier layer using processes such as sputtering, evaporation, or plasma enhanced chemical vapor deposition (PECVD) according to the desired material. The filler metal may be a conductor such as copper or a copper alloy, and may be deposited over the seed layer to fill or overfill the opening by a plating process such as electroplating or chemical plating. Once the filler metal is deposited, excess material of the filler metal, the seed layer, and the barrier layer may be removed from the outside of the opening by a planarization process such as chemical mechanical polishing. However, although a single damascene process has been described, any suitable method such as a dual damascene process may also be used.

[0025] However, the formation, patterning of the first wafer bonding layer 109 and plating the first conductive wafer bonding material 107 into openings before being planarized in the above-mentioned embodiments are merely exemplary and are not intended to be limited to the embodiments. Instead, any suitable method of forming the first wafer bonding layer 109 and the first conductive wafer bonding material 107 may be utilized. In other embodiments, the first conductive wafer bonding material 107 may be first formed using, for example, a photolithography patterning and plating process, and then a dielectric material may be used to gap-fill the area around the first conductive wafer bonding material 107 before CMP planarization. Any such manufacturing process is fully intended to be included within the scope of the embodiments.

[0026] FIG. 2A to FIG. 2B An optional process is described by which the first semiconductor devices 101 are tested, separated, and then used to form a reconstituted wafer 200 having only known good dies (KGDs) for further processing ( Figure 2B Shows Figure 2A sectional view along line BB′). In particular, in some manufacturing processes, the semiconductor wafer 100 may have a low yield (e.g., 10 or fewer good dies out of at least 100 dies manufactured on the semiconductor wafer 100). Thus, in order to ensure that each first semiconductor device 101 meets all desired specifications for a desired design, the first semiconductor devices 101 may be tested. For example, in order to test the first semiconductor devices 101, a test probe may be placed to be electrically connected to each first semiconductor device 101, and a signal may be input to and received from the first semiconductor device 101.

[0027] Once testing has been performed and the first semiconductor devices 101 have been identified as known good or known bad, the semiconductor wafer 100 may be diced (see, e.g., Figure 1A to Figure 1B ) to separate known good first semiconductor devices 101 from defective first semiconductor devices 101. In one embodiment, dicing may be performed by cutting through the first substrate 103 between the first semiconductor devices 101 using a saw blade (not shown), thereby separating one first semiconductor device 101 from another first semiconductor device 101.

[0028] However, as will be appreciated by those skilled in the art, using a saw blade to cut the first semiconductor device 101 is merely an illustrative embodiment and is not intended to be limiting. Alternatively, other methods for cutting the first semiconductor device 101 may be used, such as using one or more etchings to separate the first semiconductor device 101. These methods and any other suitable methods may be used interchangeably to cut the first semiconductor device 101.

[0029] Once the first semiconductor devices 101 are cut, those first semiconductor devices 101 that have passed the test and are known to be good are placed on a first carrier substrate 201 using a first adhesive layer 203. In one embodiment, the first carrier substrate 201 includes, for example, a silicon-based material such as glass or silicon oxide, or other materials such as aluminum oxide, a combination of any of these materials, etc. The first carrier substrate 201 is flat to accommodate the attachment of the first semiconductor devices 101.

[0030] The first adhesive layer 203 is placed over the first carrier substrate 201 and is used to provide protection to, for example, the first semiconductor device 101 once it has been attached. In one embodiment, the first adhesive layer 203 is a dielectric, such as an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the first adhesive layer 203 may be an ultraviolet (UV) glue that loses its adhesive properties when exposed to UV light. The first adhesive layer 203 may be dispensed and cured as a liquid, the first adhesive layer 203 may be a laminated film laminated on the first carrier substrate 201, or the like.

[0031] Once the first adhesion layer 203 has been placed on the first carrier substrate 201, known good dies of the first semiconductor device 101 may be placed adjacent to each other on the first adhesion layer 203. The known good first semiconductor devices 101 may be placed using, for example, a pick and place process. However, any suitable method may be utilized to place the first semiconductor device 101.

[0032] In one embodiment, a first of the first semiconductor devices 101 may be placed a first distance D1 from a second of the first semiconductor devices 101. The specific first distance D1 to be used depends on many factors, such as the size of the first semiconductor device 101, and in an embodiment where the first semiconductor device 101 is 6 mm, the first distance D1 may be between about 10 μm and about 500 μm, such as about 80 μm. However, any suitable distance may be used.

[0033] After the first semiconductor device 101 is placed, the first semiconductor device 101 may be sealed. The sealing may be performed in a molded device, which may include a top molded portion and a bottom molded portion that is separable from the top molded portion. When the top molded portion is lowered to be adjacent to the bottom molded portion, a mold cavity for the first carrier substrate 201 and the first semiconductor device 101 may be formed.

[0034] During the sealing process, the top molded portion can be placed adjacent to the bottom molded portion, thereby surrounding the first carrier substrate 201 and the first semiconductor device 101 within the molding cavity. Once surrounded, the top molded portion and the bottom molded portion can form a hermetic seal to control the flow of gas into and out of the molding cavity. Once sealed, a sealant 205 can be placed within the molding cavity.

[0035] The sealant 205 may be an epoxy resin or a molding compound resin such as polyimide, polyphenylene sulfide (PPS), polyetheretherketone (PEEK), polyethersulfone (PES), a heat-resistant crystalline resin, a combination of these, etc. The sealant 205 may be placed in the molding cavity before the top molding portion and the bottom molding portion are aligned, or may be injected into the molding cavity through an injection port using compression molding, transfer molding, etc.

[0036] Once the sealant 205 is placed in the molding cavity so that the sealant 205 seals the first carrier substrate 201 and the first semiconductor device 101, the sealant 205 can be cured in order to harden the sealant 205 for optimal protection. Although the exact curing process depends at least in part on the specific material selected for the sealant 205, in an embodiment where a molding compound is selected as the sealant 205, the sealant 205 can be cured by a process such as heating the sealant 205 to between about 100° C. and about 200° C. (such as about 125° C. for about 60 seconds to about 3000 seconds, such as about 600 seconds). In addition, an initiator and / or catalyst can be included in the sealant 205 to better control the curing process.

[0037] However, as will be appreciated by one of ordinary skill in the art, the above-described curing processes are merely exemplary processes and are not meant to limit the current embodiments. Other curing processes such as radiation or even allowing the sealant 205 to harden at ambient temperature may also be used. Any suitable curing process may be used, and all such processes are fully intended to be included within the scope of the embodiments discussed herein.

[0038] Figure 2B Further shown is the thinning of the encapsulant 205 in order to expose the first semiconductor device 101 for further processing. The thinning may be performed, for example, using mechanical grinding, chemical methods, or a chemical mechanical polishing (CMP) process, whereby chemical etchants and abrasives are used to react the encapsulant 205 and the first semiconductor device 101 and grind away the encapsulant 205, thereby exposing the wafer bonding material 107 on the first semiconductor device 101. In this way, the first semiconductor device 101 may have a flat surface that is also coplanar with the encapsulant 205. In another embodiment, grinding may be omitted. For example, if the first semiconductor device 101 is already exposed after encapsulation, grinding may be omitted.

[0039] Furthermore, although the above CMP process is presented as an illustrative embodiment, it is not intended to be limited to these embodiments. Any other suitable removal process may be used to thin the sealant 205 and the first semiconductor device 101. For example, a series of chemical etching may be used. This process and any other suitable process may be used to planarize the sealant 205 and the first semiconductor device 101, and all such processes are fully intended to be included within the scope of the embodiments.

[0040] However, while the formation of the reconstituted wafer 200 may be used to help ensure that only known good dies are utilized, the formation of the reconstituted wafer 200 is exemplary only and not limiting. Conversely, the original semiconductor wafer 100 may be used without forming the reconstituted wafer 200. Such embodiments are fully intended to be included within the scope of the embodiments.

[0041] Figure 3A 2, once the reconstituted wafer 200 has been formed, integrated fan-out through-vias (TIVs) 301 may be formed on the reconstituted wafer 200. In one embodiment, the TIVs 301 may be formed by first forming a seed layer over the reconstituted wafer 200. In one embodiment, the seed layer is a thin layer of conductive material that facilitates the formation of thicker layers in subsequent process steps. The seed layer may include about thick titanium layer, followed by approx. The seed layer may be formed to have a thickness between about 0.3 μm and about 1 μm, such as about 0.5 μm, depending on the desired material.

[0042] After forming the seed layer, a photoresist is placed on the seed layer and patterned. In one embodiment, the photoresist can be placed on the seed layer to a height between about 50 μm and about 250 μm, such as about 120 μm, using, for example, a spin coating technique. Once in place, the photoresist can then be patterned to cause a chemical reaction by exposing the photoresist to a patterned energy source (e.g., a patterned light source), thereby causing physical changes on those portions of the photoresist exposed to the patterned light source. The developer is then applied to the exposed photoresist to selectively remove the exposed portion of the photoresist or the unexposed portion of the photoresist according to the desired pattern using the physical changes.

[0043] In one embodiment, the pattern formed in the photoresist is a pattern for TIV 301. TIV 301 is formed in such a position to be positioned on a different side of a subsequently attached device, such as, for example, second semiconductor device 303. However, any suitable arrangement of the pattern for TIV 301 may be utilized, such as by positioning so that second semiconductor device 303 is placed on the opposite side of TIV 301.

[0044] In one embodiment, TIV 301 is formed in a photoresist. In one embodiment, TIV 301 includes one or more conductive materials, such as copper, tungsten, other conductive metals, etc., and can be formed, for example, by electroplating, chemical plating, etc. In one embodiment, an electroplating process is used, in which the seed layer and the photoresist are immersed or immersed in a plating solution. The surface of the seed layer is electrically connected to the negative side of an external DC (direct current) power supply, so that the seed layer is used as a cathode in the electroplating process. A solid conductive anode (such as a copper anode) is also immersed in the solution and attached to the positive side of the power supply. Atoms from the anode dissolve into the solution, and the cathode (e.g., the seed layer) obtains the dissolved atoms from the solution, thereby plating the conductive area exposed by the seed layer in the opening of the photoresist.

[0045] Once the TIV 301 has been formed using the photoresist and seed layer, the photoresist can be removed using a suitable removal process. In one embodiment, the photoresist can be removed using a plasma ashing process, whereby the temperature of the photoresist can be increased until the photoresist undergoes thermal decomposition and can be removed. However, alternatively, any other suitable process such as wet stripping can be used. Removal of the photoresist can expose a portion below the seed layer.

[0046] Once exposed, the exposed portions of the seed layer can be removed. In one embodiment, the exposed portions of the seed layer (e.g., those portions not covered by TIV 301) can be removed by, for example, one or more wet etching processes or dry etching processes. For example, in a dry etching process, TIV 301 can be used as a mask to direct reactants to the seed layer. In another embodiment, an etchant can be sprayed or otherwise contacted with the seed layer to remove the exposed portions of the seed layer. After etching away the exposed portions of the seed layer, portions of the reconstructed wafer 200 are exposed between the TIVs 301.

[0047] After the TIV 301 has been formed, the second semiconductor device 303 may be placed adjacent to the TIV 301. In one embodiment, the second semiconductor device 303 may be a system-on-chip device, such as a logic device, that is intended to work in conjunction with the first semiconductor device 101 (e.g., a wide I / O DRAM device). However, any suitable functionality may be utilized, such as a logic die, a central processing unit (CPU) die, an input / output die, a combination of these, etc.

[0048] Figure 3B A close-up view of the second semiconductor device 303 is shown, and it is shown that the second semiconductor device 303 may include a second substrate 305, a second active device, a second metallization layer 307, a through silicon via (TSV) 309, a second wafer bonding layer 311, and a second conductive wafer bonding material 313. In one embodiment, the second substrate 305, the second active device, the second metallization layer 307, the second wafer bonding layer 311, and the second conductive wafer bonding material 313 may be formed similarly to the first substrate 103, the first active device, the first metallization layer 105, the first wafer bonding layer 109, and the first conductive wafer bonding material 107, as described above with respect to Figure 1A to Figure 1B However, in other embodiments, different processes may be used to form these structures.

[0049] Additionally, in some embodiments, the second semiconductor device 303 may be formed to include a TSV 309 that provides electrical connectivity from the front side (e.g., front side) of the second semiconductor device 303 where the second active device is located to the back side of the second semiconductor device 303. In one embodiment, the TSV 309 may be formed by first forming a through silicon via (TSV) opening in the second substrate 305 and any overlying second metallization layer 307 (if required). The TSV opening may be formed by applying and developing a suitable photoresist and removing portions of the second substrate 305 that are exposed to a desired depth. The TSV opening may be formed to extend into the second substrate 305 to a depth greater than the final desired height of the second substrate 305. Thus, although the depth depends on the overall design, the depth may be between about 20 μm and about 200 μm, such as a depth of about 50 μm.

[0050] Once the TSV openings are formed in the second substrate 305 and / or any second metallization layer 307, the TSV openings may be lined with a liner. The liner may be an oxide formed, for example, from tetraethyl orthosilicate (TEOS) or silicon nitride, although any suitable dielectric material may be used. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other suitable processes such as physical vapor deposition or thermal processes may be used. Additionally, the liner may be formed to a thickness between about 0.1 μm and about 5 μm, such as about 1 μm.

[0051] Once the liner has been formed along the sidewalls and bottom of the TSV opening, a barrier layer can be formed and the remainder of the TSV opening can be filled with a first conductive material. The first conductive material can include copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, etc. can also be used. The first conductive material can be formed by electroplating copper on the seed layer, filling and overfilling the TSV opening. Once the TSV opening has been filled, the excess liner, barrier layer, seed layer and first conductive material outside the TSV opening can be removed by a planarization process such as chemical mechanical polishing (CMP), although any suitable removal process can be used.

[0052] Once the TSV openings have been filled, thinning of the back side of the second substrate 305 exposes the openings for the TSVs 309 and forms the TSVs 309 from the conductive material extending through the second substrate 305. In one embodiment, thinning of the second side of the second substrate 305 may expose the TSVs 309. The thinning of the second side of the second substrate 305 may be performed by a planarization process such as CMP or etching.

[0053] Additionally, if desired, the back side of the second substrate 305 may then be recessed to allow the TSV 309 to protrude from the back side of the second substrate 305. In one embodiment, the recessing may be performed using an etching process such as a dry etching process, although any suitable process may be used. In one embodiment, the TSV 309 may protrude from the back side of the second substrate 305 by a distance between about 0.5 μm and about 10 μm, such as about 5 μm.

[0054] Once the TSVs 309 protrude from the second substrate 305, a passivation layer 315 may be formed to protect the TSVs 309. In one embodiment, the passivation layer 315 may be made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, a polymer such as polybenzoxazole (PBO), a molding compound, a low-k dielectric such as a carbon-doped oxide, an ultra-low-k dielectric such as porous carbon-doped silicon dioxide, combinations of these, and the like. The passivation layer 315 may be formed by low temperature chemical vapor deposition (LTCVD), although any suitable deposition process may be used, such as CVD, PVD, ALD, a molding process, combinations of these, and the like. After the passivation layer 315 has been formed, the passivation layer 315 may also be thinned to expose the TSVs 309 again. In one embodiment, a chemical mechanical polishing process may be used to thin the passivation layer 315 until the TSVs 309 have been exposed.

[0055] Once the second semiconductor device 303 has been prepared, the second semiconductor device 303 is bonded to the first semiconductor device 101 using, for example, hybrid bonding. In one embodiment, the surface of the first semiconductor device 101 (e.g., the first wafer bonding layer 109 and the first conductive wafer bonding material 107) and the surface of the second semiconductor device 303 (e.g., the second wafer bonding layer 311 and the second conductive wafer bonding material 313) can be activated first. As an example, activating the top surfaces of the first semiconductor device 101 and the second semiconductor device 303 may include dry processing, wet processing, plasma processing, exposure to an inert gas plasma, exposure to H2, exposure to N2, exposure to O2, or a combination thereof. In an embodiment using wet processing, for example, RCA cleaning may be used. In another embodiment, the activation process may include other types of processing. The activation process facilitates hybrid bonding of the first semiconductor device 101 and the second semiconductor device 303.

[0056] After the activation process, the first semiconductor device 101 and the second semiconductor device 303 may be placed in contact. In a specific embodiment utilizing hybrid bonding, the first conductive wafer bonding material 107 is placed in physical contact with the second conductive wafer bonding material 313, while the first wafer bonding layer 109 is placed in physical contact with the second wafer bonding layer 311. The bonding process between the materials begins with physical contact by chemically modifying the surface through the activation process.

[0057] Once the physical contact begins the bonding process, the adhesion can then be enhanced by subjecting the assembly to a heat treatment. In one embodiment, the first semiconductor device 101 and the second semiconductor device 303 can be subjected to a temperature between about 200°C and about 400°C to enhance the bond between the first wafer bonding layer 109 and the second wafer bonding layer 311. The first semiconductor device 101 and the second semiconductor device 303 can then be subjected to a temperature at or above the eutectic point of the materials of the first conductive wafer bonding material 107 and the second conductive wafer bonding material 313. In this way, the fusion of the first semiconductor device 101 and the second semiconductor device 303 forms a hybrid bonded device.

[0058] In addition, although specific processes for initiating and enhancing hybrid bonding between the first semiconductor device 101 and the second semiconductor device 303 have been described, these descriptions are exemplary only and are not intended to limit the embodiments. Instead, any suitable combination of baking, annealing, pressing, or other bonding processes or process combinations may be used. All such processes are fully intended to be included within the scope of the embodiments.

[0059] In addition, although hybrid bonding has been described as a method of bonding the first semiconductor device 101 to the second semiconductor device 303, this is also exemplary only and is not intended to limit the embodiments. Instead, any suitable bonding method may be used, such as fusion bonding, copper-copper bonding, etc., or even solder bonding using, for example, a ball grid array. Any suitable method of bonding the first semiconductor device 101 to the second semiconductor device 303 may be used.

[0060] Figure 4 As shown, once the second semiconductor device 303 has been bonded to the first semiconductor device 101, the second semiconductor device 303, the first semiconductor device 101, and the TIV 301 may be sealed using a second sealant 401. In one embodiment, a sealant similar to that described above may be used. FIG. 2A to FIG. 2B The process described for sealing the first semiconductor device 101 seals the second semiconductor device 303 , the first semiconductor device 101 , and the TIV 301 . Once sealed, the second semiconductor device 303 , the first semiconductor device 101 , the TIV 301 , and the second encapsulant 401 may be planarized to expose the TIV 301 and the TSV 309 .

[0061] In another embodiment, instead of using a sealant such as a molding compound to seal the second semiconductor device 303 and the TIV 301, a gap-fill dielectric material may be used to seal the second semiconductor device 303 and the TIV 301 (where the TIV 301 may be considered a through dielectric via (TDV)). In some embodiments, the gap-fill dielectric material may include a non-polymer such as silicon dioxide, silicon nitride, another oxide or nitride, etc., which may be deposited using any suitable process. For example, the gap-fill material may be formed by a CVD, PECVD, or ALD deposition process, FCVD, or a spin-on glass process. However, any suitable material and any suitable deposition process may be used.

[0062] In yet another embodiment, where a gap fill material is used for the second encapsulant 401, instead of forming the TIV 301 before forming and / or placing the second encapsulant 401, the TIV 301 (or TDV) may be formed after forming and / or placing the second encapsulant 401. In such an embodiment, the second semiconductor devices 303 may be placed and the gap fill material may be placed to seal the second semiconductor devices 303. Once the gap fill material has been placed, a photolithographic mask and etching process may be used to form openings through the gap fill material between the second semiconductor devices 303 to expose the underlying first conductive wafer bonding material 107.

[0063] Once the opening has been formed, in some embodiments, the opening may be filled with a conductive material including a liner. The liner may be, for example, an oxide formed from tetraethyl orthosilicate (TEOS) or silicon nitride, although any suitable dielectric material may be used. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other suitable processes such as physical vapor deposition or thermal processes may be used. Additionally, the liner may be formed to a thickness between about 0.1 μm and about 5 μm, such as about 1 μm.

[0064] Once the liner has been formed along the sidewalls and bottom of the opening, a barrier layer can be formed and the remainder of the opening can be filled with a conductive material. The conductive material can include copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, etc. can also be used. The conductive material can be formed by electroplating copper on the seed layer, filling and overfilling the TSV opening. Once the opening has been filled, the excess liner, barrier layer, seed layer and conductive material outside the opening can be removed by a planarization process such as chemical mechanical polishing (CMP), although any suitable removal process can be used.

[0065] Figure 4Additionally shown is a redistribution structure 403 having one or more layers formed over the second encapsulant 401. In one embodiment, the redistribution structure 403 may be formed by first forming a first redistribution passivation layer 404 over the second encapsulant 401. In one embodiment, the first redistribution passivation layer 404 may be polybenzoxazole (PBO), although any suitable material such as polyimide or a polyimide derivative, such as a low temperature cured polyimide, may alternatively be used. The first redistribution passivation layer 404 may be placed to a thickness between about 5 μm and about 17 μm, for example about 7 μm, using, for example, a spin coating process, although any suitable method and thickness may alternatively be used.

[0066] Once the first redistribution passivation layer 404 has been formed, a first redistribution via 405 may be formed through the first redistribution passivation layer 404 to enable electrical connection to the second semiconductor device 303 and the TIV 301. In one embodiment, the first redistribution via 405 may be formed by using, for example, a damascene process, whereby, for example, the first redistribution passivation layer 404 is first patterned using a photolithography mask and an etching process to form an opening, or if the material of the first redistribution passivation layer 404 is a metal, the material of the first redistribution passivation layer 404 is exposed and developed to form an opening. Once patterned, the opening is filled with a conductive material such as copper, and excess material is removed using a planarization process such as chemical mechanical polishing. However, any suitable process or material may be used.

[0067] After the first redistribution via 405 has been formed, a first redistribution layer 407 is formed over and electrically connected to the first redistribution via 405. In one embodiment, the first redistribution layer 407 may be formed by first forming a second redistribution passivation layer 408. In one embodiment, the second redistribution passivation layer 408 may be polybenzoxazole (PBO), although any suitable material such as polyimide or a polyimide derivative, such as a low temperature cured polyimide, may alternatively be used. The second redistribution passivation layer 408 may be placed to a thickness between about 5 μm and about 17 μm, for example, about 7 μm, using, for example, a spin coating process, although any suitable method and thickness may alternatively be used.

[0068] Once the second redistribution passivation layer 408 has been formed, an opening through the second redistribution passivation layer 408 may be patterned using, for example, a photolithography etching process to expose the first redistribution vias 405. Once exposed, a seed layer (not shown) of a titanium-copper alloy is formed by a suitable formation process such as CVD or sputtering. A photoresist (also not shown) may then be formed to cover the seed layer, and the photoresist may then be patterned to expose those portions of the seed layer where the first redistribution layer 407 is desired to be positioned.

[0069] Once the photoresist has been formed and patterned, a conductive material such as copper may be formed on the seed layer by a deposition process such as plating. The conductive material may be formed to have a thickness between about 1 μm and about 10 μm, such as about 4 μm. However, although the materials and methods discussed are suitable for forming the conductive material, these materials are merely exemplary. Any other suitable material, such as AlCu or Au, and any other suitable formation process, such as CVD or PVD, may be used to form the first redistribution layer 407.

[0070] Once the conductive material has been formed, the photoresist can be removed by a suitable removal process such as chemical stripping and / or ashing. In addition, after removing the photoresist, those portions of the seed layer covered by the photoresist can be removed by a suitable etching process such as using the conductive material as a mask.

[0071] Once the conductive material has been formed, a third redistribution passivation layer 410 may be formed. In one embodiment, the third redistribution passivation layer 410 may be polybenzoxazole (PBO), although any suitable material such as polyimide or a polyimide derivative, such as a low temperature cured polyimide, may alternatively be used. The third redistribution passivation layer 410 may be placed to a thickness between about 5 μm and about 17 μm, for example about 7 μm, using, for example, a spin coating process, although any suitable method and thickness may alternatively be used.

[0072] Once the redistribution structure 403 has been formed, a contact pad 409 may be formed. The contact pad 409 may include aluminum, but other materials such as copper may also be used. A deposition process such as sputtering may be used to form a material layer (not shown) to form the contact pad 409, and then portions of the material layer may be removed by a suitable process (such as photolithography masking and etching) to form the contact pad 409. However, any other suitable process may be used to form the contact pad 409. The contact pad 409 may be formed to have a thickness between about 0.5 μm and about 4 μm, such as about 1.45 μm. However, any suitable thickness may be used.

[0073] A passivation layer 411 may be formed over the contact pads 409. The passivation layer 411 is deposited over the wafer using, for example, a curable resin or polyimide coating (e.g., polyimide (PI), polybenzoxazole (PBO), epoxy film, etc.) to form the passivation layer 411. The passivation layer 411 may be deposited via a spin coating technique and then cured using, for example, a low temperature curing technique. However, any suitable coating, any suitable deposition technique, and any suitable curing technique may also be used.

[0074] Once the passivation layer 411 is formed, an under bump metal (UBM) 412 and a first external connector 413 may be formed. In one embodiment, the UBM 412 may include three layers of conductive material, such as a titanium layer, a copper layer, and a nickel layer. However, one of ordinary skill in the art will recognize that there are many suitable material arrangements and layer arrangements, such as an arrangement of chromium / chromium copper alloy / copper / gold, an arrangement of titanium / titanium tungsten / copper, or an arrangement of copper / nickel / gold suitable for forming the UBM 412. Any suitable material or layer of material that may be used for the UBM 412 is fully intended to be included within the scope of the embodiments.

[0075] In one embodiment, UBM 412 is formed by forming each layer located above and through passivation layer 411 to physically and electrically contact contact pad 409. The formation of each layer can be performed using a plating process such as electroplating, although other formation processes such as sputtering, evaporation, or PECVD processes can be optionally used depending on the desired material. UBM 412 can be formed to have a thickness between about 0.7 μm and about 10 μm, such as about 5 μm.

[0076] The first external connector 413 can be a conductive pillar, such as a copper pillar. In one embodiment, the conductive pillar can be formed by first forming a seed layer, and then applying and patterning a photoresist through an opening that exposes the seed layer where the conductive pillar is desired to be located. Then, a conductive material such as copper, tungsten, other conductive metals, etc. can be formed in the photoresist using a process such as electroplating, chemical plating, etc. Once formed, the photoresist is removed and the seed layer is patterned using the conductive material as a mask.

[0077] Once the first external connector 413 has been formed, a second passivation layer 415 is formed to protect the first external connector 413. In one embodiment, the second passivation layer 415 may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, very low-k dielectrics such as porous carbon-doped silicon dioxide, combinations of these, etc. using processes such as CVD, PVD, ALD, combinations of these, etc. However, any suitable materials and processes may be used.

[0078] Figure 5 Removal of the first carrier substrate 201 and the first adhesion layer 203 and dicing of the reconstituted wafer 200 to form the first semiconductor structure 500 are shown. In one embodiment, the first carrier substrate 201 may be removed by directing energy at the first adhesion layer 203, thereby reducing its adhesion and allowing both the first adhesion layer 203 and the first carrier substrate 201 to be removed.

[0079] Once separated from the first carrier substrate 201, the reconstructed wafer 200 is diced. In one embodiment, dicing may be performed by cutting through the reconstructed wafer 200 between the first semiconductor devices 101 using a saw blade (not shown), thereby separating one first semiconductor device 101 (joined together with each second semiconductor device 303) from another first semiconductor device 101 (joined together with each second semiconductor device 303).

[0080] Figure 6 Another integrated fan-out process is shown using a second carrier substrate 601, a second adhesion layer 603, a polymer layer 605, a first redistribution layer 607, and a second integrated fan-out through-via (TIV) 609. In one embodiment, the second carrier substrate 601 includes, for example, a silicon-based material such as glass or silicon oxide, or other materials such as aluminum oxide, any combination of these materials, etc. The second carrier substrate 601 is flat to accommodate the attachment of devices such as the first semiconductor structure 500.

[0081] A second adhesive layer 603 may be placed over the second carrier substrate 601 to help attach the overlying structure to the second carrier substrate 601. In one embodiment, the second adhesive layer 603 is a die attach film (DAF). A lamination technique is used to apply a filler such as epoxy resin, phenolic resin, acrylic rubber, silica, or a combination thereof. However, any other suitable material and formation method may be used.

[0082] First, a polymer layer 605 is formed over the second adhesion layer 603. In one embodiment, the polymer layer 605 can be made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, ultra-low-k dielectrics such as porous carbon-doped silicon dioxide, combinations of these, etc. The polymer layer 605 can be formed by a process such as chemical vapor deposition (CVD), although any suitable process can be used, and the polymer layer 605 can have a thickness between about 0.5 μm and about 5 μm.

[0083] Once the polymer layer 605 is formed, an under bump metallization layer and a first redistribution layer 607 may be formed over the polymer layer 605. In one embodiment, the under bump metallization layer may include three layers of conductive material, such as a titanium layer, a copper layer, and a nickel layer. However, there are many suitable material arrangements and layer arrangements, such as an arrangement of chromium / chromium-copper alloy / copper / gold, an arrangement of titanium / titanium-tungsten / copper, or an arrangement of copper / nickel / gold suitable for forming an under bump metallization layer. Any suitable material or layer of material that may be used for the under bump metallization layer is fully intended to be included within the scope of the embodiments.

[0084] In one embodiment, the under bump metallization layer is formed by forming each layer located above the polymer layer 605. The formation of each layer can be performed using a plating process such as chemical plating, although other formation processes such as sputtering, evaporation, or PECVD processes can be optionally used depending on the desired material. The under bump metallization layer can be formed to have a thickness between about 0.7 μm and about 10 μm, such as about 5 μm.

[0085] In one embodiment, the first redistribution layer 607 includes a series of conductive layers embedded within a series of dielectric layers. In one embodiment, the first in the series of dielectric layers is formed over the polymer layer 605 and can be a material such as polybenzoxazole (PBO), although any suitable material such as polyimide or a polyimide derivative can be used. The first in the series of dielectric layers can be placed using, for example, a spin coating process, although any suitable method can be used.

[0086] After forming the first in the series of dielectric layers, an opening can be formed through the first in the series of dielectric layers by removing portions of the first in the series of dielectric layers. The opening can be formed using a suitable photolithographic mask and etching process, although any suitable process or processes that can be used to pattern the first in the series of dielectric layers can be used.

[0087] Once the first in the series of dielectric layers has been formed and patterned, the first in the series of conductive layers is formed over the first in the series of dielectric layers and through the opening formed in the first in the series of dielectric layers. In one embodiment, the first in the series of conductive layers may be formed by first forming a seed layer (not shown) of a titanium copper alloy by a suitable formation process such as CVD or sputtering. A photoresist (also not shown) may then be formed to cover the seed layer, and the photoresist may then be patterned to expose those portions of the seed layer that are located where the first in the series of conductive layers are desired to be positioned.

[0088] Once the photoresist has been formed and patterned, a conductive material such as copper can be formed on the seed layer by a deposition process such as plating. The conductive material can be formed to have a thickness between about 1 μm and about 10 μm, such as about 5 μm. However, although the materials and methods discussed are suitable for forming conductive materials, these materials are only exemplary. Any other suitable material (such as AlCu or Au) and any other suitable formation process (such as CVD or PVD) can be used to form the first in the conductive layer series. Once the conductive material is formed, the photoresist can be removed by a suitable removal process such as ashing. In addition, after removing the photoresist, those parts of the seed layer covered by the photoresist can be removed by, for example, a suitable etching process using a conductive material as a mask.

[0089] Once the first in the series of conductive layers is formed, the second in the series of dielectric layers and the second in the series of conductive layers may be formed by repeating steps similar to the first in the series of dielectric layers and the first in the series of conductive layers. These steps may be repeated as needed to electrically connect each in the series of conductive layers to the one below in the series of conductive layers, and may be repeated as many times as needed until the top in the series of conductive layers and the top in the series of dielectric layers are formed. In one embodiment, the series of conductive layers and the series of dielectric layers may continue to be deposited and patterned until the first redistribution layer 607 has a desired number of layers, although any suitable number of individual layers may be utilized.

[0090] Once the first redistribution layer 607 has been formed over the second carrier substrate 601, a second TIV 609 is formed that is electrically connected to the first redistribution layer 607. In one embodiment, the second TIV 609 may be formed by first forming a seed layer (not separately shown). In one embodiment, the seed layer is a thin layer of conductive material that facilitates the formation of thicker layers in subsequent process steps. The seed layer may include about thick titanium layer, followed by approx. The seed layer may be formed to have a thickness between about 0.3 μm and about 1 μm, such as about 0.5 μm.

[0091] Once the seed layer is formed, a photoresist (also not shown) is placed over the seed layer. In one embodiment, the photoresist can be placed on the seed layer to a height between about 50 μm and about 250 μm, such as about 120 μm, using, for example, a spin coating technique. Once in place, the photoresist can then be patterned by exposing the photoresist to a patterned energy source (e.g., a patterned light source) to cause a chemical reaction, thereby causing a physical change in those portions of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to selectively remove the exposed portion of the photoresist or the unexposed portion of the photoresist according to the desired pattern using the physical change. In one embodiment, the pattern formed in the photoresist is a pattern for a second TIV 609. The second TIV 609 is formed in such a position that it is positioned on different sides of a subsequently attached device. However, any suitable arrangement of the pattern for the second TIV 609 can be utilized.

[0092] In one embodiment, the second TIV 609 is formed in the photoresist from one or more conductive materials such as copper, tungsten, other conductive metals, etc., and can be formed, for example, by electroplating, chemical plating, etc. For example, an electroplating process is used in which the seed layer and the photoresist are immersed or dipped into a plating solution. The surface of the seed layer is electrically connected to the negative side of an external DC power supply so that the seed layer is used as a cathode in the electroplating process. A solid conductive anode (e.g., a copper anode) is also immersed in the solution and attached to the positive side of the power supply. Atoms from the anode dissolve into the solution, and the cathode (e.g., the seed layer) obtains the dissolved atoms from the solution, thereby plating the conductive areas exposed by the seed layer in the openings of the photoresist.

[0093] Once the second TIV 609 has been formed using the photoresist and seed layer, the photoresist can be removed using a suitable removal process. In one embodiment, the photoresist can be removed using a plasma ashing process, whereby the temperature of the photoresist can be increased until the photoresist undergoes thermal decomposition and can be removed. However, any other suitable process such as wet stripping can be used. Removal of the photoresist can expose the underlying portion of the seed layer.

[0094] Once exposed, the exposed portions of the seed layer can be removed. In one embodiment, the exposed portions of the seed layer (e.g., those portions not covered by the second TIV 609) can be removed by, for example, a wet etch or dry etch process. For example, in a dry etch process, the second TIV 609 can be used as a mask to direct reactants to the seed layer. In another embodiment, an etchant can be sprayed or otherwise contacted with the seed layer to remove the exposed portions of the seed layer. After etching away the exposed portions of the seed layer, portions of the first redistribution layer 607 are exposed between the second TIVs 609.

[0095] Once the second TIV 609 has been formed, the first semiconductor structure 500 may be placed on the first redistribution layer 607. In one embodiment, the first semiconductor structure 500 may be placed using, for example, a pick and place process. However, any other method of placing the first semiconductor structure 500 may be used.

[0096] Figure 6 As further shown, once the first semiconductor structure 500 has been placed, the first semiconductor structure 500 and the second TIV 609 can be sealed using a third sealant 611. In one embodiment, a sealant similar to that described above can be used. FIG. 2A to FIG. 2B The process of sealing the first semiconductor device 101 is described to seal the first semiconductor structure 500 and the second TIV 609. Once sealed, the first semiconductor structure 500 and the second TIV 609 and the third encapsulant 611 may be planarized to expose the first semiconductor structure 500 and the second TIV 609.

[0097] Figure 7 As shown, once the first semiconductor structure 500 and the second TIV 609 are sealed, a second redistribution layer 701 is formed to interconnect the first semiconductor structure 500 and the second TIV 609. In one embodiment, the first redistribution layer 607 (see above) may be formed similarly to the first redistribution layer 607. Figure 6 As described above, the second redistribution layer 701 is formed. For example, a passivation layer series and a conductive layer series are deposited and planarized to form one or more layers of conductive wiring. However, any suitable method and material may be used.

[0098] In certain embodiments, three conductive layers may be formed. However, the use of three conductive layers is exemplary only and not limiting. Rather, any suitable number of conductive layers and passivation layers may be used, and all such numbers of layers are fully intended to be included within the scope of the embodiments.

[0099] Figure 7 The formation of a third external connector 703 is further shown to electrically contact the second redistribution layer 701. In one embodiment, the third external connector 703 can be placed on the second redistribution layer 701 and can be a ball grid array (BGA) including a eutectic material (such as solder), although any suitable material can be used. Optionally, under-bump metallization can be used between the third external connector 703 and the second redistribution layer 701. In an embodiment where the third external connector 703 is a solder bump, the third external connector 703 can be formed using a ball drop method (such as a direct ball drop process). In another embodiment, the solder bump can be formed by first forming a tin layer by any suitable method such as evaporation, electroplating, printing, solder transfer, and then performing reflow to shape the material into a desired bump shape. Once the third external connector 703 is formed, testing can be performed to ensure that the structure is suitable for further processing.

[0100] Figure 7 Also shown is the debonding of the second carrier substrate 601 to the first semiconductor structure 500. In one embodiment, the third external connector 703, and therefore the structure including the first semiconductor structure 500, can be attached to the ring structure. The ring structure can be a metal ring intended to provide support and stability to the structure during and after the debonding process. In one embodiment, the third external connector 703 is attached to the ring structure using, for example, UV tape, although any other suitable adhesive or attachment can be used. Once attached, the second adhesive layer 603 can be irradiated, and the second adhesive layer 603 and the second carrier substrate 601 can be physically removed.

[0101] Once the second carrier substrate 601 has been removed and the polymer layer 605 has been exposed, the polymer layer 605 can be patterned using, for example, a laser drilling method by which a laser is directed toward those portions of the polymer layer 605 that are desired to be removed to expose the underlying first redistribution layer 607. During the laser drilling process, the drilling energy can be in the range of 0.1 mJ to about 60 mJ, and the drilling angle can be about 0 degrees to about 85 degrees from the normal to the polymer layer 605 (perpendicular to the polymer layer 605).

[0102] Figure 7 Additionally shown is the placement of a fourth external connector 707. In one embodiment, the fourth external connector 707 may be a contact bump (e.g., a microbump or a controlled collapse chip connection (C4) bump) and may include a material such as tin, or other suitable materials such as conventional solder, silver, or copper. In embodiments where the fourth external connector 707 is a tin solder bump, the fourth external connector 707 may be formed to a thickness of, for example, about 100 μm by first forming a tin layer by any suitable method such as evaporation, electroplating, printing, solder transfer, solder ball placement, etc. Once the tin layer has been formed on the structure, reflow is performed to shape the material into the desired bump shape.

[0103] Figure 7 Additionally shown is the bonding of the fourth external connector 707 to the first package 710. In one embodiment, the first package 710 may include a third substrate 709, a third semiconductor device 711, a fourth semiconductor device 713 (bonded to the third semiconductor device 711), a third contact pad 715 (for electrical connection to the fourth external connector 707), and a second encapsulant 717. In one embodiment, the third substrate 709 may be, for example, a packaging substrate including internal interconnects (e.g., through-substrate vias) to connect the third semiconductor device 711 and the fourth semiconductor device 713 to the fourth external connector 707.

[0104] In another embodiment, the third substrate 709 can be an interposer used as an intermediate substrate to connect the third semiconductor device 711 and the fourth semiconductor device 713 to the fourth external connector 707. In this embodiment, the third substrate 709 can be, for example, a doped or undoped silicon substrate or an active layer of a silicon-on-insulator (SOI) substrate. However, the third substrate 709 can also be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that can provide suitable protection and / or interconnection functions. These materials and any other suitable materials can be used for the third substrate 709.

[0105] The third semiconductor device 711 may be a semiconductor device designed for a specific purpose, such as a logic die, a central processing unit (CPU) die, a memory die (e.g., a DRAM die), a combination of these, etc. In one embodiment, the third semiconductor device 711 includes integrated circuit devices such as transistors, capacitors, inductors, resistors, a first metallization layer (not shown), etc., depending on the desire for a specific function. In one embodiment, the third semiconductor device 711 is designed and manufactured to work together or simultaneously with the first semiconductor structure 500.

[0106] The fourth semiconductor device 713 may be similar to the third semiconductor device 711. For example, the fourth semiconductor device 713 may be a semiconductor device designed for a specific purpose (e.g., a DRAM die) and include an integrated circuit device for a desired function. In one embodiment, the fourth semiconductor device 713 is designed to work together or simultaneously with the first semiconductor structure 500 and / or the third semiconductor device 711.

[0107] The fourth semiconductor device 713 may be bonded to the third semiconductor device 711. In one embodiment, the fourth semiconductor device 713 is only physically bonded to the third semiconductor device 711, such as by using an adhesive. In this embodiment, the fourth semiconductor device 713 and the third semiconductor device 711 may be electrically connected to the third substrate 709, for example, using wire bonds 719, but any suitable electrical bonding may be utilized.

[0108] In another embodiment, the fourth semiconductor device 713 may be physically and electrically bonded to the third semiconductor device 711. In this embodiment, the fourth semiconductor device 713 may include a fourth external connector (not shown). Figure 7 ), the fourth external connection and the fifth external connection on the third semiconductor device 711 (also not shown in Figure 7 ) are connected so that the fourth semiconductor device 713 is interconnected with the third semiconductor device 711.

[0109] A third contact pad 715 may be formed on the third substrate 709 to form an electrical connection between the third semiconductor device 711 and, for example, the fourth external connector 707. In one embodiment, the third contact pad 715 may be formed over an electrical wiring (e.g., a substrate through hole) within the third substrate 709 and in electrical contact with the electrical wiring. The third contact pad 715 may include aluminum, but other materials such as copper may also be used. A deposition process such as sputtering may be used to form a material layer (not shown) to form the third contact pad 715, and then a portion of the material layer may be removed by a suitable process (such as a photolithography mask and etching) to form the third contact pad 715. However, any other suitable process may be used to form the third contact pad 715. The third contact pad 715 may be formed to have a thickness between about 0.5 μm and about 4 μm, such as about 1.45 μm.

[0110] The second sealant 717 may be used to seal and protect the third semiconductor device 711, the fourth semiconductor device 713, and the third substrate 709. In one embodiment, the second sealant 717 may be a molding compound and may be placed using a molding device (not shown). Figure 7 ). For example, the third substrate 709, the third semiconductor device 711, and the fourth semiconductor device 713 can be placed in a cavity of a molding device, and the cavity can be hermetically sealed. The second sealant 717 can be placed in the cavity before the cavity is hermetically sealed, or can be injected into the cavity through an injection port. In one embodiment, the second sealant 717 can be a molding compound resin such as polyimide, PPS, PEEK, PES, a heat-resistant crystalline resin, a combination of these, and the like.

[0111] Once the second sealant 717 has been placed in the cavity so that the second sealant 717 seals the area around the third substrate 709, the third semiconductor device 711, and the fourth semiconductor device 713, the second sealant 717 can be cured to harden the second sealant 717 for optimal protection. Although the exact curing process depends at least in part on the specific material selected for the second sealant 717, in an embodiment where a molding compound is selected as the second sealant 717, curing can occur by a process such as heating the second sealant 717 to between about 100° C. and about 130° C. (such as about 125° C.) for about 60 seconds to about 3000 seconds (such as about 600 seconds). In addition, an initiator and / or catalyst can be included in the second sealant 717 to better control the curing process.

[0112] However, as will be appreciated by one of ordinary skill in the art, the above-described curing process is merely an exemplary process and is not meant to limit the current embodiments. Other curing processes may be used, such as radiation or even allowing the second sealant 717 to harden at ambient temperature. Any suitable curing process may be used, and all such processes are fully intended to be included within the scope of the embodiments discussed herein.

[0113] Once the fourth external connector 707 has been formed, the fourth external connector 707 is aligned with and placed in physical contact with the third contact pad 715, and bonding is performed. For example, in an embodiment where the fourth external connector 707 is a solder bump, the bonding process may include a reflow process whereby the temperature of the fourth external connector 707 is raised to a point where the fourth external connector 707 will liquefy and flow, thereby bonding the first package 710 to the fourth external connector 707 once the fourth external connector 707 resolidifies.

[0114] Figure 7 Also shown is an underfill material 721 placed between the first package 710 and the second redistribution layer 705. In one embodiment, the underfill material 721 is a protective material for cushioning and supporting the first package 710 from operational and environmental degradation (such as stress caused by heat generated during operation). The underfill material 721 may be injected or otherwise formed in the space between the first package 710 and the second redistribution layer 705, and may, for example, include a liquid epoxy resin that is dispensed between the first package 710 and the second redistribution layer 705 and then cured to harden.

[0115] Figure 7 Cutting is additionally shown. In one embodiment, cutting can be performed by cutting through the bottom fill material 721 and the third sealant 611 using a saw blade (not shown separately). However, as will be appreciated by those of ordinary skill in the art, cutting using a saw blade is merely an illustrative embodiment and is not intended to be limiting. Any method for performing cutting can be used, such as using one or more etchings. These methods and any other suitable method can be used to cut the structure.

[0116] By using the embodiments discussed herein, high performance and low cost structures can be manufactured. In particular, by integrating system-on-chip devices with wide I / O DRAM devices using, for example, hybrid bonding, the paths between devices are shortened, allowing for higher performance. Additionally, by using integrated fan-out technology, the structure can also incorporate other packages, allowing the device to better route desired functions (e.g., memory distribution) between different devices based on desired performance.

[0117] Figure 8Another embodiment is shown in which the second semiconductor device 303 is attached to the first semiconductor device 101 in a back-to-back configuration. In this embodiment, instead of bonding the second wafer bonding layer 311 and the second conductive wafer bonding material 313 to the first semiconductor device 101 (as described above with respect to Figure 4 ), but rather the TSV 309 and the passivation layer 315 are bonded to the first semiconductor device 101. In one embodiment, the TSV 309 and the passivation layer 315 may be bonded to the first semiconductor device 101 using, for example, a hybrid bonding process, as described above with respect to Figure 4 For example, the surfaces of the passivation layer 315 and the TSV 309 may be activated, the passivation layer 315 and the TSV 309 may be placed in physical contact with the first semiconductor device 101, and a thermal process may be performed. However, any suitable bonding process may be used.

[0118] Additionally, once the second semiconductor device 303 has been bonded in a back-to-back configuration, the Figures 4 to 7 The remaining processing steps are performed as described. In particular, a second sealant 401 (see, for example, Figure 4 ), forming a first external connector 413 (see, for example Figure 4 ), a first semiconductor structure 500 may be placed and sealed with a second TIV 609 (see, for example, Figure 6 ), and can be joined to the first package 710 (see, for example Figure 7 ). However, any suitable procedure may be used.

[0119] By using a back-to-face configuration or any suitable combination of a face-to-face configuration and a back-to-face configuration, the process window for manufacturing can be maintained. In particular, keeping the number of combinations as wide as possible allows designers to redesign the manufacturing process in an optimal way for yield, cost and time.

[0120] According to one embodiment, a semiconductor device includes: a first system-on-chip device bonded to a first memory device; a second system-on-chip device bonded to the first memory device; a first encapsulant surrounding the first system-on-chip device and the second system-on-chip device; a second encapsulant surrounding the first system-on-chip device, the second system-on-chip device, and the first memory device; and a through-hole extending from a first side of the second encapsulant to a second side of the first encapsulant, the through-hole being located outside the first encapsulant. In one embodiment, the semiconductor device also includes a first redistribution layer in physical contact with both the first system-on-chip device and the through-hole. In one embodiment, the semiconductor device also includes a second redistribution layer in physical contact with the through-hole, the second redistribution layer being on the opposite side of the first memory device from the first redistribution layer. In one embodiment, the first system-on-chip device is bonded to the first memory device using hybrid bonding. In one embodiment, the first system-on-chip device is bonded to the first memory device in a face-to-face configuration. In one embodiment, the first system-on-chip device is bonded to the first memory device in a face-to-face configuration. In one embodiment, the first encapsulant is a molding compound.

[0121] According to another embodiment, a semiconductor device includes: a first package electrically connected to a through-hole; a first redistribution layer electrically connected to the through-hole; a first system-on-chip device electrically connected to the first redistribution layer; a second system-on-chip device electrically connected to the first redistribution layer; a memory device bonded to the first system-on-chip device and the second system-on-chip device; a first encapsulant surrounding the first system-on-chip device and the second system-on-chip device; and a second encapsulant surrounding the through-hole, the first system-on-chip device, the second system-on-chip device, the memory device, and the first encapsulant. In one embodiment, the memory device is a wide I / O memory device. In one embodiment, the first system-on-chip device is a logic device. In one embodiment, the semiconductor device further includes a second interposer through-hole extending through the first encapsulant and in physical contact with the memory device. In one embodiment, the memory device is bonded to the first system-on-chip device in a face-to-face configuration. In one embodiment, the memory device is bonded to the first system-on-chip device in a face-to-face configuration. In one embodiment, the memory device is bonded to the first system-on-chip device using hybrid bonding.

[0122] In yet another embodiment, a method of manufacturing a semiconductor device includes: providing a memory device; bonding a first system-on-chip device to the memory device; bonding a second system-on-chip device to the memory device; sealing the first system-on-chip device and the second system-on-chip device with a first sealant; after sealing, bonding the first system-on-chip device and the second system-on-chip device to a redistribution layer, the redistribution layer being electrically connected to a through-hole; and sealing the through-hole, the first system-on-chip device, and the second system-on-chip device with a second sealant. In one embodiment, providing the memory device includes receiving the memory device from a manufacturer. In one embodiment, providing the memory device includes forming a reconstructed wafer. In one embodiment, bonding the first system-on-chip device includes hybrid bonding the first system-on-chip device to the memory device. In one embodiment, hybrid bonding includes: activating a surface of the first system-on-chip device; and physically contacting the surface of the first system-on-chip device with the memory device. In one embodiment, the first sealant is a dielectric material.

[0123] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: a first system-on-chip device bonded to a first memory device, wherein the first system-on-chip device comprises a first passivation layer; a second system-on-chip device bonded to the first memory device, wherein the second system-on-chip device comprises a second passivation layer; a first encapsulant surrounding the first system-on-chip device and the second system-on-chip device, wherein the first encapsulant has an outer surface coplanar with a sidewall of the first memory device, the outer surface being at a right angle to an interface between the first system-on-chip device and the first memory device, wherein the first passivation layer, the second passivation layer, the first memory device, and the first encapsulant share a plane; a second encapsulant surrounding the first system-on-chip device, the second system-on-chip device, and the first memory device; and a through hole extending from a first side of the second encapsulant to a second side of the second encapsulant, the through hole being located outside the first encapsulant, wherein the first system-on-chip device is bonded to the first memory device in a back-to-face configuration; and a first redistribution structure in physical contact with both the first system-on-chip device and the through-hole, the first redistribution structure comprising a first redistribution layer, a first external connector embedded in a third passivation layer, and a second redistribution layer, wherein the second redistribution layer extends into the second encapsulant and directly physically contacts the first system-on-chip device; a second redistribution structure in contact with both the semiconductor substrate of the first memory device and the through hole; A fourth external connector is in physical contact with the second redistribution structure and is located on opposite sides of the second redistribution structure from the first memory device and the through via.

2. The semiconductor device according to claim 1, wherein The second encapsulant includes a gap-fill dielectric material.

3. The semiconductor device according to claim 2, wherein: The second redistribution structure is on an opposite side of the first memory device from the first redistribution structure.

4. The semiconductor device according to claim 1, wherein: The first system on chip device is bonded to the first memory device using hybrid bonding.

5. The semiconductor device according to claim 4, wherein: The second encapsulant includes a molding compound.

6. The semiconductor device according to claim 4, wherein: The first system-on-chip device includes a through-via.

7. The semiconductor device according to claim 1, wherein The first encapsulant is a molding compound.

8. A semiconductor device comprising: a first package electrically connected to the through hole; a first redistribution layer electrically connected to the through hole; a first system-on-chip device electrically connected to the first redistribution layer, wherein the first system-on-chip device comprises a first through silicon via extending through a first passivation layer of the first system-on-chip device; a second system-on-chip device electrically connected to the first redistribution layer; a memory device coupled to the first system-on-chip device and the second system-on-chip device; an external connector located in the second passivation layer, the external connector connecting the first redistribution layer to the first system-on-chip device; a first encapsulant surrounding the first system-on-chip device and the second system-on-chip device, wherein the second passivation layer, the first encapsulant, and the memory device are coplanar with each other; and a second through-interposer via extending through the first encapsulant and physically contacting the memory device, wherein the first through-silicon via, the second through-interposer via, the first passivation layer, and the first encapsulant share a plane; A second sealant surrounds the through hole, the first system-on-chip device, the second system-on-chip device, the memory device, and the first sealant.

9. The semiconductor device according to claim 8, wherein: The memory device is a wide I / O memory device.

10. The semiconductor device according to claim 9, wherein The first system-on-chip device is a logic device.

11. The semiconductor device according to claim 8, further comprising: The first passivation layer includes a polymer of polybenzoxazole.

12. The semiconductor device according to claim 8, wherein The memory device is bonded to the first system-on-chip device in a face-to-face configuration.

13. The semiconductor device according to claim 8, wherein: The memory device is bonded to the first system-on-chip device in a face-to-face configuration.

14. The semiconductor device according to claim 8, wherein: The memory device is bonded to the first system-on-chip device using hybrid bonding.

15. A method for manufacturing a semiconductor device, the method comprising: Providing memory devices; bonding a first system-on-chip device to the memory device; bonding a second system-on-chip device to the memory device; sealing the first system-on-chip device and the second system-on-chip device with a first sealant; After the sealing, bonding the first system-on-chip device and the second system-on-chip device to a redistribution layer, the redistribution layer being electrically connected to the through vias; as well as sealing the through hole, the first system-on-chip device and the second system-on-chip device with a second sealant, The method further comprises forming an external connector in the passivation layer to connect the redistribution layer to the first system-on-chip device, wherein the passivation layer, the first sealant, and the memory device are coplanar with each other, The first system-on-chip device comprises a first through-silicon via, wherein the first through-silicon via extends through a first passivation layer of the first system-on-chip device, The method further includes forming a second interposer through-hole extending through the first sealant and physically contacting the memory device, wherein the first through-silicon via, the second interposer through-hole, the first passivation layer and the first sealant share a plane.

16. The method according to claim 15, wherein: Providing the memory device includes receiving the memory device from a manufacturer.

17. The method according to claim 15, wherein: Providing the memory device includes forming a reconstituted wafer.

18. The method according to claim 15, wherein: Bonding the first system-on-chip device includes hybrid bonding the first system-on-chip device to the memory device.

19. The method according to claim 18, wherein: The hybrid joining comprises: activating a surface of the first system-on-chip device; and The surface of the first system-on-chip device is brought into physical contact with the memory device.

20. The method according to claim 15, wherein: The first encapsulant is a dielectric material.

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