Fingerprint sensor and display device comprising the same

Abstract

The present application relates to a fingerprint sensor and a display device. The fingerprint sensor and the display device include a substrate. A circuit element layer is disposed on a first surface of the substrate and includes a semiconductor layer, a conductive layer, and at least one opening portion. A light emitting element layer is disposed on the circuit element layer and includes at least one light emitting element. A sensor layer is disposed on a second surface of the substrate and includes at least one light sensor corresponding to the opening portion. The opening portion is defined not to overlap the semiconductor layer and the conductive layer, the opening portion has a closed loop shape in a plan view, and at least a portion of the closed loop shape includes a curve, or an inner angle of at least a portion of the closed loop shape is an obtuse angle.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0119017, filed on September 26, 2019, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary embodiments of the present invention generally relate to fingerprint sensors and display devices including the fingerprint sensors. Background Technology

[0004] In recent years, with the widespread use of display devices such as smartphones and tablet PCs, biometric authentication methods using user fingerprints have become widely adopted. To provide fingerprint sensing functionality, fingerprint sensors can be embedded in or attached to display devices.

[0005] For example, a fingerprint sensor can be configured with a sensor that uses a light-sensing method. A fingerprint sensor using a light-sensing method may include a light source, a lens, and a light sensor array. When such a fingerprint sensor is attached to a display panel, the thickness of the display device may increase, and manufacturing costs may also increase.

[0006] The information disclosed in this background section is only for understanding the background technology of the inventive concept, and therefore may include information that does not constitute prior art. Summary of the Invention

[0007] The device constructed according to an exemplary embodiment of the present invention can provide a fingerprint sensor using a photosensitive method and a display device including the fingerprint sensor, wherein the fingerprint sensor can reduce the thickness of the module and improve reliability.

[0008] Furthermore, the device constructed according to an exemplary embodiment of the present invention can provide a fingerprint sensor and a display device including the fingerprint sensor, which can minimize incident light diffraction at the edge of an opening portion configured to control incident light in a display panel.

[0009] Other features of the inventive concept will be set forth in the following description and will be apparent in part from the description, or may be learned by practice of the inventive concept.

[0010] A fingerprint sensor according to one or more exemplary embodiments of the present invention includes a substrate; a circuit element layer disposed on a first surface of the substrate and including a semiconductor layer, a conductive layer, and at least one opening; a light-emitting element layer disposed on the circuit element layer and including at least one light-emitting element; and a sensor layer disposed on a second surface of the substrate and including at least one photosensor corresponding to the opening. The opening is defined not to overlap with the semiconductor layer and the conductive layer, the opening has a closed-loop shape in a plan view, and at least a portion of the closed-loop shape includes a curve, or at least a portion of the closed-loop shape has an obtuse angle at its interior angle.

[0011] According to an embodiment, the conductive layer may include: a first conductive layer including a first electrode extending in a first direction; a second conductive layer disposed on the first conductive layer and including a second electrode extending in the first direction; and a third conductive layer disposed on the second conductive layer and including a third electrode extending in a second direction perpendicular to the first direction, and the opening portion may be positioned between the first electrodes, between the second electrodes, and between the third electrodes in a plan view.

[0012] According to an embodiment, the first electrode may include a first wiring extending in a first direction, the second electrode may include a second wiring spaced apart from the first wiring in a plan view and extending in the first direction, and the third electrode may include a third wiring extending in a second direction perpendicular to the first direction and a bridging pattern spaced apart from the third wiring, and the opening may be defined by a portion of the first wiring, a portion of the second wiring, a portion of the third wiring and a portion of the bridging pattern.

[0013] According to an embodiment, the third wiring may include at least two first protrusions projecting toward the bridging pattern in a plan view, and at least a portion of the closed-loop shape may be defined by the at least two first protrusions.

[0014] According to the implementation method, the first protruding portion may overlap with the first wiring and the second wiring portion respectively.

[0015] According to the implementation, the interior angles of the closed-loop shape corresponding to each of the first protruding portions can be obtuse angles.

[0016] According to the implementation, one side of each of the first protrusions may extend in a direction intersecting each of the first and second directions.

[0017] According to an embodiment, at least one of the first protruding portions may have a trapezoidal planar shape.

[0018] According to an embodiment, the second wiring may include at least one second protrusion protruding toward the first wiring in a plan view, the second protrusion may not overlap with the third wiring, and the first and second protrusions may correspond to at least a portion of a closed-loop shape.

[0019] According to an embodiment, the bridging pattern may include at least one third protrusion protruding toward the third wiring in a plan view, the third protrusion may overlap with the first wiring, and the first to third protrusions may correspond to at least a portion of a closed-loop shape.

[0020] According to the implementation method, the opening portion may have an octagonal planar shape.

[0021] According to an embodiment, the first wiring may include at least one fourth protrusion protruding in a second direction, and the fourth protrusion may include a curved portion corresponding to a curve of a closed loop shape.

[0022] According to an embodiment, the second wiring may include a fifth protruding portion that protrudes in a direction opposite to the second direction, and the fifth protruding portion may include a curved portion facing the fourth protruding portion and corresponding to the curve of the closed-loop shape.

[0023] According to the implementation, the opening portion may have a circular or elliptical planar shape.

[0024] According to an embodiment, the third wiring may include at least two groove portions, which may overlap with the first wiring and the second wiring portions respectively, and the inner angle of the closed loop shape corresponding to the groove portion is an acute angle.

[0025] According to the implementation method, the second wiring may not overlap with the bridging pattern.

[0026] According to an embodiment, the semiconductor layer may include an active pattern, the active pattern including each of a source electrode and a drain electrode, and the opening may also be defined by a portion of the active pattern.

[0027] To achieve the objectives of this invention, a display device according to an embodiment includes: a substrate on which pixels are disposed; a circuit element layer disposed on a first surface of the substrate and including a conductive layer, wherein circuit elements of the pixels are disposed in the conductive layer; a light-emitting element layer disposed on the circuit element layer and including at least one light-emitting element configured with the pixels; and a sensor layer disposed on a second surface of the substrate and including at least one photosensor. At least one opening portion having a closed-loop shape in a plan view may be defined to not overlap with the conductive layer, and at least a portion of the closed-loop shape may include a curve, or the interior angle of at least a portion of the closed-loop shape may be an obtuse angle.

[0028] According to an embodiment, the conductive layer may include: a first conductive layer including light-emitting control lines extending in a first direction; a second conductive layer disposed on the first conductive layer, spaced apart from the light-emitting control lines in a plan view by a predetermined distance, and including initialization electric field lines extending in the first direction; and a third conductive layer disposed on the second conductive layer, and including electric field lines extending in a second direction perpendicular to the first direction and bridging patterns spaced apart from the electric field lines, and the opening portion may be defined by a portion of the light-emitting control lines, a portion of the initialization electric field lines, a portion of the electric field lines, and a portion of the bridging patterns.

[0029] According to an embodiment, the initial power line may include at least one second protrusion protruding toward the light-emitting control line in a plan view, the power line may include at least two first protrusions protruding toward the bridging pattern in a plan view, the bridging pattern may include at least one third protrusion protruding toward the power line in a plan view, and the first to third protrusions may be configured with at least a portion of a closed-loop shape.

[0030] According to an exemplary embodiment of the present invention, a fingerprint sensor and a display device including the fingerprint sensor can reduce the module thickness of the display device by integrally forming a light-transmitting area with the circuit element layer in the fingerprint sensor for the light-sensing method.

[0031] Furthermore, the fingerprint sensor and the display device including the fingerprint sensor according to the exemplary embodiments of the present invention can prevent or reduce light diffraction that may occur in the light-transmitting areas formed in the circuit element layer.

[0032] It should be understood that both the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0033] The accompanying drawings illustrate exemplary embodiments of the invention and, together with the specification, serve to explain the inventive concept. The drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification.

[0034] Figure 1 and Figure 2 This is a schematic plan view of a display device according to an exemplary embodiment of the concept of the present invention.

[0035] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E This is a plan view showing various implementations of the arrangement structure of pixels and light sensors.

[0036] Figure 4A This is a cross-sectional view of a display device according to an exemplary embodiment of the present invention.

[0037] Figure 4B This is a cross-sectional view of a display device according to another embodiment of the concept of the present invention.

[0038] Figure 5 This is a plan view illustrating an exemplary embodiment of a light-blocking layer according to a concept of the present invention.

[0039] Figure 6A , Figure 6B , Figure 6C and Figure 6D It is a plan view showing various implementations of the arrangement structure of pixels, pinholes, and light sensors.

[0040] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12A , Figure 12B and Figure 12C This is a cross-sectional view of a display device according to other embodiments of the present invention.

[0041] Figure 13 This is a circuit diagram illustrating a pixel according to an exemplary embodiment of the concept according to the present invention.

[0042] Figure 14 This is a circuit diagram illustrating a pixel according to another embodiment of the concept according to the present invention.

[0043] Figure 15 It is shown Figure 14 A plan view of an implementation of the pixel layout shown.

[0044] Figure 16 It is along Figure 15 A sectional view taken from line I-I'.

[0045] Figure 17 It is along Figure 15 The sectional view taken from line II-II'.

[0046] Figure 18 It shows the basis Figure 15 A plan view of the light-blocking layer in the embodiment.

[0047] Figure 19 It is shown Figure 14 A plan view of another embodiment of the pixel layout shown.

[0048] Figure 20 It shows the basis Figure 19 A plan view of the light-blocking layer in the embodiment.

[0049] Figure 21 It is shown Figure 14 A plan view of another embodiment of the pixel layout shown. Detailed Implementation

[0050] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, “implementation” and “method” are interchangeable terms and are non-limiting examples of apparatus or methods employing one or more of the inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, a particular shape, configuration, and characteristic of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0051] Unless otherwise stated, the exemplary embodiments described are to be understood as exemplary features providing details of variations in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects (hereinafter individually or collectively referred to as “elements”) of various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0052] The use of crosshairs and / or shading in the accompanying drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, scale, commonalities between the elements shown, and / or any other characteristics, properties, or characteristics of the elements. Furthermore, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a particular process sequence may be performed differently than the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Additionally, the same reference numerals denote the same elements.

[0053] When a component or layer is referred to as being "on," "connected to," or "attached to" another component or layer, it can be directly on, directly connected to, or directly attached to the other component or layer, or there can be an intermediate component or layer. However, when a component or layer is referred to as being "directly on," "directly connected to," or "directly attached to" another component or layer, there is no intermediate component or layer. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without an intermediate component. Furthermore, the D1, D2, and D3 axes are not limited to the three axes of a Cartesian coordinate system, such as the x, y, and z axes, and can be interpreted in a broader sense. For example, the D1, D2, and D3 axes can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0054] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0055] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” “side” (e.g., as in “sidewall”), etc., may be used herein to describe the relationship between one element and another element (or multiple elements) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will consequently be oriented “above” other elements or features. Thus, the exemplary term “below” can encompass both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0056] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. Furthermore, when used in this specification, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the described features, integrals, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and are therefore used to allow for inherent deviations in measurements, calculated values, and / or provided values ​​that will be recognized by those skilled in the art.

[0057] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of idealized exemplary embodiments and / or intermediate structures. Therefore, variations in the illustrated shapes should be expected, for example, due to manufacturing techniques and / or tolerances. Consequently, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the specific shapes of the regions shown, but should include, for example, deviations in shape due to manufacturing processes. In this way, the regions shown in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the areas of the device, and are therefore not necessarily intended to be limiting.

[0058] As is customary in the art, exemplary embodiments are described and illustrated in the accompanying drawings for functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electrical circuits (or optical circuits) such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connectors, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and optionally driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmable microprocessors and associated circuitry) for performing other functions. Furthermore, without departing from the scope of the inventive concept, each block, unit, and / or module in some exemplary embodiments may be physically separated into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the inventive concept, some exemplary embodiments of blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules.

[0059] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms, such as those defined in common dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0060] Figure 1 and Figure 2 This is a schematic diagram illustrating a display device according to an exemplary embodiment of the concept of the present invention. More specifically, Figure 1 and Figure 2 This is a schematic diagram illustrating a display panel included in an exemplary embodiment of a display device according to a concept of the present invention, and a driving circuit for driving the display panel. For convenience, in Figure 1 and Figure 2 In this invention, the display panel and the driving circuit are separate from each other, but the concept of the invention is not limited to this. More specifically, all or part of the driving circuit can be implemented integrally on the display panel.

[0061] refer to Figure 1 and Figure 2 The display device 10 includes a display panel 110 and a driving circuit 200 for driving the display panel 110.

[0062] Display panel 110 includes a display area AA and a non-display area NA. The display area AA is an area in which a plurality of pixels PXL (which may be referred to as subpixels) are disposed, and may be referred to as the effective area. In various embodiments, each of the pixels PXL may include at least one light-emitting element. Display device 10 displays an image in display area AA by driving the pixels PXL in correspondence with externally input image data.

[0063] In various implementations, the display area AA may include a sensing area SA. The sensing area SA may include at least some of the pixels PXL disposed in the display area AA.

[0064] In the implementation method, such as Figure 1 As shown, at least a portion of the display area AA can be set as the sensing area SA. In another example, as... Figure 2 As shown, the entire display area AA can be set as the sensing area SA.

[0065] At the same time, despite Figure 1 An example is shown in which only one sensing area SA is formed in the display area AA, but the inventive concept is not limited thereto. That is, in various embodiments, multiple sensing areas SA arranged regularly or irregularly can be formed in the display area AA. In such embodiments, the multiple sensing areas SA can have the same or different areas and shapes.

[0066] Furthermore, despite Figure 1 An example is shown in which a sensing region SA is formed in at least a portion of a display area AA, but the inventive concept is not limited thereto. That is, in various embodiments, the display area AA and the sensing region SA can be configured such that only at least a portion of the display area AA and the sensing region SA overlap.

[0067] The non-display area NA is the area surrounding the display area AA and can be referred to as an inactive area. In various embodiments, the non-display area NA can generally mean the area on the display panel 110 other than the display area AA. In embodiments, the non-display area NA may include wiring areas, pad areas, various dummy areas, etc.

[0068] In various embodiments, the display device 10 may further include a plurality of light sensors PHS disposed in the sensing area SA. In embodiments, the light sensors PHS can sense light emitted from a light source and reflected by a user's finger and analyze the reflected light to sense the user's fingerprint. Hereinafter, the inventive concept will be described using an example in which the light sensors PHS are used for fingerprint sensing purposes, but in various embodiments, the light sensors PHS can be used for purposes such as performing various functions of a touch sensor or scanner.

[0069] In various embodiments, the light sensor PHS can be disposed within the sensing region SA. In this case, the light sensor PHS can overlap with at least a portion or all of the pixel PXL disposed within the sensing region SA, or it can be disposed around the pixel PXL. For example, at least some or all of the light sensor PHS can be disposed between the pixels PXL. (See reference...) Figures 3A to 3E Various implementations of the setup relationship between the light sensor PHS and the pixel PXL are described in more detail.

[0070] In an embodiment where the optical sensor PHS is positioned adjacent to the pixel PXL, the optical sensor PHS can use a light-emitting element disposed in at least one pixel PXL as a light source, said at least one pixel PXL being disposed at or around the sensing region SA. In such an embodiment, the optical sensor PHS can be configured together with the pixel PXL (specifically, the light-emitting element disposed in the pixel PXL) of the sensing region SA to form a fingerprint sensor for the optical sensing method. As described above, when a fingerprint sensor-integrated display device is configured by using the pixel PXL as a light source instead of a separate external light source, the module thickness of the fingerprint sensor for the optical sensing method and the display device including the fingerprint sensor can be reduced, and manufacturing costs can be lowered.

[0071] In various embodiments, the light sensor PHS can be disposed on the rear surface (e.g., the back surface) of the display panel 110 opposite the surface displaying the image (e.g., the front surface). However, the inventive concept is not limited thereto.

[0072] The driving circuit 200 can drive the display panel 110. For example, the driving circuit 200 can output a data signal corresponding to image data to the display panel 110, or it can output a driving signal for the light sensor PHS and receive a sensing signal received from the light sensor PHS. The driving circuit 200 that receives the sensing signal can use the sensing signal to detect the user's fingerprint pattern.

[0073] In various embodiments, the driving circuit 200 may include a panel driver 210 and a fingerprint detector 220. For convenience, in Figure 1 and Figure 2In this embodiment, the panel driver 210 and the fingerprint detector 220 are separate from each other, but the inventive concept is not limited thereto. For example, at least a portion of the fingerprint detector 220 may be integrated with the panel driver 210, or may operate in conjunction with the panel driver 210.

[0074] The panel driver 210 can sequentially provide data signals corresponding to image data to the pixels PXL while sequentially scanning the pixels PXL of the display area AA. Then, the display panel 110 can display the image corresponding to the image data.

[0075] In one embodiment, the panel driver 210 may provide a driving signal for fingerprint sensing to the pixel PXL. The driving signal may be provided to cause the pixel PXL to emit light and operate as a light source for the light sensor PHS. In such an embodiment, the driving signal for fingerprint sensing may be provided to the pixel PXL located in a specific area within the display panel 110, for example, to the pixel PXL located in the sensing area SA. In various embodiments, the driving signal for fingerprint sensing may be provided by the fingerprint detector 220.

[0076] The fingerprint detector 220 can transmit a drive signal for driving the optical sensor PHS to the optical sensor PHS, and can detect the user's fingerprint based on the sensing signal received from the optical sensor PHS.

[0077] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E This is a plan view showing various implementations of the arrangement structure of pixels and light sensors. Figures 3A to 3E Different implementations are shown relating to the relative size, resolution, and arrangement of at least one pixel PXL disposed in the sensing area SA and the light sensor PHS.

[0078] refer to Figure 3A In the sensing area SA, the light sensors PHS can be arranged at the same resolution (density) as the pixels PXL. In other words, the same number of light sensors PHS as pixels PXL can be arranged in the sensing area SA. In such an implementation, the pixels PXL and light sensors PHS can be arranged to form a 1:1 pair. Figure 3A In one implementation, the pixel PXL and the light sensor PHS are configured to overlap each other, but in other implementations, the pixel PXL and the light sensor PHS may be configured not to overlap each other, or only a portion of the pixel PXL and the light sensor PHS may overlap each other.

[0079] At the same time, Figure 3AIn one embodiment, the size of the light sensor PHS is smaller than the size of the pixel PXL, but the inventive concept is not limited thereto. That is, in other embodiments, the light sensor PHS may have the same size as the pixel PXL, or it may have a larger size than the pixel PXL. Figure 3E This implementation is illustrated in the figure.

[0080] refer to Figures 3B to 3E The light sensor PHS can be set at a lower resolution than the pixel PXL in the sensing area SA. In other words, a light sensor PHS with a number of pixels less than the number of pixels PXL can be set in the sensing area SA. Figures 3B to 3E The example shown is an example of setting one light sensor PHS for every four pixels PXL, but the inventive concept is not limited thereto.

[0081] In such an implementation, the optical sensor PHS can have, for example... Figure 3B and Figure 3E The pixel PXL shown has a smaller size, or may have, for example... Figure 3C and Figure 3D The pixel PXL shown is a larger size.

[0082] When the light sensor PHS is set at a resolution lower than that of the pixel PXL, part or all of the light sensor PHS can be set to overlap with the pixel PXL. That is, as Figure 3B and Figure 3C As shown, the light sensor PHS can partially overlap with at least a portion of the pixel PXL.

[0083] Alternatively, such as Figure 3D As shown, the light sensor PHS can be positioned between pixels PXL and partially overlap with pixels PXL. In such an implementation, as... Figure 3D As shown, the light sensor PHS can have a size larger than the size of the pixel PXL. For example, the light sensor PHS can have a size that covers at least one pixel PXL.

[0084] Alternatively, such as Figure 3E As shown, the light sensor PHS may not overlap with the pixel PXL.

[0085] In various embodiments, the arrangement structure between the pixel PXL and the light sensor PHS is not limited to the structure described above. That is, within the scope of this invention, various modifications can be made to the shape, arrangement, relative size, number, resolution, etc., of the pixel PXL and the light sensor PHS in the sensing area SA. Furthermore, in various embodiments, the pixel PXL and the light sensor PHS can be combined... Figures 3A to 3EOne or more of the forms configured in the implementation methods.

[0086] also, Figures 3A to 3E The illustration shows that the optical sensor PHS is regularly arranged in the sensing area SA, but the inventive concept is not limited thereto, and in other embodiments, the optical sensor PHS may be irregularly arranged in the sensing area SA.

[0087] Figure 4A This is a cross-sectional view of a display device according to an exemplary embodiment of the present invention. For example... Figure 4A As shown, the display panel 110 may include a first substrate SUB1 and a circuit element layer BPL, a light-emitting element layer LDL, a first protective layer PTL1, a first adhesive layer ADL1, and a window WIN, which are sequentially disposed on one surface (e.g., the upper surface) of the first substrate SUB1. Furthermore, the display device 10 may include a second adhesive layer ADL2 and a second protective layer PTL2 sequentially disposed on another surface (e.g., the lower surface) of the first substrate SUB1.

[0088] The first substrate SUB1 can be a substantially transparent transmissive substrate that serves as the base substrate of the display panel 110. The first substrate SUB1 can be a rigid substrate comprising glass or tempered glass, or a flexible substrate of plastic material. However, the material of the first substrate SUB1 is not limited to these, and the first substrate SUB1 can be configured from various materials.

[0089] like Figure 1 and Figure 2 As shown, the first substrate SUB1 may include a display area AA and a non-display area NA. Furthermore, the display area AA may include multiple pixel areas PXA, with each pixel PXL set and / or formed in the pixel areas PXA.

[0090] The circuit element layer BPL may be disposed on one surface of the first substrate SUB1 and include at least one conductive layer. For example, the circuit element layer BPL may include multiple circuit elements configuring pixel circuitry for pixel PXL, as well as lines for providing various powers and signals to drive pixel PXL. In this case, the circuit element layer BPL may include various circuit elements such as at least one transistor and a capacitor, and multiple conductive layers for configuring lines connected to the various circuit elements. Furthermore, the circuit element layer BPL may include at least one insulating layer disposed between the multiple conductive layers. Additionally, the circuit element layer BPL may include wiring portions disposed in the non-display area NA of the first substrate SUB1 to provide powers and signals corresponding to the lines connected to pixel PXL.

[0091] The light-emitting element layer (LDL) can be disposed on one surface of the circuit element layer (BPL). The LDL may include multiple light-emitting elements (LDs) connected to the circuit element layer (BPL) via contact holes or the like. In one embodiment, at least one of the multiple light-emitting elements (LDs) may be disposed in each pixel region (PXA).

[0092] Each pixel PXL may include a circuit element disposed in the circuit element layer BPL and at least one light-emitting element LD disposed in the light-emitting element layer LDL above the circuit element layer BPL. A detailed description of the structure of pixel PXL will be given later.

[0093] The first protective layer PTL1 can be disposed above the light-emitting element layer LDL to cover the display area AA. The first protective layer PTL1 may include sealing components, such as thin-film encapsulation (TFE) or sealing substrate, and may also include a protective film in addition to sealing components.

[0094] A first adhesive layer ADL1 is disposed between a first protective layer PTL1 and a window WIN to connect the first protective layer PTL1 and the window WIN. The first adhesive layer ADL1 may include a transparent adhesive, such as an optically clear adhesive (OCA), and may include various adhesive materials.

[0095] A window (WIN) is a protective member disposed at the uppermost end of a module of a display device 10 including a display panel 110, and can be a substantially transparent transmissive substrate. The window (WIN) can have a multilayer structure selected from glass substrates, plastic films, and plastic substrates. The window (WIN) can include rigid or flexible substrates, and the materials used to configure the window (WIN) are not particularly limited.

[0096] In various embodiments, the display device 10 may also include a polarizer, a touch sensor layer (touch electrode layer), etc. (not shown). For example, the display device 10 may also include a polarizer and / or a touch sensor layer disposed between the first protective layer PTL1 and the window WIN.

[0097] The second protective layer PTL2 can be disposed on the other surface of the first substrate SUB1. The second protective layer PTL2 can be attached to the first substrate SUB1 via the second adhesive layer ADL2.

[0098] The second adhesive layer ADL2 can firmly bond (or attach) the first substrate SUB1 and the second protective layer PTL2. The second adhesive layer ADL2 may include a transparent adhesive, such as OCA. The second adhesive layer ADL2 may include a pressure-sensitive adhesive (PSA), which acts as an adhesive when pressure is applied to bond to the bonding surface. When the second adhesive layer ADL2 includes a PSA, it can adhere to the bonding surface solely by pressure without requiring additional heat treatment or UV treatment at room temperature.

[0099] In an exemplary embodiment, the second adhesive layer ADL2 may include a material that absorbs specific light, or it may include a material that blocks specific light. For example, the second adhesive layer ADL2 may include an infrared light absorbing material that absorbs infrared light with high energy density, or it may include an infrared light blocking material that blocks infrared light.

[0100] Infrared light absorbing materials may include, for example, inorganic oxides and metals. Inorganic oxides include antimony tin oxide (ATO), indium tin oxide (ITO), tungsten oxide, carbon black, etc., while metals may include, for example, Ag. In the case of inorganic oxides, the infrared light absorbing material can selectively transmit light in the visible light region and absorb infrared light. Furthermore, infrared light absorbing materials may include, for example, organic dyes. Organic dyes may be, for example, dyes used in color filters (not shown) included in the display panel 110.

[0101] For example, infrared light blocking materials can be selected from mixtures of borates, mixtures of carbonates, mixtures of alumina, mixtures of nitrates, mixtures of nitrites, lithium borate and sodium borate, potassium borate, magnesium borate, calcium borate, strontium borate, barium borate, sodium borate, and Na₂B₄O₂. X The infrared light blocking material may be at least one selected from the group consisting of borosilicate, lithium carbonate, sodium carbonate, potassium carbonate, calcium carbonate, calcite, CaCO3, dolomite, and magnesite. Furthermore, the infrared light blocking material may be at least one selected from the group consisting of nickel dithiol-based materials, dithiol-based metal complexes, anthocyanin-based materials, squalium-based materials, ketone acid-based materials, diimine-based materials, imine-based materials, ammonium-based materials, phthalocyanine-based materials, phthalocyanine-based materials, naphthalene phthalocyanine-based materials, anthraquinone-based materials, naphthoquinone-based materials, polymer condensation azopyrrole, polymethyl-based materials, and propylene-based materials.

[0102] When a user's finger is placed (or positioned) on the display surface of the display device 10 (e.g., a surface on which an image is displayed), the display device 10 can perform the function of sensing the user's fingerprint via the optical sensor PHS, which will be described later. When external light is input to the display device 10 simultaneously with the sensing of the user's fingerprint, the external light in the visible light region is blocked by the user's hand, but infrared light can pass through the user's hand and can be incident on the optical sensor PHS. The infrared light incident on the optical sensor PHS acts as noise, thereby reducing the accuracy of the recognition of light reflected from the user's hand.

[0103] When the second adhesive layer ADL2 includes an infrared light absorbing material and / or an infrared light blocking material as described in the above embodiments, even if infrared light from external light passes through the user's hand, the infrared light is absorbed and / or blocked by the second adhesive layer ADL2, and therefore the infrared light cannot be incident on the optical sensor PHS. Thus, fingerprint recognition accuracy can be improved.

[0104] The second protective layer PTL2 can prevent oxygen, moisture, etc. from flowing in from the outside, and can be configured as a single layer or multiple layers. The second protective layer PTL2 can be configured as a thin film to further ensure the flexibility of the display panel 110. The second protective layer PTL2 can be attached to the sensor layer PSL by another adhesive layer (not shown) including a transparent adhesive such as OCA.

[0105] In various embodiments, a selective light blocking film may also be provided below the second protective layer PTL2. The selective light blocking film can prevent unwanted light from entering the photosensor PHS of the sensor layer PSL by blocking external light (e.g., infrared light) entering a specific frequency region in the display device 10. In the above description, a selective light blocking film is further provided below the second protective layer PTL2, but the inventive concept is not limited thereto. That is, in another embodiment, when the selective light blocking film is provided above the sensor layer PSL, the selective light blocking film can be provided on any layer of the display device 10. Furthermore, when an infrared light blocking component is included in the display panel 110, the selective light blocking film can be omitted.

[0106] A light-blocking layer (PHL) can be disposed between the light-emitting element layer (LDL) and the sensor layer (PSL), which will be described later. For example, as... Figure 4A As shown, a light-blocking layer PHL can be disposed between the first substrate SUB1 and the circuit element layer BPL. The light-blocking layer PHL may include multiple pinholes PIH.

[0107] The display panel 110 can be formed to be transparent in the area where pinhole PIHs are provided, so that reflected light from the fingerprint area of ​​the finger can be transmitted through each pinhole PIH. In addition, in order to reduce the loss of reflected light required for fingerprint sensing, the display panel 110 can be configured such that light satisfying a predetermined viewing angle range (field of view (FOV), or "viewing angle") can be transmitted through each pinhole PIH.

[0108] For example, the display panel 110 may be formed as transparent in an area having an area larger than and overlapping with the pinhole PIH, which is centered in the area where each pinhole PIH is provided. Hereinafter, the area formed as transparent so that reflected light can be transmitted will be referred to as the optical opening area (OPA).

[0109] Based on the center of each pinhole PIH, when the desired field of view is θ, the thickness of the circuit element layer BPL is q, and the width of the optical opening region OPA formed at the boundary surface of the circuit element layer BPL and the light-emitting element layer LDL is 2p, the condition "2p=2×(q×tanθ)" can be satisfied. In the implementation, the field of view can be an angle ranging from about 30 degrees to 60 degrees, for example, 45 degrees, but is not limited to this.

[0110] The pinhole PIH can have a width w within a predetermined width range, for example, from 5 μm to 20 μm, and the width of the optical opening region OPA, taking this into account, can be 2p+w. In this way, the width of the optical opening region OPA, which should be ensured in each layer of the display device 10, can gradually increase with the increase of the distance from the light blocking layer PHL (i.e., with each increase of the distance from the upper and lower parts of the light blocking layer PHL).

[0111] The width w (or diameter) of the pinhole PIH can be set to approximately 10 times or more the wavelength of the reflected light, for example, approximately 4 μm or 5 μm or more, to prevent or reduce light diffraction. Furthermore, the width w of the pinhole PIH can be set to a size sufficient to prevent or reduce image blurring and to more clearly sense the shape of the fingerprint. For example, the width w of the pinhole PIH can be set to approximately 20 μm or less. However, the inventive concept is not limited thereto, and the width w of the pinhole PIH can be varied according to the wavelength band of the reflected light and / or the thickness of each layer of the module.

[0112] The distance (or spacing) between adjacent pinhole PIHs can be set based on the distance between the light-blocking layer PHL and the sensor layer PSL, as well as the wavelength range of the reflected light. For example, when the field of view of the reflected light to be ensured is approximately 45 degrees, the distance between adjacent pinhole PIHs can be set to twice or more the distance between the light-blocking layer PHL and the sensor layer PSL, and the distance between adjacent pinhole PIHs can be set to a value equal to or greater than the value obtained by adding a predetermined error range to the distance. In this case, the images observed by the corresponding light sensor PHS can be prevented from overlapping each other, thereby preventing or reducing image blurring.

[0113] A sensor layer PSL is attached to the rear surface (e.g., back surface) of the display panel 110 to overlap with at least one region of the display panel 110. The sensor layer PSL may be configured to overlap with the display panel 110 at least in the display area AA. The sensor layer PSL may include a plurality of light sensors PHS distributed at a predetermined resolution and / or distance. The distance between the light sensors PHS may be set closely such that reflected light from the object to be observed (e.g., a specific area of ​​a finger, such as a fingerprint area) can be incident on at least two adjacent light sensors PHS.

[0114] The optical sensor PHS in the sensor layer PSL can output an electrical signal corresponding to the reflected light received through the pinhole PIH as a sensing signal. The reflected light received by each optical sensor PHS can have different optical properties (e.g., frequency, wavelength, size, etc.) depending on whether the reflected light is due to valleys or ridges formed on the user's finger. Therefore, each of the optical sensors PHS can output a sensing signal with different electrical properties corresponding to the optical properties of the reflected light. The sensing signal output by the optical sensor PHS can be converted into image data and used for the user's fingerprint recognition.

[0115] As described above, the display device 10 according to the present invention includes a fingerprint sensor, which includes a light-emitting element layer (LDL), a sensor layer (PSL), and a light-blocking layer (PHL). The LDL may include a light-emitting element (LD), which can also serve as a light source for a sensor using a photosensitive method. The PSL may include a light sensor (PHS) that receives light emitted from the LDL and reflected from an object located above the display device 10 (e.g., the fingerprint area of ​​a finger). The PHL may include a pinhole (PIH) disposed between the LDL and the PSL to selectively transmit reflected light.

[0116] According to an embodiment, the fingerprint sensor may further include an optical opening region (OPA) formed inside the display panel 110, etc., to reduce the loss of reflected light incident on each pinhole pixel heap (PIH) within a predetermined field of view. Furthermore, the fingerprint sensor may include a light control layer disposed inside the display panel 110 to control the light path, thereby making it easier to control the field of view. Reference will be made below. Figures 9 to 12C Describe various implementations of the light control layer.

[0117] Meanwhile, the display device 10 also utilizes the light-emitting element LD of the pixel PXL as the light source for the fingerprint sensor, but the inventive concept is not limited thereto. For example, the display device according to another embodiment may have a separate light source for fingerprint sensing.

[0118] The fingerprint sensing method of the display device 10 according to the above embodiment will now be briefly described. During the fingerprint sensing cycle of activating the light sensor PHS, when the user's finger (e.g., the fingerprint area) is in contact with or near the display area AA, the pixels PXL of the display area AA (specifically, the light-emitting element LD included in the pixel PXL) can emit light. For example, during the fingerprint sensing cycle, all the pixels PXL of the display area AA can emit light simultaneously or sequentially. Alternatively, only some of the pixels PXL of the display area AA can emit light at predetermined intervals, or some pixels PXL that emit only light of a specific color (e.g., light with a short wavelength, such as blue light) can selectively emit light.

[0119] Some of the light emitted from the pixel PXL can be reflected by the user's finger and incident on the light sensor PHS through the optical opening area OPA and pinhole PIH of the display device 10. At this time, the user's fingerprint shape (fingerprint pattern) can be detected based on the difference in the amount of reflected light and / or the waveform of the reflected light reflected from the ridges and valleys of each fingerprint.

[0120] Figure 4B This is a cross-sectional view of a display device according to another embodiment. Figure 4B In the middle, the above will be omitted. Figure 4A A detailed description of the same or similar configurations in the implementation methods.

[0121] refer to Figure 4B The display panel 110 includes a second protective layer PTL2. The second protective layer PTL2 may include a base layer BSL and a first coating layer COL1 and a second coating layer COL2 formed on the lower and upper surfaces of the base layer BSL, respectively.

[0122] The base layer (BSL) can be formed as a plastic film comprising at least one organic film. For example, the plastic film can be manufactured using at least one of thermoplastic polymer resins and thermosetting polymer resins, such as polycarbonate (PC), polyimide (PI), polyethersulfone (PES), polyarylate (PAR), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), cyclic olefin copolymers, and epoxy resins; and thermosetting polymer resins such as unsaturated polyester, phenol (PF), silicone resin, and polyurethane.

[0123] In exemplary embodiments, the material of the base layer BSL is not limited to those described above, and the material of the base layer BSL can be selected as a suitable material from the materials of the layers disposed thereon, depending on the design conditions of the display panel 110. According to embodiments, the base layer BSL may also include the same material as the infrared light absorbing material and / or infrared light blocking material included in the second adhesive layer ADL2 of the display device 10.

[0124] Either the first coating layer COL1 or the second coating layer COL2 may be coated with an infrared light reflecting and blocking material, while the other may be coated with an infrared light absorbing material. For example, the first coating layer COL1 may be a layer on which a mixture of infrared light absorbing materials is applied (or coated), and the second coating layer COL2 may be a layer on which a mixture of infrared light reflecting and blocking materials is applied (or coated). Examples of infrared light reflecting and blocking materials may include titanium oxide (TiO2), magnesium fluoride (MgF2), etc., but the inventive concept is not limited thereto.

[0125] As described above, when the second protective layer PTL2 includes infrared light reflecting and blocking materials as well as infrared light absorbing materials, even if infrared light from external light passes through the user's hand, the infrared light will not pass through the second protective layer PTL2 located above the sensor layer PSL and reach the sensor layer PSL. Therefore, the optical sensor PHS can more accurately identify the user's fingerprint without being affected by external light.

[0126] According to an exemplary embodiment, infrared light can be blocked by configuring certain aspects of the display panel 110, for example, by configuring the second adhesive layer ADL2 and / or the second protective layer PTL2 to include infrared light absorbing materials and / or infrared light blocking materials, without adding separate components, such as an infrared light blocking film. Therefore, the manufacturing cost of the display device 10 can be reduced, and the thickness of the display device 10 can be further reduced.

[0127] The light-blocking layer PHL described above will be described in more detail below.

[0128] Figure 5This is a plan view illustrating a light-blocking layer according to an exemplary embodiment.

[0129] refer to Figure 5 The light-blocking layer PHL may include a light-blocking mask LBM and multiple pinholes PIH distributed in the light-blocking mask LBM.

[0130] Light-blocking masks (LBMs) ​​can be configured with light-blocking and / or light-absorbing materials. For example, a light-blocking mask LBM can be configured with an opaque metal layer (conductive layer) that is partially open in the region where each pinhole (PIH) is located. However, the materials used to configure light-blocking masks LBMs are not limited to metals, and they can be configured with a variety of materials capable of blocking light transmission. For example, a light-blocking mask LBM can be configured with currently known black matrix materials.

[0131] Pinhole PIHs can be openings dispersed within a light-blocking mask LBM. Pinhole PIHs can be dispersed in the light-blocking mask LBM in regular or irregular patterns, with a certain size and spacing.

[0132] exist Figure 5 In the embodiments described, the pinhole PIH is shown as rectangular, but the inventive concept is not limited thereto. That is, in various embodiments, the pinhole PIH can have various shapes, such as rectangular, circular, elliptical, polygonal, etc. However, the inventive concept is not limited thereto, and the size, shape, number, resolution, arrangement structure, etc. of the pinhole PIH can be varied.

[0133] The light-blocking layer PHL can be set in Figures 1 to 4B In the display device 10, between the light-emitting element layer LDL and the sensor layer PSL, a light-emitting element LD is disposed in the light-emitting element layer LDL, and a light sensor PHS is disposed in the sensor layer PSL. The light-blocking layer PHL can be configured to selectively transmit only some light and block the remaining light in an optical system.

[0134] The light-blocking layer PHL can be configured together with the aforementioned light sensor PHS for the fingerprint sensor. Furthermore, the light-blocking layer PHL can be integrally formed with the circuit element layer BPL of the display panel 110. In this case, the module thickness of the fingerprint sensor using the photosensitive method and the display device including the fingerprint sensor can be reduced or minimized.

[0135] Figures 6A to 6D This is a plan view illustrating various implementations of the arrangement structure of pixels, pinholes, and light sensors. Specifically, Figures 6A to 6D It shows the setting Figures 1 to 4B Different implementations relate to the relative size, resolution, and / or setup relationship of the pixels PXL, pinhole PIH, and light sensor PHS in the sensing area SA.

[0136] refer to Figure 6A The sensing area SA may include a number of pinhole PIHs and light sensors PHS that are fewer than the number of pixels PXL. For example, the size of the pinhole PIHs and light sensors PHS may be smaller than the size of the pixels PXL, and they may be distributed in the sensing area SA at a resolution lower than that of the pixels PXL.

[0137] On the other hand, despite Figure 6A An embodiment is shown where the number of pinhole PIHs and light sensors PHS is less than the number of pixels PXL, but the inventive concept is not limited thereto. That is, in another embodiment, pinhole PIHs and light sensors PHS can be distributed in substantially the same number and at approximately the same distance in the sensing area SA, such that pinhole PIHs and light sensors PHS can correspond one-to-one with each other. For example, pinhole PIHs and light sensors PHS can be arranged to overlap each other in a one-to-one pair. According to the embodiment, the pair of pinhole PIHs and light sensors PHS can be arranged to overlap with any one of the pixels PXL disposed in the sensing area SA, but the inventive concept is not limited thereto. For example, pinhole PIHs and light sensors PHS can be alternately arranged so that they do not overlap with each other, or they can be arranged so that they do not overlap with pixels PXL.

[0138] Pinhole PIHs and optical sensors (PHS) can have the same or different sizes. That is, there are no particular limitations on the relative size and resolution of pinhole PIHs and optical sensors (PHS).

[0139] refer to Figure 6B The sensing area SA may include a smaller number of pinhole PIHs than the number of pixels PXL and a larger number of light sensors PHS than the number of pixels PXL. For example, the pinhole PIHs and light sensors PHS may have a smaller size than the size of the pixels PXL, the pinhole PIHs may be distributed in the sensing area SA at a lower resolution than the resolution of the pixels PXL, and the light sensors PHS may be densely distributed in the sensing area SA at a higher resolution than the resolution of the pixels PXL.

[0140] At least a portion of the light sensor PHS may overlap with, but is not limited to, any of the pinhole PIH and / or pixel PXL. For example, a portion of the light sensor PHS may be configured to overlap with the pinhole PIH and / or pixel PXL, and other light sensors PHS may be configured in the gaps between pixels PXL.

[0141] refer to Figure 6C and Figure 6D The optical sensor PHS can be distributed in the sensing area SA to form a structure with a higher density than... Figure 6BThe illustrated embodiment features a smaller size and higher resolution optical sensor PHS. For example, multiple optical sensors PHS can overlap with each of the pinhole PIH and pixel PXL. Conversely, the pinhole PIH can be distributed within the sensing area SA at the same or a different resolution than the pixel PXL. For example, as... Figure 6C As shown, the pinhole PIH can be distributed in the sensing area SA at the same resolution as the pixel PXL, or as... Figure 6D As shown, the pixels can be distributed in the sensing area SA at a resolution lower than that of the pixel PXL.

[0142] Figures 6A to 6D The illustration shows an embodiment in which the pinhole PIH and the optical sensor PHS are arranged in a regular array in the sensing area SA, but the inventive concept is not limited thereto. That is, the pinhole PIH and / or the optical sensor PHS can be irregularly dispersed in the sensing area SA, or can be distributed with different densities or arrangements for each region or part of the sensing area SA.

[0143] The setup structure of the pixel PXL, pinhole PIH, and light sensor PHS is not limited to Figures 6A to 6D The implementation shown is different. For example, the shape, arrangement type, relative size, number, resolution, and mutual arrangement relationship of the pixel PXL, pinhole PIH and / or light sensor PHS can be changed.

[0144] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12A , Figure 12B and Figure 12C This is a cross-sectional view of a display device according to other embodiments. (See reference...) Figures 7 to 12C The detailed description of configurations that are the same as or similar to at least one of the above embodiments is omitted in the description.

[0145] refer to Figure 7 The display panel 110 may further include a second substrate SUB2 disposed on one surface (e.g., the lower surface) of the first substrate SUB1. The second substrate SUB2 may be disposed between the first substrate SUB1 and the sensor layer PSL. In such an embodiment, a barrier layer BRL may be disposed between the first substrate SUB1 and the second substrate SUB2.

[0146] The second substrate SUB2 may be configured with the same or a different material as the first substrate SUB1. For example, both the first substrate SUB1 and the second substrate SUB2 may be thin film substrates of polyimide (PI) material. Alternatively, the first substrate SUB1 and the second substrate SUB2 may be heterogeneous substrates comprising materials different from each other. The second substrate SUB2 may comprise at least one material previously referred to as the configured material of the first substrate SUB1, and may be configured with a variety of other materials.

[0147] The barrier layer (BRL) can be configured as a single layer or multiple layers. For example, the barrier layer (BRL) can be formed from a structure in which at least ten inorganic insulating layers are stacked.

[0148] refer to Figure 8 The circuit element layer BPL may include a first aperture array layer LTHL1 disposed in the sensing region SA. For example, the first aperture array layer LTHL1 may include a plurality of first apertures LTH1 distributed in the circuit element layer BPL. In such an embodiment, the first aperture array layer LTHL1 may be provided instead of the light blocking layer PHL. That is, the first apertures LTH1 may be used as pinholes PIH.

[0149] When Figure 8 As shown, when the pinhole PIH is configured by using multiple first openings LTH1 (or first opening portions) distributed in the circuit element layer BPL without separately setting the light blocking layer PHL, the separate mask process for forming the light blocking layer PHL can be omitted. Furthermore, according to... Figure 8 The display device 10 of the embodiment shown can prevent the increase in thickness caused by the separate provision of the light blocking layer PHL, reduce manufacturing costs, and increase process efficiency.

[0150] Furthermore, when such Figure 8 When a pinhole PIH is set in the circuit element layer BPL as shown, due to the reference Figure 4A The distance between the described pinhole PIH and the optical aperture region OPA is reduced, so the width of the optical aperture region OPA can be reduced. Then, since the size of the pixel region PXA can be reduced, a high-resolution display device 10 can be achieved.

[0151] refer to Figure 9 and Figure 10 The circuit element layer BPL may include a first aperture array layer LTHL1, which includes a plurality of first apertures LTH1. Furthermore, a light-blocking layer PHL including a plurality of pinhole PIHs may be disposed between the first substrate SUB1 and the circuit element layer BPL. Each first aperture LTH1 and each pinhole PIH is configured such that they at least partially overlap.

[0152] In various implementation methods, such as Figure 9 As shown, the first opening LTH1 and the pinhole PIH can have the same or different dimensions. For example, the width (or diameter) of the first opening LTH1 can be smaller than the width (or diameter) of the pinhole PIH. For example, the pinhole PIH and the first opening LTH1 can have widths (or diameters) ranging from 4 μm to 20 μm, and the width (or diameter) of the first opening LTH1 can be smaller than the width (or diameter) of the pinhole PIH.

[0153] In an implementation, when the first opening LTH1 has a polygonal shape, the width of the first opening LTH1 in any second direction may be the same or different from each other, and the width of the first opening LTH1 in any second direction may be different from the width of the first opening LTH1 in any first direction.

[0154] In an embodiment where the size of the first opening LTH1 is smaller than the size of the pinhole PIH, the first opening array layer LTHL1 can function as a light control layer LBL that controls the path of light (e.g., restricting the field of view of reflected light to a predetermined angular range), and the light blocking layer PHL can function as a light blocking layer.

[0155] like Figure 10 As shown, the width (or diameter) of the first opening LTH1 can be greater than the width (or diameter) of the pinhole PIH. In such an embodiment, the first opening array layer LTHL1 can perform a light blocking function, and the light blocking layer PHL can perform the function of a light control layer LBL that controls the path of light.

[0156] refer to Figure 11 The circuit element layer BPL may include a first aperture array layer LTHL1, which includes a plurality of first apertures LTH1. Furthermore, a light-blocking layer PHL including a plurality of pinhole PIHs may be disposed between a first substrate SUB1 and a second substrate SUB2. Each first aperture LTH1 and each pinhole PIH is configured such that they at least partially overlap.

[0157] In various embodiments, the first opening LTH1 and the pinhole PIH can have the same or different dimensions. For example, the width (or diameter) of the first opening LTH1 can be smaller than the width (or diameter) of the pinhole PIH. In such an embodiment, the first opening array layer LTHL1 can perform the function of the light control layer LBL, which controls the path of light, and the light blocking layer PHL can perform the function of light blocking.

[0158] refer to Figures 12A to 12CThe circuit element layer BPL may include an aperture array layer LTHL disposed in the sensing region SA. The aperture array layer LTHL may be formed by multiple layers. For example, the aperture array layer LTHL includes a first aperture array layer LTHL1 having a first aperture LTH1 and a second aperture array layer LTHL2 having a second aperture LTH2. The first aperture array layer LTHL1 may be a first layer (e.g., a first conductive layer) of the circuit element layer BPL, and the second aperture array layer LTHL2 may be a second layer (e.g., a second conductive layer) of the circuit element layer BPL.

[0159] The first opening LTH1 and the second opening LTH2 can overlap each other. The first opening LTH1 and the second opening LTH2 can have the same or different dimensions.

[0160] For example, such as Figure 12A As shown, the first opening LTH1 and the second opening LTH2 can have substantially the same width (or diameter) and can be arranged to overlap each other. In such an embodiment, the first opening LTH1 and the second opening LTH2 can be configured as a multi-layered pinhole PIH. For example, the first opening LTH1 can be configured as a first pinhole PIH1 disposed in the first layer of the circuit element layer BPL, and the second opening LTH2 can be configured as a second pinhole PIH2 disposed in the second layer of the circuit element layer BPL. In this case, the first opening array layer LTHL1 including the first opening LTH1 and the second opening array layer LTHL2 including the second opening LTH2 can be configured as a multi-layered light blocking layer PHL, for example, a first light blocking layer PHL1 and a second light blocking layer PHL2.

[0161] like Figure 12B As shown, the size of the first opening LTH1 can be smaller than the size of the second opening LTH2. In such an embodiment, the first opening array layer LTHL1, including the first opening LTH1, can perform the function of the light control layer LBL, which controls the path of light, and the second opening array layer LTHL2, including the second opening LTH2, can replace the light blocking layer PHL, which performs the function of light blocking.

[0162] like Figure 12C As shown, the size of the first opening LTH1 can be larger than the size of the second opening LTH2. In such an embodiment, the first opening array layer LTHL1, including the first opening LTH1, can replace the light blocking layer PHL that performs the light blocking function, and the second opening array layer LTHL2, including the second opening LTH2, can perform the function of the light control layer LBL that controls the path of light.

[0163] Figure 13 This is a circuit diagram illustrating a pixel according to an exemplary embodiment. Figure 13For ease of description, an active pixel is shown that is connected to the i-th (i is a natural number) scan line Si and the j-th (j is a natural number) data line Dj and includes two transistors. The i-th scan line Si is located in the i-th horizontal pixel row, and the j-th data line Dj is located in the j-th vertical pixel column. However, the structure of pixel PXL is not limited to... Figure 13 The structure shown.

[0164] refer to Figure 13 According to an exemplary embodiment, the pixel PXL may include a first transistor M1, a second transistor M2, a storage capacitor Cst, and a light-emitting element LD.

[0165] A first transistor M1 (driving transistor) is connected between the j-th data line Dj and the first node N1, and the gate electrode of the first transistor M1 is connected to the i-th scan line Si. The first transistor M1 is turned on when a scan signal with a gate on-state voltage (e.g., a low voltage) is supplied from the i-th scan line Si. When the first transistor M1 is turned on, the j-th data line Dj and the first node N1 can be electrically connected to each other.

[0166] A second transistor M2 (switching transistor) is connected between the first power supply ELVDD and the light-emitting element LD, and the gate electrode of the second transistor M2 is connected to the first node N1. The second transistor M2 controls the amount of current supplied from the first power supply ELVDD to the second power supply ELVSS through the light-emitting element LD according to the voltage of the first node N1. In various embodiments, the first power supply ELVDD can be a high-potential pixel power supply, and the second power supply ELVSS can be a low-potential pixel power supply.

[0167] The storage capacitor Cst is connected between the first power supply ELVDD and the first node N1. The storage capacitor Cst can store the voltage corresponding to the data signal provided to the first node N1.

[0168] The light-emitting element LD is connected between the second transistor M2 and the second power supply ELVSS. The light-emitting element LD emits light with a brightness corresponding to the current controlled by the second transistor M2. In various embodiments, the light-emitting element LD can be an organic light-emitting diode (OLED).

[0169] Figure 14 This is a circuit diagram illustrating a pixel according to another embodiment. Figure 14 For ease of description, an active pixel is shown that is connected to the i-th (i is a natural number) scan line Si and the j-th (j is a natural number) data line Dj and includes seven transistors. The i-th scan line Si is located in the i-th horizontal pixel row, and the j-th data line Dj is located in the j-th vertical pixel column. However, the structure of pixel PXL is not limited to... Figure 14 The structure shown.

[0170] refer to Figure 14 According to another embodiment, the pixel PXL may include a first transistor M1 to a seventh transistor M7, a storage capacitor Cst, and a light-emitting element LD.

[0171] The first electrode of the first transistor M1 can be connected to the first power supply ELVDD via the fifth transistor M5, and the second electrode of the first transistor M1 can be connected to the anode electrode of the light-emitting element LD via the sixth transistor M6. Furthermore, the gate electrode of the first transistor M1 can be connected to the first node N1. The first transistor M1 can control the amount of current flowing from the first power supply ELVDD through the light-emitting element LD to the second power supply ELVSS in accordance with the voltage of the first node N1.

[0172] The second transistor M2 (switching transistor) can be connected between the j-th data line Dj and the first electrode of the first transistor M1. Furthermore, the gate electrode of the second transistor M2 can be connected to the i-th scan line Si. When a scan signal with a gate-on voltage is provided to the i-th scan line Si, the second transistor M2 can be turned on to electrically connect the j-th data line Dj and the first electrode of the first transistor M1 to each other.

[0173] The third transistor M3 can be connected between the second electrode of the first transistor M1 and the first node N1. Furthermore, the gate electrode of the third transistor M3 can be connected to the i-th scan line Si. When a scan signal with a gate on-state voltage is provided to the i-th scan line Si, the third transistor M3 can be turned on, electrically connecting the second electrode of the first transistor M1 and the first node N1 to each other. Therefore, when the third transistor M3 is turned on, the first transistor M1 can be connected in a diode configuration.

[0174] The fourth transistor M4 (initialization transistor) can be connected between the first node N1 and the initialization power supply Vint. Furthermore, the gate electrode of the fourth transistor M4 can be connected to the (i-1)th scan line Si-1. When a scan signal with a gate on-state voltage is provided to the (i-1)th scan line Si-1, the fourth transistor M4 can be turned on to provide the initialization power supply Vint voltage to the first node N1.

[0175] Figure 14 An embodiment is shown in which the (i-1)th scan line Si-1 is used as an initialization control line for initializing the gate node (i.e., the first node N1) of the first transistor M1. However, the inventive concept is not limited thereto. For example, in another embodiment, another control line, such as the (i-2)th scan line, can be used as an initialization control line for initializing the gate node of the first transistor M1.

[0176] The fifth transistor M5 can be connected between the first power supply ELVDD and the first transistor M1. Furthermore, the gate electrode of the fifth transistor M5 can be connected to the i-th light-emitting control line Ei. When a light-emitting control signal with a gate cutoff voltage is provided to the i-th light-emitting control line Ei, the fifth transistor M5 can be turned off, and under other conditions, the fifth transistor M5 can be turned on.

[0177] The sixth transistor M6 can be connected between the first transistor M1 and the light-emitting element LD. Furthermore, the gate electrode of the sixth transistor M6 can be connected to the i-th light-emitting control line Ei. When a light-emitting control signal with a gate cutoff voltage is provided to the i-th light-emitting control line Ei, the sixth transistor M6 can be turned off, and under other conditions, the sixth transistor M6 can be turned on.

[0178] The seventh transistor M7 can be connected between the initialization power supply Vint and the first electrode (e.g., the anode electrode) of the light-emitting element LD. Furthermore, the gate electrode of the seventh transistor M7 can be connected to the (i+1)th scan line Si+1. When a scan signal with a gate on-state voltage (e.g., a low-level voltage) is provided to the (i+1)th scan line Si+1, the seventh transistor M7 can be turned on to provide the voltage of the initialization power supply Vint to the anode electrode of the light-emitting element LD. Here, the voltage of the initialization power supply Vint can be set to be lower than the voltage of the data signal. That is, the voltage of the initialization power supply Vint can be set to be equal to or less than the minimum voltage of the data signal.

[0179] Figure 14 The illustration shows a case where the gate electrode of the seventh transistor M7 is connected to the anode initialization control line of the (i+1)th scan line Si+1. However, the inventive concept is not limited to this. For example, in another embodiment, a scan signal with the same timing as the i-th scan line Si can be applied to the (i+1)th scan line Si+1 (i.e., a scan signal with a gate on-voltage can be applied to both the i-th scan line Si and the (i+1)th scan line Si+1 at the same time point).

[0180] The storage capacitor Cst can be connected between the first power supply ELVDD and the first node N1. The storage capacitor Cst can store a voltage corresponding to the data signal and the threshold voltage of the first transistor M1.

[0181] The anode of the light-emitting element (LD) can be connected to the first transistor M1 via a sixth transistor M6, and the cathode of the LD can be connected to the second power supply ELVSS. The LD generates light with a predetermined brightness corresponding to the amount of current supplied from the first transistor M1. The voltage of the first power supply ELVDD can be set higher than the voltage of the second power supply ELVSS, allowing current to flow to the LD.

[0182] On the other hand, the structure of the pixel PXL is not limited to Figure 14 The implementation shown is illustrated. For example, pixel circuits of various currently known structures can be applied to the pixel PXL.

[0183] Figure 15 It is shown Figure 14 A plan view illustrating an implementation of the pixel layout shown. Specifically, Figure 15 The layout of pixel PXL is shown, which includes settings for... Figure 1 and Figure 2 For example, in any pixel of the display area AA in PXL Figure 9 The first opening LTH1 is shown in the figure. Figure 16 It is along Figure 15 A sectional view taken by line I-I'. Figure 17 It is along Figure 15 A sectional view taken from line II-II'. Figure 15 In this image, the light-blocking layer PHL between the first substrate SUB1 and the circuit element layer BPL is omitted to better show the elements in pixel PXL. However, as... Figure 16 and Figure 17 As shown, the light blocking layer PHL can be further disposed between the first substrate SUB1 and the circuit element layer BPL. Figure 18 It shows the basis Figure 15 A plan view of the light-blocking layer in the embodiment.

[0184] In description Figures 15 to 18 In the implementation, for convenience, the scan line in the (i-1)th row is called "scan line Si-1", the scan line in the ith row is called "scan line Si", the scan line in the (i+1)th row is called "scan line Si+1", the light emission control line in the ith row is called "light emission control line Ei", the data line in the jth column is called "data line Dj", and the power line in the jth column (e.g., the power line in the jth column with the voltage of the first power supply ELVDD applied) is called "power line PL".

[0185] Refer to the above implementation methods Figures 15 to 18 The display device 10 may include a pixel PXL disposed in the display area AA and a wiring portion for providing drive signals and / or power to the pixel PXL. The wiring portion may include scan lines Si-1, Si and Si+1, data line Dj, light emission control line Ei, power line PL and initialization power line IPL.

[0186] Scan lines Si-1, Si, and Si+1 may extend in the sensing region SA along a first direction DR1. Scan lines Si-1, Si, and Si+1 may include a (i-1)th scan line Si-1, an ith scan line Si, and an (i+1)th scan line Si+1 arranged sequentially along a second direction DR2 intersecting the first direction DR1. Scan lines Si-1, Si, and Si+1 may receive scan signals. For example, the (i-1)th scan line Si-1 may receive the (i-1)th scan signal, the ith scan line Si may receive the ith scan signal, and the (i+1)th scan line Si+1 may receive the (i+1)th scan signal.

[0187] The emission control line Ei can extend in the sensing area SA along the first direction DR1, parallel to the scan lines Si-1, Si, and Si+1. The emission control line Ei can receive the emission control signal.

[0188] The data line Dj can extend in the sensing area SA along the second direction DR2. That is, the data line Dj can extend in a direction intersecting with the control lines Si-1, Si, Si+1, and Ei, which include the scan lines Si-1, Si, and Si+1, and the light emission control line Ei. The data line Dj can receive data signals.

[0189] The power line PL may extend along the second direction DR2 within the sensing area SA, but is not limited thereto. The power line PL may be positioned spaced apart from the data line Dj and may receive the voltage of the first power supply ELVDD. The power line PL may have a shape that protrudes in at least one region along the first direction DR1. For example, the power line PL may include at least two first protrusions PRT1-1 and PRT1-2 spaced apart from each other at a predetermined distance. That is, the first protrusions PRT1-1 and PRT1-2 may protrude toward the adjacent bridging pattern BRP in a plan view.

[0190] For example, at least one of the first protruding portions PRT1-1 and PRT1-2, PRT1-1, can overlap with the light-emitting control line Ei. That is, at least one of the first protruding portions PRT1-1 and PRT1-2, PRT1-1, can partially overlap with the light-emitting control line Ei. For example, at least a portion of the other protruding portion PRT1-2 of the first protruding portions PRT1-1 and PRT1-2 can overlap with the initialization power line IPL. That is, the other protruding portion PRT1-2 of the first protruding portions PRT1-1 and PRT1-2 can partially overlap with the initialization power line IPL.

[0191] The first protrusions PRT1-1 and PRT1-2 may have angular shapes. For example, the first protrusions PRT1-1 and PRT1-2 may have a semi-hexagonal planar shape or a trapezoidal planar shape. In this case, at least one side of each of the first protrusions PRT1-1 and PRT1-2 may extend in a direction (e.g., an inclined direction) intersecting each of the first direction DR1 and the second direction DR2. Furthermore, the interior angle of the first opening LTH1 corresponding to the first protrusions PRT1-1 and PRT1-2 may be an obtuse angle.

[0192] However, the inventive concept is not limited thereto, and the first protruding portions PRT1-1 and PRT1-2 can have various planar shapes, such as semi-polygons, semi-circles and semi-ellipses, and the first protruding portions PRT1-1 and PRT1-2 can have the same or different planar shapes.

[0193] The initialization power line IPL may extend along the first direction DR1 in the sensing region SA, but is not limited thereto. The initialization power line IPL may receive the voltage of the initialization power supply Vint. The initialization power line IPL may have a shape protruding in at least one region in a direction opposite to the second direction DR2. For example, the initialization power line IPL may include a second protrusion PRT2. The second protrusion PRT2 may protrude toward the light-emitting control line Ei (or bridging pattern BRP) in a plan view. For example, the second protrusion PRT2 may be formed adjacent to the sixth drain electrode DE6.

[0194] Similar to the first protrusions PRT1-1 and PRT1-2, the second protrusion PRT2 can have an angular shape. For example, the second protrusion PRT2 can have a semi-hexagonal planar shape or a trapezoidal planar shape. However, the inventive concept is not limited to this, and the second protrusion PRT2 can have various planar shapes, such as semi-polygons, semi-circles, and semi-ellipses.

[0195] In an exemplary implementation, such as Figure 14 As shown, pixel PXL may include first transistor M1 to seventh transistor M7, storage capacitor Cst and light-emitting element LD.

[0196] The first transistor M1 may include a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0197] In one embodiment, the first gate electrode GE1 may be configured to overlap with the first channel CH1 of the active pattern, and at least one insulating layer (e.g., gate insulating layer 113) may be interposed between the first channel CH1 and the first gate electrode GE1. The first gate electrode GE1 may be connected to the third drain electrode DE3 (including DE3a and DE3b) of the third transistor M3 and the fourth source electrode SE4 (including SE4a and SE4b) of the fourth transistor M4.

[0198] The first gate electrode GE1 can be connected to the third drain electrode DE3 and the fourth source electrode SE4 via the connecting wire CNL. One end of the connecting wire CNL can be connected to the first gate electrode GE1 via the first contact hole CT1, and the other end of the connecting wire CNL can be connected to the third drain electrode DE3 and the fourth source electrode SE4 via the second contact hole CT2.

[0199] In an exemplary embodiment, the first channel CH1, the first source electrode SE1, and the first drain electrode DE1 may be formed from semiconductor patterns that are undoped or doped. For example, the first source electrode SE1 and the first drain electrode DE1 may be formed from doped semiconductor patterns, and the first channel CH1 may be formed from an undoped semiconductor pattern.

[0200] The first channel CH1 can have a shape extending in any direction, and can also have a shape that bends several times along the longitudinal direction of extension. When viewed in a plan view, the first channel CH1 can overlap with the first gate electrode GE1. By forming the first channel CH1 as long, the channel region of the first transistor M1 can also be formed as long. Therefore, the driving range of the gate voltage applied to the first transistor M1 is widened. Thus, the grayscale of the light emitted from the light-emitting element LD can be precisely controlled.

[0201] The first source electrode SE1 can be connected to one end of the first channel CH1. The first source electrode SE1 can be connected to the second drain electrode DE2 of the second transistor M2 and the fifth drain electrode DE5 of the fifth transistor M5. In an embodiment, the first drain electrode DE1 can be connected to the other end of the first channel CH1. The first drain electrode DE1 can be connected to the third source electrode SE3 of the third transistor M3 and the sixth source electrode SE6 of the sixth transistor M6.

[0202] The second transistor M2 may include a second gate electrode GE2, a second channel CH2, a second source electrode SE2, and a second drain electrode DE2.

[0203] The second gate electrode GE2 may be configured to overlap with the second channel CH2, and at least one insulating layer (e.g., gate insulating layer 113) may be interposed between the second channel CH2 and the second gate electrode GE2. The second gate electrode GE2 may be connected to the i-th scan line Si.

[0204] The second channel CH2, the second source electrode SE2, and the second drain electrode DE2 can be formed from semiconductor patterns that are either undoped or doped. For example, the second source electrode SE2 and the second drain electrode DE2 can be formed from doped semiconductor patterns, and the second channel CH2 can be formed from an undoped semiconductor pattern. The second channel CH2 may correspond to the portion that overlaps with the second gate electrode GE2.

[0205] One end of the second source electrode SE2 can be connected to the second channel CH2, and the other end of the second source electrode SE2 can be connected to the data line Dj through the sixth contact hole CT6. In the embodiment, one end of the second drain electrode DE2 can be connected to the second channel CH2, and the other end of the second drain electrode DE2 can be connected to the first source electrode SE1 of the first transistor M1 and the fifth drain electrode DE5 of the fifth transistor M5.

[0206] The third transistor M3 may have a dual-gate structure to prevent leakage current. That is, the third transistor M3 may include a third transistor M3a and a third transistor M3b. The third transistor M3a may include a third gate electrode GE3a, a third channel CH3a, a third source electrode SE3a, and a third drain electrode DE3a. The third transistor M3b may include a third gate electrode GE3b, a third channel CH3b, a third source electrode SE3b, and a third drain electrode DE3b. In the following text, the third gate electrode GE3a and the third gate electrode GE3b are referred to as the third gate electrode GE3, the third channel CH3a and the third channel CH3b are referred to as the third channel CH3, the third source electrode SE3a and the third source electrode SE3b are referred to as the third source electrode SE3, and the third drain electrode DE3a and the third drain electrode DE3b are referred to as the third drain electrode DE3.

[0207] The third gate electrode GE3 may be configured to overlap with the third channel CH3, and at least one insulating layer (e.g., gate insulating layer 113) may be inserted between the third channel CH3 and the third gate electrode GE3. The third gate electrode GE3 may be connected to the i-th scan line Si.

[0208] The third channel CH3, the third source electrode SE3, and the third drain electrode DE3 can be formed from semiconductor patterns that are either undoped or doped. For example, the third source electrode SE3 and the third drain electrode DE3 can be formed from doped semiconductor patterns, and the third channel CH3 can be formed from an undoped semiconductor pattern. The third channel CH3 corresponds to the portion that overlaps with the third gate electrode GE3.

[0209] One end of the third source electrode SE3 can be connected to the third channel CH3, and the other end of the third source electrode SE3 can be connected to the first drain electrode DE1 of the first transistor M1 and the sixth source electrode SE6 of the sixth transistor M6. In an embodiment, one end of the third drain electrode DE3 can be connected to the third channel CH3, and the other end of the third drain electrode DE3 can be connected to the fourth source electrode SE4 of the fourth transistor M4. Furthermore, the third drain electrode DE3 can be connected to the first gate electrode GE1 of the first transistor M1 via the connecting line CNL, the second contact hole CT2, and the first contact hole CT1.

[0210] The fourth transistor M4 may have a dual-gate structure to prevent leakage current. That is, the fourth transistor M4 may include a fourth transistor M4a and a fourth transistor M4b. The fourth transistor M4a may include a fourth gate electrode GE4a, a fourth channel CH4a, a fourth source electrode SE4a, and a fourth drain electrode DE4a. The fourth transistor M4b may include a fourth gate electrode GE4b, a fourth channel CH4b, a fourth source electrode SE4b, and a fourth drain electrode DE4b. In the following text, the fourth gate electrode GE4a and the fourth gate electrode GE4b are referred to as the fourth gate electrode GE4, the fourth channel CH4a and the fourth channel CH4b are referred to as the fourth channel CH4, the fourth source electrode SE4a and the fourth source electrode SE4b are referred to as the fourth source electrode SE4, and the fourth drain electrode DE4a and the fourth drain electrode DE4b are referred to as the fourth drain electrode DE4.

[0211] The fourth gate electrode GE4 may be configured to overlap with the fourth channel CH4, and at least one insulating layer (e.g., gate insulating layer 113) may be interposed between the fourth channel CH4 and the fourth gate electrode GE4. The fourth gate electrode GE4 may be connected to the (i-1)th scan line Si-1.

[0212] The fourth channel CH4, the fourth source electrode SE4, and the fourth drain electrode DE4 can be formed from semiconductor patterns that are either undoped or doped. For example, the fourth source electrode SE4 and the fourth drain electrode DE4 can be formed from doped semiconductor patterns, and the fourth channel CH4 can be formed from an undoped semiconductor pattern. The fourth channel CH4 corresponds to the portion that overlaps with the fourth gate electrode GE4.

[0213] One end of the fourth source electrode SE4 can be connected to the fourth channel CH4, and the other end of the fourth source electrode SE4 can be connected to the third drain electrode DE3 of the third transistor M3. Furthermore, the fourth source electrode SE4 can be connected to the first gate electrode GE1 of the first transistor M1 via the connecting line CNL, the second contact hole CT2, and the first contact hole CT1. One end of the fourth drain electrode DE4 can be connected to the fourth channel CH4, and the other end of the fourth drain electrode DE4 can be connected to the seventh drain electrode DE7 of the seventh transistor M7 of the pixel PXL in the (i-1)th row. The fourth drain electrode DE4 can be connected to the initialization power line IPL via the auxiliary connecting line AUX, the ninth contact hole CT9, and the eighth contact hole CT8.

[0214] The fifth transistor M5 may include a fifth gate electrode GE5, a fifth channel CH5, a fifth source electrode SE5, and a fifth drain electrode DE5.

[0215] The fifth gate electrode GE5 may be configured to overlap with the fifth channel CH5, and at least one insulating layer (e.g., gate insulating layer 113) may be inserted between the fifth channel CH5 and the fifth gate electrode GE5. The fifth gate electrode GE5 may be connected to the light-emitting control line Ei.

[0216] The fifth channel CH5, the fifth source electrode SE5, and the fifth drain electrode DE5 can be formed from semiconductor patterns that are either undoped or doped. For example, the fifth source electrode SE5 and the fifth drain electrode DE5 can be formed from doped semiconductor patterns, and the fifth channel CH5 can be formed from an undoped semiconductor pattern. The fifth channel CH5 corresponds to the portion that overlaps with the fifth gate electrode GE5.

[0217] One end of the fifth source electrode SE5 can be connected to the fifth channel CH5, and at least a portion of the other end of the fifth source electrode SE5 can overlap with the power line PL and can be connected to the power line PL through the fifth contact hole CT5. In an embodiment, one end of the fifth drain electrode DE5 can be connected to the fifth channel CH5, and the other end of the fifth drain electrode DE5 can be connected to the first source electrode SE1 of the first transistor M1 and the second drain electrode DE2 of the second transistor M2.

[0218] The sixth transistor M6 may include a sixth gate electrode GE6, a sixth channel CH6, a sixth source electrode SE6, and a sixth drain electrode DE6.

[0219] The sixth gate electrode GE6 may be configured to overlap with the sixth channel CH6, and at least one insulating layer (e.g., gate insulating layer 113) may be interposed between the sixth channel CH6 and the sixth gate electrode GE6. The sixth gate electrode GE6 may be connected to the light-emitting control line Ei.

[0220] The sixth channel CH6, the sixth source electrode SE6, and the sixth drain electrode DE6 are formed from semiconductor patterns that are either undoped or doped. For example, the sixth source electrode SE6 and the sixth drain electrode DE6 may be formed from doped semiconductor patterns, and the sixth channel CH6 may be formed from an undoped semiconductor pattern. The sixth channel CH6 corresponds to the portion that overlaps with the sixth gate electrode GE6.

[0221] One end of the sixth source electrode SE6 can be connected to the sixth channel CH6, and the other end of the sixth source electrode SE6 can be connected to the first drain electrode DE1 of the first transistor M1 and the third source electrode SE3 of the third transistor M3. In an embodiment, one end of the sixth drain electrode DE6 can be connected to the sixth channel CH6, and the other end of the sixth drain electrode DE6 can be connected to the seventh source electrode SE7 of the seventh transistor M7. In an embodiment, the sixth drain electrode DE6 can be configured to be spaced apart from the fifth source electrode SE5 by a predetermined distance.

[0222] The seventh transistor M7 may include a seventh gate electrode GE7, a seventh channel CH7, a seventh source electrode SE7, and a seventh drain electrode DE7.

[0223] The seventh gate electrode GE7 may be configured to overlap with the seventh channel CH7, and at least one insulating layer (e.g., gate insulating layer 113) may be interposed between the seventh channel CH7 and the seventh gate electrode GE7. The seventh gate electrode GE7 may be connected to the (i+1)th scan line Si+1.

[0224] The seventh channel CH7, the seventh source electrode SE7, and the seventh drain electrode DE7 can be formed from semiconductor patterns that are either undoped or doped. For example, the seventh source electrode SE7 and the seventh drain electrode DE7 can be formed from doped semiconductor patterns, and the seventh channel CH7 can be formed from an undoped semiconductor pattern. The seventh channel CH7 corresponds to the portion that overlaps with the seventh gate electrode GE7.

[0225] One end of the seventh source electrode SE7 can be connected to the seventh channel CH7, and the other end of the seventh source electrode SE7 can be connected to the sixth drain electrode DE6 of the sixth transistor M6. In an embodiment, one end of the seventh drain electrode DE7 can be connected to the seventh channel CH7, and the other end of the seventh drain electrode DE7 can be connected to the initialization power line IPL through the auxiliary connection line AUX, the ninth contact hole CT9, and the eighth contact hole CT8.

[0226] The storage capacitor Cst may include a first capacitor electrode LE and a second capacitor electrode UE. In one embodiment, the first capacitor electrode LE may be the lower electrode of the storage capacitor Cst and may be integrally formed with the first gate electrode GE1 of the first transistor M1. In another embodiment, the second capacitor electrode UE may be the upper electrode of the storage capacitor Cst and may overlap with the first gate electrode GE1. Furthermore, as shown in the plan view, the second capacitor electrode UE may cover at least one region of the first capacitor electrode LE. The capacitance of the storage capacitor Cst can be increased by expanding the overlap area of ​​the first capacitor electrode LE and the second capacitor electrode UE.

[0227] The second capacitor electrode UE may extend along the first direction DR1. In an exemplary embodiment, a voltage at the same level as the first power supply ELVDD may be applied to the second capacitor electrode UE. The second capacitor electrode UE may have an opening portion OPN in the region where the first contact hole CT1 is formed, in which the first gate electrode GE1 and the connecting line CNL are in contact with each other.

[0228] A light-emitting element (LD) may include a first electrode (e.g., an anode electrode) AD, a second electrode (e.g., a cathode electrode) CD, and a light-emitting layer EML disposed between the first electrode AD and the second electrode CD. In an embodiment, the first electrode AD and the second electrode CD are arranged to overlap each other in the light-emitting region of the light-emitting element layer LDL, and the light-emitting layer EML may be formed in the light-emitting region. That is, the light-emitting region of each pixel PXL may be the region where the first electrode AD, the light-emitting layer EML, and the second electrode CD of the light-emitting element LD overlap each other.

[0229] The first electrode AD can be positioned within a predetermined light-emitting area. The first electrode AD can be connected to the seventh source electrode SE7 of the seventh transistor M7 and the sixth drain electrode DE6 of the sixth transistor M6 via the fourth contact hole CT4 and the seventh contact hole CT7.

[0230] A bridging pattern BRP can be disposed between the fourth contact hole CT4 and the seventh contact hole CT7. The bridging pattern BRP can connect the sixth drain electrode DE6, the seventh source electrode SE7, and the first electrode AD. The bridging pattern BRP can have a shape protruding in a region in a direction opposite to the first direction DR1. For example, the bridging pattern BRP may include a third protrusion PRT3 formed in a region in a direction opposite to the first direction DR1. That is, the third protrusion PRT3 can protrude toward the electric field line PL (or one of the first protrusions PRT1-1 and PRT1-2 of the electric field line PL).

[0231] For example, at least a portion of the third protrusion PRT3 may overlap with the light-emitting control line Ei. For example, the third protrusion PRT3 may be configured to correspond to a spaced-apart area of ​​the first protrusions PRT1-1 and PRT1-2, or it may be configured to face one of the first protrusions PRT1-1 and PRT1-2 of the power line PL, namely, protrusion PRT1-1.

[0232] The third protruding portion PRT3 can have an angular shape. For example, the third protruding portion PRT3 can have a semi-hexagonal shape. However, the inventive concept is not limited to this, and the third protruding portion PRT3 can have various shapes, such as semi-polygon, semi-circle, and semi-ellipse.

[0233] In the following, a stacked structure (cross-sectional structure) of a pixel PXL and a sensing region SA including the pixel PXL according to an exemplary embodiment will be described.

[0234] First, a buffer layer 112 may be disposed on a first surface of the first substrate SUB1. The buffer layer 112 can prevent or reduce the diffusion of metal atoms or impurities from the first substrate SUB1 (e.g., outgassing). Furthermore, when the surface of the first substrate SUB1 is non-uniform, the buffer layer 112 can be used to improve the surface smoothness of the first substrate SUB1. The buffer layer 112 may comprise inorganic or organic materials such as oxides or nitrides, or may comprise organic-inorganic composite materials, and may be formed from a single-layer or multi-layer structure of inorganic and organic materials. For example, the buffer layer 112 may have a structure of at least three layers formed of silicon oxide, silicon nitride, and silicon oxide.

[0235] An active pattern ACT may be disposed on the buffer layer 112. In an embodiment, the active pattern ACT may include a first channel CH1 to a seventh channel CH7. The first channel CH1 to the seventh channel CH7 may be formed of a semiconductor material.

[0236] The gate insulating layer 113 may be disposed on the buffer layer 112 on which the first channel CH1 to the seventh channel CH7 are disposed. In an embodiment, the gate insulating layer 113 may be a gate insulating film interposed between the active pattern ACT of the transistors M1 to M7 included in the pixel PXL and the gate electrodes GE1 to GE7.

[0237] The gate insulating layer 113 may include at least one inorganic film and / or an organic film. For example, the gate insulating layer 113 may be composed of SiO2. X SiN X Inorganic films such as, but not limited to, can be formed. For example, the gate insulating layer 113 may include, for example, SiO2. X SiN XSiON, SiOF or AlO X It can be an inorganic or organic insulating material, and can be a single or multiple films including at least one of these materials.

[0238] A first conductive layer may be disposed on the gate insulating layer 113. In an embodiment, the first conductive layer may be a first gate layer. The first conductive layer may be provided with control lines Si-1, Si, Si+1, and Ei, and gate electrodes GE1 to GE7. Furthermore, one electrode of the storage capacitor Cst (e.g., the first capacitor electrode LE) may be disposed in the first conductive layer. Specifically, the (i-1)th scan line Si-1, the i-th scan line Si, the (i+1)th scan line Si+1, the light emission control line Ei, and the first gate electrodes GE1 to the seventh gate electrodes GE7 may be disposed in the first conductive layer on the gate insulating layer 113. In an embodiment, the first gate electrode GE1 may also be the first capacitor electrode LE of the storage capacitor Cst. That is, the first gate electrode GE1 and the first capacitor electrode LE may be integrally formed.

[0239] The control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE serving as the lower electrode of the storage capacitor Cst, disposed in the first conductive layer, can be configured from the same material. For example, the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE serving as the storage capacitor Cst can be formed from a predetermined first gate metal.

[0240] Examples of materials capable of configuring the first gate metal include Ti, Cu, Mo, Al, Au, Cr, TiN, Ag, Pt, Pd, Ni, Sn, Co, Rh, Ir, Fe, Ru, Os, Mn, W, Nb, Ta, Bi, Sb, Pb, etc., and various other metals can also be used as materials capable of configuring the first gate metal. Examples of alloys capable of configuring the first gate metal include MoTi, AlNiLa, etc., and various other alloys can also be used as alloys capable of configuring the first gate metal. Examples of multiple films capable of configuring the first gate metal include Ti / Cu, Ti / Au, Mo / Al / Mo, ITO / Ag / ITO, TiN / Ti / Al / Ti, TiN / Ti / Cu / Ti, etc., and multiple film structures of various other conductive materials can also be used as multiple films capable of configuring the first gate metal.

[0241] On the other hand, the materials used for configuring the control lines Si-1, Si, Si+1 and Ei, the gate electrodes GE1 to GE7 and / or the first capacitor electrode LE are not limited to metals. That is, any material capable of providing sufficient conductivity to smoothly drive the pixel PXL can be used as the material for configuring the control lines Si-1, Si, Si+1 and Ei, the gate electrodes GE1 to GE7 and / or the first capacitor electrode LE.

[0242] For example, the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE can be configured with a conductive polymer or a conductive metal oxide. Examples of conductive polymers capable of configuring the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE may include polythiophene-based compounds, polypyrrole-based compounds, polyaniline-based compounds, polyacetylene-based compounds, polyphenylene-based compounds, mixtures thereof, etc., and specifically, in polythiophene-based compounds, PEDOT / PSS compounds may be used. Examples of conductive metal oxides capable of configuring the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE may include ITO, IZO, AZO, ITZO, ZnO, SnO2, etc.

[0243] The first interlayer insulating layer 114 may be disposed on the first conductive layer. In an embodiment, the first interlayer insulating layer 114 may be a first interlayer insulating film interposed between the first capacitor electrode LE and the second capacitor electrode UE. In an embodiment, the first interlayer insulating layer 114 may have a thickness limited to a predetermined range in order to sufficiently ensure the capacity of the storage capacitor Cst within a limited area.

[0244] The first interlayer insulating layer 114 may comprise one or more layers of inorganic and / or organic films. For example, the first interlayer insulating layer 114 may be composed of SiO2. X SiN X Inorganic film configurations, such as, but not limited to, are also possible. For example, the first interlayer insulating layer 114 may include, for instance, SiO2. X SiN X SiON, SiOF or AlO X It can be an inorganic or organic insulating material, and can be a single membrane or multiple membranes including at least one of these materials.

[0245] The second conductive layer can be disposed on the first interlayer insulating layer 114. In an embodiment, the second conductive layer can be a second gate layer.

[0246] The second conductive layer may be provided with a second capacitor electrode UE and an initialization power line IPL. In one embodiment, the second capacitor electrode UE may cover the first capacitor electrode LE. The second capacitor electrode UE overlaps with the first capacitor electrode LE to form a storage capacitor Cst together with the first capacitor electrode LE, and a first interlayer insulating layer 114 is inserted between the second capacitor electrode UE and the first capacitor electrode LE. The initialization power line IPL may extend along a first direction DR1 in the display area AA, but is not limited thereto. The initialization power line IPL may receive the voltage of the initialization power supply Vint.

[0247] The second capacitor electrode UE and the initialization power line IPL disposed in the second conductive layer can be configured from the same material. For example, the second capacitor electrode UE and the initialization power line IPL can be formed from a predetermined second gate metal. In embodiments, the second gate metal can be one of the metal materials previously presented as examples of the first gate metal, but is not limited thereto. Furthermore, the configuration material of the second capacitor electrode UE and the initialization power line IPL disposed in the second conductive layer is not necessarily limited to metal. That is, a material capable of providing sufficient conductivity to smoothly drive the pixel PXL can be used as the material for configuring the second capacitor electrode UE and the initialization power line IPL. For example, the second capacitor electrode UE and the initialization power line IPL disposed in the second conductive layer can be configured from a conductive polymer or a conductive metal oxide.

[0248] The second interlayer insulating layer 115 may be disposed on the second conductive layer. In an embodiment, the second interlayer insulating layer 115 may be a second interlayer insulating film.

[0249] The second interlayer insulating layer 115 may comprise one or more layers of inorganic and / or organic films. For example, the second interlayer insulating layer 115 may be composed of SiO2. X SiN X Inorganic film configurations, such as, but not limited to, are also possible. For example, the second interlayer insulating layer 115 may include, for instance, SiO2. X SiN X SiON, SiOF or AlO X It can be an inorganic or organic insulating material, and can be a single or multiple films including at least one of these materials.

[0250] The third conductive layer can be disposed on the second interlayer insulating layer 115. In an embodiment, the third conductive layer can be a source-drain layer.

[0251] The third conductive layer can be configured with data lines Dj, power lines PL, connector lines CNL, bridging patterns BRP, and auxiliary connector lines AUX.

[0252] The data line Dj can be electrically connected to the second source electrode SE2 through the sixth contact hole CT6 passing through the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115.

[0253] The power line PL can be connected to the second capacitor electrode UE, which serves as the upper electrode of the storage capacitor Cst, via the third contact hole CT3 passing through the second interlayer insulating layer 115. Furthermore, the power line PL can be connected to the fifth source electrode SE5 via the fifth contact hole CT5 passing through the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115.

[0254] The connection line CNL can be connected to the first gate electrode GE1 through the first contact hole CT1 passing through the first interlayer insulating layer 114 and the second interlayer insulating layer 115. In addition, the connection line CNL can be electrically connected to the third drain electrode DE3 and the fourth source electrode SE4 through the second contact hole CT2 passing through the gate insulating layer 113, the first interlayer insulating layer 114 and the second interlayer insulating layer 115.

[0255] The bridging pattern BRP can be a pattern of dielectric material between the sixth drain electrode DE6 and the first electrode AD, connecting the sixth drain electrode DE6 and the first electrode AD. The bridging pattern BRP can be electrically connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through a fourth contact hole CT4 passing through the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115.

[0256] The auxiliary connection line AUX can be connected to the initialization power line IPL through the eighth contact hole CT8 passing through the second interlayer insulation layer 115. Furthermore, the auxiliary connection line AUX can be connected to the seventh drain electrode DE7 through the ninth contact hole CT9 passing through the gate insulation layer 113, the first interlayer insulation layer 114, and the second interlayer insulation layer 115.

[0257] The data line Dj, power line PL, connector CNL, bridging pattern BRP, and / or auxiliary connector AUX disposed in the third conductive layer can be configured from the same material. For example, the data line Dj, power line PL, connector CNL, bridging pattern BRP, and / or auxiliary connector AUX can be formed from a predetermined source / drain metal.

[0258] The source / drain metal can be one of the metallic materials previously presented as examples of the first gate metal and / or the second gate metal, but is not limited thereto. Furthermore, the configuration materials for the data lines Dj, power lines PL, connection lines CNL, bridging patterns BRP, and / or auxiliary connection lines AUX disposed in the third conductive layer are not necessarily limited to metals. That is, any material capable of providing sufficient conductivity to smoothly drive the pixel PXL can be used as the material for configuring the data lines Dj, power lines PL, connection lines CNL, bridging patterns BRP, and / or auxiliary connection lines AUX. For example, the data lines Dj, power lines PL, connection lines CNL, bridging patterns BRP, and / or auxiliary connection lines AUX can be configured from conductive polymers or conductive metal oxides.

[0259] At least two of the first gate metal, the second gate metal, and the source / drain metal may be formed of the same material. For example, even if the first gate metal and the second gate metal are disposed on different layers, the first gate metal and the second gate metal may be formed of the same material. However, the inventive concept is not limited thereto. For example, in another embodiment, all of the first gate metal, the second gate metal, and the source / drain metal may be formed of different materials.

[0260] The protective layer 116 may be disposed on the third conductive layer. In an embodiment, the protective layer 116 may include a passivation film and / or a planarization film. The protective layer 116 may include a seventh contact hole CT7 that exposes a portion of the bridging pattern BRP.

[0261] The light-emitting element LD can be disposed on the protective layer 116. The light-emitting element LD may include a first electrode AD, a second electrode CD, and a light-emitting layer EML disposed between the first electrode AD and the second electrode CD.

[0262] In an exemplary embodiment, the protective layer 116 may have approximately to approximately (For example, about The thickness of the protective layer 116 is not limited to this.

[0263] At least one of the first electrode AD and the second electrode CD can be a transmission electrode. For example, when the light-emitting element LD is a back-surface emitting organic light-emitting display element, the first electrode AD can be a transmission electrode, and the second electrode CD can be a reflection electrode. On the other hand, when the light-emitting element LD is a front-surface emitting organic light-emitting display element, the first electrode AD can be a reflection electrode, and the second electrode CD can be a transmission electrode. Furthermore, when the light-emitting element LD is a double-surface emitting organic light-emitting display element, both the first electrode AD and the second electrode CD can be transmission electrodes. In the following, the case where the light-emitting element LD is a front-surface emitting organic light-emitting display element and the first electrode AD is an anode electrode will be described as an example. Furthermore, in this embodiment, the light-emitting element LD is used as a light source, but the inventive concept is not limited thereto. For example, the light-emitting element LD can be replaced by another type of light-emitting element.

[0264] The first electrode AD can be disposed on the protective layer 116. The first electrode AD can be connected to the bridging pattern BRP through the seventh contact hole CT7 passing through the protective layer 116. Since the bridging pattern BRP is connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through the fourth contact hole CT4, the first electrode AD can ultimately be connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through the bridging pattern BRP.

[0265] The first electrode AD may include a reflective film (not shown) capable of reflecting light and a transparent conductive film (not shown) disposed above or below the reflective film. At least one of the transparent conductive film and the reflective film may be connected to the sixth drain electrode DE6 and the seventh source electrode SE7.

[0266] The reflective film may include materials capable of reflecting light. For example, the reflective film may include at least one of aluminum (Al), silver (Ag), chromium (Cr), molybdenum (Mo), platinum (Pt), nickel (Ni), and their alloys.

[0267] Transparent conductive films may include transparent conductive oxides. For example, a transparent conductive film may include at least one transparent conductive oxide selected from indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium-doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and fluorine-doped tin oxide (FTO).

[0268] The light-emitting layer (EML) can be disposed on the exposed surface of the first electrode (AD). The EML can have a multilayer thin film structure including a light-generating layer (LGL). For example, the EML may include a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron transport layer (ETL), and / or an electron injection layer (EIL). The hole injection layer (HIL) is used to inject holes. The hole transport layer (HTL) has excellent hole transport properties and increases the recombination probability of holes and electrons by suppressing the movement of electrons not bound in the light-generating layer (the light-generating layer emits light through the recombination of injected electrons and holes). The hole blocking layer (HBL) is used to suppress the movement of holes not bound in the light-generating layer. The electron transport layer (ETL) is used to smoothly transport electrons to the light-generating layer. The electron injection layer (EIL) is used to inject electrons.

[0269] The color of the light generated in the light-generating layer can be one of red, green, blue, and white, but the present invention is not limited to this. For example, the color of the light generated in the light-generating layer EML can be one of magenta, cyan, and yellow.

[0270] The hole injection layer, hole transport layer, hole blocking layer, electron transport layer, and electron injection layer can be a common film connected to each other in adjacent light-emitting regions.

[0271] The second electrode CD can be a semi-transmissive and semi-reflective film. For example, the second electrode CD can be a thin-film metal layer with a sufficiently thin thickness to transmit light emitted from the light-emitting layer EML. For example, the second electrode CD can transmit some of the light emitted from the light-emitting layer EML and reflect the remaining portion of the light emitted from the light-emitting layer EML.

[0272] In an embodiment, the second electrode CD may include a material with a work function lower than that of the transparent conductive film. For example, the second electrode CD may include at least one of molybdenum (Mo), tungsten (W), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and alloys thereof.

[0273] Some of the light emitted from the emissive layer (EML) may not be able to penetrate the second electrode (CD), and the light reflected from the second electrode (CD) can be reflected again by the reflective film. In other words, the light emitted from the EML can resonate between the reflective film and the second electrode (CD). The light extraction efficiency of the light-emitting element (LD) can be improved through light resonance.

[0274] A pixel defining film (or dam) 117 for separating the light-emitting areas of each pixel PXL can be disposed on a first substrate SUB1 on which a first electrode AD is disposed. The pixel defining film 117 may expose the upper surface of the first electrode AD and may protrude from the first substrate SUB1 along the circumference of each light-emitting area.

[0275] The light-emitting layer EML can be disposed in the light-emitting region surrounded by the pixel-defining film 117 of each pixel PXL, and the second electrode CD can be disposed on the light-emitting layer EML. One of the first electrode AD and the second electrode CD can be an anode electrode, and the other can be a cathode electrode. For example, the first electrode AD can be an anode electrode, and the second electrode CD can be a cathode electrode.

[0276] The pixel defining film 117 may include an organic insulating material. For example, the pixel defining film 117 may include at least one of polystyrene, polymethyl methacrylate (PMMA), polyacrylonitrile (PAN), polyamide (PA), polyimide (PI), polyarylene ether (PAE), heterocyclic polymer, parylene, epoxy resin, benzocyclobutene (“BCB”), siloxane resin, and silane resin.

[0277] A first protective layer PTL1 covering the second electrode CD can be disposed on the second electrode CD. The first protective layer PTL1 can be configured as a thin-film encapsulation layer. In an embodiment, the thin-film encapsulation layer can be replaced by at least one layer of another type of encapsulation film, encapsulation substrate, protective film, etc.

[0278] Thin-film encapsulation layers can prevent or reduce the penetration of oxygen and moisture into the light-emitting element (LD). For this purpose, the thin-film encapsulation layer can include an inorganic film. The inorganic film can include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, zirconium oxide, and tin oxide.

[0279] Each of the circuit elements and wirings disposed on the first surface of the first substrate SUB1, from the buffer layer 112 to the protective layer 116, can configure the circuit element layer BPL of the display device 10 and / or the fingerprint sensor. Furthermore, the light-emitting elements LD disposed in each pixel PXL from the first electrode AD to the second electrode CD, and the thin-film encapsulation layer disposed between the light-emitting elements LD, can configure the light-emitting element layer LDL of the display device 10 and / or the fingerprint sensor.

[0280] Further reference Figures 15 to 18 According to an embodiment, a pixel PXL may include a first opening LTH1, which is defined to not overlap with a conductive layer (and semiconductor layer) in a circuit element layer BPL. A sensing region SA may include a plurality of pixels PXL having the first opening LTH1.

[0281] In other words, the first opening LTH1 can be formed so as not to overlap with the conductive layers (and semiconductor layers) stacked in the vertical direction in the circuit element layer BPL. For example, the first opening LTH1 can be formed so as not to overlap with the semiconductor layer in which the active pattern ACT of the circuit element layer BPL is disposed, the first conductive layer in which gate electrodes GE1 to GE7 are disposed, the second conductive layer in which the second capacitor electrode UE is disposed, the third conductive layer in which the power line PL is disposed, and the third conductive layer in which the bridging pattern BRP is disposed.

[0282] The first opening LTH1 may be an opening region defined by a portion of at least one region of the electric field line PL including the first protrusions PRT1-1 and PRT1-2, a portion of at least one region of the initialization electric field line IPL including the second protrusion PRT2, a portion of the light emission control line Ei, a portion of at least one region of the bridging pattern BRP including the third protrusion PRT3, a portion of the fifth source electrode SE5, and a portion of the sixth drain electrode DE6.

[0283] The first opening LTH1 may have a planar closed-loop shape. At least a portion of the closed-loop shape may include a curve, or the interior angles of at least a portion of the closed-loop shape may be obtuse angles. The first opening LTH1 may have a polygonal planar shape, and the interior angles are obtuse angles corresponding to the angular shapes of the first protrusions PRT1-1 and PRT1-2 to the third protrusions PRT3. For example, the first opening LTH1 may have the following shape: Figure 15 The planar shape shown is approximately octagonal. However, the inventive concept is not limited thereto.

[0284] When the first opening LTH1 is formed between wiring and / or conductive layers on which no protrusions are formed, the first opening LTH1 has an approximately rectangular planar shape. In this case, when incident light diffracts at the edges of the wiring and / or conductive layers forming the first opening LTH1, the sensor layer PSL may be unable to perform accurate fingerprint detection. This diffraction is more severe when acute angles are formed between the wiring and / or conductive layers.

[0285] like Figure 15 , Figure 16 and Figure 17 As shown, when the first opening LTH1 has a generally octagonal shape, the angle between the wiring and / or conductive layer forming the first opening LTH1 forms an obtuse angle. Therefore, diffraction of incident light at the edge of the first opening LTH1 can be reduced.

[0286] According to the above embodiment, an array of openings for receiving reflected light can be formed integrally with the light-emitting element layer (LDL) and the circuit element layer (BPL), without forming an additional layer inside the circuit element layer (BPL). Therefore, the module thickness of the display device 10 can be reduced.

[0287] Meanwhile, in various embodiments, the arrangement and shape of the first opening LTH1 are not limited to... Figures 15 to 17 The arrangement and shape are shown. That is, in various other embodiments, the first opening LTH1 may be formed in another region, for example, in the region including the opening portion OPN formed in the first gate electrode GE1. In such embodiments, various modifications can be made to the layout structure so that the conductive layer is not disposed in the first opening LTH1.

[0288] The width (size or diameter) w of the first opening LTH1 can be determined by the size of the opening portion (or the area of ​​the opening portion). For example, the width w of the first opening LTH1 can be determined as the minimum width of the opening portion. In an embodiment, the width w of the first opening LTH1 in the first direction DR1 can be smaller than the width in the second direction DR2 (not shown), but the inventive concept is not limited thereto.

[0289] In one embodiment, the opening portion forming the first opening LTH1 may overlap with at least one region of the pinhole PIH in the light-blocking layer PHL. When the first opening LTH1 has an approximately octagonal shape, the pinhole PIH formed in the light-blocking layer PHL may have an approximately octagonal shape corresponding to the shape of the first opening LTH1. In such an embodiment, the size of the first opening LTH1 may be the same as or different from the size of the pinhole PIH.

[0290] In an embodiment where the size of the first opening LTH1 is smaller than the size of the pinhole PIH, the first opening array layer LTHL1 can function as a light control layer LBL that controls the path of light (e.g., restricting the field of view of reflected light to a predetermined angular range), and the light blocking layer PHL can function as a light blocking layer.

[0291] However, the inventive concept is not limited thereto. That is, in another embodiment, the size of the first opening LTH1 can be larger than the size of the pinhole PIH. In such an embodiment, the first opening array layer LTHL1 can perform a light blocking function, and the light blocking layer PHL can perform the function of a light control layer LBL that controls the path of light.

[0292] Figure 19 It is shown Figure 14 A plan view of another embodiment of the pixel layout shown. Figure 20 It shows the basis Figure 19A plan view of the light-blocking layer in the embodiment.

[0293] Reference Figures 15 to 18 Compared to the described implementation, except that the first opening LTH1 and the pinhole PIH have circular or elliptical shapes, Figure 19 and Figure 20 Implementation methods and references Figures 15 to 18 The described implementation methods are essentially the same. Therefore, with Figures 15 to 18 The same components shown are indicated by the same reference numerals, and detailed descriptions thereof will be omitted.

[0294] exist Figure 19 In the implementation, the power line PL, the initial power line IPL, and the bridging pattern BRP are not included. Figure 15 The embodiments described include the first protrusion PRT1-1 and PRT1-2, the second protrusion PRT2 and the third protrusion PRT3. Alternatively, the fourth protrusion PRT4 and the fifth protrusion PRT5 are formed on the light-emitting control line Ei and the initialization power line IPL, respectively.

[0295] Specifically, the light-emitting control line Ei may have a shape that protrudes in at least one region along the second direction DR2. For example, the light-emitting control line Ei may include a fourth protruding portion PRT4 formed in the second direction DR2. The fourth protruding portion PRT4 may be formed adjacent to the fifth source electrode SE5 and the sixth drain electrode DE6. That is, the fourth protruding portion PRT4 may have a shape that extends in the first direction DR1 from the region adjacent to the fifth contact hole CT5 to the region adjacent to the sixth contact hole CT6.

[0296] In an embodiment, the protruding surface of the fourth protrusion PRT4 may have a pattern etched on at least a portion thereof. For example, the protruding surface of the fourth protrusion PRT4 may have a planar curved shape. Here, the protruding surface may be the surface corresponding to the gap region between the fifth source electrode SE5 and the sixth drain electrode DE6. That is, the fourth protruding portion PRT4 may include a curved portion corresponding to the curved portion of the first opening LTH1 (or the closed-loop shape of the first opening LTH1) in a planar view.

[0297] The initialization power line (IPL) may have a shape protruding in at least one region in a direction opposite to the second direction DR2. For example, the initialization power line (IPL) may include a fifth protrusion PRT5 formed in a direction opposite to the second direction DR2. The fifth protrusion PRT5 may be formed adjacent to the fifth source electrode SE5 and the sixth drain electrode DE6. That is, the fifth protrusion PRT5 may have a shape extending in the first direction DR1 from a region adjacent to the fifth contact hole CT5 to a region adjacent to the sixth contact hole CT6. Specifically, the fifth protrusion PRT5 may be configured to face at least one region of the fourth protrusion PRT4.

[0298] In an embodiment, the protruding surface of the fifth protrusion PRT5 may have a pattern etched on at least a portion thereof. For example, the protruding surface of the fifth protrusion PRT5 may have a curved shape. Here, the protruding surface etched with a curved shape may be a surface corresponding to the gap region between the fifth source electrode SE5 and the sixth drain electrode DE6. Furthermore, the protruding surface etched with a curved shape may be configured to face the protruding surface etched with a curved shape of the fourth protrusion PRT4. That is, the fifth protruding portion PRT5 may include a curved portion corresponding to the curved portion of the first opening LTH1 (or the closed-loop shape of the first opening LTH1) in a plan view.

[0299] In the above embodiments, the fifth source electrode SE5 and / or the sixth drain electrode DE6 may have a shape corresponding to the shape of the fourth protrusion PRT4 and / or the fifth protrusion PRT5 in at least one region adjacent to the fourth protrusion PRT4 and / or the fifth protrusion PRT5. For example, the fifth source electrode SE5 and the sixth drain electrode DE6 may have a shape in which the edges of the fifth source electrode SE5 and the sixth drain electrode DE6 are etched in at least one region adjacent to the fourth protrusion PRT4 and / or the fifth protrusion PRT5.

[0300] The first opening LTH1 may be an opening region defined by at least a portion of the fourth protrusion PRT4 (e.g., a protruding surface), a portion of the electric field line PL, at least a portion of the fifth protrusion PRT5 (e.g., a protruding surface), a portion of the bridging pattern BRP, a portion of the fifth source electrode SE5, and a portion of the sixth drain electrode DE6. The first opening LTH1 may have a generally circular or elliptical planar shape corresponding to the planar curved shape of the protruding surfaces (or curved portions) of the fourth protrusion PRT4 and the fifth protrusion PRT5.

[0301] like Figure 19As shown, when the first opening LTH1 has a generally circular or elliptical shape, the diffraction of the incident light at the edge of the first opening LTH1 can be minimized.

[0302] In one embodiment, at least one region of the first opening LTH1 may overlap with the pinhole PIH of the light-blocking layer PHL. When the first opening LTH1 has a generally circular or elliptical shape, the pinhole PIH formed in the light-blocking layer PHL may have a generally circular or elliptical shape corresponding to the shape of the first opening LTH1. In such an embodiment, the size of the first opening LTH1 may be the same as or different from the size of the pinhole PIH.

[0303] Figure 21 It is shown Figure 14 A plan view of another embodiment of the pixel layout shown.

[0304] Reference Figures 15 to 18 Compared to the described implementation, except that the first opening LTH1 and the pinhole PIH have arbitrary polygons, Figure 21 Implementation methods and references Figures 15 to 18 The described implementation methods are essentially the same. Therefore, with Figures 15 to 18 The same components shown are indicated by the same reference numerals, and detailed descriptions thereof will be omitted.

[0305] exist Figure 21 In the implementation, the power line PL, the initial power line IPL, and the bridging pattern BRP are not included. Figure 15 The embodiments described include the first protrusions PRT1-1 and PRT1-2, the second protrusion PRT2, and the third protrusion PRT3. Alternatively, the power line PL includes a first recessed portion GRV1 and a second recessed portion GRV2.

[0306] Specifically, the power line PL may have recessed portions etched in at least one region. For example, the power line PL may include a first recessed portion GRV1 and a second recessed portion GRV2 formed at predetermined distances. For example, at least a portion of the first recessed portion GRV1 may overlap with the light-emitting control line Ei. For example, at least a portion of the second recessed portion GRV2 may overlap with the initialization power line IPL. The recessed portions GRV1 and GRV2 may have angular shapes. For example, the recessed portions GRV1 and GRV2 may have various planar shapes, such as semi-hexagonal (or trapezoidal), quadrilateral, and triangular shapes.

[0307] At this point, when the resistance of the power line PL increases due to the groove portions GRV1 and GRV2 formed in the power line PL, it may be impossible to provide sufficient power to the pixel PXL through the power line PL. Therefore, in order to reduce the resistance of the power line PL, a protrusion can be formed in at least one region, thereby sufficiently maintaining the thickness of the power line PL. For example, the power line PL may include a protrusion at a position opposite to the groove portions GRV1 and GRV2. The protrusion may have a mirror shape relative to the groove portions GRV1 and GRV2, or it may have a different shape. With the protrusion, even at the position where the groove portions GRV1 and GRV2 are formed, the width of the first direction DR1 of the power line PL can be set to approximately 2 μm to 5 μm.

[0308] Continue to refer to Figure 21 The initialization power line IPL is spaced apart from the bridging pattern BRP and the sixth drain electrode DE6 by a predetermined distance. That is, the initialization power line IPL does not overlap with the bridging pattern BRP and the sixth drain electrode DE6. Furthermore, the initialization power line IPL is spaced apart from the fifth source electrode SE5 by a predetermined distance. This arrangement expands the area of ​​the first opening LTH1 surrounded by the initialization power line IPL, the bridging pattern BRP, the fifth source electrode SE5, and the sixth drain electrode DE6.

[0309] The first opening LTH1 may be an opening portion defined by a portion of at least one region of the electric field line PL, including a first recessed portion GRV1 and a second recessed portion GRV2, a portion of the light-emitting control line Ei, a portion of the bridging pattern BRP, a portion of the initialization electric field line IPL, a portion of the fifth source electrode SE5, and a portion of the sixth drain electrode DE6. The first opening LTH1 may have a polygonal shape corresponding to the angular shapes of the first recessed portion GRV1 and the second recessed portion GRV2. For example, at least some of the vertices forming the polygonal shape of the first opening LTH1 may have acute angles, and others may have obtuse angles. At least some of the vertices forming the polygonal shape of the first opening LTH1 may have right angles.

[0310] Compared to the cases where groove portions GRV1 and GRV2 are not formed in the power line PL, Figure 21 The first opening LTH1 in the illustrated embodiment has a large area. As the area of ​​the first opening LTH1 increases, the amount of light incident through it increases. Therefore, the amount of light obtained in the sensor layer PSL increases. When fingerprint detection is performed using a larger amount of light, the accuracy of fingerprint detection can be improved.

[0311] At least one region of the opening portion forming the first opening LTH1 may overlap with the pinhole PIH of the light-blocking layer PHL. When the first opening LTH1 has a polygonal shape, the pinhole PIH formed in the light-blocking layer PHL may have the same or different polygonal shape as the first opening LTH1. In such an embodiment, the size of the first opening LTH1 may be the same as or different from the size of the pinhole PIH.

[0312] Some advantages achievable through exemplary embodiments of the present invention include a fingerprint sensor and a display device including the fingerprint sensor, wherein the display device can reduce the module thickness by integrally forming a light-transmitting region with the circuit element layer in the fingerprint sensor for a photosensitive method. Furthermore, the fingerprint sensor and the display device including the fingerprint sensor according to exemplary embodiments of the present invention can prevent or reduce light diffraction that may occur in the light-transmitting region formed in the circuit element layer.

[0313] While certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from that description. Therefore, the inventive concept is not limited to these embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. Fingerprint sensor, including: Substrate; A circuit element layer is disposed on a first surface of the substrate, the circuit element layer comprising a semiconductor layer, a conductive layer and at least one opening portion; A light-emitting element layer is disposed on the circuit element layer, and the light-emitting element layer includes at least one light-emitting element; as well as A sensor layer is disposed on the second surface of the substrate, the sensor layer including at least one photosensor corresponding to the opening portion. The opening is configured not to overlap with the semiconductor layer and the conductive layer. Wherein, the opening portion has a closed-loop shape in the plan view, and Wherein, at least a portion of the closed-loop shape includes a curve, or the interior angle of at least a portion of the closed-loop shape is an obtuse angle. The conductive layer includes: A first conductive layer includes a first electrode extending in a first direction; A second conductive layer is disposed on the first conductive layer, and the second conductive layer includes a second electrode extending in the first direction; and A third conductive layer is disposed on the second conductive layer, the third conductive layer including a third electrode extending in a second direction perpendicular to the first direction, and... In the plan view, a single opening is located between the first electrode, between the second electrode, and between the third electrode, and is defined by the first conductive layer, the second conductive layer, and the third conductive layer.

2. The fingerprint sensor according to claim 1, further comprising: A light-blocking layer, disposed between the circuit element layer and the sensor layer, has multiple pinholes.

3. The fingerprint sensor according to claim 1, wherein, The first electrode includes a first wiring extending in the first direction. The second electrode includes a second wiring spaced at a predetermined distance from the first wiring in a plan view, and the second wiring extends in the first direction. The third electrode includes a third wiring extending in the second direction and a bridging pattern spaced apart from the third wiring. The opening is defined by a portion of the first wiring, a portion of the second wiring, a portion of the third wiring, and a portion of the bridging pattern.

4. The fingerprint sensor according to claim 3, wherein, The third wiring includes at least two first protrusions projecting toward the bridging pattern in the plan view, and The at least portion of the closed-loop shape is defined by the at least two first protruding portions.

5. The fingerprint sensor according to claim 4, wherein, The first protruding portion partially overlaps with the first wiring and the second wiring, respectively.

6. The fingerprint sensor according to claim 5, wherein, The interior angles of the closed-loop shape corresponding to each of the first protruding portions are obtuse angles.

7. The fingerprint sensor according to claim 6, wherein, One side of each of the first protrusions extends in a direction intersecting each of the first direction and the second direction.

8. The fingerprint sensor according to claim 7, wherein, At least one of the first protruding portions has a trapezoidal planar shape.

9. The fingerprint sensor according to claim 4, wherein, The second wiring includes at least one second protruding portion that projects toward the first wiring in the plan view. Wherein, the second protruding portion does not overlap with the third wiring, and The first protruding portion and the second protruding portion correspond to at least a portion of the closed-loop shape.

10. The fingerprint sensor according to claim 9, wherein, The bridging pattern includes at least one third protrusion that extends toward the third wiring in the plan view. Wherein, the third protruding portion overlaps with the first wiring, and Wherein, the first protruding portion to the third protruding portion correspond to at least a portion of the closed-loop shape.

11. The fingerprint sensor according to claim 10, wherein, The opening portion has an octagonal planar shape.

12. The fingerprint sensor according to claim 3, wherein, The first wiring includes at least one fourth protrusion protruding in the second direction, and The fourth protruding portion includes a curved portion corresponding to the curve of the closed-loop shape.

13. The fingerprint sensor according to claim 12, wherein, The second wiring includes a fifth protruding portion protruding in a direction opposite to the second direction, and The fifth protruding portion includes a curved portion facing the fourth protruding portion and corresponding to the curve of the closed-loop shape.

14. The fingerprint sensor according to claim 13, wherein, The opening has a circular or elliptical planar shape.

15. The fingerprint sensor according to claim 3, wherein, The third wiring includes at least two recessed portions. Wherein, the groove portion overlaps with the first wiring portion and the second wiring portion respectively, and Wherein, the inner angle of the closed-loop shape corresponding to the groove portion is an acute angle.

16. The fingerprint sensor according to claim 15, wherein, The second wiring does not overlap with the bridging pattern.

17. The fingerprint sensor according to claim 3, wherein, The semiconductor layer includes an active pattern, the active pattern including each of a source electrode and a drain electrode, and The opening portion is further defined by a part of the active pattern.

18. The fingerprint sensor according to claim 2, wherein, The opening portion at least partially overlaps with the pinhole.

19. The fingerprint sensor according to claim 2, wherein, The size of the opening is smaller than the size of the pinhole.

20. The fingerprint sensor according to claim 2, wherein, The size of the opening is larger than the size of the pinhole.

21. A display device, including: A substrate on which pixels are disposed; A circuit element layer is disposed on a first surface of the substrate, the circuit element layer including a conductive layer in which the circuit elements of the pixel are disposed; A light-emitting element layer is disposed on the circuit element layer, the light-emitting element layer including at least one light-emitting element configured with the pixel; as well as A sensor layer is disposed on the second surface of the substrate, the sensor layer including at least one light sensor. Wherein, at least one opening portion having a closed-loop shape in the plan view is defined as not overlapping with the conductive layer, and Wherein, at least a portion of the closed-loop shape includes a curve, or the interior angle of at least a portion of the closed-loop shape is an obtuse angle. The conductive layer includes: A first conductive layer, including light-emitting control lines extending in a first direction; A second conductive layer is disposed on the first conductive layer and spaced at a predetermined distance from the light-emitting control line in a plan view. The second conductive layer includes initialization electric field lines extending in the first direction; and A third conductive layer is disposed on the second conductive layer. The third conductive layer includes electric field lines extending in a second direction perpendicular to the first direction and bridging patterns spaced apart from the electric field lines. The single opening portion is defined by a portion of the light-emitting control line, a portion of the initialization power line, a portion of the power line, and a portion of the bridging pattern.

22. The display device according to claim 21, further comprising: A light-blocking layer, disposed between the circuit element layer and the sensor layer, has multiple pinholes.

23. The display device according to claim 21, wherein, The initialization power line includes at least one second protruding portion that extends toward the light-emitting control line in the plan view. The power lines include at least two first protruding portions projecting toward the bridging pattern in the plan view. The bridging pattern includes at least one third protrusion projecting toward the power line in the plan view, and Wherein, the first protruding portion to the third protruding portion are configured as at least a portion of the closed-loop shape.

24. The display device according to claim 22, wherein, The opening portion at least partially overlaps with the pinhole.

25. The display device according to claim 22, wherein, The size of the opening is smaller than the size of the pinhole.

26. The display device according to claim 22, wherein, The size of the opening is larger than the size of the pinhole.

Images