Display Devices

Abstract

The present invention includes: a substrate including a display area and a non-display area formed outside the display area; a plurality of signal lines extending from the non-display area in a first direction on the substrate and formed in the display area; and at least one connecting line extending from a first non-display area of ​​the non-display area to a second non-display area of ​​the non-display area via the display area on the substrate. The connecting line is connected to one of the plurality of signal lines in the second non-display area.

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] With the development of multimedia, display devices are becoming more and more important. Various types of display devices such as liquid crystal display (LCD) devices and organic light emitting diode (OLED) display devices are being used.

[0003] Among display devices, an OLED display device displays images using an OLED that generates light due to recombination of electrons and holes. The OLED display device has a fast response speed, high brightness, and a large viewing angle, and can be driven with low power consumption.

[0004] Meanwhile, a display device generally displays an image only on its front surface. However, a display device that displays an image even on its side surface is being developed.

[0005] The display device transmits image signals to the display area through signal lines arranged in parallel. The display area may include a front display area and a side display area located in a direction perpendicular to the extension direction of the signal lines based on the front display area. In order to additionally arrange signal lines for transmitting image signals to the side display areas, the area of ​​the signal lines may be increased, and the non-display area of ​​the display device used as the area of ​​the signal lines may be increased. Summary of the invention

[0006] The present invention is directed to providing a display device in which a non-display area of ​​the display device is minimized and degradation of display quality is prevented.

[0007] The technical problems to be solved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned can be clearly understood by those skilled in the art to which the present invention belongs according to the following description.

[0008] One aspect of the present invention provides a display device, comprising: a substrate, including a display area and a non-display area formed on the periphery of the display area; a plurality of signal lines extending from the non-display area in a first direction to be formed in the display area on the substrate; and at least one connecting line extending from a first non-display area of ​​the non-display area to a second non-display area of ​​the non-display area by passing through the display area on the substrate, wherein the at least one connecting line is connected to any one of the plurality of signal lines in the second non-display area.

[0009] The at least one connection line may include a plurality of connection lines, and the plurality of connection lines may have different lengths.

[0010] The second non-display area may be adjacent to the first non-display area, and a length of a first connection line among the plurality of connection lines may be longer than a length of a second connection line among the plurality of connection lines.

[0011] The plurality of connection lines may be spaced apart from each other and may not cross each other in the display area.

[0012] The at least one connection line may include a first portion extending in the first direction, and the first portion may overlap one signal line among the plurality of signal lines in a thickness direction of the substrate.

[0013] The at least one connecting line may further include: a second portion extending from one end of the first portion in the second direction.

[0014] The at least one connection line may further include a third portion extending from one end of the second portion in the first direction, and the third portion may be spaced apart from the first portion.

[0015] The first non-display area may include: a corner protruding from an edge of the display area, one end of a first signal line among the plurality of signal lines may be located in the corner, a second signal line among the plurality of signal lines may be spaced apart from the corner, and the first signal line may be longer than the second signal line.

[0016] The display device may further include: an insulating layer configured to insulate at least one connecting line from the signal line, a contact hole may be formed in the second non-display area to pass through the insulating layer to expose any one of the multiple signal lines, and at least one connecting line may be directly connected to any one of the multiple signal lines through the contact hole.

[0017] The display device may further include: a plurality of driving lines, sequentially arranged in a driving area of ​​the substrate in the second direction, the driving area may be adjacent to the second non-display area and may be spaced apart from the display area, at least one driving line among the plurality of driving lines may be directly connected to at least one connecting line, and the remaining driving lines among the plurality of driving lines may be directly connected to at least one signal line among the plurality of signal lines.

[0018] The display device may further include: a first insulating layer and a second insulating layer sequentially disposed between the at least one driving line and the remaining driving lines; and a power supply voltage line disposed between the first insulating layer and the second insulating layer.

[0019] The display device may further include: an insulating layer disposed on the driving line on the substrate; and a power supply voltage line disposed on the insulating layer.

[0020] The display device may further include: a power supply voltage line arranged between the signal lines on the substrate, the power supply voltage lines may be electrically connected to each other, at least one connecting line may include a first portion extending in a first direction, and the first portion may overlap with one of the power supply voltage lines in the thickness direction of the substrate.

[0021] The at least one connection line may include a plurality of connection lines, and the plurality of connection lines may have the same length.

[0022] The second non-display area may be spaced apart from the first non-display area, and the plurality of connection lines may cross the display area.

[0023] The display device may further include: a plurality of driving lines, which are sequentially arranged in a driving area of ​​the substrate in the second direction, the driving area may include a pad connected to an external device, and may be adjacent to the second non-display area, and may be spaced apart from the display area, at least one driving line among the plurality of driving lines may be directly connected to at least one connecting line, and the remaining driving lines among the plurality of driving lines may be directly connected to at least one signal line among the signal lines.

[0024] The at least one driving line may be disposed in a layer different from a layer in which the remaining driving lines are disposed to be insulated from the remaining driving lines, and the at least one driving line may be electrically connected to the at least one connection line through a contact hole formed in the driving region.

[0025] Another aspect of the present invention provides a display device including a display area and a non-display area, the display device including: a substrate; a driving element layer, arranged on the substrate and including a transistor formed in the display area; a first insulating layer, arranged on the driving element layer; a first conductive layer, arranged on the first insulating layer and including a signal line electrically connected to a first electrode of the transistor; a second insulating layer, arranged on the first conductive layer; and a second conductive layer, arranged on the second insulating layer and including a connecting line electrically connected to the signal line, wherein the connecting line is directly connected to the signal line through a contact hole passing through the second insulating layer in the non-display area.

[0026] The connection lines may overlap the signal lines in the display area.

[0027] The first conductive layer may further include: a first power supply voltage line electrically connected to the second electrode of the transistor, and the connection line may overlap the first power supply voltage line in the display area.

[0028] A display device according to an embodiment of the present invention includes a connection line arranged in a display area for transmitting an image signal to a signal line arranged in a specific display area (eg, a side display area), thereby reducing an ineffective space of the display device.

[0029] In addition, the connection line is arranged to extend to the non-display area via the display area and is connected to the signal line through the contact hole formed in the non-display area, so that degradation of display quality due to the contact hole can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a perspective view illustrating a display device according to an embodiment.

[0031] Figure 2 It is a graphic Figure 1 An expanded view of the display device in its unfolded state.

[0032] Figure 3 It is a graphic Figure 1 A plan view of an example of a display device.

[0033] Figure 4 It is a graphic Figure 3 Magnified view of area A.

[0034] Figure 5 It is a graphic Figure 3 Magnified view of area B.

[0035] Figure 6 The diagram is included in Figure 1 A circuit diagram of an example of a pixel in a display device.

[0036] Figure 7 The diagram is along Figure 4 A cross-sectional view of an example of a display device taken along line II′.

[0037] Figure 8 The diagram is along Figure 5 A cross-sectional view of an example of a display device taken along line II-II′.

[0038] Fig. 9 The diagram is along Figure 3 A cross-sectional view of an example of a display device taken along line III-III′.

[0039] Fig.10 The diagram is along Figure 3 A cross-sectional view of another example of the display device taken along line III-III′.

[0040] Fig.11 The diagram is along Figure 4 A cross-sectional view of another example of the display device taken along line II′.

[0041] Fig.12 and Fig.13 The diagram is included in Figure 1A diagram showing an example of a connection relationship between connection lines and a driving chip in a display device.

[0042] Fig.14 It is a graphic Figure 1 A plan view of another example of a display device.

[0043] Fig.15 It is a graphic Figure 1 A plan view of yet another example of a display device.

[0044] Fig.16 It is a graphic Fig.15 Magnified view of area D.

[0045] Fig.17 The diagram is along Fig.16 sectional views of an example of a display device taken along lines IV-IV′ and VV′. DETAILED DESCRIPTION

[0046] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. From the embodiments described in detail below with reference to the accompanying drawings, the advantages and features of the present invention and the methods for achieving them will become clear. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein, and the embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art to which the present invention belongs, and the present invention is limited only by the scope of the appended claims. The same reference numerals refer to the same parts throughout the present disclosure.

[0047] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein may be used with the meanings commonly understood by those skilled in the art to which the invention belongs. In addition, unless otherwise clearly defined, the terms defined in commonly used dictionaries are not ideally or excessively interpreted.

[0048] When an element is referred to as being “on” another element or layer, it includes all cases in which the element is directly disposed on the other element or layer and another layer or element is disposed between the element and the other element or layer.

[0049] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0050] Figure 1 is a perspective view illustrating a display device according to an embodiment. Figure 2 It is a graphic Figure 1 An expanded view of the display device in its unfolded state.

[0051] refer to Figure 1 and Figure 2, the display device 1 can display an image. For example, the display device 1 may be an organic light emitting diode (OLED) display device, a liquid crystal display (LCD) device, a plasma display (PDP) device, a field emission display (FED) device, or an electrophoretic display (EPD) device, etc. Hereinafter, an example in which the display device 1 is an OLED display device will be described, but the present invention is not limited thereto.

[0052] The display device 1 can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation systems, and ultra mobile PCs (UMPCs), as well as various products such as televisions, notebook computers, monitors, billboards, and the Internet of Things.

[0053] The display device 1 may include a main display surface 10 and sub display surfaces 11 to 14 .

[0054] The main display surface 10 may have a generally plate-like shape, may be located on one surface of the display device 1, and may have the largest area (or size) among the main display surface 10 and the sub-display surfaces 11 to 14. For example, the main display surface 10 may be located on the top surface of the display device 1. The main display surface 10 may have a polygonal shape such as a rectangular shape, and a planar shape such as a circular shape or an elliptical shape.

[0055] The sub-display surfaces 11 to 14 may be located on a surface different from the surface on which the main display surface 10 is located. Each of the sub-display surfaces 11 to 14 may have an area smaller than that of the main display surface 10, and the sub-display surfaces 11 to 14 may be located on different surfaces. The sub-display surfaces 11 to 14 may each be connected to an edge of the main display surface 10, and may be bent or curved from the main display surface 10 (or an edge of the main display surface 10).

[0056] For example, when the main display surface 10 has a rectangular shape, the display device 1 may include first to fourth sub-display surfaces 11 to 14, and each of the first to fourth sub-display surfaces 11 to 14 may be connected to one of the four sides of the rectangular shape.

[0057] The first sub-display surface 11 may be connected to a first long side of the main display surface 10, and may be bent from the main display surface 10 in a vertical direction to form a left side surface of the display device 1. Similarly, the second sub-display surface 12 may be connected to a second long side of the main display surface 10, and may be bent from the main display surface 10 in a vertical direction to form a right side surface of the display device 1. The third sub-display surface 13 may be connected to a first short side of the main display surface 10 to form an upper side surface of the display device 1, and the fourth sub-display surface 14 may be connected to a second short side of the main display surface 10 to form a lower side surface of the display device 1.

[0058] In this case, the display device 1 may be a three-dimensional multi-surface display device that displays screens on a top surface and side surfaces connected to the top surface. Figure 2 In the embodiment, although the bottom surface of the display device 1 is illustrated as not including a display surface, this is exemplary, and the present invention is not limited thereto. For example, the display device 1 may further include a bottom surface for displaying an image.

[0059] The display device 1 may include a display area DA and a non-display area NDA. The display area DA may be an area in which an image is displayed, and may include a pixel PX, which is a light emitting unit as a basic unit for displaying an image. The non-display area NDA may be an area in which an image is not displayed, and may not include a pixel PX. Figure 6 Let's describe the pixel PX.

[0060] First, the display area DA may include a main display area DA0 and first to fourth sub display areas DA1 to DA4.

[0061] The main display area DA0 may be located on the main display surface 10. For example, the main display surface 10 may include only the main display area DA0. The first sub-display area DA1 may be located on the first sub-display surface 11 and connected to the main display area DA0. Similarly, the second to fourth sub-display areas DA2 to DA4 may be located on the second to fourth sub-display surfaces 12 to 14, respectively, and each of the second to fourth sub-display areas DA2 to DA4 may be connected to the main display area DA0.

[0062] In the expanded view of the display device 1, the non-display area NDA may be provided along the edge of the display area DA (or the outermost edge of the main display surface 10 and the sub-display surfaces 11 to 14 as a whole). The driving lines and the driving circuits may be provided in the non-display area NDA. The non-display area NDA may include a black matrix for blocking light leakage and decorative ink, etc., but the present invention is not limited thereto.

[0063] The non-display area NDA may include first to fourth non-display areas NDA1 to DNA4 (or first to fourth sub-non-display areas). The first non-display area NDA1 may be located on the first sub-display surface 11. Similarly, the second to fourth non-display areas NDA2 to DNA4 may be located on the second to fourth sub-display surfaces 12 to 14, respectively.

[0064] In an embodiment, the non-display area NDA (or the display device 1) may include first to fourth corner wings 21 to 24 (or corners, corner areas or corner wing areas). Each of the first to fourth corner wings 21 to 24 may be disposed adjacent to a corner of the main display surface 10 (i.e., in a portion where two sides of the main display surface 10 intersect). The first to fourth corner wings 21 to 24 may be substantially identical to one another except for their positions. In the following, common features of the first to fourth corner wings 21 to 24 will be described based on the first corner wing 21, and identical descriptions will not be repeated herein.

[0065] The first corner wing 21 may have a shape protruding outward from the corner of the main display surface 10. The first corner wing 21 may be located between the first sub-display surface 11 and the fourth sub-display surface 14 (or between the first sub-display area DA1 and the fourth sub-display area DA4, or between the first non-display area NDA1 and the fourth non-display area NDA4), and the first corner wing 21 may mitigate the intersection angle between the first sub-display surface 11 and the fourth sub-display surface 14 at an obtuse angle. One end of the first corner wing 21 may be located on the first sub-display surface 11, and the other end of the first corner wing 21 may be located on the fourth sub-display surface 14.

[0066] The first corner wing 21 may provide a space in which a signal line is disposed or through which a signal line passes. When the first sub-display surface 11 and the fourth sub-display surface 14 are bent, the first corner wing 21 may be folded inwardly (i.e., in a direction toward the inner space or the center of gravity of the display device 1). In this case, the first corner wing 21 is bent along the bending line 20 so that one end of the first corner wing 21 (i.e., the first portion adjacent to the first sub-display surface 11) and the other end of the first corner wing 21 (i.e., the second portion adjacent to the fourth sub-display surface 14) may face each other.

[0067] One end and the other end of the first corner wing 21 may be in contact with each other or connected to each other through an adhesive layer.

[0068] Since the first corner wing 21 is folded inward when the first sub-display surface 11 and the fourth sub-display surface 14 are bent, the first corner wing 21 may not be exposed to the outside. Similarly, the second corner wing 22, the third corner wing 23 and the fourth corner wing 24 may not be exposed to the outside. Therefore, the first corner wing 21 to the fourth corner wing 24 may be included in the non-display area NDA.

[0069] The non-display area NDA (or the display device 1) may further include a driving region 30, and the driving region 30 may be connected to at least one sub-display surface among the first to fourth sub-display surfaces 11 to 14. For example, the driving region 30 may be connected to one side of the fourth sub-display surface 14 (e.g., the bottom side of the fourth sub-display surface 14 in the expanded view of the display device 1).

[0070] like Figure 1 As shown in FIG. 1 , when the fourth sub-display surface 14 is vertically bent based on the main display surface 10, the driving region 30 may be vertically bent again based on the fourth sub-display surface 14 (that is, may be bent at an angle of 180° based on the main display surface 10) to be disposed below the main display surface 10 in the thickness direction of the main display surface 10. The driving region 30 may overlap with the main display surface 10 and may be parallel to the main display surface 10.

[0071] The display device 1 may include a driver chip 40 (or a pad portion on which the driver chip 40 is disposed and electrically connected to the driver chip 40), and the driver chip 40 may be disposed in the drive region 30. The driver chip 40 may generate a drive signal required to drive the pixel PX, and provide the drive signal to the display region DA (or the pixel PX). For example, the driver chip 40 may generate a data signal that determines the luminous brightness of the pixel PX. In this case, the driver chip 40 may provide the data signal to the pixel PX through a drive line (not shown) formed in the drive region 30 and a signal line (not shown) (e.g., a data line) formed on the main display surface 10 and the sub-display surfaces 11 to 14.

[0072] Hereinafter, signal lines for transmitting driving signals will be described in detail.

[0073] Figure 3 It is a graphic Figure 1 A plan view of an example of a display device. Figure 4 It is a graphic Figure 3 Magnified view of area A. Figure 5 It is a graphic Figure 3 Magnified view of area B.

[0074] refer to Figures 1 to 5, the display device 1 may include a signal line 136, a connection line 146, and a driving line 60. Meanwhile, the arrangement configuration of the signal line 136, the connection line 146, and the driving line 60 may extend in the first direction W1, and may be symmetrical based on a reference axis (not shown) passing through the center of the area of ​​the display device 1. Hereinafter, the signal line 136, the connection line 146, and the driving line 60 relatively adjacent to the first sub display surface 11 will be mainly described.

[0075] The signal lines 136 may include data lines D1 to Dm (or signal lines) (here, m is an integer greater than or equal to 3).

[0076] The data lines D1 to Dm may extend in the first direction W1 and may be sequentially arranged at specific intervals in the second direction W2. Each of the data lines D1 to Dm may extend to cross the display area DA in the first direction W1. Here, the first to k-th data lines among the data lines D1 to Dm may be disposed only on one display surface (here, k is a positive integer greater than or equal to 2 and less than m). Hereinafter, an example in which k is 7 and m is greater than 14 will be described.

[0077] For example, the first to seventh data lines D1 to D7 may extend from one end of the first non-display area NDA1 to the other end of the first non-display area NDA1 (e.g., from the lower side portion to the upper side portion) by crossing the first sub-display area DA1. The eighth to fourteenth data lines D8 to D14 may extend from the fourth non-display area NDA4 to the third non-display area NDA3 by crossing the fourth sub-display area DA4, the main display area DA0, and the third sub-display area DA3. In addition, some of the data lines D1 to Dm may extend from one corner wing among the corner wings 21 to 24 to another corner wing among the corner wings 21 to 24. For example, the third to seventh data lines D3 to D7 may extend from the first corner wing 21 to the third corner wing 23.

[0078] The connection lines 146 may electrically connect some of the signal lines 136 to some of the driving lines 60. The connection lines 146 may be disposed on a layer different from the layer on which the signal lines 136 are disposed, and the connection lines 146 may be insulated from the signal lines 136 by an insulating layer. Figure 7 It is described below.

[0079] The connection lines 146 may include first to k-th data connection lines DM1 to DMk (or first to k-th connection lines) corresponding to the first to k-th data lines D1 to Dk. When k is 7, the connection lines 146 may include first to seventh data connection lines DM1 to DM7. The first to seventh data connection lines DM1 to DM7 may correspond to the data lines D1 to D7 disposed on the first sub-display surface 11, respectively.

[0080] The first to seventh data link lines DM1 to DM7 may extend from the fourth non-display area NDA4 (e.g., the lower portion of the fourth non-display area NDA4) of the fourth sub-display surface 14 via the display area DA to one end of the corresponding signal line 136 (e.g., the lower portion of the first non-display area NDA1 and the first corner wing 21). The first to seventh data link lines DM1 to DM7 may be disposed to be spaced apart from each other by a certain interval. The intervals between the first to seventh data link lines DM1 to DM7 may be the same as the intervals between the first to seventh data lines D1 to D7.

[0081] like Figure 4 and Figure 5 As shown, the first data connection line DM1 to the seventh data connection line DM7 can extend from the fourth non-display area NDA4 of the fourth sub-display surface 14 (for example, the lower part of the fourth non-display area NDA4) in the first direction W1 (for example, the upper side), extend by turning in the second direction W2 (for example, the left side) in the display area DA, and extend to one end of the corresponding signal line 136 (that is, the lower part of the first non-display area NDA1 of the first sub-display surface 11) in an area adjacent to or intersecting with the corresponding signal line 136.

[0082] That is, each of the first to seventh data link lines DM1 to DM7 may include a first portion extending from the fourth non-display area NDA4 in the first direction W1, a second portion extending from one end of the first portion in the second direction W2, and a third portion extending from one end of the second portion in the first direction W1 (or a direction opposite to the first direction W1).

[0083] like Figure 4As shown, when viewed in a plan view, a first portion of each of the first to seventh data link lines DM1 to DM7 may overlap with one of the first to m-th data lines D1 to Dm in the display area DA. For example, a first portion of the second data link line DM2 may overlap with the ninth data line D9, and a first portion of the seventh data link line DM7 may overlap with the fourteenth data line D14. However, the above description is exemplary, and the present invention is not limited thereto. For example, when viewed in a plan view, a first portion of the first to seventh data link lines DM1 to DM7 may not overlap with the first to m-th data lines D1 to Dm in the display area DA.

[0084] In addition, if Figure 5 As shown, when viewed in a plan view, the third portion of each of the first to seventh data link lines DM1 to DM7 may be disposed to overlap one of the first to m-th data lines D1 to Dm. For example, the third portion of the first data link line DM1 may overlap the seventh data line D7, and the third portion of the second data link line DM2 may overlap the sixth data line D6.

[0085] At the same time, despite Figure 4 and Figure 5 2 and 3 , the connection line 146 is illustrated as being bent at a right angle, but the present invention is not limited thereto.

[0086] When viewed in a plan view, the first to seventh data connection lines DM1 to DM7 may not cross each other, and therefore, may be arranged by bypassing other data connection lines relatively adjacent to the first corner wing 21. For example, the first data connection line DM1 may be arranged to bypass the second data connection line DM2. That is, when the connection line 146 is adjacent to the corner wing (e.g., the first corner wing 21), the bending position of the connection line 146 may be close to the driving area 30, and when the connection line 146 is away from the corner wing, the bending position of the connection line 146 may be further spaced apart from the driving area 30.

[0087] The data connection lines relatively spaced apart from the first corner wing 21 are arranged by bypassing other data connection lines relatively adjacent to the first corner wing 21, so that the first data connection lines DM1 to the seventh data connection lines DM7 can have different lengths. For example, the length of the second data connection line DM2 can be longer than the length of the first data connection line DM1. That is, the length of the i+1th data connection line DM(i+1) can be longer than the length of the i-th data connection line DMi (here, i is a positive integer).

[0088] In one embodiment, the first to seventh data link lines DM1 to DM7 may have the same resistance value. For example, when the second data link line DM2 is longer than the first data link line DM1, the first data link line DM1 may have a width greater than that of the second data link line DM2.

[0089] The first to seventh data link lines DM1 to DM7 may be directly connected one-to-one to the first to seventh data lines D1 to D7 through the contact holes CNT formed in the lower portion of the first non-display area NDA1 and the first corner wing 21 (i.e., the contact holes CNT formed in the non-display area NDA). For example, the first data link line DM1 may be electrically connected to the seventh data line D7, and the seventh data link line DM7 may be electrically connected to the first data line D1. That is, the i-th data link line DMi may be electrically connected to the k+1-i-th data line DM(k+1-i).

[0090] The driving lines 60 may include driving lines 61a to 67a and 61b to 67b (or pad lines and pad connecting lines), and the driving lines 61a to 67a and 61b to 67b may extend from the driving chip 40 (or the pad portion on which the driving chip 40 is disposed) to the fourth non-display area NDA4 of the fourth sub-display surface 14 (or a tangent 51 between the driving area 30 and the fourth sub-display surface 14).

[0091] The driving lines 61a to 67a and 61b to 67b may be divided into a first driving line group 60a and a second driving line group 60b. The driving lines 61a to 67a included in the first driving line group 60a may be disposed on a layer different from a layer on which the driving lines 61b to 67b included in the second driving line group 60b are disposed. When viewed in a plan view, the driving lines 61a to 67a included in the first driving line group 60a may intersect with the driving lines 61b to 67b included in the second driving line group 60b. The driving lines 61a to 67a included in the first driving line group 60a may be insulated from the driving lines 61b to 67b included in the second driving line group 60b by a separate insulating layer.

[0092] The driving lines 61a to 67a included in the first driving line group 60a may be electrically connected to the data lines D1 to D7 disposed on the first sub display surface 11 through the data connection lines DM1 to DM7, respectively. The driving lines 61b to 67b included in the second driving line group 60b may be electrically connected to the data lines D8 to D14 disposed on the main display surface 10, respectively.

[0093] As described above, the display device 1 may include the connection line 146 provided via the display area DA, and the image signal is provided from the driving chip 40 to the signal line 136 (e.g., the first data line D1 to the seventh data line D7) provided on the first sub-display surface 11 (and the second sub-display surface 12) through the connection line 146. Therefore, the additional dead zone required to directly connect the signal line 136 provided on the first sub-display surface 11 (and the second sub-display surface 12) to the driving line 60 may not be necessary. That is, the increase of the invalid space can be prevented.

[0094] In addition, a contact hole CNT for electrically connecting the signal line 136 to the connection line 146 disposed in the first sub-display surface 11 (and the second sub-display surface 12) is formed in the non-display area NDA, thereby eliminating or reducing interference of the contact hole CNT with respect to the pixel PX (or the driving signal provided to the pixel PX).

[0095] Hereinafter, the configuration of the pixel PX and the influence of the contact hole CNT according to the configuration of the pixel PX will be described first, and then the relationship between the signal line 136 , the connection line 146 , and the driving line 60 will be described in detail.

[0096] Figure 6 The diagram is included in Figure 1 A circuit diagram of an example of a pixel in a display device. Figure 7 The diagram is along Figure 4 A cross-sectional view of an example of a display device taken along line II′. Figure 8 The diagram is along Figure 5 A cross-sectional view of an example of a display device taken along line II-II′. Fig. 9 The diagram is along Figure 3 A cross-sectional view of an example of a display device taken along line III-III′.

[0097] First, refer to Figure 6 , the pixel PX (or pixel circuit) may include a light emitting diode OLED, first to seventh transistors T1 to T7, and a storage capacitor Cst. The data signal DATA, the first scan signal SL1k, the second scan signal SL2k, the third scan signal SL3k, the light emitting control signal EM, and the initialization voltage VINT may be applied to the pixel PX. The data signal DATA, the first scan signal SL1k, the second scan signal SL2k, the third scan signal SL3k, the light emitting control signal EM, and the initialization voltage VINT may be obtained from the reference Figure 2 The described driving chip 40 is provided.

[0098] Each of the first to seventh transistors T1 to T7 may be a thin film transistor. Each of the first to seventh transistors T1 to T7 may be a p-channel metal oxide semiconductor (PMOS) transistor (p-channel MOS field effect transistor (FET) (MOSFET)) or an n-channel MOS (NMOS) transistor (n-channel MOSFET). Figure 6 , although the first transistor T1 to the seventh transistor T7 are illustrated as PMOS transistors, this is exemplary and the present invention is not limited thereto. For example, the first transistor T1 to the seventh transistor T7 may be NMOS transistors. As another example, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be PMOS transistors, and the third transistor T3 and the fourth transistor T4 may be NMOS transistors.

[0099] The first transistor T1 (or driving transistor) may include a first electrode connected to the first node N1, a second electrode connected to the second node N2, and a gate electrode connected to the third node N3. The first transistor T1 may provide a driving current Ioled to the light emitting diode OLED based on a voltage at the third node N3 (or a data voltage stored in the storage capacitor Cst to be described below).

[0100] The second transistor T2 (or the switching transistor) may include a first electrode connected to the data line (or a line from which the data signal DATA is received), a second electrode connected to the first node N1, and a gate electrode receiving the first scan signal SL1k (here, k is a positive integer) (or connected to the first scan line). In response to the first scan signal SL1k, the second transistor T2 may be turned on to transmit the data signal DATA to the first node N1.

[0101] The third transistor T3 may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode receiving the first scan signal SL1k (or connected to the first scan line).

[0102] The storage capacitor Cst may be connected to the third node N3 and the first power supply voltage ELVDD or may be formed between the third node N3 and the first power supply voltage ELVDD. The storage capacitor Cst may store the supplied data signal DATA.

[0103] The fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the initialization voltage line or receiving the initialization voltage VINT, and a gate electrode connected to the second scan line or receiving the second scan signal SL2k. Before the data signal DATA is stored in the storage capacitor Cst or after the light emitting diode OLED emits light, the fourth transistor T4 may be turned on in response to the second scan signal SL2k, and the third node N3 (or the storage capacitor Cst) may be initialized using the initialization voltage VINT.

[0104] The fifth transistor T5 and the sixth transistor T6 (or the first and second light emission control transistors) may be connected between the first power supply voltage line and the light emitting diode OLED and may form a current flow path through which the driving current Ioled generated by the first transistor T1 flows.

[0105] The fifth transistor T5 may include a first electrode connected to the first power voltage line to receive the first power voltage ELVDD, a second electrode connected to the first node N1, and a gate electrode connected to the light emitting control signal line or receiving the light emitting control signal EM.

[0106] Similarly, the sixth transistor T6 may include a first electrode connected to the second node N2, a second electrode connected to the fourth node N4 (or the anode electrode of the light emitting diode OLED), and a gate electrode connected to the light emitting control signal line or receiving the light emitting control signal EM.

[0107] The fifth transistor T5 and the sixth transistor T6 are turned on in response to the light emitting control signal EM. In this case, the driving current Ioled may be provided to the light emitting diode OLED, and the light emitting diode OLED may emit light with brightness corresponding to the driving current Ioled.

[0108] The seventh transistor T7 may include a first electrode connected to the fourth node N4, a second electrode connected to the initialization voltage line or receiving the initialization voltage VINT, and a gate electrode connected to the third scan line or receiving the third scan signal SL3k.

[0109] Before or after the light emitting diode OLED emits light, the seventh transistor T7 may be turned on in response to the third scan signal SL3k, and the anode electrode of the light emitting diode OLED may be initialized using the initialization voltage VINT. The light emitting diode OLED may have a parasitic capacitor formed between the anode electrode and the cathode electrode (or the second power supply voltage ELVSS), and the parasitic capacitor may be charged while the light emitting diode OLED emits light, so that the anode electrode of the light emitting diode OLED may have a specific voltage. Therefore, the light emitting diode OLED may be initialized by the seventh transistor T7.

[0110] exist Figure 6 In the embodiment, although the pixel PX has been illustrated as having a 7T1C structure including seven transistors T1 to T7 and one storage capacitor Cst, this is exemplary and the pixel PX is not limited thereto. For example, the pixel PX may have various other structures such as 2T1C, 5T1C, and 6T1C.

[0111] Each of the gate electrodes of the first to seventh transistors T1 to T7, at least a portion of the scan signal line for transmitting the scan signals SL1k, SL2k, and SL3k, and the first electrode of the storage capacitor Cst may be formed as a first gate conductive layer (or a first conductive layer) disposed coplanar with each other. In addition, the second electrode of the storage capacitor Cst may be formed as a second gate conductive layer (or a second conductive layer) disposed in a layer different from the first gate conductive layer.

[0112] In addition, each of the data lines and source and drain electrodes of the first to seventh transistors T1 to T7 may be formed as at least one of a first source / drain conductive layer (or a third conductive layer) and a second source / drain conductive layer (or a fourth conductive layer).

[0113] refer to Figure 6 and Figure 7 , the display device 1 may include a substrate 101, a buffer layer 102, a semiconductor layer 105, a first insulating layer 171, a first gate conductive layer 110, a second insulating layer 172, a second gate conductive layer 120, a third insulating layer 173, a first source / drain conductive layer 130, a fourth insulating layer 174, a second source / drain conductive layer 140, a fifth insulating layer 175, a first electrode layer 150, a light emitting element layer, and a second electrode layer 160. Reference Figure 6 The described transistors T1 to T7 may be formed on the semiconductor layer 105 or the second gate conductive layer 120. Therefore, the semiconductor layer 105 or the second gate conductive layer 120 may be collectively referred to as a driving element layer.

[0114] The substrate 101 may support each layer disposed thereon. The substrate 101 may be made of an insulating material. The substrate 101 may be made of an inorganic material such as glass or quartz, or may be made of an organic material such as polyimide. The substrate 101 may be a rigid substrate or a flexible substrate.

[0115] The buffer layer 102 may be disposed on the substrate 101. The buffer layer 102 may prevent diffusion of impurity ions and penetration of moisture or external air, and may perform a surface planarization function. The buffer layer 102 may include silicon nitride, silicon oxide, silicon oxynitride, etc. Depending on the type of the substrate 101 or process conditions, the buffer layer 102 may be omitted.

[0116] The semiconductor layer 105 may be disposed on the buffer layer 102. The semiconductor layer 105 may include a first semiconductor pattern 105_1 and a second semiconductor pattern 105_2, and the first semiconductor pattern 105_1 and the second semiconductor pattern 105_2 may form a reference Figure 6 For example, the first semiconductor pattern 105_1 may constitute a channel of the first transistor T1, and the second semiconductor pattern 105_2 may constitute a channel of the second transistor T2.

[0117] The semiconductor layer 105 may include polycrystalline silicon. Portions of the semiconductor layer 105 connected to the source electrode / drain electrode of the transistor (e.g., source region / drain region) may be doped with impurity ions (e.g., p-type impurity ions). Trivalent dopants such as boron (B) may be used as p-type impurity ions. Instead of polycrystalline silicon, the semiconductor layer 105 may include single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor such as indium tin zinc oxide (ITZO) or indium gallium zinc oxide (IGZO).

[0118] The first insulating layer 171 may be disposed on the semiconductor layer 105. The first insulating layer 171 may be a gate insulating layer having a gate insulating function.

[0119] The first gate conductive layer 110 may be disposed on the first insulating layer 171. The first gate conductive pattern 110_1 and the second gate conductive pattern 110_2 are disposed in the first gate conductive layer 110. The first gate conductive pattern 110_1 and the second gate conductive pattern 110_2 may include gate electrodes of transistors (e.g., the first transistor T1 and the second transistor T2). For example, the first gate conductive pattern 110_1 may include the gate electrode of the first transistor T1, and the second gate conductive pattern 110_2 may include the gate electrode of the second transistor T2. The first gate conductive layer 110 (or the first gate conductive pattern 110_1) may include a first electrode of the storage capacitor Cst.

[0120] The first gate conductive layer 110 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu).

[0121] The second insulating layer 172 may be disposed on the first gate conductive layer 110. The second insulating layer 172 may be an interlayer insulating layer.

[0122] The second gate conductive layer 120 may be disposed on the second insulating layer 172. The second gate conductive layer 120 may include a second electrode 121 of a storage capacitor Cst. The second electrode 121 may be disposed to overlap the first gate conductive pattern 110_1 by interposing the second insulating layer 172 between the second electrode 121 and the first gate conductive pattern 110_1 to form a storage capacitor Cst. The second gate conductive layer 120 may be formed to include a material exemplified as a constituent material of the first gate conductive layer 110.

[0123] The third insulating layer 173 may be disposed on the second gate conductive layer 120 .

[0124] The first source / drain conductive layer 130 may be disposed on the third insulating layer 173. The first source / drain conductive layer 130 may include a source electrode 132 and a drain electrode 131 of the second transistor T2, a first data pattern 133, a source electrode 134 and a drain electrode 135 of the first transistor T1, a signal line 136 (ie, reference Figure 3 The first data pattern 133 may be electrically connected to the first gate conductive pattern 110_1 through a contact hole that passes through the second insulating layer 172 and the third insulating layer 173 to expose the first gate conductive pattern 110_1. The first data pattern 133 may be electrically connected to the first gate conductive pattern 110_1 through a contact hole that passes through the second insulating layer 172 and the third insulating layer 173 to expose the first gate conductive pattern 110_1. Figure 6 Corresponding to the third node N3 shown in .

[0125] The first source / drain conductive layer 130 may include one or more metals selected from Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Ti, Ta, W, and Cu. The first source / drain conductive layer 130 may be a single layer or a multilayer. For example, the first source / drain conductive layer 130 may be formed in a stacked structure such as Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu.

[0126] The fourth insulating layer 174 may be disposed on the first source / drain conductive layer 130 , and the second source / drain conductive layer 140 may be disposed on the fourth insulating layer 174 .

[0127] The second source / drain conductive layer 140 may include a connection line 146 (ie, reference Figure 3 The connection line 146 described above may be disposed to overlap the signal line 136 when viewed in a plan view. The second source / drain conductive layer 140 may include the metal constituting the first source / drain conductive layer 130.

[0128] The fifth insulating layer 175 may be disposed on the second source / drain conductive layer 140, and the first electrode layer 150 may be disposed on the fifth insulating layer 175. The first electrode layer 150 may include an anode electrode 151 of the light emitting diode OLED, and the anode electrode 151 may be electrically connected to the source electrode 134 (or reference electrode 134) of the first transistor T1 through a contact hole passing through the fifth insulating layer 175 and the fourth insulating layer 174. Figure 6 A second electrode of the sixth transistor T6 described above).

[0129] The light emitting element layer may be disposed on the first electrode layer 150 and may include a pixel defining layer 176 and an organic layer EL. The pixel defining layer 176 may be disposed on the anode electrode 151 along an edge of the anode electrode 151 and may include an opening exposing the anode electrode 151 .

[0130] The organic layer EL may be disposed in the opening of the pixel defining layer 176. The organic layer EL may include an organic light emitting layer, a hole injection / transport layer, and an electron injection / transport layer. The second electrode layer 160 (or the cathode electrode of the light emitting diode OLED) may be disposed on the organic layer EL and the pixel defining layer 176. The second electrode layer 160 may be a common electrode disposed over the entire display area DA of the display device 1.

[0131] like Figure 6 and Figure 7 As shown, a parasitic capacitor Cpara may be formed between the signal line 136 (and the connection line 146) and the third node N3 (or the first data pattern 133 connected to the gate electrode of the first transistor T1).

[0132] First, the first parasitic capacitor C 1 may be formed between the signal line 136 and the third node N3 (or the first data pattern 133). However, due to the first parasitic capacitor C 1 The capacitance of the first parasitic capacitor C is negligible and acts equally or similarly on all pixels in the display area DA, so the capacitance of the first parasitic capacitor C can be ignored or not considered. 1 resulting in degradation of display quality.

[0133] In addition, the connection line 146 is disposed adjacent to the pixel PX, so that a second parasitic capacitor C may be formed between the connection line 146 and the third node N3. 2 When the connection line 146 has the same specifications (eg, thickness, area, length, etc.) as the signal line 136 and is disposed to overlap the signal line 136, the second parasitic capacitor C 2 The capacitance can be larger than the first parasitic capacitor C 1 The capacitance of the second parasitic capacitor C is smaller and can be ignored or not considered. 2resulting in degradation of display quality.

[0134] However, when the contact hole CNT_C for electrically connecting the signal line 136 to the connection line 146 exists in the display area DA, the third parasitic capacitor C 3 The contact hole CNT_C may be formed between the contact hole CNT_C and the third node N3. Due to the length of the contact hole CNT_C in the thickness direction, it acts as a third parasitic capacitor C 3 The area component of the third parasitic capacitor C 3 The capacitance can be relatively larger than the first parasitic capacitor C 1 capacitance, so the display quality may be due to the third parasitic capacitor C 3 For example, delay and variation occur during transmission / recording of a driving signal of a pixel PX adjacent to the contact hole CNT_C, so that the corresponding pixel PX may not emit light of desired brightness, and thus a phenomenon of stripes or spots being displayed on a displayed image may occur.

[0135] Therefore, if Figure 3 and Figure 5 As shown in , the display device 1 according to an embodiment of the present invention may include a contact hole CNT formed in the non-display area NDA instead of the display area DA, and the signal line 136 and the connection line 146 may be connected through the contact hole CNT in the non-display area NDA. Therefore, the degradation of display quality due to the contact hole CNT can be prevented or reduced.

[0136] like Figure 8 As shown in FIG. 1 , the sixth data line D6 may be disposed in the first source / drain conductive layer 130, and the second data link line DM2, the third data link line DM3, and the fourth data link line DM4 may be disposed in the second source / drain conductive layer 140, and the third data link line DM3 and the fourth data link line DM4 may be insulated from the sixth data line D6 by the fourth insulating layer 174. The second data link line DM2 may extend to one end of the sixth data line D6, and may be electrically connected to the sixth data line D6 through a contact hole CNT that passes through the fourth insulating layer 174 to expose one end of the sixth data line D6.

[0137] refer to Fig. 9 , the driving lines included in the first driving line group 60a (i.e., the driving lines connected to the connection line 146) can be set in the second gate conductive layer 120, and the driving lines included in the second driving line group 60b (i.e., the driving lines directly connected to the data lines) can be set in the first gate conductive layer 110.

[0138] The first power line 137 (or a line transmitting the second power voltage ELVSS) may be disposed between the third insulating layer 173 and the fourth insulating layer 174. Fig. 9 As shown in , the first power line 137 can be disposed over the entire driving region 30. Figure 7 As described, the connection line 146 may be disposed on the fourth insulating layer 174. Since the connection line 146 and the driving line groups 60a and 60b are spaced apart from each other and the first power line 137 is disposed therebetween, signal interference between the lines may be prevented.

[0139] As reference Figure 7 and Fig. 9 As described above, the connection line 146 is arranged to be spaced apart from the gate electrode of the first transistor T1 (and the second transistor T2 to the seventh transistor T7), and is also arranged to be further away from the signal line 136, so that the second parasitic capacitor C formed between the connection line 146 and the gate electrode of the first transistor T1 can be reduced. 2 capacitance and can be reduced due to the second parasitic capacitor C 2 This causes degradation in display quality.

[0140] In addition, since the contact hole CNT_C connecting the connection line 146 to the signal line 136 is formed in the non-display area NDA instead of the display area DA, degradation of display quality due to the contact hole CNT_C may be prevented.

[0141] In addition, the driving lines included in the first driving line group 60a and the driving lines included in the second driving line group 60b are arranged in different layers to be spaced apart from each other, and the first power line 137 (or the second power line transmitting the second power voltage ELVSS) is arranged between the connecting line 146 and the driving lines, so that signal interference between the driving lines and the connecting line 146 can be prevented, and degradation of display quality can be prevented.

[0142] Fig.10 The diagram is along Figure 3 A cross-sectional view of another example of the display device taken along line III-III′.

[0143] Reference Figure 3 , Fig. 9 and Fig.10 , display device 1_1 and Fig. 9 The display device 1 is different from the display device 1_1 in that the display device 1_1 includes a connection line 146_1 and a first power line 137_1.

[0144] The connection line 146_1 may be disposed in the first source / drain conductive layer 130 , and the first power line 137_1 (or a second power line transmitting the second power voltage ELVSS) may be disposed in the second source / drain conductive layer 140 .

[0145] The connection line 146_1 is disposed on the third insulating layer 173 and the first power line 137_1 is disposed on the fifth insulating layer 175 , thereby forming a separation structure (ie, the fifth insulating layer 175 ) on the connection line 146_1 , and thus signal interference on the connection line 146_1 may be prevented.

[0146] Fig.11 The diagram is along Figure 4 A cross-sectional view of another example of the display device taken along line II′.

[0147] refer to Figure 4 , Figure 7 and Fig.11 , display device 1_2 and Figure 7 The display device 1 is different from the display device 1 in that the display device 1_2 includes a sixth insulating layer 175_2 and a connecting line 146_2. In addition to the sixth insulating layer 175_2 and the connecting line 146_2, the display device 1_2 is different from the display device 1_2. Figure 7 The display device 1 is substantially the same or similar, and therefore, the identical description thereof will not be repeated herein.

[0148] The sixth insulating layer 175_2 may be disposed between the fifth insulating layer 175 and the first electrode layer 150. The sixth insulating layer 175_2 and the fifth insulating layer 175 may be formed as a via layer. The fifth insulating layer 175 is disposed between the connection line 146_2 and the signal line 136 so that the connection line 146_2 may be further spaced apart from the signal line 136 and the first data pattern 133.

[0149] In addition, the connection line 146_2 may be disposed on the fifth insulating layer 175. In addition, the connection line 146_2 may be disposed to overlap the first power line 137 instead of the first data pattern 133.

[0150] Therefore, signal interference of the connection line 146_2 with respect to the signal line 136 and signal interference of the connection line 146_2 with respect to the first data pattern 133 may be further reduced, and degradation of display quality may be further reduced or prevented.

[0151] Fig.12 and Fig.13 The diagram is included in Figure 1 A diagram showing an example of a connection relationship between connection lines and a driving chip in a display device.

[0152] refer to Figures 1 to 3 , Fig.12 and Fig.13The signal line 136 may include a first data line D1 to a kth data line Dk (here, k is an integer greater than or equal to 2), a k+1th data line D(k+1) to a jth data line Dj (here, j is an integer greater than k), and a j+1th data line D(j+1) to an mth data line Dm (here, m is an integer greater than j) arranged sequentially in the second direction W2.

[0153] The connection lines 146 may include first to kth data connection lines DM1 to DMk disposed on the first sub display surface 11 to correspond to the first to kth data lines D1 to Dk and j+1th to mth data connection lines DM(j+1) to DMm disposed on the second sub display surface 12.

[0154] Meanwhile, the driving chip 40 may include m output terminals sequentially arranged in the second direction W2. The m output terminals may be divided into a first terminal group K, a second terminal group J, and a third terminal group M in the second direction W2. When terminal numbers are assigned to the m output terminals based on data lines D1 to Dm corresponding to the m output terminals (or data lines D1 to Dm electrically connected to the m output terminals in a one-to-one correspondence), the terminal numbers in the first terminal group K may increase in the third direction W3 (i.e., the direction opposite to the second direction W2) (e.g., ranging from 1 to k), the terminal numbers in the second terminal group J may increase in the second direction W2 (e.g., ranging from k+1 to j), and the terminal numbers in the third terminal group M may increase in the third direction W3 (e.g., ranging from j+1 to m).

[0155] That is, the order of terminal numbers included in the first terminal group K and the third terminal group M connected to the signal line 136 through the connection line 146 may be opposite to the order of terminal numbers included in the second terminal group J.

[0156] When the driving chip 40 sequentially outputs data signals corresponding to normal image data in the second direction W2 through the output terminal, the image displayed by the first sub-display surface 11 and the second sub-display surface 12 can be reversed in the left and right directions, or can be discontinuous with the image displayed on the main display surface 10.

[0157] Therefore, when the driving chip 40 generates data signals corresponding to the data lines D1 to Dm based on the image data, the driving chip 40 can generate the data signals by inverting parts of the images corresponding to the first sub-display surface 11 and the second sub-display surface 12 in advance, or output the data signals to the output terminals included in the first terminal group K and the third terminal group M in reverse order (i.e., outputting the data signals in a reverse order to the output order of the data signals for the output terminals included in the second terminal group J).

[0158] Fig.14 It is shown Figure 1 A plan view of another example of a display device.

[0159] refer to Figures 1 to 3 and Fig.14 , display device 1_3 and Figure 3 The difference between the display device 1 and the display device 1 is that the display device 1_3 includes a connection line 146_1. In addition to the connection line 146_1, the display device 1_3 and Figure 3 The display device 1 is substantially the same or similar, and therefore, the identical description thereof will not be repeated in this article.

[0160] Connect line 146_1 to reference Figure 3 The connection lines 146 described are different in that the connection lines 146_1 include first to fifth data connection lines DM1_1 to DM5_1 (or first to k-th data connection lines).

[0161] refer to Figure 3 The first to seventh data link lines DM1 to DM7 are described as extending with a relatively short length from the fourth non-display area NDA4 of the fourth sub-display surface 14 to a lower portion of the first non-display area NDA1 of the first sub-display surface 11 adjacent to the fourth non-display area NDA4. However, the first to fifth data link lines DM1_1 to DM5_1 may extend with a relatively long length (e.g., a length similar to that of the signal line 136) from the fourth non-display area NDA4 of the fourth sub-display surface 14 to an upper portion of the first non-display area NDA1 of the first sub-display surface 11, which is spaced apart from the fourth non-display area NDA4.

[0162] That is, instead of simply passing through the display area DA, the first to fifth data link lines DM1_1 to DM5_1 may be disposed to cross the display area DA.

[0163] The first to fifth data link lines DM1_1 to DM5_1 may be connected to the first to fifth data lines D1 to D5 in a one-to-one manner through contact holes CNT formed in an upper portion of the first non-display area NDA1.

[0164] In this case, even when the reference Fig.14 When the driving chip 40 described above sequentially outputs data signals corresponding to the data lines in the second direction W2 through the output terminals, a portion of the image on the first sub-display surface 11 (and the second sub-display surface 12 ) may not be inverted.

[0165] In one embodiment, the width of each of the first to fifth data link lines DM1_1 to DM5_1 (i.e., the width in a direction perpendicular to the direction in which the first to fifth data link lines DM1_1 to DM5_1 extend) may be greater than the width of the signal line 136. In this case, the resistance value of each of the first to fifth data link lines DM1_1 to DM5_1 may be reduced, and attenuation or distortion of data signals for the first to fifth data lines D1 to D5 may be reduced.

[0166] As reference Fig.14 As described, since the connection line 146_1 crosses the display area DA to be connected with the signal line 136 in the non-display area NDA, a desired image may be displayed without changing the output order of the data signals.

[0167] In addition, since the connection line 146_1 has a greater width than that of the signal line 136 , degradation of display quality due to attenuation or distortion of a data signal may be mitigated.

[0168] Fig.15 It is a graphic Figure 1 A plan view of yet another example of a display device. Fig.16 It is a graphic Fig.15 Magnified view of area D. Fig.17 The diagram is along Fig.16 sectional views of an example of a display device taken along lines IV-IV′ and VV′.

[0169] refer to Figures 1 to 3 and Figures 15 to 17 , display device 1_4 and Figure 3 The display device 1_4 is different from the display device 1_4 in that the display device 1_4 includes a signal line 136_2, a connection line 146_2, and a driving line 60_1.

[0170] In addition to the number of data lines D1_2 to D8_2 included in the signal line 136_2, the signal line 136_2 may be Figure 3 The signal line 136 described in the foregoing description is substantially the same as or similar to the signal line 136 described in the foregoing description. In addition, except for the number of data connection lines DM1_2 to DM4_2 included in the connection line 146_2, the connection line 146_2 may be the same as the reference line 136. Figure 3 The connection lines 146 described are substantially the same or similar. Therefore, the same descriptions thereof will not be repeated herein.

[0171] like Fig.16As shown, the data link lines DM1_2 to DM4_2 may be disposed to extend to the driving area 30. When the driving area 30 is divided into a first driving area 31 adjacent to the fourth sub display surface 14 (or the display area DA) and a second driving area 32 spaced apart from the fourth sub display surface 14 and in which the driving chip 40 is disposed, the data link lines DM1_2 to DM4_2 may be disposed to extend to the first driving area 31.

[0172] Each of the data link lines DM1_2 to DM4_2 may extend in a first diagonal direction DD1 (i.e., a direction intersecting the first direction W1 with respect to the first direction W1 and pointing to the center of the region of the driving region 30) from one end of a first portion extending in the first direction W1. In addition, in the first driving region 31, the data link lines DM1_2 to DM4_2 may have different lengths. For example, an end portion of the first data link line DM1_2 may be relatively adjacent to the second driving region 32, and an end portion of the fourth data link line DM4_2 may be relatively spaced apart from the second driving region 32 and may be adjacent to the fourth sub-display surface 14. The end portions of the first to fourth data link lines DM1_2 to DM4_2 may be sequentially arranged in the first driving region 31 in the second diagonal direction DD2. Therefore, the connection line 146_2 may be cross-connected with the driving line 60_1 to be described below, or the data link lines DM1_2 to DM4_2 may be connected to the driving lines 61a_1 to 64a_1 in reverse order (ie, in reverse order to which the data link lines DM1_2 to DM4_2 are arranged).

[0173] The driving lines 60_1 may include driving lines 61a_1 to 64a_1 and driving lines 61b_1 to 64b_1. The first to fourth driving lines 61a_1 to 64a_1 may be included in the first driving line group 60a_1, and the fifth to eighth driving lines 61b_1 to 64b_1 may be included in the second driving line group 60b_1.

[0174] As reference Figure 3 As described, the first to fourth driving lines 61a_1 to 64a_1 included in the first driving line group 60a_1 may be connected to the first to fourth data link lines DM1_2 to DM4_2, and the fifth to eighth driving lines 61b_1 to 64b_1 included in the second driving line group 60b_1 may be electrically connected to the fifth to eighth data lines D5_2 to D8_2.

[0175] The fifth to eighth drive lines 61b_1 to 64b_1 included in the second drive line group 60b_1 may be connected to the fifth to eighth data lines D5_2 to D8_2 in sequence (i.e., corresponding to the same line number). However, the first to fourth drive lines 61a_1 to 64a_1 included in the first drive line group 60a_1 may be connected to the first to fourth data link lines DM1_2 to DM4_2 in reverse order. For example, the first drive line 61a_1 may be connected to the fourth data link line DM4_2, and the fourth drive line 64a_1 may be connected to the first data link line DM1_2.

[0176] The first driving line 61a_1 may extend approximately from the driving chip 40 in the first direction W1, extend by turning in the direction of the second direction W2 in the first driving region 31, and may be connected to the fourth data link line DM4_2 through the contact hole. Similarly, the second driving line 62a_1 may extend approximately from the driving chip 40 in the first direction W1, extend by turning in the direction of the second direction W2 in the first driving region 31, and may be connected to the third data link line DM3_2 through the contact hole.

[0177] The fifth to eighth driving lines 61 b_1 to 64 b_1 may extend substantially in the first direction W1 in the first driving region 31 , and may extend substantially in the first diagonal direction DD1 in the second driving region 32 to the driving chip 40 .

[0178] like Fig.17 As shown, the eighth driving line 64b_1 (or the fifth to eighth driving lines 61b_1 to 64b_1 included in the second driving line group 60b_1) may be arranged at a reference Figure 7 The first insulating layer 171 or the first gate conductive layer 110 described above may be disposed on the first insulating layer 171 or the first gate conductive layer 110. The first driving line 61a_1 (or the first to fourth driving lines 61a_1 to 64a_1 included in the first driving line group 60a_1) may be disposed on the second insulating layer 172 or the second gate conductive layer 120. The eighth data line D8_2 (or the signal line 136_2) may be disposed on the third insulating layer 173 or the first source / drain conductive layer 130, and the fourth data link line DM4_2 (or the link line 146_2) may be disposed on the fourth insulating layer 174 or the second source / drain conductive layer 140.

[0179] The eighth data line D8_2 may be electrically connected to the eighth driving line 64b_1 through a contact hole that passes through the second insulating layer 172 and the third insulating layer 173 at an end portion of the eighth data line D8_2 to expose the eighth driving line 64b_1. Similarly, the fourth data link line DM4_2 may be electrically connected to the first driving line 61a_1 through a contact hole that passes through the second insulating layer 173 and the third insulating layer 174 at an end portion of the fourth data link line DM4_2 to expose the first driving line 61a_1.

[0180] That is, the second driving line group 60b_1, the first driving line group 60a_1, the signal line 136_2, and the connection line 146_2 may be disposed in different layers, may be insulated from one another by the insulating layers 172 to 174 interposed therebetween, and may be connected to corresponding lines through contact holes.

[0181] As reference Figures 15 to 17 As described, the display device 1_4 may include driving lines 61a_1 to 64a_1 connected to the data link lines DM1_1 to DM4_2 in a reverse order (ie, in an arrangement order opposite to the arrangement order of the lines). Therefore, a desired image may be displayed without changing the output order of the data signals.

[0182] At the same time, Fig.17 Although the signal line 136_2 is illustrated as not overlapping the connection line 146_2 in the display area DA, this is exemplary in order to distinguish the signal line 136_2 from the connection line 146_2, but the present invention is not limited thereto. For example, the signal line 136_2 may overlap the connection line 146_2 in the display area DA.

[0183] In addition, Fig.17 Although the second driving line group 60b_1, the first driving line group 60a_1, the signal line 136_2 and the connection line 146_2 have been described as being sequentially arranged in an upward direction, the present invention is not limited thereto. For example, the first driving line group 60a_1 may be arranged further downward than the second driving line group 60b_1.

[0184] Those skilled in the art to which the present invention belongs will appreciate that the present invention may be implemented in a modified form without departing from the essential features of the present disclosure. Therefore, the disclosed embodiments should be considered as illustrative rather than definitive. The scope of the present invention is defined by the appended claims rather than the preceding description, and all differences within the scope of equivalents of the appended claims should be interpreted as included in the present invention.

Claims

1. A display device, comprising: A substrate including a display area and a non-display area formed around the display area; a plurality of signal lines extending from the non-display area in a first direction to be formed in the display area on the substrate; as well as at least one connecting line extends from a first non-display area of ​​the non-display area to a second non-display area of ​​the non-display area by passing through the display area on the substrate, Wherein, the at least one connecting line is connected to any one signal line among the plurality of signal lines in the second non-display area.

2. The display device according to claim 1, wherein: The at least one connecting line comprises a plurality of connecting lines, and The plurality of connection lines have different lengths.

3. The display device according to claim 2, wherein: The second non-display area is adjacent to the first non-display area, and A length of a first connection line among the plurality of connection lines is longer than a length of a second connection line among the plurality of connection lines.

4. The display device according to claim 2, wherein: The plurality of connection lines are spaced apart from each other and do not cross each other in the display area.

5. The display device according to claim 1, wherein: The at least one connecting line comprises: a first portion extending in the first direction, and The first portion overlaps one signal line among the plurality of signal lines in a thickness direction of the substrate.

6. The display device according to claim 5, wherein: The at least one connecting line further comprises: The second portion extends from one end of the first portion in a second direction.

7. The display device according to claim 6, wherein: The at least one connecting line further comprises: a third portion extending from one end of the second portion in the first direction, and The third portion is spaced apart from the first portion.

8. The display device according to claim 1, wherein: The first non-display area includes: A corner portion protruding from an edge of the display area, One end of a first signal line among the plurality of signal lines is located in the corner portion, A second signal line among the plurality of signal lines is spaced apart from the corner portion, and The first signal line is longer than the second signal line.

9. The display device according to claim 1, further comprising: an insulating layer configured to insulate the at least one connecting line from the signal line, wherein a contact hole is formed in the second non-display area to penetrate the insulating layer to expose the arbitrary one signal line among the plurality of signal lines, and The at least one connection line is directly connected to the any one signal line among the plurality of signal lines through the contact hole.

10. The display device according to claim 1, further comprising: A plurality of driving lines are sequentially arranged in a driving region of the substrate in a second direction, The driving area is adjacent to the second non-display area and is spaced apart from the display area. At least one driving line among the plurality of driving lines is directly connected to the at least one connecting line, and The remaining driving lines among the plurality of driving lines are directly connected to at least one signal line among the plurality of signal lines.

11. The display device according to claim 10, further comprising: A first insulating layer, disposed between the at least one driving line and the remaining driving lines; A second insulating layer and a third insulating layer are sequentially arranged on the at least one driving line and the remaining driving lines; as well as A power supply voltage line is arranged between the second insulating layer and the third insulating layer.

12. The display device according to claim 10, further comprising: an insulating layer, disposed on the driving line on the substrate; as well as The power supply voltage line is arranged on the insulating layer.

13. The display device according to claim 1, further comprising: a power supply voltage line disposed between the signal lines on the substrate, wherein the power supply voltage lines are electrically connected to each other, The at least one connecting line includes a first portion extending in the first direction, and The first portion overlaps one of the power supply voltage lines in a thickness direction of the substrate.

14. The display device according to claim 1, wherein: The at least one connecting line includes a plurality of connecting lines, Wherein, the plurality of connecting lines have the same length.

15. The display device according to claim 14, wherein: The second non-display area is spaced apart from the first non-display area, and The plurality of connection lines cross the display area.

16. The display device according to claim 1, further comprising: A plurality of driving lines are sequentially arranged in a driving region of the substrate in a second direction, wherein the driving area includes a pad connected to an external device, is adjacent to the second non-display area, and is spaced apart from the display area, At least one driving line among the plurality of driving lines is directly connected to the at least one connecting line, and The remaining driving lines among the plurality of driving lines are directly connected to at least one signal line among the signal lines.

17. The display device according to claim 16, wherein: The at least one driving line is disposed in a layer different from a layer in which the remaining driving lines are disposed so as to be insulated from the remaining driving lines, and The at least one driving line is electrically connected to the at least one connection line through a contact hole formed in the driving region.

18. A display device comprising a display area and a non-display area, comprising: substrate; a driving element layer disposed on the substrate and including transistors formed in the display area; A first insulating layer, disposed on the driving element layer; a first conductive layer, disposed on the first insulating layer and comprising a signal line electrically connected to the first electrode of the transistor; a second insulating layer, disposed on the first conductive layer; as well as a second conductive layer, disposed on the second insulating layer, and comprising a connecting line electrically connected to the signal line and passing through the display area, The connection line is directly connected to the signal line through a contact hole passing through the second insulating layer in the non-display area.

19. The display device according to claim 18, wherein: The connection line overlaps the signal line in the display area.

20. The display device according to claim 18, wherein: The first conductive layer further comprises: a first power supply voltage line electrically connected to the second electrode of the transistor, and The connection line overlaps the first power supply voltage line in the display area.

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