Semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a MOSFET, which is provided on a first surface on a substrate and has a first electrode portion with alloy films (4a) and (5a) formed on the upper portion; a resistor, which is provided on a second surface at a position higher than the first surface and has a second electrode portion with an alloy film (6c) and a silicon nitride film covering a portion of the alloy film (6c) formed on the upper portion; a BPSG film, which is provided on the MOSFET and the resistor; a first contact hole, which is formed in a manner of penetrating the BPSG film on the first electrode portion and reaching the alloy films (4a) and (5a); a second contact hole, which is formed in a manner of penetrating the BPSG film and the silicon nitride film on the second electrode portion and reaching the alloy film (6c); and a metal wiring, which is embedded in the first contact hole and the second contact hole.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Among semiconductor devices in which microscopic components are formed on a semiconductor substrate such as silicon, there are semiconductor devices in which semiconductor components such as resistors and fuses are formed while semiconductor components such as MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor) and MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) are formed.

[0003] For example, in order to form a MOSFET and a resistor element on the same semiconductor substrate, the following semiconductor device is considered: in order to electrically separate each element, the upper surface of the semiconductor substrate is partially oxidized to form an oxide film with a thick film thickness (LOCOS: Local Oxidation of Silicon). In this semiconductor device, a MOSFET is formed on the surface of the semiconductor substrate in the thin film thickness portion (active region) of the oxide film, and a resistor element is formed on the thick film thickness portion (field region) of the oxide film. If contact holes are formed separately from the upper surface of the insulating layer formed in a manner covering the upper surface of each element, since the setting heights of each element are different, when viewed from the surface of the flat insulating film, the contact hole of the resistor element becomes shallower, while the contact hole of the MOSFET becomes deeper. If contact holes of different depths are uniformly formed by the same etching process, the resistor element with a shallow contact hole is over-etched and penetrated. Therefore, the contact area with the metal part filled in the contact hole is reduced, and the quality may be reduced due to poor conduction.

[0004] In such a case, a technique of using a silicon nitride film as an etching stopper insulating film is known (for example, see Patent Document 1).

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2004-165236 Summary of the invention

[0008] Problems to be solved by the invention

[0009] An object of the present invention is to provide a semiconductor device capable of reducing the resistance value of a conduction path due to the formation of a contact hole and suppressing the occurrence of a malfunction due to hydrogen generated over time.

[0010] Means for solving problems

[0011] A semiconductor device according to an embodiment of the present invention as a means for solving the above-mentioned problems has:

[0012] a first semiconductor element provided on a first surface of the substrate and having a first electrode portion having a first metal silicide film formed on an upper portion;

[0013] A second semiconductor element provided on a second surface at a position higher than the first surface, and having a second electrode portion having a second metal silicide film and a hydrogen supply film covering a portion of the second metal silicide film formed on an upper portion;

[0014] an interlayer insulating film provided on the first semiconductor element and the second semiconductor element;

[0015] a first contact hole formed so as to penetrate the interlayer insulating film on the first electrode portion and reach the first metal silicide film;

[0016] a second contact hole formed so as to penetrate the interlayer insulating film and the hydrogen supply film on the second electrode portion and reach the second metal silicide film; and

[0017] The metal wiring is embedded in the first contact hole and the second contact hole.

[0018] Effects of the Invention

[0019] According to the present invention, it is possible to provide a semiconductor device capable of reducing the resistance value of a conduction path due to a contact hole and suppressing the occurrence of a malfunction due to hydrogen generated over time. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram showing a cross section of the semiconductor device in the first embodiment of the present invention.

[0021] Figure 2A It is a schematic diagram for explaining a series of process flows for manufacturing the semiconductor device in the first embodiment of the present invention.

[0022] Figure 2B It is a schematic diagram for explaining a series of process flows for manufacturing the semiconductor device in the first embodiment of the present invention.

[0023] Figure 2CIt is a schematic diagram for explaining a series of process flows for manufacturing the semiconductor device in the first embodiment of the present invention.

[0024] Figure 2D It is a schematic diagram for explaining a series of process flows for manufacturing the semiconductor device in the first embodiment of the present invention.

[0025] Figure 2E It is a schematic diagram for explaining a series of process flows for manufacturing the semiconductor device in the first embodiment of the present invention.

[0026] Figure 2F It is a schematic diagram for explaining a series of process flows for manufacturing the semiconductor device in the first embodiment of the present invention.

[0027] Figure 2G It is a schematic diagram for explaining a series of process flows for manufacturing the semiconductor device in the first embodiment of the present invention.

[0028] Figure 3 It is a schematic diagram showing a cross section of a semiconductor device in accordance with a second embodiment of the present invention. DETAILED DESCRIPTION

[0029] A semiconductor device according to an embodiment of the present invention comprises: a first semiconductor element, which is provided on a first surface on a substrate and has a first electrode portion with a first metal silicide film formed on the upper portion; a second semiconductor element, which is provided on a second surface at a position higher than the first surface and has a second electrode portion with a second metal silicide film and a hydrogen supply film covering a portion of the second metal silicide film formed on the upper portion; an interlayer insulating film, which is provided on the first semiconductor element and the second semiconductor element; a first contact hole, which is formed in a manner of penetrating the interlayer insulating film on the first electrode portion and reaching the first metal silicide film; a second contact hole, which is formed in a manner of penetrating the interlayer insulating film and the hydrogen supply film on the second electrode portion and reaching the second metal silicide film; and metal wiring, which is buried in the first contact hole and the second contact hole.

[0030] The semiconductor device according to the embodiment of the present invention is completed based on the following technical ideas.

[0031] Generally, in a semiconductor device, the first surface provided with the first semiconductor element and the second surface provided with the second semiconductor element have different heights, and the second contact hole may be shallower than the first contact hole. In this case, even if contact holes of different depths are uniformly formed by the same etching process as in the technique described in Patent Document 1, in the semiconductor device according to the embodiment of the present invention, since the hydrogen supply film present on the second electrode portion functions as an etching stopper film, the second contact hole can be formed without the second semiconductor element being overetched and penetrated.

[0032] However, in the technology described in Patent Document 1, if the metal wiring is directly in contact with the electrode portion formed of silicon at the junction of the metal wiring and the electrode portion of the semiconductor element due to the contact hole, the resistance value may increase. In addition, Patent Document 1 describes a scheme for forming a silicon nitride film (hydrogen supply film) as an etching stopper film by reduced pressure CVD, but a high temperature of about 700°C is required in reduced pressure CVD, so it is sometimes impossible to form a silicon nitride film on a metal film or an alloy film. In addition, the silicon nitride film formed by reduced pressure CVD has good crystallinity, so the permeability from the outside is low, and hydrogen treatment is required, which has the problem of increasing the number of steps.

[0033] Therefore, in order to reduce the resistance value of the junction between the metal wiring and the electrode portion, the semiconductor device of the embodiment of the present invention forms a low-resistance metal silicide film on the upper portion of the electrode portion. In addition, if the lower surface of the contact hole is formed in the metal silicide film, the lower surface (bottom surface) of the metal wiring buried in the contact hole is in contact with the low-resistance metal silicide film, so the resistance value of the junction between the metal wiring and the electrode portion can be further reduced.

[0034] In addition, the hydrogen supply film in the semiconductor device of the embodiment of the present invention does not cover the entire second semiconductor element, but only covers a portion of the second metal silicide film as an etching stopper film, thereby reducing the volume and area. As a result, the semiconductor device of the present invention can reduce the amount of hydrogen released from the hydrogen supply film over time, and can suppress the occurrence of adverse conditions caused by hydrogen. In addition, since the volume and area of ​​the hydrogen supply film are small, it is also possible to suppress the occurrence of adverse conditions caused by residual stress.

[0035] As described above, the semiconductor device according to the embodiment of the present invention can reduce the resistance value of the conduction path due to the contact hole and can suppress the occurrence of malfunctions due to hydrogen generated over time.

[0036] As an example of the semiconductor device according to the embodiment of the present invention, it is preferable to further include a metal film provided in the vicinity of an upper portion of the second semiconductor element.

[0037] In this preferred embodiment, for example, by providing a metal film through which hydrogen and moisture do not easily pass in the vicinity above the second semiconductor element, it is possible to suppress the occurrence of a malfunction due to hydrogen and moisture.

[0038] As another example of the semiconductor device according to the embodiment of the present invention, preferably, the second semiconductor element is a resistor element formed of a polysilicon film having a low-concentration impurity region and a high-concentration impurity region, and the hydrogen supply film is disposed at a position away from the low-concentration impurity region.

[0039] In this preferred embodiment, by arranging the low-concentration impurity region of the resistor body and the hydrogen supply film as the resistance element at separate positions, the resistor body is less susceptible to the influence of hydrogen released from the hydrogen supply film, thereby reducing the change in resistance value over time.

[0040] As another example of the semiconductor device according to the embodiment of the present invention, it is preferable to further include a hydrogen barrier film on the low-concentration impurity region.

[0041] In this preferred embodiment, by providing a hydrogen barrier film capable of blocking hydrogen on the low-concentration impurity region of the resistor body serving as the resistance element, the resistor body is less susceptible to the influence of hydrogen and the change in resistance value over time can be reduced.

[0042] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the following steps: a first semiconductor element forming step, forming a first semiconductor element on a first surface on a substrate, the first semiconductor element having a first electrode portion with a first metal silicide film formed on an upper portion; a second semiconductor element forming step, forming a second semiconductor element on a second surface at a position higher than the first surface, the second semiconductor element having a second electrode portion with a second metal silicide film and a hydrogen supply film covering a portion of the second metal silicide film formed on an upper portion; an interlayer insulating film forming step, forming an interlayer insulating film on the first semiconductor element and the second semiconductor element; a first contact hole forming step, forming a first contact hole in a manner of penetrating the interlayer insulating film on the first electrode portion and reaching the first metal silicide film; a second contact hole forming step, forming a second contact hole in a manner of penetrating the interlayer insulating film and the hydrogen supply film on the second electrode portion and reaching the second metal silicide film; and a metal wiring embedding step, embedding metal wiring in the first contact hole and the second contact hole.

[0043] The method for manufacturing a semiconductor device according to an embodiment of the present invention is a method for manufacturing the above-mentioned semiconductor device, and thus a semiconductor device can be manufactured that can reduce the resistance value of the conduction path caused by the contact hole and can suppress the occurrence of adverse conditions caused by hydrogen generated over time.

[0044] Next, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings.

[0045] It should be noted that, in the following, the number, position, shape, structure, size, etc. of two or more films or semiconductor elements obtained by structurally combining them are not limited to the embodiments shown below, and can be set to the number, position, shape, structure, size, etc. that are preferably used to implement the present invention.

[0046] It should be noted that the drawings are schematic diagrams, and the relationship between film thickness and plane size, the ratio of each film thickness, etc. are not as shown in the drawings.

[0047] [First embodiment]

[0048] (Semiconductor Device)

[0049] Figure 1 It is a schematic diagram showing a cross section of the semiconductor device of the present invention in the first embodiment.

[0050] like Figure 1 As shown, the semiconductor device 100 of this embodiment includes a substrate 1, an oxide film for separation 2, a gate oxide film 3, a source / drain region 4, a gate electrode 5, a polysilicon film 6, a silicon nitride film 7, a metal silicide blocking film 8, a silicon oxide film to which phosphorus and boron are added (hereinafter referred to as a "BPSG film") 9, a first contact hole 10, a second contact hole 11, a metal wiring 12, and a passivation film 13. By structurally combining these, a MOSFET 110 as an insulated gate field effect transistor and a resistor 120 are provided in the semiconductor device 100.

[0051] The substrate 1 is a wafer-shaped P-type silicon semiconductor substrate.

[0052] It should be noted that, in the present embodiment, a wafer-shaped P-type silicon semiconductor substrate is used as the substrate 1 , but the present invention is not limited thereto, and the shape, structure, size and material of the substrate 1 may be appropriately selected according to the purpose.

[0053] Here, in the substrate 1, the surface on which other films or layers are stacked using a semiconductor manufacturing process is referred to as an "upper surface", and the surface opposite to the upper surface is referred to as a "lower surface".

[0054] The isolation oxide film 2 is LOCOS (Local Oxidation of Silicon) formed on the substrate 1. A resistor element 120 is provided on the isolation oxide film 2.

[0055] Here, the surface (active region) provided with the MOSFET 110 is referred to as the “first surface S1 .” The surface (field region) provided with the resistor 120 , that is, the surface (field region) with the thicker isolation oxide film 2 is referred to as the “second surface S2 .”

[0056] It should be noted that the thickness of the separation oxide film 2 before and after the change is not particularly limited and can be appropriately selected depending on the purpose.

[0057] The MOSFET 110 as the first semiconductor element is provided on the first surface S1, and includes a gate oxide film 3, a source / drain region 4, and a gate electrode 5. Among these, the source / drain region 4 and the gate electrode 5 correspond to the first electrode portion.

[0058] The gate oxide film 3 is formed of a silicon oxide film.

[0059] It should be noted that the shape, structure, size and material of the gate oxide film 3 can be appropriately selected according to the purpose, and preferably a structure forming a self-aligned metal silicide barrier layer is formed.

[0060] The source / drain region 4 is formed by implanting impurities. In addition, an alloy film 4a of cobalt, titanium or the like is formed on the source / drain region 4 as a first metal silicide film.

[0061] It should be noted that the shape, structure, size, and type and concentration of impurities of the source / drain region 4 can be appropriately selected depending on the purpose.

[0062] In addition, in this embodiment, the first metal silicide film and the second metal silicide film are alloy films of cobalt, titanium, etc., but are not limited thereto and can be appropriately selected according to the purpose, for example, alloys of molybdenum, cobalt, titanium, nickel, etc. Examples of the alloy include MoSi, CoSi, TiSi, NiSi, etc.

[0063] The gate electrode 5 is formed of a polysilicon film and impurities are implanted in. Moreover, on the gate electrode 5, an alloy film 5a of cobalt, titanium or the like is formed on the upper portion as a first metal silicide film.

[0064] It should be noted that the shape, structure, size, material, and type and concentration of impurities of the gate electrode 5 can be appropriately selected according to the purpose.

[0065] A BPSG film 9 as an interlayer insulating film is formed on the upper surface of the MOSFET 110. First contact holes 10 are provided that penetrate the BPSG film 9 and reach the alloy film 4a and the alloy film 5a. By burying a metal wiring 12 (tungsten) in the first contact hole 10, a conduction path between the source / drain region 4 and the gate electrode 5 is formed.

[0066] It should be noted that, in the present embodiment, the interlayer insulating film is the BPSG film 9 , but the present invention is not limited thereto.

[0067] The first contact holes 10 are formed in the source / drain region 4 and the gate electrode 5 so that the lower surface of the first contact hole 10 is located in the alloy film 4a and the alloy film 5a, respectively. Therefore, the lower surface of the metal wiring 12 buried in the first contact hole 10 reaches the low-resistance alloy film 4a and the alloy film 5a, respectively, thereby reducing the resistance value of the junction between the metal wiring 12 and the first electrode portion of the MOSFET 110.

[0068] The resistor 120 as the second semiconductor element is provided on the second surface S2 higher than the first surface S1 and is formed of a polysilicon film 6. The polysilicon film 6 has a low-concentration impurity region 6a and high-concentration impurity regions 6b as second electrode portions at both ends thereof.

[0069] It should be noted that, in the present embodiment, the resistor element 120 is formed of the polysilicon film 6 , but the present invention is not limited thereto, and may be, for example, CrSiO, CrSiN, TiN, or the like.

[0070] The low-concentration impurity region 6 a serving as a resistor is adjusted to a desired resistance value by adjusting the impurity concentration and size.

[0071] An alloy film 6c of cobalt, titanium or the like having lower resistance than that of the high-concentration impurity region 6b is formed on the upper surface of the high-concentration impurity region 6b as a second metal silicide film.

[0072] The silicon nitride film 7 as the hydrogen supply film is formed so as to cover a part of the alloy film 6c. Since the silicon nitride film 7 does not cover the entire resistor element 120 but covers only a part of the alloy film 6c, even if the residual stress is significantly different from the residual stress of the adjacent film, the small volume and area can suppress the occurrence of adverse conditions due to the residual stress. In addition, in the case where the silicon nitride film 7 is formed by plasma and easily contains hydrogen, since the silicon nitride film 7 covers only a part of the alloy film 6c and has a small volume, the amount of hydrogen released from the silicon nitride film 7 over time can be reduced, and the occurrence of adverse conditions due to hydrogen can be suppressed.

[0073] In addition, the silicon nitride film 7 is disposed at a position away from the low-concentration impurity region 6a. Therefore, the low-concentration impurity region 6a is less susceptible to the influence of hydrogen released from the silicon nitride film 7, and thus the change in resistance value over time can be reduced.

[0074] It should be noted that the distance between the low-concentration impurity region 6 a and the silicon nitride film 7 is not particularly limited and may be appropriately selected according to the purpose, but is preferably not less than 1 μm and not more than 3 μm.

[0075] In this embodiment, the hydrogen supply film is made of silicon nitride film 7, but there is no limitation as long as it is a material that easily contains hydrogen and has a lower etching rate than the material of the interlayer insulating film. For example, it can be metal oxides, metal nitrides, carbon compounds, etc.

[0076] The metal silicide blocking film 8 is formed in such a manner that the entire upper surface of the low-concentration impurity region 6a serving as a resistor is covered with the low-resistance alloy film 6c, thereby not hindering its function as a resistor.

[0077] In addition, a metal silicide barrier film 8 serving as a hydrogen barrier film is formed on the entire upper surface of the low-concentration impurity region 6a and a portion of the upper surface of the high-concentration impurity region 6b, so that the low-concentration impurity region 6a is not easily affected by hydrogen annealing during manufacturing or hydrogen released over time from the silicon nitride film 7.

[0078] Furthermore, the metal silicide barrier film 8 is formed of TEOS (tetraethoxysilane) so as not to be in contact with the silicon nitride film 7. Thus, the low-concentration impurity region 6a as a resistor is not easily affected by the residual stress of the silicon nitride film 7 via the metal silicide barrier film 8, thereby suppressing changes in resistance value.

[0079] The BPSG film 9 is formed on the upper surface of the resistor element 120 similarly to the upper surface of the MOSFET 110. The second contact holes 11 are formed in the BPSG film 9 so as to penetrate the silicon nitride film 7. By embedding the metal wiring 12 in the second contact hole 11, a conduction path of the resistor element 120 is formed.

[0080] The lower surface of the second contact hole 11 is formed so as to be located in the alloy film 6c. Therefore, the lower surface of the metal wiring 12 embedded in the second contact hole 11 reaches the low-resistance alloy film 6c, thereby reducing the resistance value of the junction between the metal wiring 12 and the second electrode portion of the resistor 120.

[0081] It should be noted that, in the present embodiment, the material of the metal wiring 12 is tungsten, but the material is not limited to this and can be appropriately selected according to the purpose.

[0082] A passivation film 13 is provided as a protective film on the uppermost surface of the semiconductor device 100 .

[0083] The shape, structure, size, and material of the passivation film 13 are not particularly limited and may be appropriately selected according to the intended purpose.

[0084] In addition to the semiconductor device 100 in this embodiment, a metal film that does not easily pass hydrogen or moisture may be further provided near the upper portion of the resistor 120. The semiconductor device 100 having such a metal film can suppress the occurrence of malfunctions caused by hydrogen or moisture.

[0085] The shape, structure, size and material of the metal film are not particularly limited and may be appropriately selected according to the purpose.

[0086] (Method for manufacturing semiconductor device)

[0087] Next refer to Figure 2A to Figure 2G The schematic diagram for explaining a series of process flows for manufacturing the semiconductor device according to the first embodiment will explain the method for manufacturing the semiconductor device 100 according to the first embodiment.

[0088] A method for manufacturing a semiconductor device of the present invention includes a first semiconductor element forming step, a second semiconductor element forming step, a first contact hole forming step, a second contact hole forming step, and a metal wiring embedding step.

[0089] like Figure 2A As shown, first, a substrate 1 is prepared, and a LOCOS forming process is performed to form a separation oxide film 2 on the substrate 1 .

[0090] Next, in the first semiconductor element forming step, a gate oxide film 3, a source / drain region 4, and a gate electrode 5 are formed on the first surface S1 by conventional MOSFET manufacturing techniques such as a gate oxide film forming process, a source / drain region forming process, and a polysilicon-based gate electrode forming process. Then, alloy films 4a and 5a of cobalt, titanium, or the like are formed on the source / drain region 4 and the gate electrode 5 as the first metal silicide film.

[0091] In this way, in the first semiconductor element forming step, the MOSFET 110 having the first electrode portion with the alloy films 4 a and 5 a formed thereon is formed on the first surface S1 on the substrate 1 .

[0092] In the second semiconductor element forming step, Figure 2B As shown in FIG. 1 , a polysilicon film 6 for forming a resistor 120 is also formed on the second surface S2. In order to obtain a desired resistivity in the resistor 120, impurities are implanted by adjusting the implantation amount over the entire upper surface of the polysilicon film 6 to form a low-concentration impurity region 6a. In addition, impurities are implanted into the polysilicon film 6 by another photomask process to form a high-concentration impurity region 6b.

[0093] Next, a metal silicide blocking film 8 is formed from TEOS (tetraethoxysilane) on the entire upper surface of the low-concentration impurity region 6a and a portion of the upper surface of the high-concentration impurity region 6b. Then, an alloy film 6c of cobalt, titanium, or the like is formed as a second metal silicide film on the portion of the high-concentration impurity region 6b not covered by the metal silicide blocking film 8.

[0094] Then, if Figure 2C As shown, the silicon nitride film 7 is formed by plasma so as to cover the entire surface. In this embodiment, if the silicon nitride film 7 is formed by reduced pressure CVD, the alloy film may be melted, so the silicon nitride film 7 is formed by plasma CVD.

[0095] The method for forming the silicon nitride film 7 is not particularly limited and may be appropriately selected according to the purpose. However, a method using plasma is preferred because the film formation temperature can be reduced.

[0096] Then, if Figure 2D As shown, the silicon nitride film 7 is processed into a portion covering the alloy film 6 c in a manner not to contact the metal silicide barrier film 8 by photomask processing and etching processing, and the polysilicon film 6 and the silicon nitride film 7 are processed into the shape of the resistor element 120 .

[0097] It should be noted that the etching process for the silicon nitride film 7 is not particularly limited and may be appropriately selected depending on the purpose. For example, wet etching, anisotropic or isotropic dry etching, and the like may be mentioned.

[0098] Thus, in the second semiconductor element forming step, the resistor element 120 having the second electrode portion having the alloy film 6c formed thereon and the silicon nitride film 7 covering a portion of the alloy film 6c is formed on the second surface S2 located higher than the first surface S1.

[0099] Next, in the interlayer insulating film forming step, as shown in FIG. Figure 2E As shown, a BPSG film 9 is formed as an interlayer insulating film.

[0100] There is no particular limitation on the method for forming the BPSG film 9, and it can be appropriately selected according to the purpose. In addition, there is no particular limitation on the method for planarizing the BPSG film 9, and it can be appropriately selected according to the purpose, for example, a reflow method, an etch-back method, a CMP (Chemical Mechanical Polishing) method, etc. Regarding the reflow method, specifically, after forming an oxide film containing phosphorus or boron, planarization can be performed by heat treatment at 850° C. or above.

[0101] In this way, in the interlayer insulating film forming step, the BPSG film 9 is formed on the MOSFET 110 and the resistor 120 .

[0102] Next, in the first contact hole forming step and the second contact hole forming step, as shown in FIG. Figure 2F As shown, the necessary parts such as the source / drain region 4, the gate electrode 5, and the second electrode portion of the resistor 120 are subjected to photomask processing, and the first contact hole 10 and the second contact hole 11 are formed uniformly by dry etching. At this time, the first surface S1 provided with the MOSFET 110 and the second surface S2 provided with the resistor 120 have different heights from the bottom surface of the substrate 1 as a height reference, and the second contact hole 11 is shallower than the first contact hole 10. In this case, in the semiconductor device 100 of the present embodiment, even if contact holes of different depths are uniformly formed by the same etching process, since the silicon nitride film 7 existing on the second electrode portion functions as an etching stopper film, the second contact hole 11 can be formed without excessively corroding and penetrating the resistor 120.

[0103] Thus, in the first contact hole forming step, the first contact hole 10 is formed so as to penetrate the BPSG film 9 on the first electrode portion and reach the alloy films 4a and 5a. In addition, in the second contact hole forming step, the second contact hole 11 is formed so as to penetrate the BPSG film 9 and the silicon nitride film 7 on the second electrode portion and reach the alloy film 6c.

[0104] Next, in the metal wiring embedding process, Figure 2G As shown, by embedding tungsten as the metal wiring 12 in the first contact hole 10 and the second contact hole 11, conduction paths of the MOSFET 110 and the resistor 120 are formed respectively.

[0105] In this way, in the metal wiring embedding step, the metal wiring 12 is embedded in the first contact hole 10 and the second contact hole 11 .

[0106] And, finally, a passivation film 13 is formed as a protective film on the entire upper surface.

[0107] The semiconductor device 100 of this embodiment can be manufactured in this manner.

[0108] It should be noted that when the gate electrode 5 is formed using a polysilicon film, the polysilicon film 6 for forming the resistor 120 may also be formed on the second surface S2 .

[0109] In addition, when alloy films 4a and 5a of cobalt, titanium, etc. are formed as the first metal silicide film on the upper part of the source / drain region 4 and the gate electrode 5, an alloy film 6c of cobalt, titanium, etc. can be formed as the second metal silicide film on the upper part of the low-concentration impurity region 6a not covered by the metal silicide barrier film 8.

[0110] At this time, as for the impurities, phosphorus, arsenic, etc. are used when the region is made N-type, and boron, BF2, etc. are used when the region is made P-type. The amount of impurity injection depends on the desired resistivity, for example, 1×10 15 atoms / cm 3 Up to 1×10 22 atoms / cm 3 This impurity injection process can also serve as an impurity injection process for forming the source / drain region 4 of the MOSFET 110. Specifically, when injecting N-type impurities into the resistor element 120, the impurities can be injected by the same process as the impurities used when forming the N-type source / drain region. In addition, when injecting P-type impurities into the resistor element 120, the impurities can be injected by the same process as the impurities used when forming the P-type source / drain region.

[0111] [Second embodiment]

[0112] Figure 3 It is a schematic diagram showing a cross section of a semiconductor device in accordance with a second embodiment of the present invention.

[0113] like Figure 3As shown, in the semiconductor device 100 of the second embodiment, the resistor element 120 as the second semiconductor element in the first embodiment is replaced with a fuse 130 and the film on the upper surface of the fuse 130 is opened. The semiconductor device 100 of the second embodiment is the same as the semiconductor device 100 of the first embodiment.

[0114] The fuse 130 includes a high-concentration impurity region 14a and an alloy film 14b of cobalt, titanium, etc. covering the entire upper surface of the high-concentration impurity region 14a. In addition, a silicon nitride film 7 that functions as an etching stopper is formed on a portion of the upper surface of the alloy film 14b of cobalt, titanium, etc. In other words, the fuse 130 is provided on the second surface S2 at a position higher than the first surface S1, and has a second electrode portion having the alloy film 14b and the silicon nitride film 7 covering a portion of the alloy film 14b formed on the upper portion. In addition, unlike the resistor element 120, the fuse 130 has a structure in which the second electrode portion is spread over the entire element.

[0115] The fuse 130 functions by irradiating energy from the opening as necessary, thereby melting the high-concentration impurity region 14 a and the alloy film 14 b .

[0116] It is clear that when the alloy film 14b is in contact with the silicon nitride film 7 over an area greater than a certain level, a gap is formed due to the difference in thermal stress, and moisture penetrates into the gap. Therefore, in the fuse 130, as in the resistor element 120, the silicon nitride film 7 is formed only on a portion of the upper surface of the alloy film 14b.

[0117] It should be noted that the first semiconductor element and the second semiconductor element are MOSFET110 and resistor element 120 in the first embodiment, and are MOSFET110 and fuse 130 in the second embodiment, but are not limited to this. For example, they may also be any one of MOSFET, MOSFET, capacitor, resistor element, fuse, etc.

[0118] As described above, the semiconductor device of the present invention comprises: a first semiconductor element, which is arranged on the first surface of the substrate and has a first electrode portion with a first metal silicide film formed on the upper portion; a second semiconductor element, which is arranged on the second surface at a position higher than the first surface and has a second electrode portion with a second metal silicide film and a hydrogen supply film covering a portion of the second metal silicide film formed on the upper portion; an interlayer insulating film, which is arranged on the first semiconductor element and the second semiconductor element; a first contact hole, which is formed in a manner of penetrating the interlayer insulating film on the first electrode portion and reaching the first metal silicide film; a second contact hole, which is formed in a manner of penetrating the interlayer insulating film and the hydrogen supply film on the second electrode portion and reaching the second metal silicide film; and metal wiring, which is buried in the first contact hole and the second contact hole.

[0119] Thus, the semiconductor device of the present invention can reduce the resistance value of the conduction path caused by the contact hole and can suppress the occurrence of malfunctions caused by hydrogen generated over time.

[0120] Explanation of symbols

[0121] 1 substrate

[0122] 2 Separation oxide film

[0123] 3 Gate oxide film

[0124] 4 Source and drain regions

[0125] 4a Alloy film (first metal silicide film)

[0126] 5. Gate electrode

[0127] 5a Alloy film (first metal silicide film)

[0128] 6 Polysilicon film

[0129] 6a Low concentration impurity area

[0130] 6b High concentration impurity region

[0131] 6c Alloy film (second metal silicide film)

[0132] 7 Silicon nitride film (hydrogen supply film)

[0133] 8 Metal silicide barrier film (hydrogen barrier film)

[0134] 9 BPSG film (interlayer insulation film)

[0135] 10 1st contact hole

[0136] 11. Second contact hole

[0137] 12 Metal wiring

[0138] 13 Passivation film

[0139] 14a High concentration impurity area

[0140] 14b Alloy film (second metal silicide film)

[0141] 100 Semiconductor devices

[0142] 110 MOSFET

[0143] 120 Resistor

[0144] 130 Fuse

[0145] S1 Page 1

[0146] S2 Page 2

Claims

1. A semiconductor device, characterized in that: It has: a first semiconductor element provided on a first surface of the substrate and having a first electrode portion having a first metal silicide film formed on an upper portion; a second semiconductor element provided on a second surface at a position higher than the first surface, and having a second electrode portion having a second metal silicide film and a hydrogen supply film covering a portion of the second metal silicide film formed on an upper portion; an interlayer insulating film provided on the first semiconductor element and the second semiconductor element; a first contact hole formed so as to penetrate the interlayer insulating film on the first electrode portion and reach the first metal silicide film; a second contact hole formed so as to penetrate the interlayer insulating film and the hydrogen supply film on the second electrode portion and reach the second metal silicide film; as well as a metal wiring embedded in the first contact hole and the second contact hole, The second semiconductor element is a resistor element formed of a polysilicon film having a low-concentration impurity region and a high-concentration impurity region. The hydrogen supply film is disposed at a position away from the low-concentration impurity region.

2. The semiconductor device according to claim 1, wherein: The device further includes a metal film provided in the vicinity of an upper portion of the second semiconductor element.

3. The semiconductor device according to claim 1, wherein: A hydrogen barrier film is further provided on the low-concentration impurity region.

4. A method for manufacturing a semiconductor device, characterized in that: It includes the following steps: a first semiconductor element forming step of forming a first semiconductor element on a first surface of a substrate, the first semiconductor element having a first electrode portion having a first metal silicide film formed on an upper portion; a second semiconductor element forming step of forming a second semiconductor element on a second surface at a position higher than the first surface, the second semiconductor element having a second electrode portion, the second electrode portion being formed with a polysilicon film having a low-concentration impurity region and a high-concentration impurity region, a second metal silicide film being formed on an upper portion of the high-concentration impurity region, and a hydrogen supply film being formed at a position covering a portion of the second metal silicide film and away from the low-concentration impurity region; an interlayer insulating film forming step of forming an interlayer insulating film on the first semiconductor element and the second semiconductor element; a first contact hole forming step of forming a first contact hole so as to penetrate the interlayer insulating film on the first electrode portion and reach the first metal silicide film; a second contact hole forming step of forming a second contact hole so as to penetrate the interlayer insulating film and the hydrogen supply film on the second electrode portion and reach the second metal silicide film; as well as The metal wiring embedding step embeds the metal wiring in the first contact hole and the second contact hole.

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