Semiconductor device

Abstract

A semiconductor device is provided, including a device isolation layer defining a first active region and a second active region; a buried contact connected to the second active region; and a first bit line structure and a second bit line structure disposed on the first active region and the second active region. Each of the first bit line structure and the second bit line structure includes a bit line contact portion and a bit line pass portion. The bit line contact portion is electrically connected to the first active region. The bit line pass portion is disposed on the device isolation layer. A height of a lowest portion of the buried contact is less than a height of a lowest portion of the bit line pass portion. The height of the lowest portion of the buried contact is greater than a height of a lowest portion of the bit line contact portion. A lower end of the bit line pass portion is buried in the second active region.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0119542, filed on September 27, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device, and more specifically, to a semiconductor device comprising a plurality of intersecting wiring lines and buried contacts, and a method of manufacturing the semiconductor device. Background Technology

[0003] As semiconductor devices become more highly integrated, individual circuit patterns are becoming smaller in order to implement more semiconductor devices in the same area. For example, as the integration level of semiconductor devices increases, the design specifications of semiconductor device components decrease.

[0004] In highly miniaturized semiconductor devices, the process of forming multiple wiring lines and multiple buried contacts inserted between the wiring lines is becoming increasingly complex and difficult. Summary of the Invention

[0005] This disclosure provides a semiconductor device with improved reliability and performance.

[0006] This disclosure also provides a method for manufacturing a semiconductor device with improved reliability and performance.

[0007] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the detailed description of the disclosure given below.

[0008] According to an exemplary embodiment of the present invention, a semiconductor device includes: a device isolation layer formed in a substrate and defining a first active region and a second active region spaced apart from each other in a first direction; a buried contact connected to the second active region; a first bit line structure disposed on the first active region and extending in a second direction different from the first direction; and a second bit line structure spaced apart from the first bit line structure in the first direction and disposed on the second active region. Each of the first bit line structure and the second bit line structure includes a bit line stack extending in the second direction. Each of the first bit line structure and the second bit line structure includes bit line contact portions and bit line passage portions alternately arranged in the second direction. The bit line contact portion of the first bit line structure is disposed on the first active region and electrically connected to the first active region. The bit line passage portion of the second bit line structure is disposed on the device isolation layer. The lowest portion of the buried contact is at a lower height from the bottom surface of the device isolation layer than the lowest portion of the bit line passage portion of the second bit line structure is at a higher height from the bottom surface of the device isolation layer. The lowest portion of the buried contact is at a higher height from the bottom surface of the device isolation layer than the lowest portion of the bit line contact portion of the first bit line structure is at a higher height from the bottom surface of the device isolation layer. The bit lines of the second bit line structure are partially buried in the second active region at their lower ends.

[0009] According to an exemplary embodiment of the present invention, a semiconductor device includes: a device isolation layer formed in a substrate and defining a first active region and a second active region spaced apart from each other in a first direction; a buried contact connected to the second active region; a first bit line structure disposed on the first active region and extending in a second direction different from the first direction; and a second bit line structure disposed on the second active region and spaced apart from the first bit line structure in the first direction. Each of the first bit line structure and the second bit line structure includes a bit line spacer, a bit line stack filling a portion of a bit line trench defined by the bit line spacer, and a bit line mask pattern disposed on the bit line stack. Each of the first bit line structure and the second bit line structure includes bit line contact portions and bit line through portions alternately arranged in the second direction. The bit line contact portion of the first bit line structure is electrically connected to the first active region. The lower end of the bit line through portion of the second bit line structure is buried in the second active region. The bit line spacer includes a lower bit line spacer and an upper bit line spacer. The lower bit line spacer is disposed on a portion of each sidewall of the bit line stack. The upper bit line spacer is disposed on the lower bit line spacer.

[0010] According to an exemplary embodiment of the present invention, a semiconductor device includes: a device isolation layer formed in a substrate and defining a first active region and a second active region spaced apart from each other in a first direction, each of the first active region and the second active region including a pair of memory connection regions and a bit line connection region disposed between the pair of memory connection regions; a pair of word lines extending in the first direction and disposed in the substrate and the device isolation layer, the pair of word lines being spaced apart from each other in a second direction different from the first direction, and one of the bit line connection regions of the first active region and the pair of memory connection regions of the second active region being disposed between the pair of word lines and spaced apart from each other in the first direction; a buried contact connected to one of the pair of memory connection regions; a first bit line structure extending in the second direction and disposed on the bit line connection region of the first active region; a second bit line structure extending in the second direction and disposed on the bit line connection region of the second active region; a pad disposed on the buried contact and connected to a mask contact; and a memory capacitor disposed on the pad and connected to the pad. Each of the first first bit line structure and the second bit line structure includes a bit line contact portion and a bit line through portion. The bit line contact portions of each of the first and second bit line structures are electrically connected to the bit line connection regions of each of the first and second active regions, respectively. The lowest portion of the buried contact is lower than the lowest portion of the bit line through portion of the second bit line structure. The lowest portion of the buried contact is higher than the lowest portion of the bit line contact portion of the first bit line structure. The lower end of the bit line through portion of the second bit line structure is buried in one of a pair of memory connection regions in the second active region.

[0011] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate including a cell region, a peripheral region, and a cell boundary region between the cell region and the peripheral region; a device isolation layer formed in the substrate of the cell region and defining an active region; a bit line stack configured to extend across the cell region and the cell boundary region and electrically connected to the active region; and a bit line peripheral contact connected to the bit line stack in the cell boundary region. The bit line stack includes a semiconductor material pattern connected to the active region and a metal conductive layer pattern disposed on the semiconductor material pattern. The thickness of the metal conductive layer pattern in the cell region is greater than the thickness of the metal conductive layer pattern in the cell boundary region. Attached Figure Description

[0012] These and / or other aspects will become more apparent and readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0013] Figure 1This is a schematic layout diagram of the cell regions of a semiconductor device according to an embodiment;

[0014] Figure 2 It includes Figure 1 A schematic layout diagram of semiconductor devices in a unit region;

[0015] Figure 3 yes Figure 1 The layout diagram of the single-character lines and active regions;

[0016] Figure 4A and Figure 4C It is along Figure 1 A cross-sectional view taken from line AA according to different embodiments;

[0017] Figure 4B yes Figure 4A A magnified view of part P;

[0018] Figure 5 It is along Figure 1 A sectional view taken by line BB;

[0019] Figure 6A and Figure 6B It is along Figure 2 A cross-sectional view taken by line CC according to different embodiments;

[0020] Figures 7 to 10 A semiconductor device according to an embodiment is shown according to different embodiments;

[0021] Figures 11 to 13 A semiconductor device according to an embodiment is shown according to different embodiments;

[0022] Figures 14 to 16 A semiconductor device according to an embodiment is shown according to various embodiments; and

[0023] Figures 17A to 34C This is a view illustrating the steps of a method for manufacturing a semiconductor device according to an embodiment. Detailed Implementation

[0024] Figure 1 This is a schematic layout diagram of cell region 20 of a semiconductor device according to an embodiment. Figure 2 It includes Figure 1 A schematic layout diagram of the semiconductor device in cell region 20. Figure 3 It has Figure 1 The layout diagram of the word line WL and the active region ACT. Figure 4A and Figure 4C It is along Figure 1 The sectional view taken by line AA according to different embodiments. Figure 4B yes Figure 4AEnlarged view of part P. Figure 5 It is along Figure 1 The sectional view taken by line BB. Figure 6A and Figure 6B It is along Figure 2 The cross-sectional view is taken from the CC line according to different embodiments. For reference, Figure 6A and Figure 6B It can be along Figure 1 The figure shows a cross-sectional view of the bit line BL according to different embodiments. Dynamic random access memory (DRAM) is shown as an example in the accompanying drawings of the semiconductor device according to an embodiment.

[0025] Reference Figures 1 to 3 The semiconductor device according to the embodiment may include a cell region 20, a cell boundary region 22, and a peripheral region 24.

[0026] The unit boundary region 22 can be formed along the edge of the unit region 20. The unit boundary region 22 can separate the unit region 20 from the surrounding region 24.

[0027] Unit region 20 may include multiple active regions ACT. The active regions ACT may be formed on substrate 100 (see [reference]). Figure 4A Device isolation layer 105 in ) (see Figure 4A (Limitation). As the design dimensions of semiconductor devices shrink, the active region ACT can be set in the form of diagonal lines or slanted bars as shown in the attached figure. For example, the active region ACT can extend along the third direction D3.

[0028] Multiple gate electrodes may extend across the active region ACT in a first direction D1. The gate electrodes may extend parallel to each other. The gate electrodes may be, for example, multiple word lines WL. The word lines WL may be arranged at equal intervals (i.e., spaced apart) in a second direction D2, different from the first direction D1. The width of each word line WL or the spacing between adjacent word lines WL may be determined according to design specifications. The first direction D1, the second direction D2, and the third direction D3 may correspond to and differ from each other in a horizontal direction relative to the upper surface of the substrate 100. For example, the third direction D3 may correspond to the diagonal direction between the first direction D1 and the second direction D2.

[0029] Each of the active regions ACT can be divided into three parts by two word lines WL extending in the first direction D1. Each of the active regions ACT may include a memory connection region 103b and a bit line connection region 103a. The bit line connection region 103a may be located in the middle portion of each of the active regions ACT, and the memory connection regions 103b may be located at opposite ends of each of the active regions ACT. For example, the bit line connection region 103a may be disposed between the two word lines WL intersecting each of the active regions ACT. One of the two word lines WL may be disposed between the bit line connection region 103a and one of the two memory connection regions 103b, and the other may be disposed between the bit line connection region 103a and the other of the two memory connection regions 103b.

[0030] Multiple bit lines BL can be positioned on word lines WL and extend in a second direction D2 orthogonal to the word lines WL. Bit lines BL can extend parallel to each other. Bit lines BL can be positioned at equal intervals (i.e., spaced apart) in a first direction D1. The width of each bit line BL or the spacing between adjacent bit lines BL can be determined according to design specifications.

[0031] The semiconductor device according to the embodiments may include various contact arrays formed on the active region ACT. The various contact arrays may include, for example, direct contacts DC, buried contacts BC, and pads LP.

[0032] Here, the direct contact DC can be a contact that electrically connects the active region ACT to the bit line BL. The buried contact BC can be a contact that connects the active region ACT to the lower electrode 191 of the capacitor (see...). Figure 4A The contact area between the buried contact BC and the active region ACT may be small due to the arrangement. Therefore, a conductive pad LP can be introduced to increase the contact area between the buried contact BC and the active region ACT, and also to increase the contact area between the buried contact BC and the lower electrode 191 of the capacitor (see...). Figure 4A ) contact area.

[0033] A pad LP may be disposed between the buried contact BC and the lower electrode 191 of the capacitor. Although not shown, the pad LP may be disposed between the active region ACT and the buried contact BC. In the semiconductor device according to the embodiment, the pad LP may be disposed between the buried contact BC and the lower electrode 191 of the capacitor. The increased contact area by introducing the pad LP can reduce the contact resistance between the active region ACT and the lower electrode 191 of the capacitor.

[0034] Direct contacts DC can be connected to bit line connection area 103a. Buried contacts BC can be connected to storage connection area 103b. Since the buried contacts BC are located at opposite ends of each active region ACT, pads LP can be configured to be adjacent to opposite ends of each active region ACT, so as to partially overlap with the buried contacts BC. For example, the buried contacts BC can be formed with the active regions ACT and device isolation layer 105 located between adjacent word lines WL and adjacent bit lines BL (see...). Figure 4A Stacked.

[0035] Word lines WL can be embedded in the substrate 100. Word lines WL can intersect with active regions ACT located between direct contacts DC or embedded contacts BC. As shown, two word lines WL can intersect with one active region ACT. Since the active region ACT extends in the third direction D3, word lines WL can form an angle of less than 90 degrees with the active region ACT.

[0036] Direct contacts (DC) and buried contacts (BC) can be symmetrically or repeatedly arranged on the active region ACT. For example, direct contacts (DC) can be spaced apart from each other in the first direction D1 and the second direction D2, and buried contacts (BC) can be spaced apart from each other in the first direction D1 and the second direction D2. Unlike direct contacts (DC) and buried contacts (BC), pads (LP) can be arranged in a zigzag pattern on the active region ACT along the second direction D2 where bit lines (BL) extend. Additionally, pads (LP) can be stacked on the same side of each bit line (BL) along the first direction D1 where word lines (WL) extend. For example, each pad (LP) in the first row can be stacked on the left side of the corresponding bit line (BL), and each pad (LP) in the second row can be stacked on the right side of the corresponding bit line (BL).

[0037] Reference Figures 1 to 6B The semiconductor device according to the embodiment may include a plurality of gate structures 110, a plurality of bit line structures 130, a plurality of memory contacts 120 and an information storage unit (i.e., memory capacitor) 190.

[0038] The substrate 100 may be, for example, bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100 may be, but is not limited to, a silicon substrate or a substrate made of another material such as silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In the following description, the substrate 100 will be described as a silicon substrate.

[0039] Device isolation layer 105 can be formed in substrate 100. Device isolation layer 105 can have a shallow trench isolation (STI) structure, which has superior device isolation characteristics. Device isolation layer 105 can define an active region ACT in substrate 100. The active region ACT defined by device isolation layer 105 can be shaped similarly to... Figure 1 The islands shown all include both short and long axes. The active region ACT can be shaped to resemble a diagonal line forming an angle of less than 90 degrees with the word line WL formed in the device isolation layer 105. Alternatively, the active region ACT can be shaped to resemble a diagonal line forming an angle of less than 90 degrees with the bit line BL formed on the device isolation layer 105.

[0040] A cell boundary separation layer with an STI structure can be formed in the cell boundary region 22.

[0041] The device isolation layer 105 may include at least one of, for example, a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Although in Figures 4A to 5 The intermediate device isolation layer 105 is formed as a single insulating layer, but this is merely for ease of description, and the embodiments are not limited to this. Additionally, the cell boundary separation layer may include at least one of, for example, a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0042] exist Figure 6A and Figure 6B In this embodiment, the upper surface of the device isolation layer 105, the upper surface of the substrate 100, and the upper surface of the cell boundary separation layer of the cell boundary region 22 are located in the same plane (i.e., coplanar). However, this is merely for ease of description, and the embodiments are not limited to this case.

[0043] A gate structure 110 may be formed in the substrate 100 and the device isolation layer 105. The gate structure 110 may be formed across the device isolation layer 105 and the active region ACT defined by the device isolation layer 105. A gate structure 110 may be formed in the substrate 100 and the device isolation layer 105 positioned along a first direction D1 along which the gate structure 110 extends. Each of the gate structures 110 may include a gate trench 114, a gate insulating layer 111, a gate electrode 112, and a gate overlay pattern 113 formed in the substrate 100 and the device isolation layer 105. Here, the gate electrode 112 may correspond to a word line WL.

[0044] The gate insulating layer 111 may extend along the sidewalls and bottom surface of the gate trench 114. The gate insulating layer 111 may extend along the contour of at least a portion of the gate trench 114. The gate insulating layer 111 may comprise silicon oxide, silicon nitride, silicon oxynitride, or a high-k material having a higher dielectric constant than silicon oxide. High-k materials may include, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0045] The gate electrode 112 may be formed on the gate insulating layer 111. The gate electrode 112 may fill a portion of the gate trench 114.

[0046] The gate electrode 112 may include, for example, polysilicon, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum carbonitride (TaCN). The following are at least one of the following: tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof.

[0047] A gate overlay pattern 113 may be formed on the gate electrode 112. The gate overlay pattern 113 may fill the portion of the gate trench 114 except for the portion in which the gate electrode 112 is formed. Although the gate insulating layer 111 is shown extending along the sidewall of the gate overlay pattern 113, the embodiment is not limited to this.

[0048] The gate cover pattern 113 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and combinations thereof.

[0049] exist Figure 5In this process, the location of the lowest portion of the gate structure 110 formed in the substrate 100 may differ from the location of the lowest portion of the gate structure 110 formed in the device isolation layer 105. This difference arises from the difference between the etching rate of the substrate 100 and the etching rate of the device isolation layer 105 during the process of forming the gate trench 114. Although not shown, an impurity-doped region may be formed on at least one side of each gate structure 110. The impurity-doped region may be a source / drain region of a transistor.

[0050] Each bit line structure 130 may be formed on a substrate 100 and a device isolation layer 105 in which a gate structure 110 is formed or buried. Each bit line structure 130 may intersect with the device isolation layer 105 and an active region ACT defined by the device isolation layer 105. Each bit line structure 130 may include a bit line contact portion 130_1 and a bit line through portion 130_2. For example, in each bit line structure 130, the bit line contact portion 130_1 and the bit line through portion 130_2 may be repeated alternately in a second direction D2. In this case, the bit line contact portion 130_1 of one bit line structure 130 may be spaced apart in a first direction D1 from the bit line through portion 130_2 of another bit line structure 130 adjacent to said one bit line structure 130 (e.g., see...). Figure 1 and 4A ).

[0051] Bit line contact portion 130_1 can be electrically connected to the active region ACT. For example, the bit line contact portion 130_1 of each bit line structure 130 can be connected to the active region ACT. The bit line contact portion 130_1 can be located on the bit line connection region 103a. The bit line contact portion 130_1 can be connected to the bit line connection region 103a. The bit line contact portion 130_1 can be a portion in which a direct contact DC is positioned. A portion of the bit line contact portion 130_1 can correspond to the direct contact DC.

[0052] The bit line through portion 130_2 of each bit line structure 130 is not directly electrically connected to the active region ACT. The bit line through portion 130_2 is electrically connected to the active region ACT, but is electrically connected to the active region ACT through bit line contact portion 130_1. The bit line through portion 130_2 can be disposed between adjacent bit line contact portions 130_1 in the second direction D2. For example, in each bit line structure 130, the bit line contact portion 130_1 and the bit line through portion 130_2 can be alternately repeated in the second direction D2.

[0053] Bit line through portions 130_2 can be located on a device isolation layer 105 between adjacent memory connection regions 103b in the first direction D1. A bit line through portion 130_2 of one bit line structure 130 can be spaced apart in the first direction D1 from a bit line contact portion 130_1 of another bit line structure 130 adjacent to said bit line structure 130 (e.g., see...). Figure 1 and Figure 4A ).

[0054] A view of the area between adjacent word lines WL, intercepted along the first direction D1. Figure 4A and Figure 4C In this configuration, the bit line contact portion 130_1 can be located on the bit line connection region 103a and the device isolation layer 105, and the bit line through portion 130_2 can be located on the memory connection region 103b and the device isolation layer 105. For example, the bit line connection region 103a and the memory connection region 103b, which are spaced apart from each other in the first direction D1, can be respectively provided on two different active regions ACT that are spaced apart from each other in the first direction D1.

[0055] The bitline structure 130 may include bitline stack 140, bitline spacers 150, and bitline mask pattern 155.

[0056] In the bit line contact portion 130_1, the bit line spacer 150 may include a bit line contact opening 150op that exposes an active region ACT (e.g., bit line connection region 103a). In the bit line contact portion 130_1, the bit line spacer 150 defining the bit line contact opening 150op exposes the active region ACT. The bit line structure 130 can be connected to the active region ACT through the bit line contact opening 150op. For example, in the bit line contact portion 130_1, the bit line spacer 150 may be disposed on opposite sidewalls of the bit line stack 140.

[0057] In the bitline passage portion 130_2, the bitline spacer 150 may extend along the sidewalls and bottom surface of the bitline stack 140. The bitline spacer 150 may define the bitline groove 150t.

[0058] Bit line spacers 150 may include a lower bit spacer 151 and an upper bit spacer 152. The upper bit spacer 152 may be disposed on the lower bit spacer 151. For example, the upper bit spacer 152 may be vertically stacked with the lower bit spacer 151. In the semiconductor device according to the embodiment, the stacking structure of the lower bit spacer 151 may be different from the stacking structure of the upper bit spacer 152.

[0059] In the bit line contact portion 130_1, the lower line spacer 151 may define a bit line contact opening 150op that exposes the bit line connection region 103a. In the bit line contact portion 130_1, the lower line spacer 151 exposes the active region ACT. The lower line spacer 151 may be disposed on a portion of each sidewall of the bit line stack 140. In the bit line through portion 130_2, the lower line spacer 151 may include one or more insulating layers extending continuously along a portion of each sidewall of the bit line stack 140 and the bottom surface of the bit line stack 140. In the semiconductor device according to the embodiment, the lower line spacer 151 may include an insulating layer extending continuously along a portion of opposite sidewalls of the bit line stack 140 and the bottom surface of the bit line stack 140.

[0060] The upper spacer 152 may include a first sub-upper spacer 152a to a third sub-upper spacer 152c. The first sub-upper spacer 152a may have an L-shape. The first sub-upper spacer 152a may include a bottom portion extending along the upper surface of the lower spacer 151 and a protruding portion protruding from the bottom portion and extending vertically in the thickness direction of the base 100. Here, "L-shape" includes not only the case where the bottom portion and the protruding portion form a 90-degree angle, but also the case where the bottom portion and the protruding portion meet at an angle greater than 90 degrees and less than 180 degrees or at an angle greater than 0 degrees and less than 90 degrees. In addition, "L-shape" here includes not only an L-shape with an angled curved portion, but also an L-shape with a rounded curved portion. The first sub-upper spacer 152a may be bent toward the bit line stack 140.

[0061] The second sub-spacer 152b can be disposed on the bottom portion of the first sub-spacer 152a. The third sub-spacer 152c can be disposed on the first sub-spacer 152a and the second sub-spacer 152b.

[0062] Each of the lower line spacer 151, the first sub-upper spacer 152a, and the third sub-upper spacer 152c may include at least one of, for example, silicon oxide, silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiOCN). The second sub-upper spacer 152b may be an air spacer (i.e., an air gap). When at least one of the first sub-upper spacer 152a and the third sub-upper spacer 152c comprises the same material as the lower line spacer 151, the first sub-upper spacer 152a and / or the third sub-upper spacer 152c may be considered integral with the lower line spacer 151. Since the second sub-upper spacer 152b is an air spacer, the upper line spacer 152 may include an air spacer. The lower line spacer 151 does not include an air spacer. As discussed herein, the term "air" may refer to the atmosphere or other gases that may be present during the manufacturing process.

[0063] exist Figure 4A and Figure 4C In this embodiment, the second sub-spacer 152b can be positioned between the first sub-spacer 152a and the third sub-spacer 152c. In an example embodiment, the first sub-spacer 152a, the sacrificial layer, and the third sub-spacer 152c can be sequentially disposed on the sidewall of the bit line stack 140, and then the sacrificial layer can be removed to form an air spacer for the second sub-spacer 152b. However, this is merely for ease of description, and the embodiments are not limited to this approach.

[0064] Bit line stack 140 can be disposed on substrate 100 and device isolation layer 105 positioned along a second direction D2 in which bit line stack 140 extends. Bit line stack 140 can fill a portion (e.g., the lower portion) of bit line trench 150t. Bit line stack 140 can be formed to intersect gate structure 110. Here, bit line stack 140 can correspond to bit line BL. Additionally, in bit line contact portion 130_1, a portion of bit line stack 140 can correspond to direct contact DC.

[0065] Bit line stack 140 may include, for example, a first conductive layer 141, a second conductive layer 142, and a third conductive layer 143. The first conductive layer 141 to the third conductive layer 143 may be sequentially stacked on the substrate 100 and the device isolation layer 105. Each of the first conductive layer 141 to the third conductive layer 143 may include at least one of a doped semiconductor material, a conductive silicide, a conductive metal nitride, and a metal. For example, the first conductive layer 141 may include a doped semiconductor material pattern, the second conductive layer 142 may include a conductive silicide pattern, and the third conductive layer 143 may include a metal conductive layer pattern. The metal conductive layer pattern may include, but is not limited to, at least one of a conductive metal nitride and a metal.

[0066] Although the third conductive layer 143 is in Figure 4A , Figure 4C , Figure 6A and Figure 6B The third conductive layer 143 is shown as a single layer, but this is merely for ease of description, and the embodiment is not limited to this. The third conductive layer 143 may include a barrier conductive layer and a fill conductive layer that fills the barrier recesses defined by the barrier conductive layer. The barrier conductive layer may extend along a portion of the upper surface of the second conductive layer 142 and each sidewall of the bitline trench 150t.

[0067] In the bit line contact portion 130_1, a portion of the first conductive layer 141 may correspond to the direct contact DC. The first conductive layer 141 can electrically connect the bit line stack 140 to the active region ACT, such as the bit line connection region 103a.

[0068] Bit line mask pattern 155 may be disposed on bit line stack 140. Bit line mask pattern 155 may fill other portions (e.g., the upper portion) of bit line trench 150t. Bit line mask pattern 155 may include at least one of silicon oxide, silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiOCN).

[0069] The bitline stack 140 can be configured to extend across the cell region 20 and the cell boundary region 22. A portion of the bitline stack 140 can also be located on the cell boundary region 22.

[0070] exist Figure 2 and Figure 6A In this embodiment, the thickness t12 of the third conductive layer 143 in the cell region 20 may be greater than the thickness t11 of the third conductive layer 143 in the cell boundary region 22. Although the thickness t11 of the third conductive layer 143 in the cell boundary region 22 is shown to be smaller than the thickness t12 of the third conductive layer 143 in the cell region 20, the embodiment is not limited to this. In the cell boundary region 22, the third conductive layer 143 may also include a portion having a thickness t12 of the third conductive layer 143 in the cell region 20 and a portion having a thickness t11 smaller than the thickness t12 of the third conductive layer 143 in the cell region 20.

[0071] Because a portion of the peripheral buffer insulation layer 106 and a portion of the cell buffer insulation layer 107 are positioned between the bit line stack 140 and the cell boundary region 22, the thickness t11 of the third conductive layer 143 in the cell boundary region 22 can be smaller than the thickness t12 of the third conductive layer 143 in the cell region 20. The peripheral buffer insulation layer 106 and the cell buffer insulation layer 107 do not extend into the cell region 20.

[0072] exist Figure 2 and Figure 6B In this configuration, the thickness t12 of the third conductive layer 143 in the cell region 20 can be substantially the same as the thickness t11 of the third conductive layer 143 in the cell boundary region 22. The peripheral buffer insulating layer 106 and the cell buffer insulating layer 107 may not be placed between the bit line stack 140 and the cell boundary region 22.

[0073] exist Figure 4A and Figure 4BIn the bit line structure 130, a boundary surface 130i may be included that intersects with the device isolation layer 105 and the memory connection region 103b. The bit line through portion 130_2 may include the boundary surface 130i that intersects with the device isolation layer 105 and the memory connection region 103b. The boundary surface 130i of the bit line through portion 130_2 includes a first sub-boundary surface 130ia that intersects with the device isolation layer 105 and a second sub-boundary surface 130ib that intersects with the memory connection region 103b.

[0074] For example, the first sub-boundary surface 130ia of the bit line through portion 130_2 may be concave. The second sub-boundary surface 130ib of the bit line through portion 130_2 may be bent toward the bit line stack 140.

[0075] The bit line extends through portion 130_2 into the memory connection region 103b. For example, each of the memory connection regions 103b may have a profile OL if no etching occurs during the manufacturing process. However, a portion of each of the memory connection regions 103b may be etched during the process of forming the bit line structure 130. Therefore, a portion (e.g., the lower end) of the bit line through portion 130_2 may extend into the memory connection region 103b. For example, the lower end of the bit line through portion 130_2 may be buried in the memory connection region 103b. The second sub-boundary surface 103ib of the bit line through portion 130_2 is recessed toward the substrate 100 more than the profile OL of each of the memory connection regions 103b. Unlike in the figures, in the profile OL of each memory connection region 103b, the portion of the upper surface of the profile OL that connects to each sidewall of the profile OL may be rounded.

[0076] exist Figure 4A and Figure 4C In the example embodiment, the bit line through portion 130_2 extending into the memory connection region 103b is symmetrical with respect to the device isolation layer 105. However, this is merely for ease of description, and the embodiment is not limited to this case. In the example embodiment, the bit line through portion 130_2 extending into the memory connection region 103b is asymmetrical with respect to the device isolation layer 105. For example, the depth of the bit line through portion 130_2 extending into the memory connection region 103b on one side of the device isolation layer 105 may be different from the depth of the bit line through portion 130_2 extending into the memory connection region 103b on the other side of the device isolation layer 105.

[0077] A gate pattern 170 may be formed on a substrate 100 and a device isolation layer 105. The gate pattern 170 may be formed and stacked with a gate structure 110 formed or buried in the substrate 100 and the device isolation layer 105. The gate pattern 170 may be formed on the gate structure 110 and may extend in a first direction D1. The gate pattern 170 may be disposed between bit line structures 130 extending in a second direction D2. The gate pattern 170 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. Although each of the gate patterns 170 is shown as a single layer, this is merely for ease of description, and the embodiments are not limited to this.

[0078] Each of the memory contacts 120 may be formed between adjacent gate structures 110 and adjacent bit line structures 130. Each of the memory contacts 120 may be stacked with the substrate 100 and the device isolation layer 105 between adjacent gate structures 110 and adjacent bit line structures 130. Here, the memory contacts 120 may correspond to buried contacts BC. Each of the memory contacts 120 may include a portion extending along the sidewalls of the bit line structure 130 and the sidewalls of the gate pattern 170.

[0079] Each of the storage contacts 120 may include at least one of, for example, a semiconductor material doped with impurities, a conductive silicide, a conductive metal nitride, and a metal.

[0080] In the semiconductor device according to the embodiment, the height h12 of the lowest portion of each memory contact 120 from the bottom surface of the device isolation layer 105 can be smaller than the height h13 of the lowest portion of the bit line through portion 130_2 from the bottom surface of the device isolation layer 105. Additionally, the height h12 of the lowest portion of each memory contact 120 from the bottom surface of the device isolation layer 105 can be larger than the height h11 of the lowest portion of the bit line contact portion 130_1 from the bottom surface of the device isolation layer 105. Here, it can be based on along... Figure 1 The height is compared using the sectional view taken from the first direction D1.

[0081] exist Figures 4A to 4C In this embodiment, each memory contact 120 is not vertically stacked with the bottom surface of the bit line through portion 130_2. However, the embodiment is not limited to this. Depending on the manufacturing process margin, a portion of each memory contact 120 may extend along the bottom surface of the bit line through portion 130_2 to stack with the bottom surface of the bit line through portion 130_2. In this case, each memory contact 120 may have a shape similar to the letter L.

[0082] exist Figure 4A and Figure 4BIn this configuration, each storage contact 120 may include a boundary surface 120i that intersects with the device isolation layer 105 and the storage connection region 103b. The boundary surface 120i of each storage contact 120 includes a third sub-boundary surface 120ia that intersects with the device isolation layer 105 and a fourth sub-boundary surface 120ib that intersects with the storage connection region 103b. For example, the fourth sub-boundary surface 120ib of each storage contact 120 may be located at a greater height from the bottom surface of the device isolation layer 105 than the third sub-boundary surface 120ia of each storage contact 120. Figure 4B In this embodiment, a portion of the fourth sub-boundary surface 120ib of the storage contact 120 is located at the same level as the third sub-boundary surface 120ia of the storage contact 120. However, the embodiment is not limited to this. Depending on the margin in the manufacturing process, the fourth sub-boundary surface 120ib of each storage contact 120 may generally be higher than the third sub-boundary surface 120ia of each storage contact 120.

[0083] In the semiconductor device according to the embodiment, the height h13 of the lowest portion of the bit line passing through the portion 130_2 from the bottom surface of the device isolation layer 105 can be smaller than the height h14 of the highest portion of the fourth sub-boundary surface 120ib of each memory contact 120 from the bottom surface of the device isolation layer 105 and larger than the height h12 of the lowest portion of the fourth sub-boundary surface 120ib of each memory contact 120 from the bottom surface of the device isolation layer 105.

[0084] Each memory connection region 103b may include an upper portion 130b_1 that intersects with a memory contact 120 and a lower portion 130b_2 that does not intersect with a memory contact 120. Each memory contact 120 extends into the memory connection region 103b. The fourth sub-boundary surface 120b of each memory contact 120 is recessed further toward the substrate 100 than the contour OL of the memory connection region 103b. In the semiconductor device according to an embodiment, the upper portion 130b_1 of each memory connection region 103b is recessed further toward the substrate 100 than the contour OL of each memory connection region 103b.

[0085] exist Figure 4A and Figure 4B In this context, the upper portion 130b_1 of each storage connection area 103b can be rounded. Optionally, by considering Figure 4B Reference Figure 4C In the upper part 130b_1 of each storage connection region 103b, the upper surface of the storage connection region 103b and each sidewall of the storage connection region 103b can intersect at an angle.

[0086] Storage pad 160 may be formed on storage contact 120. Storage pad 160 may be electrically connected to storage contact 120. Here, storage pad 160 may correspond to contact pad LP. Storage pad 160 may be partially stacked with the upper surface of bit line structure 130 or may not be stacked with the upper surface of bit line structure 130. Storage pad 160 may include at least one of, for example, a semiconductor material doped with impurities, a conductive silicide, a conductive metal nitride, and a metal.

[0087] A pad separation layer 180 may be formed on the storage pad 160, the bit line structure 130, and the fence pattern 170. The pad separation layer 180 may define each of the spaced-apart storage pads 160. Additionally, the pad separation layer 180 may be patterned to expose a portion of the upper surface of each storage pad 160. The pad separation layer 180 may include an insulating material to electrically isolate the storage pads 160 from each other. For example, the pad separation layer 180 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and combinations thereof.

[0088] An etch stop layer 185 may be formed on the pad separation layer 180 and the storage pad 160. The etch stop layer 185 may include at least one of a silicon nitride layer, a silicon carbonitride layer, a silicon oxynitride layer, and a silicon oxycarbide layer.

[0089] Information storage unit 190 may be formed on pad separation layer 180. Information storage unit 190 may be electrically connected to storage pad 160. For example, information storage unit 190 may be electrically connected to storage contact 120. A portion of information storage unit 190 may be disposed in etch stop layer 185. Information storage unit 190 may include, for example, a capacitor. Information storage unit 190 includes a lower electrode 191, a capacitor insulating layer 192, and an upper electrode 193.

[0090] Each lower electrode 191 is shown as having a cylindrical shape. However, the shape of each lower electrode 191 is not limited to a cylindrical shape, and each lower electrode 191 may also have a columnar or L-shaped shape. A capacitor insulating layer 192 is formed on the lower electrode 191. The capacitor insulating layer 192 may be formed along the contour of the lower electrode 191. The capacitor insulating layer 192 may be formed along the outer and inner sidewalls of the lower electrode 191. An upper electrode 193 is formed on the capacitor insulating layer 192. The upper electrode 193 may cover the outer sidewall of the lower electrode 191.

[0091] The lower electrode 191 may include, but is not limited to, doped semiconductor materials, conductive metal nitrides (such as titanium nitride, tantalum nitride, or tungsten nitride), metals (such as ruthenium, iridium, titanium, or tantalum), or conductive metal oxides (such as iridium oxide). The capacitor insulating layer 192 may include, but is not limited to, one of silicon oxide, silicon nitride, silicon oxynitride, high-k materials, and combinations thereof. The upper electrode 193 may include, for example, at least one of doped semiconductor materials, metals, conductive metal nitrides, and metal silicides.

[0092] A peripheral transistor PRTr can be formed in the peripheral region 24. A peripheral insulating layer 50 can be formed around the peripheral transistor PRTr. The peripheral insulating layer 50 may include a lower peripheral insulating layer 52 and an upper peripheral insulating layer 51.

[0093] Connection wiring 165 may be disposed on the peripheral insulating layer 50. Connection wiring 165 may be connected to the bit line stack 140 via bit line peripheral contacts 166. Bit line peripheral contacts 166 may be formed in the cell boundary region 22. Connection wiring 165 may connect the peripheral transistor PRTr and the bit line stack 140. Connection wiring 165 and bit line peripheral contacts 166 may include at least one of conductive metal nitride and metal.

[0094] Figures 7 to 10 Semiconductor devices according to different embodiments are shown. For ease of description, the main description will be related to... Figures 1 to 6B Differences in the implementation examples.

[0095] Reference Figure 7 In the semiconductor device according to the embodiment, the upper line spacer 152 may include a fourth sub-upper line spacer 152d instead of the second sub-upper line spacer 152b (see [link]). Figure 4A ).

[0096] The fourth upper spacer 152d may include at least one of, for example, silicon oxide, silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride oxy-carbon (SiOCN). In the semiconductor device according to the embodiment, the upper line spacer 152 may not include an air spacer.

[0097] Reference Figure 8 In the semiconductor device according to the embodiment, the bit line through portion 130_2 may not include the first conductive layer 141.

[0098] For example, the bit line stack 140 of the bit line through portion 130_2 may have a structure in which a second conductive layer 142 and a third conductive layer 143 are stacked.

[0099] Reference Figure 9According to an embodiment, the storage contact 120 disposed on the first side of the bit line contact portion 130_1 may not extend into the storage connection region 103b in the semiconductor device. The storage contact 120 disposed on the second side of the bit line contact portion 130_1 opposite to the first side may extend into the storage connection region 103b.

[0100] On the first side of the bit line contact portion 130_1, the boundary surface 120i between the storage connection region 103b and the storage contact 120 may have Figure 4B The outline OL of the storage connection region 103b. On the second side of the bit line contact portion 130_1, the sidewall of the storage connection region 103b may include a step.

[0101] Reference Figure 10 The semiconductor device according to the embodiment may further include a protruding buffer pattern 131 that protrudes from the bit line through the sidewall of the portion 130_2.

[0102] Each protruding buffer pattern 131 may be disposed on a portion of the upper surface of the storage connection region 103b. For example, each protruding buffer pattern 131 in the first direction D1 (see...) Figure 1 The width on the ) is smaller than the width of each storage contact 120 in the first direction D1. For example, each protruding buffer pattern 131 extends into the storage contact 120, but not into the bit line contact portion 130_1. At least a portion of each protruding buffer pattern 131 may be connected to Figure 6A and Figure 6B The unit buffer insulating layer 107 is formed in the same manufacturing process. The protruding buffer pattern 131 may include at least one of, for example, silicon oxide, silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiOCN). Although each protruding buffer pattern 131 is shown as a single layer, this is only for the purpose of description, and the embodiments are not limited to this.

[0103] Figures 11 to 13 Semiconductor devices according to different embodiments are shown. For ease of description, the main description will be related to... Figures 1 to 6B Differences in the implementation examples.

[0104] Reference Figure 11 In the semiconductor device according to the embodiment, the bit line spacer 150 may further include a bottom line spacer 153. A bottom line spacer 151 may be disposed on the bottom line spacer 153. For example, the bottom line spacer 151 may be located between the bottom line spacer 153 and the top line spacer 152.

[0105] Because a portion of the bit line structure 130 extends into the memory connection region 103b, the bottom surface of the bit line structure 130 can have a curved shape. A bottom line spacer 153 can fill the curved portion of the bottom surface of the bit line structure 130. The bottom line spacer 153 can be located within the bit line through portion 130_2.

[0106] The bottom line spacer 153 may include at least one of, for example, silicon oxide, silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiOCN). Although the bottom line spacer 153 is shown as a single layer, this is merely for ease of description, and the embodiments are not limited to this.

[0107] Reference Figure 12 In the semiconductor device according to the embodiment, the lower line spacer 151 may include a first sub-lower spacer 151a to a third sub-lower spacer 151c. Each of the first sub-lower spacers 151a to the third sub-lower spacer 151c may extend continuously along a portion of each sidewall of the bit line stack 140 and the bottom surface of the bit line stack 140.

[0108] The first sub-lower spacer 151a to the third sub-lower spacer 151c can be stacked sequentially on the substrate 100. In the bit line contact portion 130_1, the first sub-lower spacer 151a and the second sub-lower spacer 151b can be L-shaped.

[0109] Each of the first sub-lower spacers 151a to the third sub-lower spacers 151c may include at least one of, for example, silicon oxide, silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), and silicon oxycarbonitrile (SiOCN).

[0110] Although the lower line spacer 151 is shown as comprising three sub-lower spacers, the embodiment is not limited to this. The lower line spacer 151 may also comprise two or four or more sub-lower spacers.

[0111] Reference Figure 13 In the semiconductor device according to the embodiment, the upper line spacer 152 may include a first sub-upper spacer 152a and a fifth sub-upper spacer 152e.

[0112] The first sub-spacer 152a may be, for example, I-shaped. A portion of the fifth sub-spacer 152e may be disposed between the bit line stack 140 and the bit line mask pattern 155. The fifth sub-spacer 152e may extend along the sidewalls and top surface of the third conductive layer 143.

[0113] The fifth sub-spacer 152e may extend along a portion of each of the opposing sidewalls of the bit line mask pattern 155. A portion of the bit line mask pattern 155 may protrude above the upper surface of the bit line spacer 150. The fifth sub-spacer 152e may comprise at least one of, for example, silicon oxide, silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiOCN).

[0114] Unlike in the accompanying drawings, the fifth sub-spacer 152e between the third conductive layer 143 and the first sub-spacer 152a may include an air gap or a seam pattern.

[0115] Figures 14 to 16 Semiconductor devices according to different embodiments are shown. For ease of description, the main description will be related to... Figures 1 to 6B Differences in the implementation examples.

[0116] Reference Figure 14 and Figure 15 In the semiconductor device according to the embodiment, the upper line spacer 152 may further include a sixth sub-upper line spacer 152f.

[0117] The sixth sub-spacer 152f may be disposed on the second sub-spacer 152b. The sixth sub-spacer 152f may extend along a portion of the third sub-spacer 152c. The first sub-spacer 152a, the third sub-spacer 152c and the sixth sub-spacer 152f may be located around the second sub-spacer 152b, which serves as an air spacer.

[0118] The sixth spacer 152f may include at least one of silicon oxide, silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxynitride (SiON), and silicon oxycarbonitrile (SiOCN).

[0119] exist Figure 14 In the cross-sectional view taken along the first direction D1, each storage contact 120 extends along a portion of the first sub-upper spacer 152a, but does not include the portion extending along the sixth sub-upper spacer 152f. For example, each storage contact 120 is not laterally stacked with the sixth sub-upper spacer 152f.

[0120] exist Figure 15 In this configuration, each storage contact 120 may include a portion extending along the sixth sub-upper spacer 152f. For example, each storage contact 120 may be laterally stacked with the sixth sub-upper spacer 152f. A portion of each storage contact 120 may be disposed on the upper surface of the first sub-upper spacer 152a. The portion of each storage contact 120 that is positioned higher than the lower surface of the third conductive layer 143 may be, for example, T-shaped.

[0121] Reference Figure 16 In the semiconductor device according to the embodiment, the height h12 of the lowest portion of each memory contact 120 from the bottom surface of the device isolation layer 105 can be greater than the height h13 of the lowest portion of the bit line through portion 130_2 from the bottom surface of the device isolation layer 105. Additionally, the height h12 of the lowest portion of each memory contact 120 from the bottom surface of the device isolation layer 105 can be greater than the height h11 of the lowest portion of the bit line contact portion 130_1 from the bottom surface of the device isolation layer 105.

[0122] Each storage contact 120 may not extend into the storage connection region 103b. The boundary surface 120i between the storage connection region 103b and each storage contact 120 may have Figure 4B The outline OL of the storage connection area 103b.

[0123] Figures 17A to 34C This is a view illustrating the steps of a method for manufacturing a semiconductor device according to an embodiment.

[0124] Reference Figure 1 , Figure 2 and Figures 17A to 17C A device isolation layer 105 can be formed in the cell region 20 to define an active region ACT extending in the third direction D3. A plurality of gate structures 110 extending in the first direction D1 can be formed in the substrate 100 and the device isolation layer 105.

[0125] Next, a pre-cell buffer insulating layer 107a can be formed on the peripheral buffer insulating layer 106 of the exposed cell region 20. The pre-cell buffer insulating layer 107a can be formed on the entire surface of the substrate 100. The peripheral buffer insulating layer 106 and the pre-cell buffer insulating layer 107a are patterned to expose the peripheral region 24. A peripheral transistor PRTr can be formed on the exposed peripheral region 24. Although the pre-cell buffer insulating layer 107a is shown as a single layer, the embodiment is not limited to this.

[0126] Reference Figures 18A to 18C A peripheral insulating layer 50 can be formed on the substrate 100. The peripheral insulating layer 50 can be formed on the entire surface of the substrate 100. The peripheral insulating layer 50 can cover the peripheral transistor PRTr.

[0127] The peripheral insulating layer 50 may include a lower peripheral insulating layer 52 and an upper peripheral insulating layer 51. After the lower peripheral insulating layer 52 is formed on the substrate 100, its upper surface can be planarized using a planarization process. Then, the upper peripheral insulating layer 51 can be formed. Each of the lower peripheral insulating layer 52 and the upper peripheral insulating layer 51 may include at least one of, for example, silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, and silicon carbonitride. Although the peripheral insulating layer 50 is shown as comprising multiple layers, the embodiment is not limited to this. The peripheral insulating layer 50 may also be a single layer.

[0128] Reference Figures 19A to 19C The peripheral insulating layer 50 on the cell region 20 can be patterned to expose the pre-cell buffer insulating layer 107a on the cell region 20.

[0129] Next, a cell etch stop layer 53 can be formed on the substrate 100. The cell etch stop layer 53 can extend along the pre-cell buffer insulating layer 107a on the cell region 20 and the sidewalls and top surface of the peripheral insulating layer 50.

[0130] A fence molding layer 54 may be formed on the unit etch stop layer 53. After the fence molding layer 54 is formed on the substrate 100, the unit etch stop layer 53 on the upper surface of the peripheral insulating layer 50 may be exposed by a planarization process. Each of the unit etch stop layer 53 and the fence molding layer 54 may include, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, and a silicon carbonitride layer.

[0131] Reference Figures 20A to 20C A first mask pattern 55 can be formed on the gate molding layer 54 and the peripheral insulating layer 50. The first mask pattern 55 can be used to pattern the gate molding layer 54. Therefore, a gate molding pattern 54p can be formed on the cell region 20. The gate molding pattern 54p can expose the upper surface of the gate structure 110. While patterning the gate molding layer 54, a portion of the peripheral insulating layer 50 can also be etched. In addition, while patterning the gate molding layer 54, the pre-cell buffer insulating layer 107a and the cell etch stop layer 53 can be patterned to form the cell buffer insulating layer 107a and the cell etch stop pattern 53p.

[0132] Reference Figures 21A to 21CA gate pattern 170 extending along the gate structure 110 can be formed on the gate structure 110 using a gate molding pattern 54p. Then, the gate molding pattern 54p and the first mask pattern 55 can be removed. Additionally, the cell etch stop pattern 53p formed on the cell region 20 can be removed. While removing the cell etch stop pattern 53p extending along the upper surface of the substrate 100 of the cell region 20, the cell etch stop pattern 53p formed on the sidewalls of the peripheral insulating layer 50 can be retained without removal.

[0133] With use Figures 19A to 21C Depending on the circumstances, the peripheral insulating layer 50 may also be patterned to form a gate pattern 170 on the gate structure 110, such that the gate pattern 170 extends along the gate structure 110.

[0134] Reference Figures 22A to 22D A second mask pattern 56 can be formed on the substrate 100. The second mask pattern 56 can cover the cell boundary region 22 and the peripheral region 24. Alternatively, the second mask pattern 56 can be disposed on the cell region 20 in the form of pillars.

[0135] exist Figure 22D In this configuration, each of the second mask patterns 56 can simultaneously at least partially cover the end of an adjacent active region ACT. For example, each of the second mask patterns 56 can simultaneously at least partially cover an adjacent storage connection region 103b. The second mask pattern 56 can be, but is not limited to, a carbon mask pattern.

[0136] A portion of the substrate 100 and a portion of the device isolation layer 105 are removed using a second mask pattern 56 to form a first line contact recess 130r_1. The bottom surface of each of the first line contact recesses 130r_1 may be defined by the device isolation layer 105 and the substrate 100.

[0137] The second mask pattern 56 can cover one or more gate structures 110 adjacent to the cell boundary region 22. Therefore, since the substrate 100 between the gate structures 110 adjacent to the cell boundary region 22 is not removed, the first line contact recess 130r_1 can be omitted therein. This differs from the above situation, as... Figure 27D As shown, a first bit line contact recess 130r_1 can also be formed on the bit line connection area 103a using a mask pattern with an opening.

[0138] Reference Figure 23A and Figure 23B This can remove the second mask pattern 56.

[0139] Then, the cell buffer insulation layer 107 on the cell region 20 can be removed. However, the cell buffer insulation layer 107 covered by the outer insulation layer 50 on the cell boundary region 22 can be retained. While removing the cell buffer insulation layer 107 on the cell region 20, the upper part of the first line contact recess 130r_1 is rounded. However, the embodiment is not limited to this case.

[0140] Reference Figures 24A to 24C A buried contact layer 121 can be formed on the substrate 100. The buried contact layer 121 can fill each space between adjacent fence patterns 170. The buried contact layer 121 can fill the first line contact recess 130r_1.

[0141] The buried contact layer 121 is formed to cover the fence pattern 170. The upper surface of the fence pattern 170 can be exposed by a planarization process. The buried contact layer 121 may include, for example, polysilicon.

[0142] Reference Figures 25A to 25C A third mask pattern 57 can be formed on the substrate 100. The third mask pattern 57 can be used to partially remove the buried contact layer 121 and the gate pattern 170 to form a line structure trench 130t extending in the second direction D2. The line structure trench 130t may intersect with the gate structure 110 formed in the substrate 100. The line structure trench 130t may extend to a portion of the cell boundary region 22. The line structure trench 130t may pass through the first line contact recess 130r_1. Simultaneously with forming the line structure trench 130t, a second bit line contact recess 130r_2 can be formed in the bottom surface of the first line contact recess 130r_1. The second bit line contact recess 130r_2 can be formed at a location overlapping the first line contact recess 130r_1. Since the buried contact layer 121 is patterned by the line structure trench 130t, a buried contact pattern 121p can be formed on the substrate 100.

[0143] exist Figure 25C In the original embodiment, the unit buffer insulation layer 107 and the outer buffer insulation layer 106 on the unit boundary region 22 are not removed while forming the line structure trench 130t. However, the embodiment is not limited to this. Unlike in the figures, the unit buffer insulation layer 107 and the outer buffer insulation layer 106 on the unit boundary region 22 can be removed while forming the line structure trench 130t. In this case, the unit buffer insulation layer 107 and the outer buffer insulation layer 106 can be as follows: Figure 6B The shape shown.

[0144] Reference Figures 26A to 26CA pre-spacer layer 151p can be formed along the sidewalls and bottom surface of each line structure groove 130t. The pre-spacer layer 151p can extend along the upper surface of the third mask pattern 57.

[0145] Reference Figures 27A to 27D A fourth mask pattern 58 can be formed on the substrate 100. The fourth mask pattern 58 can cover not only the cell boundary region 22 and the peripheral region 24, but also the cell region 20.

[0146] exist Figure 27D In this process, the fourth mask pattern 58 may include a mask opening 58op formed at a position corresponding to the bit line connection region 103a. The fourth mask pattern 58 may be, but is not limited to, a carbon mask pattern.

[0147] The pre-spacer layer 151p can be removed using the fourth mask pattern 58 to form the pre-lower spacer 151pp. The pre-spacer layer 151p located at the position corresponding to the mask opening 58op can be removed. The pre-lower spacer 151pp may include a bit line contact opening 150op for exposing the bit line connection region 103a of the active region ACT. The bit line contact opening 150op can be formed at a position overlapping with the second bit line contact recess 130r_2.

[0148] Reference Figures 28A to 28C Remove the fourth mask pattern 58.

[0149] Reference Figure 29A and Figure 29B A first conductive layer 141 may be formed between portions of the pre-placed spacer 151pp. The first conductive layer 141 may fill a portion of each wire structure trench 130t. The first conductive layer 141 may be connected to each active region ACT, such as each bit line connection region 103a, through bit line contact openings 150op.

[0150] Reference Figures 30A to 30C A portion of the pre-lower spacer 151pp can be removed to form the lower line spacer 151. A portion of the pre-lower spacer 151pp formed on the opposite sidewalls of each line structure groove 130t and the pre-lower spacer 151pp disposed on the upper surface of the third mask pattern 57 can be removed.

[0151] Reference Figure 31A and Figure 31BA pre-upper spacer 152p can be formed on the lower line spacer 151 to extend along a portion of each sidewall of each line structure trench 130t. The pre-upper spacer 152p can include a first pre-upper spacer 152ap to a third pre-upper spacer 152cp. After the first pre-upper spacer 152ap and the second pre-upper spacer 152bp are formed to expose the upper surface of the first conductive layer 141, the third pre-upper spacer 152cp can be formed along the sidewalls of the first pre-upper spacer 152ap and the second pre-upper spacer 152bp.

[0152] Reference Figures 32A to 32C A second conductive layer 142 and a third conductive layer 143 can be formed on the first conductive layer 141. The bit line stack 140 may include the first conductive layer 141 to the third conductive layer 143. The bit line stack 140 can fill a portion of each line structure trench 130t. A bit line mask pattern 155 can be formed on the bit line stack 140 to fill the remaining portion of each line structure trench 130t. The third mask pattern 57 can be removed.

[0153] Unlike in the accompanying drawings, a portion of the pre-upper spacer 152p can also be removed along with the removal of the third mask pattern 57. In this case, the bit line mask pattern 155 can protrude above the upper surface of the pre-upper spacer 152p and the upper surface of the buried contact pattern 121p.

[0154] Reference Figure 33A and Figure 33B The buried contact pattern 121p can be partially removed to form the storage contact 120. The buried contact pattern 121p can be partially removed to expose the sidewall of the pre-spacer 152p.

[0155] The first pre-upper spacer 152ap and the second pre-upper spacer 152bp with exposed sidewalls can be partially removed. Then, the buried contact pattern 121p can be partially removed again to form the storage contact 120.

[0156] Reference Figures 34A to 34C A pad conductive layer can be formed to cover the storage contact 120 and the bit line mask pattern 155. A pad separation layer 180 can then be formed to divide the pad conductive layer into storage pads 160. To form the pad separation layer 180, the pad conductive layer and each bit line mask pattern 155 are partially removed to expose a second pre-upper spacer 152bp, and then the exposed second pre-upper spacer 152bp is removed to form an air gap. After forming the air gap, the pad separation layer 180 can be formed to form a second sub-upper spacer 152b as an air spacer. Therefore, the upper line spacer 152 can be formed.

[0157] and Figures 22A to 23BUnlike in the previous case, if the sidewalls of the storage connection region 103b are not exposed by the first line contact recess 130r_1, the device isolation layer 105 can be additionally removed by a wet etching process. In this case, the resulting structure can be as follows: Figure 9 The shape shown is as depicted.

[0158] exist Figures 22A to 22D In this process, the second mask pattern 56 can be used to remove the single-cell buffer insulating layer 107. After removing the second mask pattern 56, a portion of the device isolation layer 105 can be removed. In the example embodiment, a buried contact layer 121 can be formed in this state to form a structure that can be... Figure 10 The resulting structure is shown in the figure.

[0159] After removing all cell buffer insulation layers 107 on cell region 20, a portion of the device isolation layer 105 in cell region 20 can be removed. In an example embodiment, a buried contact layer 121 can be formed in this state to form a structure that can be... Figure 16 The resulting structure is shown in the figure.

[0160] In concluding with the detailed description, those skilled in the art will understand that many changes and modifications can be made to various embodiments without substantially departing from the principles of the inventive concept. Therefore, the disclosed embodiments of the invention are used only in a general and descriptive sense and not for limiting purposes.

Claims

1. A semiconductor device, the semiconductor device comprising: A device isolation layer is formed in a substrate and defines a first active region and a second active region spaced apart from each other in a first direction; Buried contact element, connected to the second active area; The first line structure is disposed on the first active region and extends in a second direction different from the first direction; as well as The second bit line structure is spaced apart from the first bit line structure in the first direction and disposed on the second active region. in: Each of the first bit line structure and the second bit line structure includes a bit line stack extending in the second direction. Each of the first bit line structure and the second bit line structure includes bit line contact portions and bit line passing portions arranged alternately in the second direction. The bit line contact portion of the first bit structure is disposed on the first active region and electrically connected to the first active region. The bit lines of the second bit line structure are partially disposed on the device isolation layer. The lowest part of the buried contact is lower than the lowest part of the bit line passing through the bottom surface of the device isolation layer. The lowest part of the buried contact is higher than the bottom surface of the device isolation layer than the lowest part of the bit line contact of the first bit line structure is higher than the bottom surface of the device isolation layer. The bit lines of the second bit line structure are partially buried in the second active region at their lower ends. The boundary surface of the buried contact includes a first sub-boundary surface that intersects with the device isolation layer and a second sub-boundary surface that intersects with the second active region. With the bottom surface of the device isolation layer as a reference, the second sub-boundary surface is generally higher than the first sub-boundary surface, or with the bottom surface of the device isolation layer as a reference, a portion of the second sub-boundary surface is at the same level as the first sub-boundary surface, and the remaining portion of the second sub-boundary surface is higher than the first sub-boundary surface.

2. The semiconductor device according to claim 1, in, Each of the first bit line structure and the second bit line structure also includes bit line spacers and bit line mask patterns. The bitline mask pattern is set on the bitline stack, and The bit line stack fills a portion of the bit line trench defined by the bit line spacer.

3. The semiconductor device according to claim 2, in, In the bit line passage portion of the second bit line structure, the bit line spacer extends along the opposing sidewalls of the bit line stack and the bottom surface of the bit line stack, and In the bit line passing portion of the second bit line structure, the bit line spacer is placed between the second active region and the bit line stack.

4. The semiconductor device according to claim 2, in, In the bit line contact portion of the first bit line structure, the bit line spacer exposes the first active region.

5. The semiconductor device according to claim 2, in, The line spacers include a lower line spacer and an upper line spacer, and The upper line spacer is installed on the lower line spacer, and the upper line spacer includes an air spacer.

6. The semiconductor device according to claim 1, in, In the bit line contact portion of the first bit line structure, the bit line stack includes a semiconductor material pattern, a silicide pattern disposed on the semiconductor material pattern, and a metal conductive layer pattern disposed on the silicide pattern.

7. The semiconductor device according to claim 1, in, The second active region includes an upper portion that intersects with the buried contact element and a lower portion that does not intersect with the buried contact element, and a portion of the upper portion of the second active region is recessed.

8. The semiconductor device according to claim 1, further comprising: The buffer pattern, protruding in a first direction from the bit lines of the second bit line structure through each of the opposing sidewalls of the portion, The width of the buffer pattern in the first direction is smaller than the width of the buried contact in the first direction.

9. The semiconductor device according to claim 1, in, In the cross-sectional view taken along the first direction, the buried contact includes a boundary surface that intersects with the second active region. The boundary surface extends in a first direction from a first height from the bottom surface of the device isolation layer to a second height from the bottom surface of the device isolation layer, the second height being different from the first height, and The lowest part of the bit line in the second bit line structure is positioned between the first height and the second height from the bottom surface of the device isolation layer.

10. A semiconductor device, the semiconductor device comprising: A device isolation layer is formed in a substrate and defines a first active region and a second active region spaced apart from each other in a first direction; Buried contact element, connected to the second active area; The first line structure is disposed on the first active region and extends in a second direction different from the first direction; as well as The second bit line structure is disposed on the second active region and spaced apart from the first bit line structure in the first direction. in: Each of the first bitline structure and the second bitline structure includes a bitline spacer, a bitline stack that fills a portion of a bitline trench defined by the bitline spacer, and a bitline mask pattern disposed on the bitline stack. Each of the first bit line structure and the second bit line structure includes bit line contact portions and bit line passing portions arranged alternately in the second direction. The bit line contact portion of the first bit structure is electrically connected to the first active region. The bit lines of the second bit line structure are partially buried in the second active region at their lower ends. The position line spacers include lower position line spacers and upper position line spacers. The lower line spacer is disposed on a portion of each sidewall of the bit line stack, and The upper line spacer is installed on the lower line spacer. The boundary surface of the buried contact includes a first sub-boundary surface that intersects with the device isolation layer and a second sub-boundary surface that intersects with the second active region. With the bottom surface of the device isolation layer as a reference, the second sub-boundary surface is generally higher than the first sub-boundary surface, or with the bottom surface of the device isolation layer as a reference, a portion of the second sub-boundary surface is at the same level as the first sub-boundary surface, and the remaining portion of the second sub-boundary surface is higher than the first sub-boundary surface.

11. The semiconductor device according to claim 10, in, In the bit line passage portion of the second bit line structure, the lower bit line spacer extends along the bottom surface of the bit line stack, and In the bit line passing portion of the second bit line structure, the lower line spacer is placed between the second active region and the bit line stack.

12. The semiconductor device according to claim 10, in, In the bit line contact portion of the first bit structure, the lower bit spacer exposes the first active region.

13. The semiconductor device according to claim 10, in, The lowest portion of the buried contact is lower than the lowest portion of the bit line passing through the bottom surface of the device isolation layer. In this case, the lowest part of the buried contact is higher than the bottom surface of the device isolation layer than the lowest part of the bit line contact of the first bit line structure is higher than the bottom surface of the device isolation layer.

14. The semiconductor device according to claim 10, in, The stacking structure of the lower line spacer is different from that of the upper line spacer.

15. The semiconductor device according to claim 14, in, The upper line spacer includes air spacers, while the lower line spacer does not include air spacers.

16. The semiconductor device according to claim 10, in, In the bit line passage portion of the second bit line structure, the lower bit spacer includes a portion of each sidewall of the bit line stack and one or more insulating layers extending along the bottom surface of the bit line stack.

17. A semiconductor device, the semiconductor device comprising: A device isolation layer is formed in a substrate and defines a first active region and a second active region spaced apart from each other in a first direction, wherein each of the first active region and the second active region includes a pair of memory connection regions and a bit line connection region disposed between the pair of memory connection regions. A pair of word lines extends in a first direction and is disposed in a substrate and device isolation layer, wherein the pair of word lines are spaced apart from each other in a second direction different from the first direction, and wherein one of the bit line connection regions of the first active region and a pair of memory connection regions of the second active region is disposed between the pair of word lines and spaced apart from each other in the first direction; The buried contact element connects to one of a pair of storage connection areas; The first bit line structure extends in the second direction and is disposed on the bit line connection region of the first active region; The second bit line structure extends in the second direction and is disposed on the bit line connection region of the second active region; A pad is provided on the buried contact and connected to the mask contact; The memory capacitor is mounted on and connected to the pad. in: Each of the first bit line structure and the second bit line structure includes a bit line contact portion and a bit line passage portion. The bit line contact portion of each of the first bit line structure and the second bit line structure is electrically connected to the bit line connection region of each of the first active region and the second active region, respectively. The lowest part of the buried contact is lower than the lowest part of the bit line passing through the bottom surface of the device isolation layer. The lowest part of the buried contact is higher than the bottom surface of the device isolation layer than the lowest part of the bit line contact of the first bit line structure is higher than the bottom surface of the device isolation layer. The bit lines of the second bit line structure are partially buried at the bottom in one of a pair of memory connection regions in the second active region. The boundary surface of the buried contact includes a first sub-boundary surface that intersects with the device isolation layer and a second sub-boundary surface that intersects with the second active region. With the bottom surface of the device isolation layer as a reference, the second sub-boundary surface is generally higher than the first sub-boundary surface, or with the bottom surface of the device isolation layer as a reference, a portion of the second sub-boundary surface is at the same level as the first sub-boundary surface, and the remaining portion of the second sub-boundary surface is higher than the first sub-boundary surface.

18. The semiconductor device according to claim 17, in, Each of the first bitline structure and the second bitline structure includes a bitline spacer, a bitline stack that fills a portion of a bitline trench defined by the bitline spacer, and a bitline mask pattern disposed on the bitline stack.

19. The semiconductor device according to claim 18, in, The line spacer includes a lower line spacer and an upper line spacer, with the upper line spacer disposed on the lower line spacer and including an air spacer.

20. The semiconductor device according to claim 18, in, In the bit line contact portion of each of the first bit line structure and the second bit line structure, the bit line stack includes a semiconductor material pattern, a silicide pattern disposed on the semiconductor material pattern, and a metal conductive layer pattern disposed on the silicide pattern.

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