Semiconductor device and method of manufacturing semiconductor device

By designing the coupling of the substrate, electronic components and directional antenna components in the semiconductor device, the problems of high cost, low reliability and large package size in the prior art are solved, and a smaller package size and higher reliability are achieved.

CN112599515BActive Publication Date: 2025-10-10AMKOR TECH SINGAPORE HLDG PTE LTD
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Patent Information

Application Number
CN202011070747.6
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2019-10-02
Filing Date
2020-10-09
Publication Date
2025-10-10
Estimated Expiration
2040-10-09

AI Technical Summary

Technical Problem

Existing semiconductor packages have the problems of high cost, low reliability and large package size.

Method used

A semiconductor device is designed, including a substrate, an electronic component, and an antenna assembly. The antenna assembly is coupled to a substrate conductive structure through a substrate dielectric structure. The antenna pattern is oriented to communicate along different directions and is protected by an encapsulation. The substrate conductive structure couples the antenna assembly to the electronic component.

Benefits of technology

This achieves smaller package sizes, improves the reliability and performance of semiconductor devices, and reduces costs.

✦ Generated by Eureka AI based on patent content.

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Abstract

Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device can include a substrate dielectric structure and a substrate conductive structure traversing the substrate dielectric structure and including a first substrate terminal and a second substrate terminal; an electronic component having a component terminal coupled to the first substrate terminal; and a first antenna assembly having a first assembly terminal coupled to the second substrate terminal, a first assembly head side adjacent to a first antenna pattern, a first assembly base side opposite the first assembly side, and a first assembly sidewall. The first assembly terminal can be exposed from the first assembly dielectric structure at the first assembly base side or at the first assembly sidewall. The first antenna pattern can be coupled to the substrate via the first assembly terminal. The substrate conductive structure can couple the first antenna assembly to the electronic component.
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Description

Technical Field

[0001] The present disclosure relates generally to electronic components and, more particularly, to semiconductor devices and methods for fabricating semiconductor devices. Background Art

[0002] Existing semiconductor packages and methods for forming semiconductor packages are deficient, resulting in, for example, excessive costs, reduced reliability, relatively low performance, or excessively large package sizes. Further limitations and shortcomings of conventional and traditional approaches will become apparent to those skilled in the art by comparing the present disclosure and the accompanying drawings. Summary of the Invention

[0003] One aspect of the present invention is a semiconductor device comprising: a substrate comprising: a substrate top side; a substrate bottom side; a substrate dielectric structure between the substrate top side and the substrate bottom side; and a substrate conductive structure extending through the substrate dielectric structure and comprising: a first substrate terminal; and a second substrate terminal at the substrate top side; an electronic component coupled to the substrate and comprising: a component terminal coupled to the first substrate terminal; and a first antenna assembly coupled to the substrate and comprising: a first assembly dielectric structure; a first antenna pattern coupled to the first assembly dielectric structure; a first group a first component terminal coupled to the second substrate terminal; a first component head side, the first component head side being adjacent to the first antenna pattern; a first component base side, the first component base side being opposite to the first component side; and a first component sidewall, the first component sidewall being between the first component head side and the first component base side; wherein: the first component terminal is exposed from the first component dielectric structure at at least one of the first component base side or the first component sidewall; the first antenna pattern is coupled to the substrate via the first component terminal; the first antenna component is coupled to the substrate outside the coverage area of ​​the electronic component; and the substrate conductive structure couples the first antenna component to the electronic component.

[0004] In the semiconductor device according to one aspect of the present invention, the first antenna component includes a first antenna path, the first antenna path passing through the first component dielectric structure and coupled to the first antenna pattern and the first component terminal.

[0005] In the semiconductor device according to one aspect of the present invention, the first antenna pattern is oriented to communicate along a direction substantially orthogonal to a side of the first antenna head.

[0006] The semiconductor device of one aspect of the present invention, the first antenna assembly includes: the first assembly head side facing a vertical direction, and the first antenna pattern oriented to communicate along the vertical direction; and the first assembly base side coupled to the substrate.

[0007] The semiconductor device of one aspect of the present invention, the first antenna assembly includes: the first assembly head side facing a first horizontal direction, and the first antenna pattern oriented to communicate along the first horizontal direction; and the first assembly side wall coupled to the substrate.

[0008] The semiconductor device of one aspect of the present invention, the semiconductor device includes: a second antenna assembly coupled to the substrate; wherein: the substrate surrounding a footprint of the electronic component includes: a substrate left portion, a substrate right portion, a substrate up portion, and a substrate down portion; the first antenna assembly is coupled to the substrate top side at the substrate left portion; and the second antenna assembly is coupled to the substrate top side at the substrate right portion.

[0009] The semiconductor device of one aspect of the present invention, the semiconductor device includes: an encapsulant on the substrate top side; wherein: the second antenna assembly includes a second antenna pattern adjacent to a second assembly head side; the second antenna assembly includes a second assembly side wall; the encapsulant covers the first assembly side wall and the second assembly side wall; and the encapsulant exposes the first assembly head side and the second assembly head side.

[0010] The semiconductor device of one aspect of the present invention, the electronic component includes: a component first side coupled to the substrate top side; a component second side opposite the component first side; a component side wall between the component first side and the component second side; and a shield structure covering the component second side and the component side wall; and the encapsulant covers the shield structure adjacent to the component side wall.

[0011] The semiconductor device of one aspect of the present invention, the first antenna assembly includes: the first assembly head side facing a vertical direction, and the first antenna pattern oriented to communicate along the vertical direction; and the first assembly base side coupled to the substrate; and the second antenna assembly includes: a second assembly head side facing the vertical direction, and a second antenna pattern oriented to communicate along the vertical direction; and a second assembly base side coupled to the substrate.

[0012] In the semiconductor device according to one aspect of the present invention, the first antenna pattern is oriented to communicate toward the top along the vertical direction; and the second antenna pattern is oriented to communicate toward the bottom along the vertical direction.

[0013] In a semiconductor device as described in one embodiment of the present invention, the first antenna component includes: the first component head side facing the right direction, and the first antenna pattern oriented to communicate along the right direction; and the first component sidewall coupled to the substrate; and the second antenna component includes: a second component head side facing the left direction opposite to the right direction, and the second antenna pattern oriented to communicate along the left direction; and a second component sidewall coupled to the substrate.

[0014] In a semiconductor device as described in one embodiment of the present invention, the first antenna component includes: the first component head side facing the vertical direction, and the first antenna pattern oriented to communicate along the vertical direction; and the first component base side coupled to the substrate; and the second antenna component includes: the second component head side facing the right direction, and the second antenna pattern oriented to communicate along the right direction; and a second component sidewall coupled to the substrate.

[0015] A semiconductor device as described in one embodiment of the present invention includes: a third antenna component, which is coupled to the substrate at an upward portion of the substrate and includes: a third component head side facing an upward direction and a third antenna pattern oriented to communicate along the upward direction; and a third component sidewall coupled to the substrate.

[0016] A semiconductor device as described in one embodiment of the present invention includes: a fourth antenna component, which is coupled to the substrate at a downward portion of the substrate and includes: a fourth component head side facing a downward direction and a fourth antenna pattern oriented to communicate along the downward direction; and a fourth component sidewall coupled to the substrate.

[0017] A semiconductor device as described in one embodiment of the present invention includes: a fifth antenna component, which is coupled to the substrate at a left portion of the substrate and includes: a fifth component head side facing the left direction and a fifth antenna pattern oriented to communicate along the left direction; and a fifth component sidewall coupled to the substrate.

[0018] The semiconductor device as described in an aspect of this disclosure includes a sixth antenna assembly coupled to the substrate at the substrate right portion and including a sixth assembly head side and a sixth antenna pattern oriented to communicate along the vertical direction; and a sixth assembly sidewall coupled to the substrate.

[0019] The semiconductor device as described in an aspect of this disclosure includes the electronic component coupled to the substrate bottom side.

[0020] The semiconductor device as described in an aspect of this disclosure includes a passive component coupled to the substrate above the electronic component.

[0021] The semiconductor device as described in an aspect of this disclosure includes a passive component coupled to the substrate top side between the first antenna assembly and the second antenna assembly.

[0022] Another aspect of this disclosure is a method including providing a substrate including a substrate top side; a substrate bottom side; a substrate dielectric structure between the substrate top side and the substrate bottom side; and a substrate conductive structure traversing the substrate dielectric structure and including a first substrate terminal; and a second substrate terminal at the substrate top side; coupling an electronic component to the substrate, the electronic component including a component terminal coupled to the first substrate terminal; and coupling a first antenna assembly to the substrate, the first antenna assembly including a first assembly dielectric structure; a first antenna pattern coupled to the first assembly dielectric structure; a first assembly terminal coupled to the second substrate terminal; a first assembly head side adjacent to the first antenna pattern; a first assembly base side opposite the first assembly side; and a first assembly sidewall between the first assembly head side and the first assembly base side; wherein: the first assembly terminal is exposed from the first assembly dielectric structure at at least one of the first assembly base side or the first assembly sidewall; the first antenna pattern is coupled to the substrate via the first assembly terminal; the first antenna assembly is coupled to the substrate outside a footprint of the electronic component; and the substrate conductive structure couples the first antenna assembly to the electronic component. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A cross-sectional view of an exemplary semiconductor device is shown.

[0024] Figures 2A to 2IA cross-sectional view of an exemplary method for fabricating an exemplary semiconductor device is shown.

[0025] Figure 3 Shown as Figure 2C A plan view of an exemplary method for fabricating an exemplary semiconductor device is shown in FIG.

[0026] Figure 4A and Figure 4B Shown are plan views and cross-sectional views of an exemplary antenna assembly and an exemplary layout of the antenna assembly, which can be applied to an exemplary method for manufacturing an exemplary semiconductor device.

[0027] Figures 5A to 5C Shown are plan views and cross-sectional views of an exemplary antenna assembly and an exemplary layout of the antenna assembly, which can be applied to an exemplary method for manufacturing an exemplary semiconductor device.

[0028] Figures 6A to 6F Shown are plan views and cross-sectional views of an exemplary antenna assembly and an exemplary layout of the antenna assembly, which can be applied to an exemplary method for manufacturing an exemplary semiconductor device.

[0029] 7A to 7D Plan views and cross-sectional views of an exemplary semiconductor device are shown.

[0030] Figures 8A to 8F A cross-sectional view of an exemplary method for fabricating an exemplary semiconductor device is shown.

[0031] 9A to 9F Shown as Figures 8A to 8F A cross-sectional view of an exemplary method for fabricating an exemplary semiconductor device is shown in FIG.

[0032] Figure 10A and Figure 10B Shown as Figure 8A and Figure 8B A plan view of an exemplary method for fabricating an exemplary semiconductor device is shown in FIG.

[0033] Figure 11 A cross-sectional view of an exemplary semiconductor device is shown.

[0034] 12A to 12F A cross-sectional view of an exemplary method for fabricating an exemplary semiconductor device is shown.

[0035] Figure 13 Shown as Figure 12A A plan view of an exemplary method for fabricating an exemplary semiconductor device is shown in FIG.

[0036] Figure 14 A cross-sectional view of an exemplary semiconductor device is shown.

[0037] Figures 15A to 15G A cross-sectional view of an exemplary method for fabricating an exemplary semiconductor device is shown.

[0038] Figure 16A and Figure 16B Shown as Figure 15A and Figure 15B A plan view of an exemplary method for fabricating an exemplary semiconductor device is shown in FIG. DETAILED DESCRIPTION

[0039] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. These examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed herein. In the following discussion, the terms "example" and "for example" are non-limiting.

[0040] These figures illustrate general constructional aspects, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. Furthermore, the components in the drawings are not necessarily drawn to scale. For example, the dimensions of some components in the drawings may be exaggerated relative to other components to help enhance understanding of the examples discussed in the present disclosure. Identical reference numerals in different figures represent identical components.

[0041] The term "or" refers to any one or more of the items in the list linked by "or". For example, "x or y" refers to any one of the three components in the set {(x), (y), (x, y)}. As another example, "x, y or z" refers to any one of the seven components in the set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0042] The terms “comprise” or “comprising” are “open” terms and specify the presence of stated features but do not preclude the presence or addition of one or more other features.

[0043] The terms "first," "second," etc. may be used herein to describe various components, and these components should not be limited by these terms. These terms are only used to distinguish one component from another. Thus, for example, a first component discussed in this disclosure could be referred to as a second component without departing from the teachings of this disclosure.

[0044] Unless otherwise stated, the term "coupled" can be used to describe two components or elements that are in direct contact with each other or that are indirectly connected to each other through one or more other components or elements. For example, if component A is coupled to component B, then component A can be directly in contact with component B or can be indirectly connected to component B through intervening component C. Similarly, the terms "on" or "over" can be used to describe two components that are directly in contact with each other or that are indirectly connected to each other through one or more other components.

[0045] In an example, a semiconductor device can include: (a) a substrate including: a substrate top side; a substrate bottom side; a substrate dielectric structure between the substrate top side and the substrate bottom side; and a substrate conductive structure traversing the substrate dielectric structure and including: a first substrate terminal; and a second substrate terminal at the substrate top side; (b) an electronic component coupled to the substrate and including a component terminal coupled to the first substrate terminal; and (c) a first antenna assembly coupled to the substrate and including: a first assembly dielectric structure; a first antenna pattern coupled to the first assembly dielectric structure; a first assembly terminal coupled to the second substrate terminal; a first assembly head side adjacent to the first antenna pattern; a first assembly base side opposite the first assembly side; and a first assembly sidewall between the first assembly head side and the first assembly base side. The first assembly terminal can be exposed from the first assembly dielectric structure at at least one of the first assembly base side or the first assembly sidewall. The first antenna pattern can be coupled to the substrate via the first assembly terminal. The first antenna assembly can be coupled to the substrate outside a footprint of the electronic component. The substrate conductive structure can couple the first antenna assembly to the electronic component.

[0046] Other examples are included in the disclosure. Such examples can be found in the drawings, in the claims, or in the detailed description of the disclosure.

[0047] Figure 1 A cross-sectional view of an example semiconductor device 100 is shown. In Figure 1 In the example shown, the semiconductor device 100 can include an electronic component 110, an antenna assembly 130, an encapsulant 140, a substrate 150, and an external interconnect 160.

[0048] The electronic component 110 includes an internal interconnect 111 and an electromagnetic interference (EMI) shield 112. The antenna assembly 130 can include a dielectric structure 131, conductive structures 132 and 133, and an antenna pattern 134. The substrate 150 can include dielectric structures 151 and 153 and a conductive structure 152.

[0049] Antenna assembly 130, encapsulant 140, substrate 150, and external interconnects 160 may comprise or be referred to as semiconductor package 101 or package 101, and may protect electronic component 110 from exposure to external components or the environment. Semiconductor package 101 may provide electrical coupling between external components and electronic component 110.

[0050] Figures 2A to 2I A cross-sectional view of an exemplary method for fabricating an exemplary semiconductor device 100 is shown. Figure 3 A plan view of an exemplary method for fabricating an exemplary semiconductor device 100 is shown.

[0051] Figure 2A FIG. 1 shows a cross-sectional view of a semiconductor device 100 at an early stage of manufacture. Figure 2A In the example shown, the bottom surface 110b of the electronic component 110 may be attached to the temporary bonding layer 11 formed on the carrier 10. In some examples, a plurality of electronic components 110 may be arranged in a matrix configuration having rows or columns and spaced apart from each other and may be attached to the carrier 10.

[0052] In some examples, the pick-and-place device can pick up and place the electronic component 110 on the temporary bonding layer 11 of the carrier 10 and can be bonded to the temporary bonding layer 11. The electronic component 110 can have a substantially flat top surface (or inactive area), a substantially bottom surface (or active area) opposite the top surface, and side surfaces connecting the top surface and the bottom surface to each other. The bottom surface of the electronic component 110 can be bonded to the temporary bonding layer 11 of the carrier 10. The electronic component 110 can include at least one internal interconnect 111 on its bottom surface. The internal interconnect 111 can be bonded to the temporary bonding layer 11 of the carrier 10. The internal interconnect 111 can be an external input / output terminal of the electronic component 110 and can include or be referred to as a die pad or a bonding pad. The internal interconnect 111 can have a width ranging from about 2 μm (micrometers) to about 500 μm. The internal interconnect 111 can have a thickness ranging from about 3 μm to about 50 μm. The internal interconnection 111 may include a conductive material, such as a metal material, aluminum, copper, an aluminum alloy, or a copper alloy.

[0053] Electronic component 110 may include or be referred to as a semiconductor die, semiconductor chip, or semiconductor package or subpackage. In some examples, electronic component 110 may include at least one of an application-specific integrated circuit, a logic die, a microcontroller unit, memory, a digital signal processor, a network processor, a power management unit, an audio processor, a radio frequency circuit, and a wireless baseband system-on-chip processor. Electronic component 110 may have a thickness ranging from approximately 0.01 mm (millimeter) to approximately 1 mm.

[0054] The carrier 10 may be a substantially flat plate. For example, the carrier 10 may include or be referred to as a plate, wafer, panel, semiconductor, or strip. In some examples, the carrier 10 may include, for example, steel, stainless steel, aluminum, copper, ceramic, glass, or a wafer. The carrier 10 may have a thickness ranging from approximately 0.5 mm to approximately 1.5 mm and a width ranging from approximately 200 mm to approximately 320 mm.

[0055] The carrier 10 may function to process a plurality of components in an integrated manner to attach the electronic member 110 and the antenna assembly 130, form the EMI shield 112, and form the encapsulation 140. The carrier 10 may be frequently applied to some examples of the present disclosure.

[0056] The temporary bonding layer 11 can be provided on the surface of the carrier 10. The temporary bonding layer 11 can be provided on the surface of the carrier 10 using a coating process such as spin coating, doctor blade, casting, spray coating, slot die coating, curtain coating, slide coating or knife over edge coating; a printing process such as screen printing, pad printing, gravure printing, flexographic coating or offset printing; an inkjet printing process having intermediate features of coating and printing; or direct attachment of an adhesive film or adhesive tape. The temporary bonding layer 11 may include or be referred to as a temporary adhesive film or a temporary adhesive tape. The temporary bonding layer 11 may be, for example, a heat-peelable tape (film) or a UV-peelable tape (film), and its bonding strength is weakened or removed by heating or UV irradiation. In some examples, the temporary bonding layer 11 may have a weakened bonding strength or may be removed by a physical or chemical external force. The temporary bonding layer 11 may have a thickness ranging from about 20 μm to about 500 μm. The temporary bonding layer 11 may allow the carrier 10 to be separated after the encapsulation 140 described later is formed. The temporary bonding layer 11 may be frequently applied to some examples of the present disclosure.

[0057] Figure 2B FIG. 1 shows a semiconductor device 100 at a later stage of manufacture. Figure 2B In the example shown, EMI shield 112 can cover electronic component 110. EMI shield 112 can contact the top and side surfaces of electronic component 110. EMI shield 112 can completely cover the top and side surfaces of electronic component 110 to achieve a uniform thickness.

[0058] EMI shield 112 may be made of a conductive material to perform the function of shielding EMI induced by antenna assembly 130 or shielding EMI induced externally to electronic component 110. In some examples, EMI shield 112 may include silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), palladium (Pd), or chromium (Cr). In some examples, EMI shield 112 may be formed by sputtering, spraying, coating, or plating. In some examples, a cap-shaped metal cover may be used as EMI shield 112. EMI shield 112 may have a thickness ranging from about 0.1 μm to about 10 μm.

[0059] Figure 2C and Figure 3 FIG. 1 shows a semiconductor device 100 at a later stage of manufacture. Figure 2C In the example shown, the bottom surface 130 b of the antenna assembly 130 may be bonded to a temporary bonding layer 11 disposed on the carrier 10 .

[0060] In some examples, a pick-and-place device can pick up antenna assembly 130, place it on the surface of temporary bonding layer 11 of carrier 10, and bond it. In some examples, antenna assembly 130 can be configured so that two antennas are bonded to carrier 10 and positioned on opposite sides of electronic component 110. An interior surface 130c of antenna assembly 130 can be spaced apart from side surface 110c of electronic component 110 having EMI shield 112. Here, interior surface 130c of antenna assembly 130 can face side surface 110c of electronic component 110, and exterior surface 130d of antenna assembly 130 can face outwardly opposite interior surface 130c of antenna assembly 130. Antenna assembly 130 can extend parallel to side surface 110c of electronic component 110. Antenna assembly 130 can have a length ranging from approximately 0.01 mm to approximately 20 mm. Antenna assembly 130 can have a width ranging from approximately 0.01 mm to approximately 20 mm. Each of antenna assemblies 130 may have a thickness or height ranging from about 0.01 mm to about 1 mm. In some examples, antenna assembly 130 may include or be referred to as an antenna substrate, an antenna module, or an antenna block.

[0061] Antenna assembly 130 may include a dielectric structure 131 having substantially flat top and bottom surfaces; conductive structures 132 and 133 exposed to the interior and bottom surfaces of dielectric structure 131; and an antenna pattern 134 exposed to the top surface of dielectric structure 131. Conductive structures 132 and 133 may include a conductive pattern or terminal 132 exposed to the bottom surface of dielectric structure 131; and a conductive path 133 formed within dielectric structure 131. In some examples, antenna assembly 130 may be configured such that one or more of dielectric structure 131 and conductive path 133 are stacked vertically in sequence.

[0062] In some examples, dielectric structure 131 can have substantially flat top and bottom surfaces. In some examples, dielectric structure 131 can include or be referred to as one or more dielectric layers, dielectrics, dielectric materials, insulating layers, or insulating materials. In some examples, dielectric structure 131 can include epoxy, phenolic, glass epoxy, polyimide, polyester, epoxy molding compound, glass, or ceramic. Dielectric structure 131 can be configured such that one or more dielectric layers are stacked upward. Dielectric structure 131 can maintain antenna assembly 130 in a substantially flat state.

[0063] Conductive terminals 132 may be exposed through the bottom surface of dielectric structure 131. Conductive terminals 132 may have one or more patterns. Conductive terminals 132 may be electrically connected to at least one conductive path 133. Each of conductive terminals 132 may include or be referred to as a conductor, conductive material, antenna land, conductive land, antenna pad, routing pad, connection pad, micropad, trace, or under-bump metallurgy (UBM). In some examples, conductive terminals 132 may include copper, iron, nickel, gold, silver, palladium, or tin.

[0064] Conductive path 133 may pass through dielectric structure 131 to electrically connect conductive terminal 132 and antenna pattern 134. In some examples, conductive path 133 may include or be referred to as a conductor, conductive material, conductive via, conductive path, conductive trace, conductive pattern, conductive layer, redistribution layer, or circuit pattern. Conductive path 133 may be configured such that one or more conductive layers are stacked upward using various patterns. In some examples, conductive path 133 may include copper, iron, nickel, gold, silver, palladium, or tin.

[0065] Antenna pattern 134 may be exposed through top surface 130a of dielectric structure 131 to enable communication. Antenna pattern 134 may have one or more patterns. Antenna pattern 134 may be electrically connected to at least one conductive path 132. In some examples, each of antenna patterns 134 may include or be referred to as a dipole antenna, a monopole antenna, a patch antenna, a loop antenna, a beam antenna, a dipole antenna, a folded antenna, a diamond antenna, or a half-wave antenna. In some examples, antenna pattern 134 may include copper, gold, or silver.

[0066] Antenna assembly 130 can vertically transmit and receive signals using antenna pattern 134 positioned on the upper portion of antenna assembly 130. Antenna assembly 130 can be a vertical antenna. Antenna assembly 130 can be modified in various ways, taking into account its structure and layout. The following discussion will describe various exemplary antenna assemblies and exemplary layouts of antenna assemblies.

[0067] Figure 4A and Figure 4B A diagram showing an exemplary antenna assembly layout is shown having a Figure 4A 4B-4B in FIG. 4B, which may be applied to an exemplary method for manufacturing an exemplary semiconductor device such as semiconductor device 100 or semiconductor device 1004. In some examples, antenna assembly 230 may be similar to antenna assembly 130 but may be oriented differently. Figure 4A and Figure 4B In the example shown, two antenna assemblies 230 may be coupled to the carrier 10 or substrate 150 so as to be positioned at opposite sides of the electronic component 110, as shown in FIG. Figure 2C and Figure 3 In some examples, the antenna assembly 230 may be similar to the antenna assembly 130 shown in FIG. Figure 2C The antenna assembly 130 shown in FIG is provided. In some examples, the antenna assembly 230 can be configured such that one or more of each of the dielectric structure 231 and the conductive structure 232 are stacked sequentially, whether in an inward, outward, or upward manner.

[0068] Each of the antenna assemblies 230 may include: a dielectric structure 231 having substantially flat top and bottom surfaces; a conductive structure 232 formed within the dielectric structure 231 and exposed to a portion of the bottom surface 230b of the dielectric structure 231; and an antenna pattern 234 exposed to an external surface 230d of the dielectric structure 231.

[0069] In some examples, the dielectric structure 231 may be similar to FIG. 2 and FIG. Figure 3The dielectric structure 131 is shown. The dielectric structure 231 can be configured such that one or more dielectric layers are stacked along the y-axis.

[0070] Conductive structure 232 may be formed within dielectric structure 131 and may be exposed to bottom surface 230 b of dielectric structure 231. Conductive structure 232 may be electrically connected to antenna pattern 134 and may be exposed to bottom surface 230 b of dielectric structure 231. In some examples, conductive structure 232 may include or be referred to as a conductor, conductive material, conductive via, conductive path, conductive trace, conductive pattern, conductive layer, redistribution layer (RDL), or circuit pattern. Conductive structure 232 may be configured such that one or more conductive layers are stacked from inner surface 230 c to outer surface 230 d using various patterns. In some examples, conductive path 232 may include copper, iron, nickel, gold, silver, palladium, or tin.

[0071] The antenna pattern 234 may be exposed through the outer surface 230a of the dielectric structure 231 to enable communication. The antenna pattern 234 may be formed on the outer surface 230a of the dielectric structure 231 to have one or more patterns. The antenna pattern 234 may be electrically connected to the at least one conductive structure 232. In some examples, each of the antenna patterns 134 may include or be referred to as a dipole antenna, a monopole antenna, a patch antenna, a loop antenna, a beam antenna, a dipole antenna, a folded antenna, a diamond antenna, or a half-wave antenna. In some examples, the antenna pattern 234 may include copper, gold, or silver.

[0072] The antenna assembly 230 may transmit / receive signals externally using an antenna pattern 234 positioned on an outer surface 230d of the antenna assembly 230. The antenna assembly 230 may be a horizontal antenna.

[0073] Figure 5A 、 Figure 5B and Figure 5C A diagram showing an exemplary antenna assembly layout is shown having a Figure 5A The cross-sectional views taken along lines 5B-5B and 5C-5C in FIG. 5 may be applied to an exemplary method for manufacturing an exemplary semiconductor device such as the semiconductor device 100 or the semiconductor device 1005. Figures 5A to 5C In the example shown, four antenna assemblies 330 may be coupled to the carrier 10 or substrate 150 such that two antennas are positioned at opposite sides of the electronic component 110. The antenna assemblies 330 may include similar Figure 2C and Figure 3 The antenna assembly 130 is shown with two vertical antennas 330x having antenna patterns 334x, and a similar Figure 4A and Figure 4BThe antenna assembly 230 shown has two horizontal antennas 330y with antenna patterns 334y. The vertical antennas 330x can be similar to Figure 2C and Figure 3 the antenna assembly 130 shown, and the horizontal antennas 330y can be similar to Figure 4A and Figure 4B the antenna assembly 230 shown.

[0074] The antenna assembly 330 can use the vertical antennas 330x with antenna patterns 334x located on the upper portion of the antenna assembly 330 to transmit / receive signals vertically, and can use the horizontal antennas 330y with antenna patterns 334y located on the outer surface of the horizontal antennas 330y to transmit / receive signals laterally.

[0075] The antenna assembly 330 can be configured such that two antennas 330x and 330y with different orientations are disposed lengthwise on one side of the electronic component 110, and two antennas 330x and 330y with different orientations are disposed lengthwise on the other side of the electronic component 110.

[0076] Each of the antennas 330x and 330y can extend a length ranging from about 0.01 mm to about 20 mm. Each of the antennas 330x and 330y can extend a width ranging from about 0.01 mm to about 20 mm. Each of the antenna assemblies 330x and 330y can have a thickness or height ranging from about 0.01 mm to about 1 mm. In some examples, each of the antenna assemblies 330 can include or be referred to as an antenna substrate, an antenna module, or an antenna block.

[0077] Figure 6A 、 Figure 6B 、 Figure 6C and Figure 6D views showing layouts of exemplary antenna assemblies with antenna patterns 434z taken along lines 6B-6B, 6C-6C, and 6D-6D in Figure 6A may be applied to exemplary methods used to manufacture exemplary semiconductor devices, such as the semiconductor device 100 or the semiconductor device 1006. In the example shown in 6A to 6D six antenna assemblies can be coupled with the carrier 10 or the substrate 150 such that the antennas 330x and 330y are disposed lengthwise on a first opposite side of the electronic component 110, as shown in Figure 5A 、 Figure 5B and Figure 5C the layout of the antenna assembly 330 shown, and the antennas 430z are disposed lengthwise on a second opposite side of the electronic component 110.

[0078] The antenna assembly 330 may include: a vertical antenna assembly 330x having an antenna pattern 334 facing one or more vertical directions at the assembly head side 135; and two horizontal antennas 330y having antenna patterns similar to those at the assembly head side 135. Figures 5A to 5C Antenna assembly 330 is shown with antenna patterns 334 facing horizontally to the right and left, respectively. Antenna assembly 430 may include a horizontal antenna assembly 430z having antenna patterns 134 at an assembly head side 135 facing horizontally upward and downward, respectively.

[0079] Vertical Antenna 330x can be used with Figure 2C and Figure 3 , and the horizontal antennas 330y and 430z may be configured in a manner similar to the antenna assembly 130 shown in FIG. Figure 4A and Figure 4B The antenna assembly 230 shown in FIG. 1 is configured in a similar manner.

[0080] The antenna components of semiconductor device 1006 can transmit / receive signals vertically using vertical antenna component 330x and can transmit / receive signals horizontally using horizontal antenna components 330y and 430z. In some examples, individual antenna components 330x, 330y, and 430z can all be similar to antenna component 130 or to each other. In some examples, the primary difference between antenna components 330x, 330y, and 430z can be that they are oriented in different directions when coupled to carrier 10 or substrate 150.

[0081] Apart from Figure 2C 、 Figure 3 、 Figure 4A 、 Figure 4B 、 Figures 5A to 5C and 6A to 6D In addition to the configuration and layout of antenna assemblies 130, 230, 330, and 430 shown in FIG, the configuration and layout of the antenna assemblies may be changed by arranging vertical antennas or horizontal antennas similar to the vertical antennas or horizontal antennas described in various manners.

[0082] Figure 2D FIG. 1 shows a semiconductor device 100 at a later stage of fabrication. Figure 2D In the example shown, encapsulant 140 may cover carrier 10, electronic component 110, and antenna assembly 130. In some examples, encapsulant 140 may be in contact with the top surface of temporary bonding layer 11 of carrier 10, the outer surface of EMI shield 112 of electronic component 110, and the side surfaces of antenna assembly 130. Here, antenna pattern 134 of antenna assembly 130 may be exposed.

[0083] In some examples, the encapsulant 140 can include or be referred to as an epoxy molding compound, an epoxy molding resin, or a sealant. In some examples, the encapsulant 140 can include or be referred to as a molding portion, a sealing portion, an encapsulant portion, a protective portion, a package, or a body. In some examples, the encapsulant 140 can include an organic resin, an inorganic filler, a curing agent, a catalyst, a coupling agent, a colorant, and a flame retardant. The encapsulant 140 can be formed by any one of a variety of processes. In some examples, the encapsulant 140 can be formed using compression molding, transfer molding, liquid phase encapsulant molding, vacuum lamination, paste printing, or film assisted molding. The encapsulant 140 can have a thickness ranging from about 0.1 mm to about 2 mm. The encapsulant 140 can cover the electronic component 110 and the antenna assembly 130 to protect the electronic component 110 and the antenna assembly 130 from exposure to external components or the environment.

[0084] Figure 2E The semiconductor device 100 is shown at a later stage of fabrication. In the example shown, the dielectric structure 151 can be formed on the top surface 110b of the electronic component 110, the top surface 130b of the antenna assembly 130, and the top surface 140b of the encapsulant 140. The dielectric structure 151 can be patterned to expose the internal interconnects 111 and the conductive terminals 132. Figure 2E In the example shown, the semiconductor device 100 can be flipped to remove the carrier 110 in a state where the carrier 10 is positioned on the electronic component 110, the antenna assembly 130, and the encapsulant 140. If the semiconductor device 100 is flipped in this manner, the antenna pattern 134 of the antenna assembly 130 can be positioned on the bottom surface of the semiconductor device 100.

[0085] The carrier 10 can be removed from the top surface 110b of the electronic component 110, the top surface 130b of the antenna assembly 130, and the top surface 140b of the encapsulant 140. The temporary bonding layer 11 can be removed from the electronic component 110, the antenna assembly 130, and the encapsulant 140 in a state where the temporary bonding layer 11 is adhered to the carrier 10. In some examples, heat, light, a chemical solution, or a physical force can be formed on the temporary bonding layer 11 to remove or reduce the bonding strength of the temporary bonding layer 11. As a result, the top surface 110b of the electronic component 110, the top surface 130b of the antenna assembly 130, and the top surface 140b of the encapsulant 110 can be exposed. The internal interconnects 111 of the electronic component 110 and the conductive terminals 130 of the antenna assembly 130 can also be exposed.

[0086] Figure 2F The semiconductor device 100 is shown at a later stage of fabrication. In the example shown, the dielectric structure 151 can be formed on the top surface 110b of the electronic component 110, the top surface 130b of the antenna assembly 130, and the top surface 140b of the encapsulant 140. The dielectric structure 151 can be patterned to expose the internal interconnects 111 and the conductive terminals 132. Figure 2F In the example shown, the dielectric structure 151 can be formed on the top surface 110b of the electronic component 110, the top surface 130b of the antenna assembly 130, and the top surface 140b of the encapsulant 140, and can be patterned to expose the internal interconnects 111 and the conductive terminals 132.

[0087] The dielectric structure 151 may have a uniform thickness to cover the top surface 110b of the electronic component 110, the top surface 130b of the antenna assembly 130, and the top surface 140b of the encapsulant 140. Holes 151x and 151y may be formed in the dielectric structure 151 to expose the internal interconnects 111 of the electronic component 110 and the conductive terminals 132 of the antenna assembly 130.

[0088] The dielectric structure 151 may include or be referred to as a dielectric, a dielectric material, a dielectric layer, a passivation layer, an insulating layer, or a protective layer. In some examples, the dielectric structure 151 may include an electrically insulating material, such as a polymer, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), a molding material, a phenolic resin, an epoxy resin, a silicone resin, or an acrylate polymer. In some examples, the dielectric structure 151 may be formed by any of a variety of processes. The dielectric structure 151 may be formed by, for example, spin coating, spray coating, printing, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. The dielectric structure 151 may have a thickness ranging from about 5 μm to about 50 μm.

[0089] For example, a shielding pattern may be formed on the top surface of dielectric structure 151, and the exposed dielectric structure 151 may be removed by etching to form holes 151x and 151y. Holes 151x and 151y may include or be referred to as openings or holes. Dielectric structure 151 may expose the top surface of internal interconnect 111 of electronic component 110 through hole 151x, and expose the top surface of conductive terminal 132 of antenna assembly 130 through hole 151y. For example, photoresist may be used as the shielding pattern.

[0090] Figure 2G FIG. 1 shows a semiconductor device 100 at a later stage of fabrication. Figure 2G In the example shown, the conductive structure 152 may cover the top surface of the dielectric structure 151 exposed through the holes 151 x and 151 y , the internal interconnects 111 of the electronic component 110 , and the conductive terminals 132 of the antenna assembly 130 .

[0091] Conductive structure 152 can have various patterns and can contact and electrically connect the internal interconnect 111 of electronic component 110 and the conductive terminal 132 of antenna assembly 130, respectively, exposed through holes 151x and 151y. Conductive structure 152 can include conductor 152x, which electrically connects internal interconnect 111 of electronic component 110 and conductive terminal 132 of antenna assembly 130. Conductor 152x can extend from a point above electronic component 110 to a point above each of antenna assemblies 130 to electrically connect electronic component 110 with antenna assembly 130.

[0092] In some examples, the conductive structure 152 may include or be referred to as a conductor, a conductive material, a conductive layer, a redistribution layer (RDL), a wiring pattern, a trace pattern, or a circuit pattern. In some examples, the conductive terminal 132 may include copper, iron, nickel, gold, silver, palladium, or tin. In some examples, one or more conductors 152x may include or be referred to as a trace, a terminal, a pad, a via, a conductive pattern, a conductive layer, or a conductive path, and may extend within and beyond the footprint of the electronic component 110. In some examples, the conductive structure 152 may be formed using, for example, any of a variety of conductive materials (e.g., copper, gold, silver, or equivalents). The conductive structure 152 may be formed by any of a variety of processes (e.g., sputtering, electroless plating, electrolytic plating, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or equivalent methods). The conductive structure 152 may be formed to have a uniform thickness to cover the top surface of the dielectric structure 151 exposed through the holes 151x and 151y, the internal interconnect 111 of the electronic component 110, and the conductive terminal 132 of the antenna assembly 130, and may be patterned using a shielding pattern to have multiple patterns. The conductive structure 152 may have a thickness ranging from about 3 μm to about 50 μm.

[0093] Figure 2H FIG. 1 shows a semiconductor device 100 at a later stage of fabrication. Figure 2H In the example shown, dielectric structure 153 may cover dielectric structure 151 and conductive structure 152 to achieve a uniform thickness. Holes 153x exposing top surface 152b of conductive structure 152 may be formed in dielectric structure 153. Dielectric structure 153 may also expose the top surface of conductor 152x through hole 153x. Dielectric structure 153 may be similar to dielectric structure 151 and may be formed similarly to dielectric structure 151.

[0094] Although only two dielectric structures 151 and 153 and one conductive structure 152 are shown in substrate 150, this is not a limitation of the present disclosure. In some examples, the number of structures comprising substrate 150 can be less than or greater than the number of structures shown in the present disclosure.

[0095] In this example, substrate 150 is presented as a redistribution layer (RDL) substrate. The RDL substrate may include one or more conductive redistribution layers and one or more dielectric layers, which (a) may be formed layer by layer over the electronic components to which the RDL substrate is electrically coupled, or (b) may be formed layer by layer over a carrier that may be completely or at least partially removed after the electronic components and the RDL substrate are coupled together. The RDL substrate may be manufactured layer by layer as a wafer-level substrate on a circular wafer in a wafer-level process, or as a panel-level substrate on a rectangular or square panel carrier in a panel-level process. The RDL substrate may be formed in an additive build-up process, which may include one or more dielectric layers stacked alternately with one or more conductive layers defining respective conductive redistribution patterns or traces, the conductive redistribution patterns or traces being configured to collectively (a) fan out the electrical traces outside the footprint of the electronic components, or (b) fan in the electrical traces into the footprint of the electronic components. The conductive pattern can be formed using a plating process such as an electrolytic plating process or an electroless plating process. The conductive pattern can include a conductive material such as copper or other plateable metal. The location of the conductive pattern can be formed using a photolithography process and a photoresist material forming a photolithography mask. The dielectric layer of the RDL substrate can be patterned using a photopatterning process, which can include a photolithography mask through which light is exposed to have desired photopattern features (such as through holes in the dielectric layer). The dielectric layer can be made of a photodefinable organic dielectric material, such as polyimide (PI), benzocyclobutene (BCB) or polybenzoxazole (PBO). This dielectric material can be applied by spin coating or other means in liquid form, rather than being attached as a preformed film. To allow the desired photodefinable features to be properly formed, this photodefinable dielectric material can omit structural reinforcement or can be filler-free, without strands, weaves or other particles that may interfere with the photopatterning process. In some examples, this unfilled characteristic of having an unfilled dielectric material can reduce the thickness of the resulting dielectric layer. Although the above-mentioned photodefinable dielectric material can be an organic material, in some examples, the dielectric material of the RDL substrate can include one or more inorganic dielectric layers. Some examples of inorganic dielectric layers can include silicon nitride (Si3N4), silicon oxide (SiO2) or SiON. The inorganic dielectric layer can be formed by growing the inorganic dielectric layer using an oxidation or nitridation process instead of a photodefined organic dielectric material. This inorganic dielectric layer can be unfilled, without strands, braids or other different inorganic particles. In some examples, the RDL substrate can omit a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and these types of RDL substrates can include or be referred to as coreless substrates. Other substrates in the present disclosure may also include RDL substrates.

[0096] In some examples, the substrate 150 can be a pre-formed substrate. The pre-formed substrate can be fabricated prior to attachment to the electronic components and can include dielectric layers between individual conductive layers. The conductive layers can include copper and can be formed using an electrolytic plating process. The dielectric layers can be relatively thick, photo-undefinable layers that can be attached as pre-formed films rather than as liquids and can include a resin with fillers, such as strands, weaves, or other inorganic particles, to increase rigidity or structural support. Because the dielectric layers are photo-undefinable, features such as vias or openings can be formed using drilling or laser. In some examples, the dielectric layers can include a prepreg or an anisotropic build-up film (ABF). The pre-formed substrate can include a permanent core structure or carrier, such as a dielectric material including a bismaleimide triazine (BT) or FR4, and the dielectric layers and conductive layers can be formed on the permanent core structure. In some examples, the pre-formed substrate can be a coreless substrate that omits the permanent core structure, and the dielectric layers and conductive layers can be formed on a sacrificial carrier that is removed after the dielectric layers and conductive layers are formed and prior to attachment to the electronic components. The pre-formed substrate can be referred to as a printed circuit board (PCB) or a laminate substrate. Such pre-formed substrates can be formed by a semi-additive or modified semi-additive process. Other substrates in the present disclosure can also include pre-formed substrates.

[0097] Figure 2I The semiconductor device 100 is shown at a back end of fabrication. In the example shown, the electronic components 110 are attached to the substrate 150. Figure 2I In the example shown, the external interconnects 160 can be formed on the top surface 152b of the conductive structure 152.

[0098] The external interconnects 160 can be electrically connected to the top surface 152b of the conductive structure 152. The external interconnects 160 can be electrically connected to the electronic components 110 or to the antenna assembly 130 through the substrate 150. The external interconnects 160 can be electrically connected to the electronic components 110 and to the antenna assembly 130 through the conductor 152x of the substrate 150.

[0099] In some examples, the external interconnect 160 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. The external interconnect 160 may be formed using, for example, a ball drop process, a screen printing process, or an electrolytic plating process. For example, the external interconnect 160 may be formed by pre-preparing a conductive material including solder on the top surface 152b of the conductive structure 152 of the substrate 150 using a ball drop process followed by a reflow process. The external interconnect 160 may include or be referred to as a conductive ball (e.g., a solder ball), a conductive pillar (e.g., a copper pillar), or a conductive rod having a solder cap on the copper pillar. The external interconnect 160 may have a size ranging from about 0.01 mm to about 1 mm. The completed semiconductor device 100 may be flipped over so that the external interconnect 160 is positioned on the bottom surface 100 y of the semiconductor device 100 .

[0100] entire Figures 2A to 2I The proposed method can be used to fabricate various semiconductor devices, such as Figures 4A to 6F For example, Figure 6A A top view of semiconductor device 1006 is shown. Figures 6B to 6F A cross-sectional view of the semiconductor device 1006 along different antenna components 330x, 330y, 430z is shown.

[0101] Figure 6A Several antenna assemblies are shown coupled to substrate 150 at a portion of the substrate defined around footprint 119 of electronic component 110, or around the center of the arrangement of antenna assemblies, the substrate portion being demarcated by a dashed line. Antenna assembly 330x1 is shown coupled to substrate left portion 156, antenna assembly 330x2 is shown coupled to substrate right portion 157, antenna assembly 330y1 is shown coupled to substrate right portion 157, antenna assembly 330y2 is shown coupled to substrate left portion 156, antenna assembly 430z1 is shown coupled to substrate upward portion 158, and antenna assembly 430z2 is shown coupled to substrate downward portion 159.

[0102] Substrate 150 includes a substrate dielectric structure having one or more dielectric layers, such as dielectric layers 151 and 153, between a substrate top side 154 and a substrate bottom side 155. Substrate 150 also includes a substrate conductive structure 152, which includes one or more conductors, conductive layers, pads, vias, or traces that extend horizontally or vertically through the substrate dielectric structure. Substrate conductive structure 152 may include substrate terminals 1521 and may include substrate terminals 1522 exposed at substrate top side 154. In some examples, substrate terminals 1521 and 1522 may include or be referred to as pads, vias, or traces.

[0103] Electronic component 110 can be coupled to substrate 150 and can include component terminals 115 coupled to substrate terminals 1521. In some examples, component terminals 115 can include or be referred to as pads, bumps, or posts. In some examples, component side surfaces 117 of electronic component 110 can directly contact substrate top side 154. In some examples, such as when component terminals 115 include bumps or posts, component side surfaces 117 of electronic component 110 can be separated from substrate top side by a gap distance defined by the height of component terminals 115.

[0104] In some examples, Figure 6A The footprint 119 shown in FIG. 1 may represent an area of ​​the substrate 150 that is covered by the electronic component 110 , wherein the electronic component 110 may be associated with, for example, Figures 1 to 2I The electronic component 110 may be coupled to the substrate top side 154 in the manner shown and described, or the ... Figures 11 to 16B 1 and 2 are coupled to substrate bottom side 155 in the manner shown and described with reference to the corresponding components in FIG.

[0105] Semiconductor device 1006 may include one or more passive components coupled to substrate 150. In some examples, the passive components may be similar in features or locations to those described below with respect to 7A to 10B or Figures 14 to 16BThe further described passive members 520 or 720. In some examples, one or more of the passive members can be coupled to the substrate 150 at least partially within the footprint 119 of the electronic member 110, whether this passive member is on the substrate bottom side 155 and the electronic member 110 is on the substrate top side 154, or this passive member is on the substrate top side 154 and the electronic member 110 is on the substrate bottom side 155. In some examples, one or more of the passive members can be coupled to the substrate upward portion 158, whether at the substrate top side 154 or the substrate bottom side 155, between the antenna assembly 330xl and the antenna assembly 330yl, adjacent the antenna assembly 430zl, or adjacent the electronic member 110. In some examples, one or more of the passive members can be coupled to the substrate downward portion 159, whether at the substrate top side 154 or the substrate bottom side 155, between the antenna assembly 330yl and the antenna assembly 330x2, adjacent the antenna assembly 430z2, or adjacent the electronic member 110. In some examples, one or more of the passive members can be coupled to the substrate leftward portion 156, whether at the substrate top side 154 or the substrate bottom side 155, between the antenna assembly 430zl and the antenna assembly 430z2, adjacent the antenna assembly 330xl or the antenna assembly 330yl, or adjacent the electronic member 110. In some examples, one or more of the passive members can be coupled to the substrate rightward portion 157, whether at the substrate top side 154 or the substrate bottom side 155, between the antenna assembly 430zl and the antenna assembly 430z2, adjacent the antenna assembly 330yl or the antenna assembly 330x2, or adjacent the electronic member 110.

[0106] The antenna assembly 330x, 330y, 430z can include an outward vertical surface facing horizontally outward from the semiconductor device 1006, and an inward vertical surface opposite the outward vertical surface. Depending on the antenna assembly, the outward vertical surface can correspond to the assembly head side 135 or the assembly sidewall 136, and the inward vertical surface can correspond to the assembly base side 137 or the assembly sidewall 136. The semiconductor device 1006 can include an encapsulant 140 on the substrate top side 154. In some examples, the encapsulant 140 can cover the inward vertical surface of the antenna assembly 330x, 330y, or 430z. In some examples, the encapsulant 140 can cover the outward vertical surface of the antenna assembly 330x, 330y, or 430z. In some examples, the encapsulant 140 exposes the outward vertical surface of the antenna assembly 330x, 330y, or 430z. The encapsulant 140 can also cover the component sidewall 116 or the component side 115 of the electronic component 110. In some examples, the shield structure 112 can cover the component sidewall 116 and the component side 115, and the encapsulant 140 can then cover the shield structure 112 adjacent to the component sidewall 116 or adjacent to the component side 115. In some examples, the encapsulant 140 can expose the shield structure 112 adjacent to the component side 115.

[0107] Figure 6B The illustrated cross-sectional view corresponds to line 6B-6B of Figure 6A and shows antenna assembly 330xl and antenna assembly 330x2 coupled to the substrate 150 outside the footprint 119 of the electronic component 110. The antenna assembly 330xl or the antenna assembly 330x2 can be similar to the previously described antenna assembly 130. The antenna assembly 330xl can be similar to the antenna assembly 330x2, but can be coupled opposite one another. The configuration, orientation, or features of the antenna assembly 330yl and 330y2 can be similar to the configuration, orientation, or features previously described with respect to the antenna assembly 130 in Figures 1 to 3 .

[0108] As an example, antenna assembly 330x2 includes an assembly dielectric structure 131 comprising one or more dielectric layers; an antenna pattern 134 coupled to assembly dielectric structure 131; and an assembly terminal 132 coupled to substrate terminal 1522. Assembly terminal 132 may be part of a conductive structure 133 that provides a conductive path or antenna path comprising one or more traces or vias that traverse assembly dielectric structure 131 to couple antenna pattern 134 to assembly terminal 132. Antenna assembly 330x1 also includes an assembly head side 135 adjacent to antenna pattern 134; an assembly substrate side 137 opposite assembly head side 135; and an assembly sidewall 136 between assembly head side 135 and assembly substrate side 137. In some examples, antenna pattern 134 may be exposed at or through assembly head side 134 for outbound or inbound wireless communications. In this example, component terminals 132 are exposed at component substrate side 137, and antenna pattern 134 is coupled to substrate 150 through component terminals 132 and substrate terminals 1522. Substrate conductive structures 152 couple antenna assembly 330x2 to electronic component 110, providing a conductive path between component terminals 132 and component terminals 115.

[0109] The antenna pattern 134 can be configured or oriented to transmit or receive wireless communications in a direction substantially orthogonal to the antenna head side 135 or the antenna pattern 134. For antenna assembly 330x2, the assembly head side 135 faces in a vertical direction toward the top, the antenna pattern 134 is oriented for communication in this vertical direction, and the assembly base side 137 is coupled to the substrate 150. Similarly, in this example, antenna assembly 330x1 includes an assembly head side 135 facing in a vertical direction toward the top, the antenna pattern 134 is oriented for communication in this vertical direction, and the assembly base side 137 is coupled to the substrate 150. In some examples, the encapsulant 140 can cover the assembly head side 135 or the antenna pattern 134. In some examples, the encapsulant 140 can be applied, or the antenna assembly 330x1 or the antenna assembly 330x2 can be positioned, such that the assembly head side 135 or the antenna pattern 134 remains exposed from the encapsulant 140.

[0110] However, there are multiple examples in which one or both of antenna assembly 330x1 or antenna assembly 330x2 can be oriented so that antenna head side 135 faces a horizontal direction for communication along this horizontal direction. In these examples, assembly sidewall 136 can be coupled to substrate 150, or assembly terminal 132 can be exposed at assembly sidewall 137 and coupled to substrate terminal 1522. There are multiple examples in which one of antenna assembly 330x1 or antenna assembly 330x2 can be oriented as described above for vertical communication toward the top, and the other of antenna assembly 330x1 or antenna assembly 330x2 can be oriented so that antenna head side 135 faces a vertical direction toward the bottom for communication along this vertical direction.

[0111] Figure 6C The cross-section shown in corresponds to Figure 6A 6C-6C and shows antenna assembly 330y1 and antenna assembly 330y2 coupled to substrate 150 outside component footprint 119 of electronic component 110. Antenna assembly 330y1 or antenna assembly 330y2 can be similar to antenna assembly 130 described previously. Antenna assembly 330y1 can be similar to antenna assembly 330y2, but can be coupled opposite each other. The configuration, orientation, or features of antenna assemblies 330y1 and 330y2 can be similar to those described above with respect to Figures 4A to 4B The antenna assembly 230 in FIG.

[0112] exist Figure 6C , antenna assembly 330y1 includes an assembly head side 135 facing the right horizontal direction, has an antenna pattern 134 oriented to communicate along the right horizontal direction, and has an assembly sidewall 136 coupled to substrate 150. Antenna assembly 330y2 includes an assembly head side 135 facing the left horizontal direction, has an antenna pattern 134 facing the left horizontal direction, and has an assembly sidewall 136 coupled to substrate 150. In some examples, encapsulant 140 may cover assembly head side 135 or antenna pattern 134. In some examples, encapsulant 140 may be applied or antenna assembly 330y1 or antenna assembly 330y2 may be positioned such that assembly head side 135 or antenna pattern 134 remain exposed from encapsulant 140.

[0113] Figure 6D The cross-section shown in corresponds to Figure 6A 6D-6D and shows antenna assembly 330x1 and antenna assembly 330y1 coupled to substrate 150 outside of component footprint 119 of electronic component 110. Antenna assembly 330x1 or antenna assembly 330y1 can be similar to previously described antenna assembly 130. Antenna assembly 330x1 can be similar to antenna assembly 330y1, but can be coupled opposite each other or in a different orientation.

[0114] exist Figure 6D , antenna assembly 330x1 includes an assembly head side 135 facing a vertically upward direction, has an antenna pattern 134 oriented for communication along the vertically upward direction, and has an assembly base side 137 coupled to substrate 150. Antenna assembly 330y1 includes an assembly head side 135 facing a rightward horizontal direction, has an antenna pattern 134 oriented for communication along the rightward horizontal direction, and has an assembly sidewall 136 coupled to substrate 150. In some examples, encapsulation 140 may cover assembly head side 135 or antenna pattern 134. In some examples, encapsulation 140 may be applied or antenna assembly 330x1 or antenna assembly 330y1 may be positioned such that assembly head side 135 or antenna pattern 134 remain exposed from encapsulation 140.

[0115] Figure 6E The cross-section shown in corresponds to Figure 6A 6E-6E and shows antenna assembly 330y2 and antenna assembly 330x2 coupled to substrate 150 outside of component footprint 119 of electronic component 110. Antenna assembly 330y2 or antenna assembly 330x2 can be similar to previously described antenna assembly 130. Antenna assembly 330x2 can be similar to antenna assembly 330y2, but can be coupled opposite each other or in a different orientation.

[0116] exist Figure 6E , antenna component 330y2 includes a component head side 135 facing a left horizontal direction, has an antenna pattern 134 facing the left horizontal direction, and has a component sidewall 136 coupled to substrate 150. Antenna component 330x2 includes a component head side 135 facing a top vertical direction, has an antenna pattern 134 oriented to communicate along the top vertical direction, and has a component base side 137 coupled to substrate 150. In some examples, encapsulant 140 may cover component head side 135 or antenna pattern 134. In some examples, encapsulant 140 may be applied or antenna component 330y2 or antenna component 330x2 may be positioned such that component head side 135 or antenna pattern 134 remain exposed from encapsulant 140.

[0117] Figure 6F The cross-section shown in corresponds to Figure 6A 6F-6F and shows antenna assembly 430z1 and antenna assembly 430z2 coupled to substrate 150 outside of component footprint 119 of electronic component 110. Antenna assembly 430z1 or antenna assembly 430z2 can be similar to previously described antenna assembly 130. Antenna assembly 430z1 can be similar to antenna assembly 430z2, but can be coupled opposite each other or in a different orientation.

[0118] exist Figure 6F , antenna assembly 430z1 includes an assembly head side 135 facing an upward vertical direction, has an antenna pattern 134 oriented to communicate along the upward vertical direction, and has an assembly sidewall 136 coupled to substrate 150. Antenna assembly 430z2 includes an assembly head side 135 facing a downward vertical direction, has an antenna pattern 134 oriented to communicate along the downward vertical direction, and has an assembly base side 137 coupled to substrate 150. In some examples, encapsulant 140 may cover assembly head side 135 or antenna pattern 134. In some examples, encapsulant 140 may be applied or antenna assembly 430z1 or antenna assembly 430z2 may be positioned such that assembly head side 135 or antenna pattern 134 remain exposed from encapsulant 140.

[0119] Figures 7A to 7D A perspective plan view showing an exemplary semiconductor device, along Figure 7A The cross-sectional view along line 7B-7B, Figure 7A The cross-sectional view along line 7C-7C and the Figure 7A A cross-sectional view along line 7D-7D.

[0120] In such Figures 7A to 7D In the example shown, the semiconductor device 500 may include an electronic component 110 , a passive component 520 , an antenna element 130 , an encapsulant 540 , a substrate 550 , and external interconnects 160 .

[0121] The electronic component 110, antenna assembly 130, and external interconnect 160 may be similar to the Figure 1 Components of the semiconductor device 100 are shown in FIG. Passive component 520 may include terminal 521 . Substrate 550 may include dielectric structures 551 and 553 and conductive structure 552 .

[0122] The antenna assembly 130, encapsulant 540, substrate 550, and external interconnect 160 may comprise or be referred to as a semiconductor package 501 or package 501, and may protect the electronic components 110 and the passive components 520 from external components or environmental exposure. The semiconductor package 501 may provide electrical coupling between external components and the electronic components, and between the external components and the passive components 520.

[0123] Figures 8A to 8F A cross-sectional view of an exemplary method for fabricating an exemplary semiconductor device 500 is shown. Figures 9A to 9F Display for manufacturing Figures 8A to 8F 5. In particular, in the cross-sectional view of the exemplary method of manufacturing the exemplary semiconductor device 500, Figures 8A to 8F Display along Figure 7AA cross-sectional view taken along line 7C-7C in FIG. Figures 9A to 9F Display along Figure 7A In particular, along the line 7D-7D Figure 7A The cross-sectional view of line 7B-7B in FIG. Figure 2C to Figure 2I The cross-sectional view shown.

[0124] Figure 8A 、 Figure 9A and Figure 10A A semiconductor device 500 is shown at an early stage of manufacturing.

[0125] As in Figure 8A 、 Figure 9A and Figure 10A In the example shown in FIG, a semiconductor device 500 can be prepared. Figure 8A 、 Figure 9A and Figure 10A The semiconductor device 500 shown in FIG. Figures 2A to 2C and Figure 3 The semiconductor device 100 is manufactured by the exemplary method of manufacturing the semiconductor device 100 shown in FIG.

[0126] Figure 8B 、 9B 10B and 10B show a semiconductor device 500 in a later manufacturing stage. Figure 8B 、 Figure 9B and Figure 10B In the example shown, the bottom surface 520b of the passive component 520 can be bonded to a surface of the temporary bonding layer 11 of the carrier 10. The passive component 520 can be bonded to the carrier 10 so as to be positioned on opposite sides of the electronic component 110 along the first direction x. The passive components 520 can be arranged on the temporary bonding layer 11 of the carrier 10 in a matrix configuration having rows or columns and bonded to the temporary bonding layer 11 of the carrier 10 so that the passive components 520 can be positioned between the antenna assemblies 130 spaced apart from each other in the second direction y. The terminals 521 of the passive component 520 can be bonded to the temporary bonding layer 11.

[0127] In some examples, a pick-and-place device can pick up and place the passive component 520 on the temporary bonding layer 11 of the carrier 10 and can be bonded to the temporary bonding layer 11. The bottom surface of the passive component 520 can be bonded to the temporary bonding layer 11. The passive component 520 can include a terminal 521 exposed on its bottom surface. The terminal 521 can be bonded to the temporary bonding layer 11 of the carrier 10. The terminal 521 can be an input terminal or an output terminal of the passive component 520.

[0128] In some examples, the passive component 520 may include at least one of a resistor, a capacitor, an inductor, a connector, and the like. The passive component 520 may have an overall thickness ranging from about 0.01 mm to about 2 mm.

[0129] The antenna assembly 130 can be Figure 2C 、 Figure 3 、 Figure 4A 、 Figure 4B 、 Figures 5A to 5C as well as Figures 6A to 6D The passive component 520 can be changed based on the layout of the antenna components 130, 230, 330, and 430 shown in FIG. Alternatively, the antenna component 130 can be changed by arbitrarily configuring a vertical antenna or a horizontal antenna in various ways. Here, the passive component 520 can be changed based on the layout, so that it can be configured in various ways within the surface of the temporary bonding layer 11 of the carrier 10 based on the layout of the antenna components 130, 230, 330, and 430.

[0130] Figure 8C and Figure 9C The semiconductor device 500 is shown in the latter stage of manufacturing. Figure 8C and Figure 9C In the example shown, encapsulant 540 may cover carrier 10, electronic component 110, passive component 520, and antenna assembly 130. In some examples, encapsulant 540 may contact the top surface of temporary bonding layer 11 of carrier 10, the outer surface of EMI shield 112, the top and side surfaces of passive component 520, and the side surfaces of antenna assembly 130. Here, antenna pattern 134 of antenna assembly 130 may be exposed. Encapsulant 540 may be similar to encapsulant 140 and may be formed similarly to encapsulant 140.

[0131] Figure 8D and Figure 9D The semiconductor device 500 is shown in the latter stage of manufacturing. Figure 8D and Figure 9D In the example shown, the semiconductor device 500 can be turned over to remove the carrier 10 while the carrier 10 is positioned on the electronic component 110 , the passive component 520 , the antenna assembly 130 , and the encapsulant 540 .

[0132] The carrier 10 can be removed from the top surface 110b of the electronic component 110, the top surface 520b of the passive component 520, the top surface of the antenna assembly 130, and the top surface 540b of the encapsulation 540. As a result, the top surface 110b of the electronic component 110, the top surface 520b of the passive component 520, the top surface of the antenna assembly 130, and the top surface 540b of the encapsulation 540 can be exposed. The internal interconnects 111 of the electronic component 110, the terminals 521 of the passive component 520, and the conductive terminals 132 of the antenna assembly 130 can also be exposed. The removal of the carrier 10 can be similar to Figure 2E Removal of the carrier 10 shown in FIG.

[0133] Figure 8E and Figure 9E The semiconductor device 500 is shown in the latter stage of manufacturing. Figure 8E and Figure 9E In the example shown, substrate 550 may be formed on top surface 110b of electronic component 110, top surface 520b of passive component 520, top surface 540b of antenna assembly 130, and top surface 540b of encapsulant 540. In some examples, substrate 550 may be similar to substrate 150 or may include or be referred to as a substrate. Substrate 550 may include dielectric structure 551, conductive structure 552, and dielectric structure 553, and may be formed sequentially.

[0134] A dielectric structure 551 may first be formed on the substrate 550 to uniformly cover the top surface 110b of the electronic component 110, the top surface 520b of the passive component 520, the top surface of the antenna assembly 130, and the top surface 540b of the encapsulant 540. Holes 551x, 551y, and 551z may be formed in the dielectric structure 551 to expose the internal interconnect 111 of the electronic component 110, the conductive terminal 132 of the antenna assembly 130, and the terminal 521 of the passive component 520, respectively. The dielectric structure 551 may expose the top surface of the internal interconnect 111 of the electronic component 110 through hole 551x, the top surface of the conductive terminal 132 of the antenna assembly 130 through hole 551y, and the top surface of the terminal 521 of the passive component 520 through hole 551z, respectively. The dielectric structure 551 may be similar to the dielectric structure 151 and may be formed similarly to the dielectric structure 151.

[0135] The conductive structure 552 may cover the internal interconnect 111 of the electronic component 110 , the conductive terminal 132 of the antenna assembly 130 , and the terminal 521 of the passive component 520 and be exposed through the top surface of the dielectric structure 551 and the holes 551 x , 551 y , and 551 z .

[0136] The conductive structure 552 may be formed to have a plurality of patterns and is connected to the interconnect 111 of the electronic component 110, the conductive terminal 132 of the antenna assembly 130, and the terminal 521 of the passive component 520, and may be exposed through the holes 551x, 551y, and 551z, respectively, and may be electrically connected. The conductive structure 552 may include a trace 552x that electrically connects the internal interconnect 111 of the electronic component 110 and the terminal 521 of the passive component 520 to each other. The trace 552x may extend from a point on the electronic component 110 to a point on the passive component 520 to electrically connect the internal interconnect 111 of the electronic component 110 and the conductive terminal 132 of the antenna assembly 130 to each other, just like the passive component 520. The trace 552x may also electrically connect the internal interconnect 111 of the electronic component 110 and the conductive terminal 132 of the antenna assembly 130, just like Figure 2G Conductive structure 552 may be similar to conductive structure 152 and may be formed similarly to conductive structure 152 .

[0137] Dielectric structure 553 may cover dielectric structure 551 and conductive structure 552 to a uniform thickness. Holes 553x that expose top surface 552b of conductive structure 552 may be formed in dielectric structure 553. Dielectric structure 553 may also expose the top surface of trace 552y through hole 553x. Dielectric structure 553 may be similar to dielectric structure 151 and may be formed similarly to dielectric structure 151.

[0138] Although only two dielectric structures 551 and 553 and one conductive structure 552 are shown in substrate 550, this is not a limitation of the present invention. In some examples, the number of structures used to construct substrate 550 can be less than or greater than the number shown in the examples of the present invention.

[0139] Figure 8F and Figure 9F A semiconductor device 500 is shown in the latter stages of manufacturing. Figure 8F and Figure 9F In the example shown, the external interconnect 160 may be formed on the top surface 552 b of the conductive structure 552 .

[0140] External interconnect 160 may be electrically connected to top surface 552b of conductive structure 552. External interconnect 160 may be electrically connected to electronic component 110, passive component 520, or antenna assembly 130 via substrate 150. External interconnect 160 may be electrically connected to electronic component 110 and antenna assembly 130 via conductor 152x, or external interconnect 160 may be electrically connected to both electronic component 110 and passive component 520. External interconnect 160 may be similar to external interconnect 160 of semiconductor device 100 and may be formed similarly to external interconnect 160 of semiconductor device 100.

[0141] Figure 11 A cross-sectional view of an exemplary semiconductor device 600 is shown. Figure 11 In the example shown in , the semiconductor device 600 may include an electronic component 610 , an antenna assembly 630 , an encapsulant 640 , a substrate 650 , and external interconnects 660 .

[0142] The electronic component 610 may include an internal interconnect 611. The antenna assembly 630 may include a dielectric structure 631, conductive structures 632 and 633, and an antenna pattern 634. The substrate 650 may include dielectric structures 651 and 653, and a conductive structure 652.

[0143] Antenna assembly 630 , encapsulant 640 , substrate 650 , and external interconnects 660 may comprise or be referred to as semiconductor package 601 or package 601 , and may protect electronic component 610 from external components or environmental exposure.

[0144] Figures 12A to 12F A cross-sectional view of an exemplary method for fabricating an exemplary semiconductor device 600 is shown. Figure 13 Display used to make Figure 12A FIG. 4 is a cross-sectional view of an exemplary method of manufacturing an exemplary semiconductor device 600 shown in FIG.

[0145] Figure 12A and Figure 13 The semiconductor device 600 is shown in an earlier stage of manufacturing. Figure 12A and Figure 13 In the example shown in FIG. 6 , the bottom surface 630 b of the antenna assembly 630 may be adhered to a temporary bonding layer 11 provided on the carrier 10 .

[0146] In some examples, a pick-and-place device can pick up and place the antenna assembly 630 on a surface of the temporary bonding layer 11 of the carrier 10 and can be bonded to the temporary bonding layer 11. In some examples, two antenna assemblies 630 can be bonded to the carrier 10 so as to be positioned at opposite sides along the second direction y. The two antenna assemblies 630 can be arranged so that the inner surfaces 630c of the two antenna assemblies 630 face each other and can be separated from each other. Each of the antenna assemblies 630 can extend longitudinally along the first direction x. The antenna assembly 630 can be similar to the antenna assembly 130 and can be formed similarly to the antenna assembly 130. The antenna assembly 630 can be formed by Figure 3 、 Figure 4A 、 Figure 4B 、 Figures 5A to 5C as well as Figures 6A to 6D Alternatively, antenna assembly 630 may be modified by arbitrarily configuring vertical antennas or horizontal antennas in various ways.

[0147] Figure 12B The semiconductor device 600 is shown in the latter stage of manufacturing. Figure 12B In the example shown, encapsulant 640 may cover carrier 10 and antenna assembly 630. In some examples, encapsulant 640 may contact the top surface of temporary bonding layer 11 of carrier 10 and the side surfaces of antenna assembly 630. Here, antenna pattern 634 of antenna assembly 630 may be exposed. Encapsulant 640 may be similar to encapsulant 140 and may be formed similarly to encapsulant 140.

[0148] Figure 12C The semiconductor device 600 is shown in the latter stage of manufacturing. Figure 12C In the example shown, the semiconductor device 600 can be flipped over to remove the carrier 10 while the carrier 10 is positioned on the antenna assembly 630 and the encapsulant 640 .

[0149] The carrier 10 can be removed from the top surface 630b of the antenna component 630 and the top surface 640b of the encapsulation 640. As a result, the top surface 630b of the antenna component 630 and the top surface 640b of the encapsulation 640 can be exposed. The conductive pattern 632 of the antenna component 630 can also be exposed. The removal of the carrier 10 is similar to Figure 2E Removal of the carrier 10 is shown.

[0150] Figure 12D The semiconductor device 600 is shown in the latter stage of manufacturing. Figure 12DIn the example shown, substrate 650 can be formed on top surface 630b of antenna assembly 630 and top surface 640b of encapsulant 640. In some examples, substrate 650 can be similar to substrate 150, or can include or be referred to as a substrate. Substrate 650 can include dielectric structure 651, conductive structure 652, and dielectric structure 653, formed sequentially.

[0151] The dielectric structure 651 may cover the top surface 630b of the antenna assembly 630 and the top surface 640b of the encapsulant 640 to a uniform thickness. A hole 651x exposing the conductive pattern 632 of the antenna assembly 630 may be formed in the dielectric structure 651. The dielectric structure 651 may expose the top surface of the conductive pattern 632 of the antenna assembly 630 through the hole 651x. The dielectric structure 651 may be similar to the dielectric structure 151 and may be formed similarly to the dielectric structure 151.

[0152] The conductive structure 652 may cover the top surface of the dielectric structure 651 and the conductive pattern 632 of the antenna assembly 630 exposed through the hole 651x. The conductive structure 652 may have multiple patterns that are in contact with and electrically connected to the conductive pattern 632 of the antenna assembly 630 exposed through the hole 651x. The conductive structure 652 may be electrically connected to the conductive pattern 632 of the antenna assembly 630 and may include a trace 652x extending along the top surface 640b of the encapsulant 640. The conductive structure 652 may be similar to the conductive structure 152 and may be formed similarly to the conductive structure 152.

[0153] The dielectric structure 653 may cover the dielectric structure 651 and the conductive structure 652 to a uniform thickness. A hole 653x may be formed in the dielectric structure 653 to expose the top surface 652b of the conductive structure 652. The dielectric structure 653 may also expose the top surface of the trace 652x through the hole 653x. The dielectric structure 653 may be similar to the dielectric structure 651 and may be formed similarly to the dielectric structure 651.

[0154] Although only two dielectric structures 651 and 653 and one conductive structure 652 are shown in substrate 650, this is not a limitation of the present invention. In some examples, the number of structures used to construct substrate 650 can be less than or greater than the number shown in the examples of the present invention.

[0155] Figure 12E The semiconductor device 600 is shown in the latter stage of manufacturing. Figure 12E In the example shown, the internal interconnect 611 of the electronic component 610 can be electrically connected to the top surface 652b of the conductive structure 652. The electronic component 610 can be positioned in the center of the substrate 650.

[0156] In some examples, a pick-and-place device can pick up and place the electronic component 610 onto the trace 652x of the conductive structure 652 of the substrate 650. The electronic component 610 can then be electrically connected to the conductive structure 652 of the substrate 650 using a mass reflow process, a thermal press process, or a film assist bonding process. The electronic component 610 can then be electrically connected to the antenna assembly 630 via the conductive structure 652 of the substrate 650.

[0157] In some examples, electronic component 610 may include an active region and an inactive region. In some examples, the active region may be formed to face substrate 650. In some examples, the active region may include internal interconnects 611. In some examples, internal interconnects 611 may include or be referred to as die pads, bonding pads, aluminum pads, conductive pillars, or conductive rods.

[0158] The internal interconnect 611 can be connected to the conductive structure 652 of the substrate 650 using a low-melting-point material 612. In some examples, the low-melting-point material 612 can include one selected from the group consisting of Sn, Ag, Pb, Cu, Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, Sn-Ag-Cu, and equivalents. The internal interconnect 611 of the electronic component 610 and the conductive structure 652 of the substrate 650 can be electrically connected to each other via the low-melting-point material 612. The electronic component 610 can have an overall thickness ranging from approximately 0.1 mm to approximately 1 mm.

[0159] Figure 12F The semiconductor device 600 is shown in the latter stage of manufacturing. Figure 12F In the example shown, the external interconnect 660 is formed on the top surface 652b of the conductive structure 652. The external interconnect 660 can be electrically connected to the top surface 652b of the conductive structure 652.

[0160] External interconnects 660 may be provided outside electronic component 610 and spaced apart from each other in a matrix configuration having rows or columns. External interconnects 660 may be electrically connected to electronic component 610 or antenna assembly 630 via substrate 650. External interconnects 660 may be electrically connected to electronic component 610 and antenna assembly 630 via traces 652x. External interconnects 660 may be similar to external interconnects 160 and may be formed similarly to external interconnects 160.

[0161] Figure 14 A cross-sectional view of an exemplary semiconductor device 700 is shown. Figure 14In the example shown, semiconductor device 700 may include electronic components 710 , passive components 720 , antenna assembly 630 , encapsulation 740 , substrate 750 , and external interconnects 760 .

[0162] Electronic component 710 may include internal interconnect 711. Passive component 720 may include terminal 721. Antenna assembly 630 may include dielectric structure 631, conductive structures 632 and 133, and antenna pattern 634. Substrate 750 may include dielectric structures 751 and 653, and conductive structure 752.

[0163] Antenna assembly 630, encapsulant 740, substrate 750, and external interconnects 760 may comprise or be referred to as semiconductor package 701 or package 701, and may protect electronic component 710 from external components or environmental exposure. Semiconductor package 701 may provide electrical coupling between external components and electronic component 710.

[0164] Figures 15A to 15G A cross-sectional view of an exemplary method for fabricating an exemplary semiconductor device 700 is shown. FIG. 16A to FIG. 16B Display for manufacturing FIG. 15A to FIG. 15B A plan view of an exemplary method of illustrating an exemplary semiconductor device 700 is shown.

[0165] Figure 15A and Figure 16A The semiconductor device 700 is shown in an earlier stage of manufacturing. Figure 15A and Figure 16A In the example shown, a semiconductor device 700 may be prepared. Figure 15A and Figure 16A The semiconductor device 700 shown in FIG. Figure 12A and Figure 13 . A semiconductor device 600 manufactured by an exemplary method is shown in FIG.

[0166] Figure 15B The semiconductor device 700 is shown at the end of the manufacturing process. Figure 15B In the example shown, the bottom surface 720b of the passive component 720 may be bonded to a surface of the temporary bonding layer 11 of the carrier 10. The passive component 720 may be positioned between the inner side surfaces 630c of the two spaced-apart antenna assemblies 630. The passive component 720 may be arranged on the temporary bonding layer 11 of the carrier 10 and spaced apart from each other in a matrix configuration having rows or columns, so as to be positioned between the two antenna assemblies 630 spaced apart from each other in the second direction y and bonded to the temporary bonding layer 11 of the carrier 10. The terminal 721 of the passive component 720 may also be bonded to the temporary bonding layer 11. The passive component 720 may be similar to the passive component 520 and may be formed similarly to the passive component 520.

[0167] Figure 15C FIG. 7 shows a semiconductor device 700 at the end of manufacturing. Figure 15C In the example shown, encapsulant 740 may cover carrier 10, passive component 720, and antenna assembly 630. In some examples, encapsulant 740 may contact the top surface of temporary bonding layer 11 of carrier 10, the side surfaces of passive component 720, and the side surfaces of antenna assembly 630. Here, antenna pattern 634 of antenna assembly 630 may be exposed. Encapsulant 740 may be similar to encapsulant 140 and may be formed similarly to encapsulant 140.

[0168] Figure 15D FIG. 7 shows a semiconductor device 700 at the end of manufacturing. Figure 15D In the example shown, the semiconductor device 700 may be turned over, and the carrier 10 may be removed while the carrier 10 is positioned on the antenna element 630 and the encapsulant 740 .

[0169] The carrier 10 can be removed from the top surface 630b of the antenna assembly 630, the top surface 720b of the passive component 720, and the top surface 740b of the encapsulation 740. As a result, the top surface 630b of the antenna assembly 630, the top surface 720b of the passive component 720, and the top surface 740b of the encapsulation 740 can also be exposed. The terminal 721 of the passive component 720 and the conductive pattern 632 of the antenna assembly 630 can also be exposed. The removal of the carrier 10 can be similar to the following. Figure 2E Removal of the carrier 10 shown in FIG.

[0170] Figure 15E FIG. 7 shows a semiconductor device 700 at the end of manufacturing. Figure 15E In the example shown, substrate 750 can be formed on top surface 630b of antenna assembly 630 and top surface 740b of encapsulant 740. In some examples, substrate 650 can be similar to substrate 150, or can include or be referred to as a substrate. Substrate 750 can include dielectric structure 751, conductive structure 752, and dielectric structure 753, formed sequentially.

[0171] The dielectric structure 751 may cover the top surface 630b of the antenna assembly 630, the top surface 720b of the passive component 720, and the top surface 740b of the encapsulant 740 to a uniform thickness. Holes 751x and 751y that expose the conductive pattern 632 of the antenna assembly 630 and the terminal 721 of the passive component 720 may be formed in the dielectric structure 751. The dielectric structure 751 may also expose the conductive pattern 632 of the antenna assembly 630 and the terminal 721 of the passive component 720 through the holes 751x and 751y. The dielectric structure 751 may be similar to the dielectric structure 151 and may be formed similarly to the dielectric structure 151.

[0172] The conductive structure 752 may cover the top surface of the dielectric structure 751 exposed through the holes 751x and 751y, the conductive pattern 632 of the antenna assembly 630, and the terminal 721 of the passive component 720. The conductive structure 752 may have a plurality of patterns, and the plurality of patterns are in contact with the conductive pattern 632 of the antenna assembly 630 and the terminal 721 of the passive component 720 exposed through the holes 751x and 751y, respectively, and may be electrically connected. The conductive structure 752 may be electrically connected to the terminal 721 of the passive component 720 and may include a trace 752y extending along the top surface 740b of the encapsulation 740. The trace 752y may be electrically connected to the conductive pattern 632 of the antenna assembly 630 (such as Figure 12D The conductive structure 752 is shown as a conductive structure 652) and can extend along the top surface 740b of the encapsulation 740. The conductive structure 752 can be similar to the conductive structure 152 and can be formed similarly to the conductive structure 152.

[0173] The dielectric structure 753 may cover the dielectric structure 751 and the conductive structure 752 to a uniform thickness. A hole 753x that exposes the top surface 752b of the conductive structure 752 may be formed in the dielectric structure 753. The dielectric structure 753 may also expose the top surface of the trace 752y through the hole 753x. The dielectric structure 753 may be similar to the dielectric structure 751 and may be formed similarly to the dielectric structure 751.

[0174] Although only two dielectric structures 751 and 753 and one conductive structure 752 are shown in substrate 750, this is not a limitation of the present invention. In some examples, the number of structures used to construct substrate 750 can be less than or greater than the number shown in the examples of the present invention.

[0175] Figure 15F FIG. 7 shows a semiconductor device 700 at the end of manufacturing. Figure 15F In the example shown, internal interconnects 711 of electronic component 710 can be electrically connected to top surface 752b of conductive structure 752. Electronic component 710 can be positioned in the center of substrate 750. Electronic component 710 can be positioned on trace 752y to be electrically connected to conductive structure 752. Electronic component 710 can be electrically connected to passive component 720 or antenna assembly 730 via substrate 750. Electronic component 710 can be similar to electronic component 610 and can be formed similarly to electronic component 610.

[0176] Figure 15G FIG. 7 shows a semiconductor device 700 at the end of manufacturing. Figure 15GIn the example shown, the external interconnect 760 can be formed on the top surface 752b of the conductive structure 752. The external interconnect 760 can be electrically connected to the top surface 752b of the conductive structure 752.

[0177] External interconnects 760 may be formed outside electronic component 710 and spaced apart from each other in a matrix configuration having rows or columns. External interconnects 760 may be electrically connected to electronic component 710, passive component 720, or antenna assembly 730 via substrate 750. External interconnects 760 may be electrically connected to both electronic component 710 and passive component 720 via traces 752y, or may be electrically connected to electronic component 710 and antenna assembly 630. External interconnects 760 may be similar to external interconnects 160 and may be formed similarly to external interconnects 160.

[0178] This disclosure includes references to certain examples. However, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of this disclosure. Additionally, modifications may be made to the disclosed examples without departing from the scope of this disclosure. Therefore, it is contemplated that this disclosure is not limited to the disclosed examples, but rather that this disclosure will include all examples falling within the scope of the appended claims.

Claims

1. A semiconductor device comprising: Substrate, including: substrate top side; bottom side of the substrate; a substrate dielectric structure between the substrate top side and the substrate bottom side; and a substrate conductive structure, the substrate conductive structure passing through the substrate dielectric structure and comprising: a first substrate terminal; a second substrate terminal at the substrate top side; and a third substrate terminal; an electronic component coupled to the substrate and comprising: a component terminal coupled to the first substrate terminal; as well as A first antenna assembly coupled to the substrate and comprising: a first component dielectric structure; a first antenna pattern coupled to the first component dielectric structure; a first assembly terminal exposed from the first assembly dielectric structure; a first component head side, the first component head side being adjacent to the first antenna pattern; a first component substrate side, the first component substrate side being opposite the first component head side; and a first component sidewall, the first component sidewall being between the first component head side and the first component base side; A second antenna assembly coupled to the substrate and comprising: a second component dielectric structure; a second antenna pattern coupled to the second component dielectric structure; a second component terminal exposed from the second component dielectric structure; a second component head side, the second component head side being adjacent to the second antenna pattern; a second component substrate side, the second component substrate side being opposite the second component head side; and a second component sidewall, the second component sidewall being between the second component head side and the second component base side; in: a bottom side of the first assembly terminal exposed from the first assembly dielectric structure at the first assembly base side and a lateral side of the first assembly terminal exposed from the first assembly dielectric structure at the first assembly sidewall, and the bottom side of the first assembly terminal coupled to the second substrate terminal; The first antenna pattern is coupled to the substrate via the first component terminal; the first antenna assembly being coupled to the substrate outside of a footprint of the electronic component; The substrate conductive structure couples the first antenna assembly to the electronic component; a bottom side of the second assembly terminal exposed from the second assembly dielectric structure at the second assembly base side and a lateral side of the second assembly terminal exposed from the second assembly dielectric structure at the second assembly sidewall, and the lateral side of the second assembly terminal coupled to the third substrate terminal; The second antenna pattern is coupled to the substrate via the second component terminal; The second antenna assembly is coupled to the substrate outside of a footprint of the electronic component; and The substrate conductive structure couples the second antenna assembly to the electronic component.

2. The semiconductor device according to claim 1, wherein: The first antenna assembly includes: A first antenna path traverses the first component dielectric structure and is coupled to the first antenna pattern and the first component terminal.

3. The semiconductor device according to claim 1, wherein: The first antenna pattern is oriented to communicate in a direction substantially orthogonal to a head side of the first component.

4. The semiconductor device according to claim 1, wherein: The first antenna assembly includes: a first component head side facing a vertical direction, and the first antenna pattern oriented to communicate along the vertical direction; coupled to the first component base side of the substrate; and The bottom side of the first component terminal is coupled to the second substrate terminal.

5. The semiconductor device according to claim 1, wherein: The second antenna assembly includes: a second component head side facing a second horizontal direction, and a second antenna pattern oriented to communicate along the second horizontal direction; the second component sidewall coupled to the substrate; and The lateral side of the second component terminal is coupled to the third substrate terminal.

6. The semiconductor device according to claim 1, in: The substrate surrounding the footprint of the electronic component comprises: a leftward portion of the substrate, a rightward portion of the substrate, an upward portion of the substrate, and a downward portion of the substrate; The first antenna assembly is coupled to the substrate top side at a leftward portion of the substrate; and The second antenna assembly is coupled to the substrate top side at a right portion of the substrate.

7. The semiconductor device according to claim 6, comprising: an encapsulation on a top side of the substrate; in: The encapsulation covers the first component sidewall and the second component sidewall; and The encapsulation exposes the first component head side and the second component head side.

8. The semiconductor device according to claim 7, wherein: The electronic component comprises: a member first side coupled to the substrate top side; a second side of the component, the second side of the component being opposite to the first side of the component; a component sidewall between the component first side and the component second side; and a shield structure contacting the component second side and the component sidewall; and The encapsulation covers the shielding structure adjacent to the component sidewall.

9. The semiconductor device according to claim 6, wherein: The first antenna assembly includes: the first component head side facing a vertical direction, and the first antenna pattern oriented to communicate along the vertical direction; and coupled to the first component base side of the substrate; and The second antenna assembly includes: a second component head side facing a horizontal direction, and the second antenna pattern oriented to communicate along the horizontal direction; and The second component base side is coupled to the substrate.

10. The semiconductor device according to claim 6, wherein: The first antenna assembly includes: the first component head side facing a rightward direction, and the first antenna pattern oriented to communicate in the rightward direction; and the first component sidewall coupled to the substrate; and the lateral side of the first component terminal being coupled to the second substrate terminal; and The second antenna assembly includes: a second component head side facing a left direction opposite to the right direction, and a second antenna pattern oriented to communicate in the left direction; and The second component sidewall is coupled to the substrate.

11. The semiconductor device according to claim 6, wherein: The first antenna assembly includes: the first component head side facing a vertical direction, and the first antenna pattern oriented to communicate along the vertical direction; and coupled to the first component base side of the substrate; and The second antenna assembly includes: the second component head side facing a rightward direction, and the second antenna pattern oriented to communicate in the rightward direction; and The second component sidewall is coupled to the substrate.

12. The semiconductor device according to claim 11, comprising: A third antenna assembly coupled to the substrate at the substrate-upward portion and comprising: a third component head side facing an upward direction, and a third antenna pattern oriented to communicate in the upward direction; and A third component sidewall is coupled to the substrate.

13. The semiconductor device according to claim 12, comprising: a fourth antenna assembly coupled to the substrate at a lower portion of the substrate and comprising: a fourth component head side facing in a downward direction, and a fourth antenna pattern oriented to communicate in the downward direction; and A fourth component sidewall is coupled to the substrate.

14. The semiconductor device according to claim 13, comprising: a fifth antenna assembly coupled to the substrate at a leftward portion of the substrate and comprising: a fifth component head side facing a leftward direction and a fifth antenna pattern oriented to communicate in said leftward direction; and A fifth component sidewall is coupled to the substrate.

15. The semiconductor device according to claim 14, comprising: a sixth antenna assembly coupled to the substrate at a rightward portion of the substrate and comprising: a sixth component head side, and a sixth antenna pattern oriented to communicate along the vertical direction; and A sixth component sidewall is coupled to the substrate.

16. The semiconductor device according to claim 6, wherein: The electronic components are coupled to the substrate bottom side.

17. The semiconductor device according to claim 16, comprising: A passive component is coupled to the substrate and is above the electronic component.

18. The semiconductor device according to claim 6, comprising: A passive component is coupled to the top side of the substrate between the first antenna assembly and the second antenna assembly.

19. A method of manufacturing a semiconductor device, comprising: A substrate is provided, comprising: substrate top side; bottom side of the substrate; a substrate dielectric structure between the substrate top side and the substrate bottom side; and a substrate conductive structure, the substrate conductive structure passing through the substrate dielectric structure and comprising: a first substrate terminal; a second substrate terminal at the top side of the substrate; and a third substrate terminal; coupling an electronic component to the substrate, the electronic component comprising: a component terminal coupled to the first substrate terminal; A first antenna assembly is coupled to the substrate, the first antenna assembly comprising: a first component dielectric structure; a first antenna pattern coupled to the first component dielectric structure; a first assembly terminal exposed from the first assembly dielectric structure; a first component head side, the first component head side being adjacent to the first antenna pattern; a first component substrate side, the first component substrate side being opposite the first component head side; and a first assembly sidewall between the first assembly head side and the first assembly base side; and A second antenna assembly is coupled to the substrate, the second antenna assembly comprising: a second component dielectric structure; a second antenna pattern coupled to the second component dielectric structure; a second component terminal exposed from the second component dielectric structure; a second component head side, the second component head side being adjacent to the second antenna pattern; a second component substrate side, the second component substrate side being opposite the second component head side; and a second component sidewall, the second component sidewall being between the second component head side and the second component base side; in: a bottom side of the first component terminal exposed from the first component dielectric structure at the first component base side and a lateral side of the first component terminal exposed from the first component dielectric structure at the first component sidewall, and at least one of the bottom side of the first component terminal or the lateral side of the first component terminal coupled to the second substrate terminal; The first antenna pattern is coupled to the substrate via the first component terminal; The first antenna assembly is coupled to the substrate outside of a footprint of the electronic component; and The substrate conductive structure couples the first antenna assembly to the electronic component; a bottom side of the second assembly terminal exposed from the second assembly dielectric structure at the second assembly base side and a lateral side of the second assembly terminal exposed from the second assembly dielectric structure at the second assembly sidewall, and the lateral side of the second assembly terminal coupled to the third substrate terminal; The second antenna pattern is coupled to the substrate via the second component terminal; The second antenna assembly is coupled to the substrate outside of a footprint of the electronic component; and The substrate conductive structure couples the second antenna assembly to the electronic component.

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