Domain crossing when executing instructions in a computer processor

Abstract

Systems, devices, and methods related to securing domain crossover using domain access tables are described. For example, a computer processor may have registers configured to store the locations of domain access tables for predefined, non-hierarchical domains. Each respective domain access table may be pre-associated with a respective domain and may have entries configured to identify entry points for the respective domains. The processor is configured to use the domain access tables to perform domain crossovers during instruction execution and to prevent arbitrary and / or unauthorized domain crossovers from occurring.

Description

[0001] Related applications

[0002] This application claims the benefit of the filing dates of: U.S. Patent Application No. 16 / 520,299, filed on July 23, 2018, and entitled “Domain Crossing in Executing Instructions in Computer Processors”; Provisional U.S. Patent Application No. 62 / 725,030, filed on August 30, 2018, and entitled “Domain Crossing in Executing Instructions in Computer Processors”; Provisional U.S. Patent Application No. 62 / 724,896, filed on August 30, 2018, and entitled “Memory Access Control through Permissions Specified in Page Table Entries for Execution Domains”; and Provisional U.S. Patent Application No. 62 / 725,030, filed on August 30, 2018, and entitled “Memory Access Control through Permissions Specified in Page Table Entries for Execution Domains”. Provisional U.S. Patent Application No. 62 / 724,913, filed on August 30, 2018, entitled “Access Control for Processor Registers based on Execution Domains”; Provisional U.S. Patent Application No. 62 / 724,929, filed on August 30, 2018, entitled “Access Control for Processor Registers based on Execution Domains”; and Provisional U.S. Patent Application No. 62 / 724,999, filed on August 30, 2018, entitled “Domain Register for Instructions being Executed in Computer Processors”, the entire disclosures of which are hereby incorporated by reference herein. Technical Field

[0003] At least some embodiments disclosed herein relate generally to computer architecture, and more particularly, but not limited to, securing domain crossing when executing instructions in a computer processor. Background Art

[0004] Instructions programmed for a computer can be structured in a layered manner. One layer can provide resources and services to another layer. For example, a hypervisor can create or provide a virtual machine implemented on computer hardware components. An operating system can use resources available in a computer with a predefined architecture to provide resources and services. The computer resources or computer operated by the operating system can be actual computer hardware components or virtual machine components provided by the hypervisor. Applications can use the services and resources provided by the operating system to provide application-specific functionality. Summary of the Invention

[0005] According to one embodiment of the present disclosure, a computer system includes: a memory configured to store at least instructions of routines of a set of predefined domains, a plurality of domain access tables, and a processor coupled to the memory. In the computer system, each corresponding domain access table in the plurality of domain access tables is pre-associated with a corresponding domain in the set of predefined domains, the corresponding domain access table having one or more entries configured to identify one or more entry points of the corresponding domain, each of the one or more entries being used to transfer execution control from a corresponding source domain in the set of predefined domains to the corresponding domain; and the processor is configured to execute a transition instruction across the set of predefined domains through an entry point specified in the domain access table, wherein the domain access table is configured to allow execution of the transition instruction across the set of predefined domains without relying on a predefined domain hierarchy.

[0006] According to another embodiment of the present disclosure, a method for executing an instruction includes: receiving an instruction executed in a first domain of a set of predefined domains, the instruction requesting execution to transition to a routine in a second domain of the set of predefined domains, the instruction specifying an entry index; retrieving an entry in a domain access table of a plurality of domain access tables using the entry index, the entry being used to transfer execution control from the first domain to the second domain; and securing the execution transition to the routine in the second domain based on the entry retrieved from the domain access table.

[0007] According to yet another embodiment of the present disclosure, a computer processor includes a plurality of registers configured to respectively store locations of a plurality of domain access tables, wherein each corresponding domain access table in the plurality of domain access tables is pre-associated with a corresponding domain among a plurality of domains, the corresponding domain access table having one or more entries configured to identify one or more entry points of the corresponding domain, each of the one or more entries being used to transfer execution control from a corresponding source domain among the plurality of domains to the corresponding domain; and at least one execution unit configured to execute instructions; wherein the computer processor is configured to use the domain access tables to perform domain crossing when the instruction is executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments are illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which like references indicate similar elements.

[0009] Figure 1 Execution of instructions using a domain access table to access routines in different domains is shown in accordance with some embodiments.

[0010] Figure 2 Illustrate the use of a domain access table to access routines in a domain.

[0011] Figure 3 A computer processor with domain registers is shown in accordance with some embodiments.

[0012] Figure 4 A system is shown that controls security operations applied to resources based on domain registers.

[0013] Figure 5 Shows the page table entries of an execution domain with security configuration.

[0014] Figure 6 A computer system is shown having a domain register that controls security operations.

[0015] Figure 7 A method of performing domain interleaving when executing instructions in a computer processor is shown. DETAILED DESCRIPTION

[0016] The present disclosure includes techniques for securing calls to execution routines across different non-hierarchical domains.

[0017] In conventional systems, different levels of privilege and / or trust may be given to different layers of instructions (e.g., user applications versus the operating system). Typically, protection rings are constructed and implemented in computers to protect data and functionality from failures and malicious behavior based on a hierarchy of rings. Rings are statically arranged into a hierarchy from the most privileged (and therefore most trusted) to the least privileged (and therefore least trusted). For example, a hierarchy may include an operating system kernel ring with the highest privilege, a device driver ring, and an application ring with the lowest privilege. Programs or routines in lower privilege rings may be restricted by corresponding dedicated hardware-enforced control gates to access resources and services of higher privilege rings in the hierarchy. Gated access between rings can improve security.

[0018] In the technology disclosed herein, instructions or routines programmed for a computer system can be categorized into a set of predefined, non-hierarchical domains, such as a hypervisor domain, an operating system domain, an application domain, and the like. One or more domain access tables can be used to specify entry points that allow calls to execute routines in domains different from the current domain. Each domain access table can be associated with a corresponding domain. A set of registers can be used to identify the base address of the domain access table for a domain. The domain register can be configured in the processor to store an identifier or indicator of the current domain of the instruction currently being executed in the processor. After a call to execute a routine is successfully processed via the domain access table, the contents of the domain register are updated to indicate the domain of the domain access table used to process the call. When execution of a called routine returns to the calling routine across domains, the return can be processed in a manner similar to the call. Thus, arbitrary and / or unauthorized domain crossings can be prevented.

[0019] Figure 1 Execution of instructions 193 is shown using domain access tables 217, ..., 227 to access routines in different domains (eg, 101, ..., 105) in accordance with some embodiments.

[0020] Routines programmed for a computer system can be categorized into various predefined, non-hierarchical domains (e.g., 101, ..., 105). Examples of execution domains include a hypervisor's domain, an operating system's domain, an application's domain, and the like. A hypervisor or virtual machine monitor (VMM) creates and manages virtual machines. The hypervisor can control basic functions such as physical memory and input / output.

[0021] Instructions 193 of a routine 191 currently executing in a computer processor in a domain may request a transition to a routine in another domain. Figure 1 Instruction 193 of the instruction 193 requests a transition from a source domain to a destination domain, so instruction 193 is configured to identify a domain identifier 197 of the destination domain, as well as an operation 195 specific to the transaction. For example, operation 195 may be a call to a routine in the destination domain or a return to a routine in the destination domain from a previous call. Domain identifier 197 in instruction 193 explicitly identifies the destination domain (e.g., 101, ..., or 105); and entry index 199 provided in instruction 193 specifies an entry point in a domain access table (e.g., 217, ..., or 227) corresponding to the destination domain (e.g., 101, ..., or 105). In some embodiments, domain identifier 197 may be specified in a register (or stack) configured to store the identifier 197 of the destination domain for execution of an instruction (e.g., 193) required to perform a control transition (e.g., call a called routine, or return to a calling routine).

[0022] exist Figure 1In the embodiment of the present invention, each domain (e.g., 101, ..., or 105) has a corresponding register (e.g., 219, ..., or 229) that identifies the base address or memory location of the corresponding domain access table (e.g., 217, ..., or 229). The computer system is loaded with the contents of the valid domain access table (e.g., 217, ..., or 229).

[0023] For example, when domain identifier 197 is domain A 101, its associated register 219 is used to locate domain access table A 217. Domain access table A 217 stores a number of available entries 211 that can be used to validate entry index 199 of domain A 101. For example, the processor can validate entry index 199 provided in instruction 193 against a valid index range defined by number of available entries 211. If entry index 199 is valid given number of entries 211 of domain access table 217, entry index 199 can be used to look up an entry (e.g., 213, ..., or 215) in domain access table A 217. The entry (e.g., 213, ..., or 215) found in domain access table A 217 can be used to securely transfer execution control from the source domain of instruction 193 of routine 191 to the destination domain 101 identified by domain identifier 197 provided in instruction 193.

[0024] Similarly, when domain identifier 197 is domain C 105, its associated register 229 can be used to locate the corresponding domain access table C 227, which is specifically configured for domain C 105. Entry number 221 of domain access table C 227 is used to check the validity of entry index 199 provided in instruction 193; and if entry index 199 is valid, then an entry (e.g., 223, ..., or 225) is looked up in domain access table C 227 to transfer execution control from the source domain of routine 191 containing instruction 193 to the destination domain 105.

[0025] In some embodiments, the transfer of execution control from one domain 101 to another domain (e.g., 105) is permitted only through predefined domain access tables (e.g., 217, ..., 227). Arbitrary domain crossing is prohibited. Thus, the security of the computer system is improved.

[0026] In some embodiments, the entries of the domain access tables 217, ..., 227 (e.g., 213, ..., 215; 223, ..., 225) may optionally include permission data for authorizing transitions from a source domain to the corresponding entry points represented by the corresponding entries (e.g., 213, ..., 215; 223, ..., 225).

[0027] For example, entry X 223 of domain A 105 may have permission data that allows transitions from the domain of instruction 193 to an entry point in domain 105 identified by entry X 223; and entry Z 225 of the same domain A 105 may have different permission data that denies transitions from the same domain of the same instruction 193 to an entry point in the same destination domain 105 identified by entry Z 225.

[0028] In some embodiments, the entries (e.g., 213, ..., 215; 223, ..., 225) may optionally include security option data for transitioning from various source domains to the corresponding entry points represented by the entries (e.g., 213, ..., 215; 223, ..., 225).

[0029] For example, entry X 223 of destination domain 105 may have security option data that requires sandboxing to transition from the source domain of instruction 193 to the entry point defined by entry X 223 in domain 105; and entry Z 225 of a different entry point in destination domain 105 may have different security option data that does not use sandboxing to transition from the same source domain of instruction 193 to the entry point defined by entry Z 225 in the same destination domain 105.

[0030] In some embodiments, the entries (e.g., 213, ..., 215; 223, ..., 225) may provide virtual memory addresses for accessing routines that are entry points to domains 101, ..., 105. Permission data and security option data may be specified in the page table entries to convert virtual memory addresses to physical addresses, as discussed further below.

[0031] Figure 1 An example is shown using separate domain access tables 217, ..., 227 for different domains (e.g., 101, ..., 105). Alternatively, the entries (e.g., 213, ..., 215; 223, ..., 225) can be combined in a combined domain access table, where the entries of the table contain information identifying the domain of the routine identified by the entry (e.g., 213, ..., 215; 223, ..., 225). For example, the entry (e.g., 213, ..., 215; 223, ..., 225) can be a memory address for locating the corresponding routine; and the identifier of the domain can be encoded or embedded in the memory address. In some embodiments, the processor is configured to reject requests that are not using Figure 1 Domain crossing is performed in the form of the instructions shown (e.g., 193).

[0032] In one embodiment, each domain 101, ..., or 105 has a separate memory area configured to store the values ​​of registers for the corresponding domain 101, ..., or 105. Such a separate memory area for storing the values ​​of registers specific to a domain (e.g., 101) when execution temporarily transitions to another domain is accessible to the corresponding domain (e.g., 101), but is inaccessible to other domains (e.g., 105). Because other domains (e.g., 101) cannot access the register value area of ​​a given domain (e.g., 105), the register state of the given domain (e.g., 105) is isolated and protected from execution in other domains (e.g., 101). For example, the memory area for domain-specific registers of a particular domain (e.g., 101) may store the value of the program counter (PC) of the instruction currently executing in the processor, the value of the stack pointer (SP) for the stack used for instruction execution, the value of the stack frame pointer (FP), the value of the stack variable parameter pointer (AP), and / or the value of the processor status word (PSW), etc. The specific domain (e.g., 101) may have a separate stack separate from the stacks of other domains (e.g., 105), and the stack of the specific domain (e.g., 101) is not accessible to other domains. When a calling routine running in a domain (e.g., 101) uses a domain call instruction 193 to call a called routine in another domain (e.g., 105), the values ​​of registers (e.g., PC, SP, FP, AP, PSW) for the calling domain (e.g., 101) are stored in a register value area of ​​the calling domain (e.g., 101) in memory. Before transferring execution from the calling domain (e.g., 101), the processor may store the current values ​​of registers (e.g., PC, SP, FP, AP, PSW) in the register value area of ​​the calling domain (e.g., 101); and after transferring execution to the called domain (e.g., 105), the processor may initialize the register value area of ​​the called domain (e.g., 105). For example, the program counter (PC) of the called domain (e.g., 105) can be initialized to a value obtained from an entry (e.g., 223, ..., or 225) of the domain access table 227 of the called domain (e.g., 105), which allows the processor to begin processing the called routine in the called domain 105. When the domain return instruction 193 specifies a destination domain (e.g., 101) to return to, the processor can retrieve register values ​​for return in the register value area of ​​the destination domain (e.g., 101) and initialize corresponding registers (e.g., PC, SP, FP, AP, PSW) using the retrieved values. If there is a valid return block on the stack of the destination domain (e.g., 101), a return to the corresponding return point identified for the return on the stack of the destination domain (e.g., 101) can be executed.

[0033] Alternatively and / or in combination, each domain 101 , . . . or 105 may have a separate set of such registers (e.g., PC, SP, FP, AP, PSW) that may serve as register value areas for the corresponding domain 101 , . . . or 105 .

[0034] Figure 2 The use of a domain access table 217 to access routines 135, ..., 136 in domain 101 is shown.

[0035] exist Figure 2 In the domain access table 227, each of the entries 223, ..., 225 identifies the location of the corresponding routine 135, ..., or 136 in the domain 105. For example, the location can be identified as the memory address of the instruction (e.g., 132, ..., or 134) at the beginning of the corresponding routine (e.g., 135, ..., or 136). For example, each entry 223, ..., or 225 can be the memory address of the corresponding routine 135, ..., 136; and the processor of the computer system can use the memory address found from the domain access table 227 to pass execution control to the processor using Figure 1 The routine is called by instruction 193.

[0036] Optionally, a domain register of a computer processor can be used to store a domain identifier of a routine (e.g., 191) currently executing in the computer processor. For example, after executing instruction 193 that causes a domain cross, the contents of the domain register can be updated to store the domain identifier 197 of instruction 193 after instruction 193 is successfully processed (e.g., using domain access table 227) to execute the target routine (e.g., 135, ..., or 136). The contents of the domain register can control various security operations of the processor.

[0037] For example, when execution of an instruction results in a request to access a memory location identified using a virtual memory address, the virtual memory address can be converted into a physical memory address using one or more page tables. The contents of a domain register can be used to select permission bits in a page table entry for memory accesses in the current domain. The selected permission bits can control the processing of the request to access the memory location identified by the virtual memory address.

[0038] For example, when a routine with a virtual memory address is called for execution, the contents of the domain register can be used to select a security bit in a page table entry for translating the virtual memory address into a physical memory address. The selected security bit is used to execute the routine while servicing the current domain identified by the domain register. The selected security bit controls the security of resources and / or data between the called routine and the calling routine.

[0039] For example, when the execution of an instruction generates a request to access a privileged register, the contents of the domain register may be used to select permission bits in, for example, a permission register for the current domain to access the privileged register. The permission bits may control the acceptance or rejection of the request to access the privileged register.

[0040] Figure 3 A computer processor 169 is shown with domain registers 117 in accordance with some embodiments.

[0041] Figure 3 The computer processor 169 is coupled to a memory 109 that stores routines for various predefined non-hierarchical domains 101, 103, ..., 105, such as domain 101 for a hypervisor 102, domain 103 for an operating system 104, and domain 105 for an application 106. The physical memory 109 may be used to store data and instructions for various routines programmed for the computer system.

[0042] For example, the routines of hypervisor 102 may be classified in domain A 101; the routines of operating system 104 may be classified in another domain B 103; and the routines of application 106 may be classified in another domain C 105. A hypervisor or virtual machine monitor (VMM) creates and manages virtual machines. The hypervisor may control basic functions such as physical memory and input / output (I / O).

[0043] In general, a routine may include a pre-programmed set of instructions stored in memory 109. A routine may also have input data, output data, and / or temporary data stored in memory 109. A routine may activate or call another routine for a service and / or resource. The calling routine and the called routine may be in the same or different domains (e.g., 101, 103, ..., 105).

[0044] Figure 3 The processor 169 has an execution unit (e.g., 185), such as an arithmetic logic unit. The processor 169 may include an internal cache 187 as a proxy for a portion of the memory 109. The processor 169 has registers 183 for storing instructions for execution, data that are operands of the instructions, and / or results of the execution of the instructions.

[0045] Domain register 117 is one of registers 183 of processor 169. Domain register 117 stores an identifier or indicator of the current domain of a set of instructions (e.g., a routine) being executed in processor 169. The contents of domain register 117 control security operations in processor 189, as discussed further below.

[0046] In one embodiment, when a computer system having processor 169 is initially powered on (booted), processor 169 is configured to automatically execute routines of hypervisor 102 or operating system 104 (if a hypervisor is not used). This is part of the boot process. Therefore, domain register 117 is initially set to indicate domain 101 of hypervisor 102 or domain 103 of operating system 104. Subsequently, execution control may use instructions identifying the destination domain (e.g., Figure 1 193 shown) from one domain to another; and the contents of the domain register 117 can be moved according to such instructions (e.g., Figure 1 The processing of 193) shown is updated.

[0047] Alternatively, or in combination, the domain of the currently running routine may be identified based on a memory address, stored attributes of the routine, or the like.

[0048] For example, some techniques for specifying the current domain 123 in the domain register 117 in the computer processor 169 can be found in U.S. patent application Ser. No. 62 / 724,999, filed on Aug. 30, 2018, and entitled “Domain Register for Instructions being Executed in Computer Processors,” the entire disclosure of which is hereby incorporated by reference herein.

[0049] In some examples, current domain 123 may be identified based on a memory address used to load instruction 193 of routine 191 for execution.

[0050] For example, a memory address may have a predetermined width (e.g., a predetermined number of bits) for processor 169. The memory address may include a portion representing an object ID and a portion representing an offset within the object represented by the object ID. For example, routine 191 may be the object located at the address; the object ID of the address may be used to identify certain characteristics of instruction 193 and / or routine 191; and current domain 123 may be determined based on the characteristics.

[0051] For example, a static object ID having a predetermined value (e.g., 0) may be used to represent a kernel object of the operating system 104. Thus, a static object ID specified in a memory address may be used to identify the current domain 123 for execution of the routine 191. Some details and examples of static object IDs in memory addresses of a computer processor that loads instructions for execution may be found in U.S. patent application Ser. No. 16 / 028,840, filed on July 6, 2018, and entitled “Static Identifications in Object-based Memory Access,” the entire disclosure of which is hereby incorporated herein by reference.

[0052] In some instances, the object ID of a memory address may include a portion indicating an object type. For example, an object type having values ​​0 to 3 may be used to identify kernel objects in an operating system. For example, an object type having values ​​4 to 5 may be used to specify that an offset is an address of a different width (e.g., a 64-bit address or a 32-bit address contained within a 128-bit memory address). For example, an object type having values ​​6 to 7 may be used to specify that a predetermined portion of an object ID is to be interpreted as an identifier for a local object or an object in a partitioned global address space (PGAS). For example, an object type having a value 32 may be used to specify that the remainder of an object ID is to be interpreted as an identifier for an object defined in a server (e.g., 197). For example, an object name server may store data indicating the name of the object represented by the object ID, access control parameters for the object, and / or other attributes of the object.

[0053] For example, the object ID 199 of the memory address used to load the routine 191 for execution may have attributes stored in the object name server. The attributes may be used to determine or infer the current domain 123 of the routine loaded from the memory address.

[0054] In some examples, routine 191 has attributes stored in association with routine 191 (e.g., in memory 109, in a page table entry used to determine the physical address of instruction 193, in an entry table used to make a call to execute the routine). When routine 191 is loaded for execution, the attributes of routine 191 are used to determine the current domain 123 for executing routine 191.

[0055] Figure 4 A system is shown that controls security operations applied to resources (eg, 131 ) according to domain register 117 .

[0056] exist Figure 4, security controls 119 are implemented based on a current domain 123 specified in a domain register 117 and a security configuration 107 having settings 111, 113, ..., 115 that are individually specified for predefined domains 101, 103, ..., 105. Security controls 119 are applied to resources 131, which may be privileged registers 133, called routines 135, memory areas 137, and the like.

[0057] The security configuration 107 may have settings 111 , 113 , . . . , 115 for the domains 101 , 103 , . . . , 105 , respectively, without relying on a static trust hierarchy among the domains 101 , 103 , . . . , 105 .

[0058] When routine 191 is being executed in processor 169, domain register 117 causes security control 119 to select settings (e.g., 111, 113, ..., or 115) that are previously associated with a domain (e.g., 101, 103, ..., or 105) that matches current domain 123. The selected settings (e.g., 111, 113, ..., or 115) are used by security control 119 for customizing security operations for resource 131.

[0059] For example, when execution of instructions 193 of routine 191 in processor 169 requests memory access to memory area 137, a selected setting (e.g., 111, 113, ..., or 115) that matches its pre-associated domain (e.g., 101, 103, ..., 105) with the current domain 123 is used by security control 119 to determine whether memory access is permitted.

[0060] For example, different regions (e.g., 137) in memory 109 may be configured with different security configurations (e.g., 107); and each security configuration (e.g., 107) may include different permissions (e.g., 111, 113, ..., 115) for different domains 101, 103, ..., 105. For example, security configuration 107 may be specified in a page table entry used for logical to physical address translation of virtual memory addresses, such that the structure of a memory region may correspond to a memory page structure, as described below in conjunction with Figure 5 Further discussion.

[0061] For example, physical memory 109 may be divided into multiple regions; each region (eg, 137) may be a page of physical memory 109 or a group of pages of physical memory 109 used for memory management.

[0062] For example, a typical memory area 137 may have a corresponding security configuration 107 specified for the set of predefined domains 101, 103, ..., 105. The security configuration 107 explicitly identifies the permissions (e.g., 111, 113, ..., 115) for each domain 101, 103, ..., 105. Therefore, the privileges of a routine accessing the memory area 137 do not depend on the hierarchy of the domains 101, 103, ..., 105.

[0063] In one example, when a routine 191 executing in the current domain 123 causes memory access to a memory region 137 for instruction reading, writing, or execution, the domain register 117 causes the security control 119 to check the permissions specified in the settings 111, 113, . . . , or 115 corresponding to the current domain 123. Whether access to the memory region 137 is blocked (or denied) for a particular operation type (e.g., read, write, execute) by executing instructions 193 of the routine 191 in the current domain 123 may be determined based on the corresponding permission bits selected for the operation type according to the current domain 123 of the memory region 137. Some details and examples of permissions for memory access to memory region 137 can be found in U.S. patent application Ser. No. 62 / 724,896, filed on Aug. 30, 2018, entitled “Memory Access Control through Permissions Specified in Page Table Entries for Execution Domains,” the disclosure of which is hereby incorporated by reference herein in its entirety.

[0064] In general, different routines of the same domain (eg, 103) may be configured in different memory regions, and therefore configured to have different permissions and security settings for the same domain (eg, 103).

[0065] Furthermore, a routine may be configured to store different portions of its data in different memory areas (eg, 137), and thus configured to have different rights of access from the same domain (eg, 101, 103, ..., or 105).

[0066] In another example, when a routine 191 executing in a current domain 123 calls a callee routine 135 stored in a memory area 137 for execution, the domain register 117 causes the security control 119 to check the permissions specified in the settings 111, 113, ..., or 115 corresponding to the current domain 123. Whether to deploy security measures to protect the resources of the calling routine 191 from the callee routine 135 and / or to protect the resources of the callee routine 135 from the calling routine can be determined based on the corresponding permission bits specified for the current domain 123 and the memory area 137.

[0067] Security measures may include sandboxing. Sandboxing generally includes computer security measures that isolate the execution of a set of instructions (e.g., an application) from certain system resources and / or other sets of instructions / programs. For example, sandboxing can be implemented using a shadow stack structure, in which the calling routine and the called routine are configured to use separate stacks and stack-related control registers, and the calling routine may not be able to access the stack assigned to the called routine, and the called routine may not be able to access the stack assigned to the calling routine. Some details and examples of the shadow stack structure can be found in U.S. patent application No. 62 / 724,913, filed on August 30, 2018, entitled "Security Configurations in Page Table Entries for Execution Domains," the entire disclosure of which is hereby incorporated by reference herein.

[0068] For example, the security configuration 107 of a typical memory region 137 may have sandboxing settings (e.g., 111, 113, ..., 115) specified for each of the set of predefined domains (e.g., 101, 103, ..., 105). The sandboxing configuration 107 explicitly identifies whether sandboxing is required for calls to callee routines 135 stored in the region 137. Calls to the same routine 135 executed in different domains 101, 103, ..., 105 may have different settings 111, 113, ..., 115; and the settings 111, 113, ..., 115 specify whether calls from the respective domains 101, 103, ..., 105 require sandboxing (e.g., protecting the callee routine 135 and the calling routine 191 from each other). Thus, based on the current domain 123 identified in the domain register 117 and the explicit settings (e.g., 111, 113, ..., 115) configured for the corresponding domains 101, 103, ..., 105, sandboxing operations can be selectively applied to the execution of the called routine 135 stored in the memory area 137 without relying on a predefined hierarchy of domains 101, 103, ..., 105.

[0069] For example, a calling routine 191 in the current domain 123 may call a callee routine 135. Whether a sandboxing operation is activated for execution of a call to the callee routine 135 stored in the memory area 137 may be determined based on the sandboxing settings (e.g., 111, 113, ..., or 115) specified for the corresponding domain (e.g., 101, 103, ..., or 105) of the current domain 123 that matches the memory area 137. Thus, the sandboxing operation may be activated independent of the relative hierarchy between the domain of the callee routine 135 and the current calling domain 123.

[0070] For example, the sandbox settings 107 for a routine stored in the memory region 137 may be specified in a page table entry used for logical to physical address translation of virtual memory addresses, such that the structure of the memory region may correspond to a memory page structure, as described below in conjunction with Figure 5 Further discussion.

[0071] In another example, when a routine 191 executing in the current domain 123 requests access to the privilege register 133, the domain register 117 causes the security control 119 to check the permissions specified in the settings 111, 113, ..., or 115 of the privilege register 133. Whether access is granted or blocked can be determined based on the corresponding permission bits specified for the current domain 123 and the privilege register 133.

[0072] For example, the privilege register 133 may have different permissions 111, 113, ..., 115 for different domains 101, 103, ..., 105, respectively. When an instruction executed in the current domain 123 requests access to the privilege register 133, the domain register 117 causes the security control 119 to select a corresponding permission (e.g., 111, 113, ..., or 115) corresponding to the current domain 123 to control access.

[0073] , 105 ) individually specified explicit permissions 111 , 113 , . . . , 115 (eg, non-hierarchical) for the domains 101 , 103 , . . . , 105 , respectively, without relying on a predefined trust hierarchy for the domains 101 , 103 , . . . , 105 .

[0074] In some examples, privileged register 133 may be accessed for different operation types, such as read, write, execute, etc. The permission (e.g., 111, 113, ..., or 115) for a particular domain (e.g., 101, 103, ..., or 105) to access privileged register 133 may have separate permission bits for the corresponding operation type (e.g., read, write, and / or execute).

[0075] Security configuration 107 may be configured to allow instructions executing in one domain (eg, 101, 103, ..., 105) to access register 133 for one operation type (eg, read), but not for another operation type (eg, write).

[0076] The security configuration 107 may be configured to allow instructions executing in one domain (e.g., 103) to access registers (e.g., 133) via one permission setting (e.g., 113) of the domain (e.g., 103), but prohibit the same instructions running in another domain (e.g., 101) from accessing register 133 via another parallel setting (e.g., 111) of the domain (e.g., 101), even though in a conventional protection ring the disallowed domain (e.g., 101) may have higher privileges (and therefore be more trusted) than the allowed domain (e.g., 103).

[0077] In one embodiment, security configuration 107 is hardwired into the processor in privileged registers 133. In another embodiment, security configuration 107 may be set via firmware in the processor's registers 133 during the computer system's startup / boot process. In another embodiment, security configuration 107 may be changed during normal operation of the computer system via privileged software.

[0078] For example, the security configuration 107 of the privileged registers 133 may change when the processor 169 switches from running a program in one domain (eg, 101 ) to running a program in another domain (eg, 103 ).

[0079] For example, the security configuration 107 of the privileged registers 133 may be changed upon request when the computer system switches from running one routine to another, where the routines may be in the same domain (eg, 101).

[0080] For example, the security configuration 107 of the privileged register 133 can be configured in a permission register that controls access to the privileged register 133 using permission bits stored in the permission register; and the contents of the permission register can be updated by an authorized process that adjusts / customizes the security level of the computer system for the current calculation. Alternatively, the permission bits of the different domains 101, 103, ..., 105 can be specified in separate registers corresponding to domains 101, 103, ..., 105, respectively. Some details and examples of permission registers can be found in U.S. patent application No. 62 / 724,929, filed on August 30, 2018, entitled "Access Control for Processor Registers based on Execution Domains," the entire disclosure of which is hereby incorporated by reference herein.

[0081] because Figure 4 The security control system does not rely on a predefined domain trust hierarchy (ie, it is non-hierarchical), so it can provide better flexibility and finer control granularity than conventional protection rings.

[0082] Figure 5 Page table entries 153 with security configuration 107 for execution domains (eg, 101 , 103 , . . . , 105 ) are shown.

[0083] For example, the security configuration 107 in the page table entry may be a sandboxing configuration for permissions to access the memory region 137 identified by the page table entry 153 and / or for calling routines stored in the memory region 137 identified by the page table entry 153 .

[0084] A typical virtual address 141 in virtual address space 127 may be translated into a corresponding physical address 159 in physical address space 129 using page table 151. In general, multiple page tables (eg, 151) may be used to map virtual address space 127 to physical address space 129.

[0085] Virtual address 141 may include table ID 143, entry ID 145, and offset 147. Table ID 143 may be used to identify page table 151 containing a page table entry 153 for the page containing the memory location identified by virtual address 141 and physical address 159. Entry ID 145 serves as an index into page table 151 to efficiently locate page table entry 153. Page table entry 153 provides a base address 157 for physical address 159. Physical addresses in the same memory page share the same base address 157. Therefore, base address 157 identifies region 137 in memory 109. Offset 147 of virtual address 141 serves as the corresponding offset 147 for page or region 137 in memory 109. The combination of base address 157 and offset 147 provides physical address 159 corresponding to virtual address 141.

[0086] exist Figure 5 In FIG, the page table entry 153 specifies not only the base address 157 of the page or region 137, but also the security configuration 107 for the page or memory region 137, such as the permission to read data into the memory region 137 corresponding to the base address 157, the permission to write data into the memory region 137, the permission to execute instructions stored in the memory region 137, and the sandboxing requirement for calling routines stored in the memory region 137. The security configuration 107 may have the following types: Figure 3 and 4 , 105. The current domain 123 in the domain register 117 controls which of the settings 111, 113, ..., 115 is used for the current memory access or current call to the routine 135 stored in the memory area 137.

[0087] Optionally, the page table entry 153 may specify other attributes 155 of the physical memory page, such as whether the data in the page is valid, whether the page is in main memory, or whether the page is invalid (e.g., changes to the data in the physical memory page have not yet been flushed to long-term memory / storage relative to the memory area 137). For example, the attributes 155 may include a page fault bit that indicates whether the page is in the computer's main memory or in the computer's storage. If the permissions of the security configuration 107 allow current access to the memory page and the page fault bit indicates that the page is not currently in the computer's main memory, then the memory management unit 181 may swap the page from the storage into the computer's main memory to facilitate access to the page identified by the page table entry 153. However, if the permissions of the security configuration 107 deny current access to the page for the current execution domain, then it is not necessary to evaluate the page fault bit and / or perform a swap in the page corresponding to the page table entry 153.

[0088] In general, table ID 143 may be divided into multiple fields used to locate page table 151. For example, table ID 143 may include a top table ID that identifies the top-level page table and a top table entry ID that is used as an index into the top-level page table to retrieve a page table entry containing an identifier for page table 151 (similar to how entry ID 145 indexes page table 151 to identify page table entry 153 containing base address 157).

[0089] In general, entry ID 145 can be considered a virtual page number in page table 151 ; and the virtual page number (eg, 145 ) can be used in page table 151 to look up a page table entry 153 containing base address 157 .

[0090] For example, table ID 143 may include a set of virtual page numbers that can be used to identify a series of page tables, such as 151. Each virtual page number is used as an index into a page table (or page directory) to identify a page table entry (or page directory entry) that contains the identifier or base address of the next level of page table (or page directory).

[0091] In some instances, different running processes in a computer may have different virtual address spaces (e.g., 127); and the process ID of the running process may be used to determine the top-level page table (or page directory). In some instances, a hash of a portion of virtual address 141, the process ID, and / or an identification of a virtual machine hosted in the computer system may be used to locate the top-level page table (or page directory). In some instances, the hash is used as an index or key to look up a page table entry. Regardless of how page table entry 153 is located (e.g., via indexing through multiple page tables, via use of a hash as an index or key), the contents of page table entry 153 may be Figure 5 The manner shown in FIG. 1 is configured to provide a security configuration 107 for different domains 101 , 103 , . . . , 105 to access pages / memory areas 137 corresponding to base addresses 157 and / or routines stored in memory areas 137 .

[0092] exist Figure 5 , the security configuration 107 for a page or region 137 is specified in an underlying page table 151 , where a page table entry 153 in the underlying page table 151 provides a base address 157 for a physical address 159 .

[0093] Alternatively, or in combination, a higher-level page table (or page directory) may also have security configurations for its page table entries (or page directory entries). For example, a page table entry (or page directory entry) identifying page table 151 may have security configurations for all pages in page table 151; and therefore, the domain permission data in the page table entry may apply to the memory region defined by page table 151. The hierarchy of security configurations in the series of page table entries leading to page table 151 and the security configuration 107 in the underlying page table entry 153 may be combined via a logical AND operation or a logical OR operation.

[0094] For example, if all permission bits in the series of page table entries leading to base address 157 (including bottom table entry 153) have values ​​that allow access, then a routine running in a domain (e.g., 101, 103, ..., 105) may be permitted to access the page identified by base address 157. Alternatively, if any permission bit in the series of page table entries leading to base address 157 (including bottom table entry 153) has a value that allows access, then a routine running in a domain (e.g., 101, 103, ..., 105) may be permitted to access the page identified by base address 157.

[0095] For example, if any permission bit in the series of page table entries leading to base address 157 (including bottom table entry 153) has a value that denies access, then a routine running in a domain (e.g., 101, 103, ..., 105) may be denied access to the page identified by base address 157. Alternatively, a routine running in a domain (e.g., 101, 103, ..., 105) may be denied access to the page identified by base address 157 only if all permission bits in the series of page table entries leading to base address 157 (including bottom table entry 153) have a value that denies access.

[0096] For example, when a non-lower level page table entry (or page directory entry) indicates that memory access is prohibited, the translation from virtual address 141 to physical address 159 may be interrupted to deny memory access associated with virtual address 141. In response to the denial, a software trap designated to handle the denial may be used.

[0097] For example, the security configuration 107 may include a set of sandbox setting bits (e.g., 111, 113, ..., 115) for the set of domains 101, 103, ..., 105, respectively. When the sandbox setting bit (e.g., 111, 113, ..., or 115) corresponding to the current domain 123 in the domain register 117 is set to have a first value (e.g., 1 or 0), the current call from the routine 191 in the current domain 123 to the callee routine 135 stored in the area 137 is implemented to protect the calling routine 191 and the callee routine 135 from each other using a sandboxing operation (e.g., by using a shadow stack to separate the caller and the callee in stack usage). When the sandbox setting bit (e.g., 111, 113, . . . or 115) corresponding to the current domain 123 in the domain register 117 is set to have a second value (e.g., 0 or 1), a call from the routine 191 in the current domain 123 to the called routine 135 stored in the memory area 137 is performed without using a sandboxing operation to isolate the caller and the called program from each other (e.g., without using a shadow stack).

[0098] Optionally, the security configuration (eg, 107) is specified in the bottom level page table 151 rather than in a higher level page table (directory).

[0099] Figure 6 A computer system is shown having a domain register 117 that controls security operations.

[0100] For example, Figure 6 The computer system may optionally have storage for Figure 3 and 4 The routines in the predefined domains 101, 103, ..., 105 shown in FIG are accessed by Figure 5 The page table entry 153 identifies the memory region of the security configuration 107 of the page table (eg, 151). In addition, Figure 6 The computer system may optionally have Figure 1 and 2 Domain access tables 217, ..., 227 are provided to facilitate and protect domain crossing.

[0101] For example, Figure 6 The computer system may have storage for accessing Figure 3 and 4 One or more permission registers of the security configuration 107 of the privilege registers 133 of the predefined domains 101, 103, ..., 105 shown in FIG.

[0102] The domain register 117 of the processor 169 stores an identifier of the current domain 123. The contents of the domain register 117 select a set of applicable settings in the security configuration 107 that corresponds to the current domain 123.

[0103] Figure 6 The computer system has a host system 165 coupled to a memory system 161 via one or more buses 163. The memory system 161 has memory components 171, ..., 173.

[0104] For example, bus 163 may include a memory bus connected to one or more memory modules and / or include a peripheral Internet connection to one or more storage devices. Some of the memory components 171, ..., 173 may provide random access; and some of the memory components 171, ..., 173 may provide permanent storage capabilities. Some of the memory components 171, ..., 173 may be volatile, in that the data stored in the memory component will be damaged and / or erased when the power supply to the memory component is temporarily disconnected. Some of the memory components 171, ..., 173 may be non-volatile, in that the memory component is able to retain its stored contents for a long period of time without power.

[0105] In general, the memory system 161 may also be referred to as a memory device. An example of a memory device is a memory module connected to a central processing unit (CPU) via a memory bus. Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), non-volatile dual inline memory modules (NVDIMMs), and the like. Another example of a memory device is a storage device connected to a central processing unit (CPU) via a peripheral interconnect (e.g., an input / output bus, a storage area network). Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, and hard disk drives (HDDs). In some examples, the memory device is a hybrid memory / storage system that provides both memory and storage functions.

[0106] Memory components 171, ..., 173 may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include NAND-type flash memory having one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC), such as triple-level cells (TLC) or quad-level cells (QLC). In some examples, a particular memory component may include both an SLC portion and an MLC portion of memory cells. Each memory cell may store one or more data bits (e.g., a data block) for use by host system 165. Alternatively, or in combination, memory components 171, ..., or 173 may include a type of volatile memory. In some examples, memory components 171 , . . . , or 173 may include, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, ferroelectric random access memory (FeTRAM), ferroelectric RAM (FeRAM), conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), nanowire-based nonvolatile memory, memory with memristor technology, and / or a cross-point array of nonvolatile memory cells. The cross-point array of nonvolatile memory can be combined with a stackable crossbar grid data access array to perform bit storage based on changes in bulk resistance. Additionally, in contrast to many flash-based memories, cross-point non-volatile memories can perform write-in-place operations, where non-volatile memory cells can be programmed without previously erasing the non-volatile memory cells.

[0107] In general, host system 165 can utilize memory system 161 as physical memory 109 including one or more memory components 171, . . . , 173. Host system 165 can load instructions from memory system 161 for execution, provide data to be stored at memory system 161, and request data to be retrieved from memory system 161.

[0108] exist Figure 6In the embodiment of the present invention, the host system 165 includes a memory management unit (MMU) 181 and a processor 169. The processor 169 has an execution unit (e.g., 185), such as an arithmetic logic unit. The processor 169 has registers 183 (e.g., 133) to store instructions for execution, data that are operands of instructions, and / or results of instruction execution. The processor 169 may have an internal cache 187 as a proxy for part of the memory system 161.

[0109] In some examples, host system 165 may include multiple processors (eg, 169 ) integrated as multiple processing cores of a central processing unit (CPU) on the same silicon die.

[0110] Routines programmed for execution in processor 169 may be initially stored in memory system 161. Routines may include instructions for hypervisor 102, operating system 104, and application programs 106. Routines initially stored in memory system 161 may be loaded into internal cache 187 and / or registers 183 (e.g., 133) for execution in execution unit 185.

[0111] The running instances of the routines form an execution 167 of the hypervisor 102, the operating system 104, and the application programs 106. In some instances, the hypervisor 102 is not used; and the operating system 104 controls the hardware components (e.g., the memory system 161, peripheral input / output devices, and / or network interface cards) without the hypervisor.

[0112] The execution 167 of the hypervisor 102, operating system 104, and / or application 106 accesses memory 137 (e.g., in memory components 171, ..., 173) using virtual memory addresses (e.g., 141) defined in one or more virtual memory spaces (e.g., 127). At least one page table 151 (e.g., as shown in FIG. 1 ) may be used. Figure 5 ) converts a virtual memory address (eg, 141 ) used in execution into a physical memory address (eg, 159 ) of a memory component (eg, 171 , . . . , 173 ).

[0113] like Figure 3As shown in FIG, the execution of routines of the hypervisor 102, the operating system 104, and the application 106 can be organized into a plurality of domains 101, 103, ..., 105. For each of the execution domains 101, 103, ..., 105 and a memory region 137 identified by a page table entry 153, the page table entry 153 identifies the setting of security configuration bits (e.g., 111, 113, ..., 115) for accessing the region 137 in predefined operation types (e.g., read, write, execute, etc.). The configuration bits of the corresponding security configuration (e.g., 107) control the corresponding type of memory access in the corresponding execution domain (e.g., 101) and / or control sandboxing operations for isolating the calling routine (e.g., 191) and the called routine (e.g., 135).

[0114] The security configuration 107 of the privileged register 133 can be stored in a separate permission register. Each of the permission registers is pre-associated with a domain (e.g., 101, 103, ..., 105). The permission register stores permission bits for accessing the privileged register 133 from the corresponding domain (e.g., 101, 103, ..., or 105). Different permission bits in the permission register can be configured for different privileged registers (e.g., 133). In some examples, the privileged register 133 can have multiple permission bits in the permission register for different access types (e.g., read, write, execute).

[0115] Alternatively, the permission bits of privilege register 133 may be specified in the same permission register. Additionally, the permission bits of different privilege registers (eg, 133) may be stored in different portions of the same permission register.

[0116] Figure 7 A method of performing domain interleaving when executing instructions in computer processor 169 is shown.

[0117] For example, Figure 7 The method can be Figure 6 Used in computer systems Figure 1 and 2 Domain access table 217, ..., 227, Figure 5 Designated for Figure 3 and 4 The execution domains 101, 103, ..., 105 shown in FIG. Figure 4 The security configuration 107 is executed by the page table 151.

[0118] At block 301 , the computer processor 169 receives instructions 193 calling to execute a routine (eg, 191 ).

[0119] For example, Figure 1The instruction 193 shown in may specify an identifier 197 of a domain 105 for a routine (eg, 191 ) and an entry index 199 for locating an entry in a domain access table 227 associated with the domain 105 .

[0120] At block 303 , the computer processor 169 extracts the identifier 197 and the entry index 199 of the domain 105 of the routine 191 from the instruction.

[0121] At block 305 , the computer processor 169 processes the call using the domain access table 227 identified by the register 229 pre-associated with the identifier 197 of the domain 105 .

[0122] At block 307 , the computer processor 169 checks the validity of the entry index 199 of the domain access table 227 .

[0123] For example, the entry index 199 is outside the upper and / or lower limits of the domain access table 227 using the valid index of the number of entries 221 stored in or with the domain access table 227 .

[0124] At block 309 , if the entry index 199 is valid, the computer processor 169 retrieves an entry (eg, 223 ) in the domain access table 227 using the entry index 199 .

[0125] At block 311 , the computer processor 169 verifies permission to enter the domain 105 via the entry point identified by the entry index 199 .

[0126] For example, permissions for different source domains (e.g., the domain of instruction 193) may be stored as part of entry 223. Alternatively, entry 223 may contain the virtual memory address 141 of routine 191; and the permissions and / or other security option data for routine 191 may be stored as part of security configuration 107 in the page table entry 153 used to translate virtual memory address 141 into physical memory address 159 to load instruction 193.

[0127] At block 313 , the computer processor 169 transitions to routine 191 in domain 105 .

[0128] For example, during a transition to executing instruction 193, the computer processor 169 may update the domain register 117 by storing the domain identifier 197 of the destination domain 105 to identify the current domain 123. The current domain 123 specified in the domain register 117 controls the selection of a setting (e.g., 111, 113, ..., or 115) of the security configuration 107 that specifies a corresponding domain (e.g., 101, 103, ..., or 105) that matches the current domain 123; and the selected setting (e.g., 111, 113, ..., or 115) is used to control security operations during execution of instruction 193.

[0129] The techniques disclosed herein are applicable to at least computer systems in which a processor is separate from memory and the processor communicates with memory and storage via a communication bus and / or a computer network. In addition, the techniques disclosed herein are applicable to computer systems in which processing capabilities are integrated into memory / storage devices. For example, processing circuits including execution units and / or registers of a typical processor can be implemented within an integrated circuit and / or integrated circuit package of a memory medium to perform processing within the memory device. Therefore, the processor (e.g., 101) discussed above and shown in the accompanying figures is not necessarily a central processing unit in a von Neumann architecture. The processor can be a unit integrated into the memory to overcome the von Neumann bottleneck, which limits computing performance due to throughput limitations caused by the latency of data movement between a central processing unit and memory configured separately according to the von Neumann architecture.

[0130] The description and drawings of the present disclosure are illustrative and should not be construed as limiting. Numerous specific details are described to provide a thorough understanding. However, in some instances, well-known or conventional details are not described to avoid obscuring the description. Reference to one or a certain embodiment in the present disclosure is not necessarily a reference to the same embodiment; and such reference means at least one.

[0131] In the foregoing description, the present disclosure has been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A computer system comprising: a memory configured to store at least a set of instructions for a predefined domain routine; a plurality of domain access tables, wherein each respective domain access table in the plurality of domain access tables is pre-associated with a respective domain in the set of predefined domains, the respective domain access table having one or more entries configured to identify one or more entry points of the respective domain; as well as a processor coupled to the memory, the processor configured to execute across the set of predefined domain transition instructions through entry points specified in the domain access table, wherein the domain access table is configured to allow execution across the set of predefined domain transition instructions without relying on a predefined domain hierarchy, wherein the processor is configured to retrieve an entry containing permission bits specifying permission to call a routine from a first domain included in the set of predefined domains, and wherein the entry contains a virtual memory address and convert the virtual memory address to a physical memory address.

2. The computer system of claim 1 , wherein the set of predefined domains further includes a second domain; and an instruction executed in the first domain requesting execution of a routine in the second domain contains an identifier of the second domain and an index to an entry in a domain access table pre-associated with the second domain.

3. The computer system of claim 2 , wherein the processor is further configured to extract the identifier of the second domain from the instruction, locate the domain access table pre-associated with the second domain, and determine whether the entry index of the domain access table pre-associated with the second domain is valid.

4. The computer system of claim 3, wherein the domain access table pre-associated with the second domain has an entry count; and the processor is configured to perform a bounds check on the entry index using the entry count.

5. The computer system of claim 3, wherein the processor is further configured to use the entry index to retrieve the entry in the domain access table pre-associated with the second domain, and to load the routine of the second domain using the retrieved entry. 6 . The computer system of claim 5 , wherein the processor is further configured to check the permission to call the routine from the first domain based at least in part on the entry retrieved using the entry index.

7. The computer system of claim 6, wherein the processor comprises a domain register configured to store an identifier of the first domain during execution of the instruction.

8. The computer system of claim 7, wherein the processor is configured to update the domain register and store the identifier of the second domain in the domain register during execution of the routine in the second domain.

9. A method for executing an instruction, comprising: receiving the instruction executed in a first domain of a set of predefined domains, the instruction requesting execution to transition to a routine in a second domain of the set of predefined domains, the instruction specifying an entry index; retrieving an entry in a domain access table of a plurality of domain access tables using the entry index, wherein the entry contains permission bits specifying permission to enter the second domain from the first domain, and wherein the entry contains a virtual memory address and translating the virtual memory address into a physical memory address; An execution transition to the routine in the second domain is secured based on the entry retrieved in the domain access table.

10. The method of claim 9, wherein retrieving the entry in the domain access table comprises: A bounds check is performed on the entry index.

11. The method according to claim 10, further comprising: Execution of instructions in a computer processor is prevented from bypassing the domain access table to transition from a domain other than the second domain to the second domain.

12. The method according to claim 10, further comprising: extracting an identifier of the second field from the instruction; as well as The domain access table is selected by using a register identified by the identifier of the second domain extracted from the instruction.

13. The method according to claim 12, further comprising: The authority to enter the second domain from the first domain is verified based at least in part on the entry retrieved in the domain access table.

14. A computer processor comprising: a plurality of registers configured to respectively store locations of a plurality of domain access tables, wherein each respective domain access table of the plurality of domain access tables is pre-associated with a respective domain of the plurality of domains, the respective domain access table having one or more entries configured to identify one or more entry points of the respective domain; as well as at least one execution unit configured to execute instructions; The entry to be retrieved from the one or more entries contains permission bits that specify permission to call a routine in a destination domain from a current domain, and wherein the entry contains a virtual memory address and the virtual memory address is translated into a physical memory address.

15. The computer processor of claim 14, further comprising: a domain register configured to store an identifier of a domain of a routine currently executing in said computer processor; The computer processor is configured to receive an instruction specifying the destination domain that causes a domain crossover, and to update the domain register according to the destination domain specified in the instruction.

16. The computer processor of claim 15, further comprising: a plurality of separate stacks configured for execution in the plurality of domains, respectively; as well as a plurality of register value areas configured to store values ​​of control registers respectively used for the execution in the plurality of domains; The control register includes at least one of a program counter PC, a stack pointer SP, a frame pointer FP, a variable parameter pointer AP or a processor status word PSW, or any combination thereof.

17. The computer processor of claim 16 , further configured to perform a security operation upon instruction execution based at least on the identifier stored in the domain register; wherein the security operation comprises at least one of: controlling access to a memory area based on permissions and a memory access type specified for the current domain identified by the domain register, controlling access to privileged registers of the processor based on permissions specified for the current domain, or selectively deploying a security mechanism that isolates resources of a calling routine and a called routine based on permissions specified for the current domain, or any combination thereof.

18. The computer processor of claim 14, wherein the plurality of domains comprises at least one of a hypervisor's domain, an operating system's domain, or an application's domain, or any combination thereof.

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