Storage device and storage system including the same

Abstract

A storage device includes: an array of storage cells configured to store data; and a data output circuit configured to transmit status data to an external device via at least one data line during a waiting period in response to a read enable signal received from the external device, and transmit data read from the array of storage cells to the external device via at least one data line during a period after the waiting period.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2019 - 0123349, filed on Oct. 4, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Example embodiments of the inventive concept relate to a storage device. For example, at least some example embodiments relate to a storage device that sends data to a memory controller and / or a storage system including the storage device. Background art

[0004] Storage devices can generally be classified into volatile storage devices such as dynamic random access memory (DRAM), static RAM (SRAM), etc., and non - volatile storage devices such as electrically erasable programmable read - only memory (EEPROM), ferroelectric RAM (FRAM), phase - change RAM (RRAM), magnetic RAM (MRAM), flash memory, etc. Non - volatile memory stores the stored data even when power is turned off.

[0005] A memory controller connected to a storage device may perform a training operation on the storage device after power - on to meet a desired (or alternatively, optimal) alignment condition between data and a clock signal, and control memory operations such as write operations, read operations, etc. When a desired (or alternatively, predetermined) time has elapsed after the training operation, due to a change in the memory operation environment, a deviation may occur between the data and the clock signal, and thus, a failure may occur during a write operation or a read operation. The memory controller may perform a retraining operation on the storage device to account for the deviation. However, conventionally, it may be difficult for a storage device to effectively send data (e.g., status data indicating the state of the storage device) to the memory controller to determine whether the memory controller should perform a retraining operation. Summary of the invention

[0006] Example embodiments of the inventive concept provide a storage device and a storage system including the storage device that effectively send data for determining whether to perform a retraining operation to a memory controller, such that the retraining operation can be performed in a timely manner according to its state, thereby improving memory performance.

[0007] According to an exemplary embodiment of the inventive concept, there is provided a storage device including: a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line during a waiting period in response to a read enable signal received from the external device, and transmit data stored in the memory cell array to the external device through at least one data line during a period after the waiting period.

[0008] According to other exemplary embodiments of the inventive concept, there is provided a storage system including: a memory controller; and a storage device configured to transmit status data to the memory controller through a plurality of data lines during a waiting period in response to a read enable signal received from the memory controller, and transmit data stored in the storage device to the memory controller through a plurality of data lines during a period after the waiting period.

[0009] According to other exemplary embodiments of the inventive concept, there is provided a storage device including: a memory cell array configured to store first data and second data; and a data output circuit configured to transmit the first data to an external device through a plurality of data lines at a first transfer rate during a waiting period in response to a read enable signal received from the external device, and transmit the second data to the external device through a plurality of data lines at a second transfer rate during a period after the waiting period. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram showing a storage system according to an exemplary embodiment of the inventive concept;

[0012] Figure 2 is a block diagram of a storage system for describing a method of transmitting status data according to an exemplary embodiment of the inventive concept;

[0013] Figure 3 is a flowchart showing a method of transmitting status data performed by a storage device according to an exemplary embodiment of the inventive concept;

[0014] Figure 4 is a block diagram showing an exemplary embodiment of a data output circuit according to an exemplary embodiment of the inventive concept;

[0015] Figure 5 is a timing diagram for describing an operation of a storage device according to an exemplary embodiment of the inventive concept;

[0016] Figures 6A to 6Cis a timing diagram showing a method of transmitting status data performed by a storage device according to an exemplary embodiment of the inventive concept;

[0017] Figure 7 is a timing diagram showing a method of transmitting status data performed by a storage device according to an exemplary embodiment of the inventive concept;

[0018] Figure 8A and Figure 8B is a timing diagram for describing a method of transmitting status data performed by a storage device according to an exemplary embodiment of the inventive concept;

[0019] Figures 9A to 9C is a diagram showing a configuration of data signals transmitted from a storage device to a memory controller through a data line according to an exemplary embodiment of the inventive concept;

[0020] Figure 10 is a flowchart showing operations of a storage system according to an exemplary embodiment of the inventive concept;

[0021] Figure 11A is a diagram showing a configuration of data signals transmitted from a storage device to a memory controller through a data line according to an exemplary embodiment of the inventive concept;

[0022] Figure 11B is a flowchart showing a method of operating a storage system according to an exemplary embodiment of the inventive concept, the storage system using a configuration of data signals to determine validity of status data;

[0023] Figure 12 is a block diagram showing a solid state drive (SSD) system according to an exemplary embodiment of the inventive concept; and

[0024] Figure 13 is a block diagram showing a storage module to which a storage device is applied according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0025] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0026] Figure 1 is a block diagram showing a storage system 100 according to an exemplary embodiment of the inventive concept.

[0027] Referring Figure 1 , the storage system 100 may include a memory controller 110 and a storage device 120.

[0028] The storage device 120 may receive a clock signal CK, a reset signal RESET, a command CMD, and an address ADD from the memory controller 110. For example, the storage device 120 may be a flash memory as a non-volatile storage device. Specifically, the storage device 120 may include a NAND flash memory. The storage system 100 may be a flash-based storage device and may be implemented as a memory card such as a solid state drive, a secure digital (SD) card, or a multimedia card (MMC). In addition, the storage system 100 may be implemented in a small size such as an embedded SSD (eSSD), an embedded MMC (eMMC), a universal flash storage (UFS), etc., and may be embedded in a portable electronic device. The eSSD may be used in a laptop computer or an e-book. The eMMC may be used in a mobile device, etc. However, the scope of the inventive concept is not limited thereto. The storage device 120 may include a volatile memory such as DRAM, SRAM, etc., or a non-volatile memory such as PRAM, RRAM, FRAM, etc. In some embodiments, the storage device 120 may be a three-dimensional storage device including a vertically stacked three-dimensional storage cell array (e.g., a VNAND storage cell array), and in addition, a vertically stacked three-dimensional storage cell array of 100 levels or more may be applied to the storage device 120. In addition, the peripheral on-die core (CoP) technology may be applied to the storage device 120.

[0029] Meanwhile, the storage device 120 may perform memory operations in various frequency domains, and in some embodiments, the storage device 120 may operate in a frequency domain of 1000Mhz or higher.

[0030] After the power of the storage system 100 is turned on, the memory controller 110 may send the reset signal RESET to the storage device 120. The storage device 120 may perform a reset operation by receiving the reset signal RESET. According to the reset operation, the storage device 120 may perform an initialization operation. Alternatively, the storage device 120 may receive an initialization command together with the reset signal RESET to perform the initialization operation. At this time, the transmission method of the state data of the storage device 120 to the memory controller 110, which will be described below, may be set through a setting feature operation between the storage device 120 and the memory controller 110.

[0031] The storage device 120 may perform an operation corresponding to the command CMD in response to the command CMD. For example, the command CMD may include a read command and a program command. The storage device 120 may perform a read operation and a program operation based on the address ADD.

[0032] The storage device 120 may output a data strobe signal DQS and data signals DQ. According to an embodiment, the storage device 120 may be connected to the memory controller 110 via a data strobe line and a plurality of data lines, may transmit the data strobe signal DQS via the data strobe line, and may output the data signals DQ via the plurality of data lines, respectively. When the storage device 120 receives a read command from the memory controller 110, the storage device 120 may generate a data strobe signal DQS synchronized with a clock signal CK. The storage device 120 may transmit the data signal DQ including read data aligned with the data strobe signal DQS to the memory controller 110 together with the data strobe signal DQS.

[0033] The storage device 120 according to an exemplary embodiment of the inventive concept may include a status data generation circuit 121, a data output circuit 123, a control logic 125, and a memory cell array (MCA) 127.

[0034] The status data generation circuit 121 may generate status data indicating the status of the storage device 120. The memory controller 110 may determine whether to perform a retrain operation on the storage device 120 based on the status data and perform the retrain operation on the storage device 120. In some exemplary embodiments, the memory controller 110 may transfer the status data received from the storage device 120 to the host, and the host may determine whether to perform the retrain operation based on the status data and control the retrain of the storage device 120 via the memory controller 110.

[0035] In an exemplary embodiment, the status data may include data for determining whether to perform a retrain operation on the storage device 120. For example, the status data generation circuit 121 may detect the degree of misalignment between the clock signal CK and the data signal DQ in the storage device 120 and generate status data indicating whether to perform a retrain operation on the storage device 120. As another example, when specific data promised by the storage device 120 and the memory controller 110 is written to the storage device 110, the status data generation circuit 121 may generate status data indicating whether the specific data is correctly written to the storage device 120.

[0036] In another exemplary embodiment, the status data may include data indicating the degree of change in the temperature environment or the operating voltage environment of the storage device 120. The status data generation circuit 121 may generate status data that changes depending on the change in the temperature environment or the operating voltage environment of the storage device 120. Specifically, the status data may include read or write training result data (or input / output training result data), data on duty cycle modulation of signals (e.g., data strobe signal DQS, data signal DQ, etc.) of the storage device 120, data on the oscillation of the data strobe signal DQS, memory core status data of the storage device 120, ZQ code, etc. The data on duty cycle modulation may indicate whether the duty cycle of the clock signal CK that meets the target duty cycle according to the standard specification of the storage device 120 has changed. The data on the oscillation of the data strobe signal DQS may indicate whether the number of toggles of the signal in the oscillator that outputs the data strobe signal DQS per unit time in the path or the replication path of the data strobe signal DQS has changed. The memory core status data may indicate the current state of the core of the storage device 120, and may indicate, for example, whether the core of the storage device 120 is in an erase operation state, a write operation state, a read operation state, etc. The ZQ code may be used to adjust the gain (or strength) of the input / output driver. However, this is only an exemplary embodiment, and the inventive concept is not limited thereto. In addition to metadata or user data for read operations, write operations, erase operations, etc., the status data may include various data for determining a retraining operation.

[0037] The MCA 127 may include a first type data area 127a and a second type data area 127b. In an exemplary embodiment, the status data of the storage device 120 may be stored in the first type data area 127a, and the user data may be stored in the second type data area 127b.

[0038] According to an example embodiment, the data output circuit 123 may output the status data and user data stored in the MCA 127 to the memory controller 110 through a plurality of data lines as data signals DQ. The data output circuit 123 may output the status data read from the first type data area 127a within a desired (or, predetermined) latency period before outputting the data read from the second type data area 127b in response to a read command from the memory controller 110. The latency period, which is a period set according to the latency cycle before the storage device 120 sends the read data to the memory controller 110, may correspond to a period during which an initial data strobe signal is sent when the data strobe signal DQS does not satisfy the target duty cycle. The number of cycles of the initial data strobe signal in the latency period may be defined as the latency cycle. The storage device 120 may be in a state for preparing the transmission of the read data until the end of the latency period, or may perform a predetermined memory operation (e.g., a duty cycle correction operation on the signals of the storage device 120) during the latency period.

[0039] The data output circuit 123 may output the status data through at least one data line within the latency period before outputting the read data to the memory controller 110 in response to a read command from the memory controller 110. The memory controller 110 may determine whether to perform a retraining operation on the storage device 120 based on the status data received during the latency period.

[0040] In addition, the storage device 120 and the memory controller 110 may pre-determine the transmission method of the status data during the latency period by setting feature information, and the memory controller 110 may confirm the status data received from the storage device 120 based on the set feature information. The set feature information includes information required for communication between the memory controller 110 and the storage device 120, and may be defined to conform to a standard. The set feature information may be set through a set feature operation between the memory controller 110 and the storage device 120, and may include information about the latency cycle and the transmission method of the status data.

[0041] For example, the transmission method of the status data may be determined according to the length of the latency cycle. The transmission method of the status data may include at least one of the following: the transmission start timing of the status data during the latency period, the transmission rate of the status data, and the data type included in the status data. Details of the transmission method of the status data will be described later.

[0042] The control logic 125 may control the memory operations of the storage device 120 based on the command CMD, and control the status data generation operation of the status data generation circuit 121 and the status data output operation of the data output circuit 123.

[0043] As described above, the storage device 120 according to the exemplary embodiment of the inventive concept may use the waiting period to send the status data to the memory controller 110, thereby effectively providing the status data to the memory controller 110 without a separate command and a separate section. Accordingly, the memory controller 110 may determine whether to perform a retraining operation on the storage device 120 based on the status data, thereby managing the storage device 120 and generally improving the performance of the storage system 100.

[0044] Figure 2 FIG. is a block diagram of a storage system 100 for describing a method of sending status data according to an exemplary embodiment of the inventive concept. Hereinafter, redundant descriptions between Figure 1 and Figure 2 are omitted.

[0045] Referring to Figure 2 , the memory controller 110 and the storage device 120 may be connected to each other through a data strobe line and a plurality of data lines. The memory controller 110 may include an enable signal generator 111 and a first-in first-out (FIFO) circuit 113. The enable signal generator 111 may provide a read enable signal RE to the storage device 120. The read enable signal RE may be used for the memory operations of the storage device 120 and may be toggled during the memory operation period of the storage device 120.

[0046] The storage device 120 may include a data output circuit 124, an MCA 127, and a DQS generator 129. The DQS generator 129 may generate a data strobe signal DQS in response to the read enable signal RE. The DQS generator 129 may send the data strobe signal DQS to the memory controller 110 through the data strobe line.

[0047] According to an example embodiment of the inventive concept, the data output circuit 124 may transmit status data read from the first type data area 127a of the MCA 127 to the memory controller 110 through at least one data line during a waiting period from an initial transition time of the data strobe signal DQS until a predetermined waiting period is satisfied, in response to a read enable signal RE. For example, the data output circuit 124 may transmit data signals DQ1 to DQn including status data to the memory controller 110 through a plurality of data lines. Various example embodiments of transmitting status data will be described later. The data output circuit 124 may transmit data signals DQ1 to DQn including data read from the second type data area 127b of the MCA 127 to the memory controller 110 through a plurality of data lines during a period after the waiting period. The data signals DQ1 to DQn may be output by being aligned with a rising edge or a falling edge of the data strobe signal DQS. The data signals DQ1 to DQn output from the storage device 120 may be sequentially stored in the latch circuits LAT1 to LAT8 of the FIFO circuit 113. The memory controller 110 may obtain status data and read data from the data signals of the stored data signals DQ1 to DQn. The memory controller 110 may quickly determine whether to perform a retraining operation on the storage device 120 based on the obtained status data.

[0048] Figure 3 is a flowchart illustrating a method of transmitting status data performed by a storage device according to an example embodiment of the inventive concept.

[0049] Referring to Figure 3 , in operation S100, the storage device 120 may receive a read enable signal RE and a read command from the memory controller 110.

[0050] In operation S110, the storage device 120 may generate a data strobe signal DQS aligned with a transition timing of the read enable signal RE and provide it to the memory controller 110.

[0051] In operation S120, the storage device 120 may transmit status data to the memory controller 110 through at least one data line during a waiting period in response to the read enable signal RE based on a desired (or, predetermined) transmission method, the waiting period being from an initial transition time of the data strobe signal DQS until a desired (or, predetermined) waiting period is satisfied.

[0052] In operation S130, the storage device 120 may transmit read data DQ to the memory controller 110 through at least one data line during a period after the waiting period.

[0053] Figure 4is a block diagram showing an implementation example of a data output circuit 124 according to an exemplary embodiment of the inventive concept. However, Figure 4 the illustrated implementation example is merely an example, and thus the configuration of the data output circuit 124 is not limited thereto.

[0054] Referring to Figure 4 , the data output circuit 124 may include a status register 124a, a latch register 124b, a multiplexer 124c, a read enable signal buffer 124d, a wait counter 124e, a parallel register 124f, and a data output driver 124g. The status register 124a may receive status data DATA_1 from a memory cell array of a storage device and sequentially store the status data DATA_1. The latch register 124b may receive read data DATA_2 from the memory cell array of the storage device and sequentially store the received read data. Outputs of each of the status register 124a and the latch register 124b may be coupled to the multiplexer 124c. The read enable signal buffer 124d may buffer a read enable signal RE and provide it to the wait counter 124e and the data output driver 124g.

[0055] The wait counter 124e may also receive wait cycle information LC_I, which may indicate the length of a desired (or alternatively, a predetermined) wait cycle. The wait counter 124e may provide a control signal MUX_CS to the multiplexer 124c so as to output status data DATA_1 received from the status register 124a based on the read enable signal RE and the wait cycle information LC_I during a wait period to the parallel register 124f. Additionally, the wait counter 124e may provide the control signal MUX_CS to the multiplexer 124c so as to output read data DATA_2 received from the latch register 124b based on the read enable signal RE and the wait cycle information LC_I during a period after the wait period to the parallel register 124f.

[0056] The parallel register 124f may align a received status data DATA_1 or read data DATA_2 with a data strobe signal based on a count result signal CS received from the wait counter 124e, and provide it to the data output driver 124g. The data output driver 124g may output a data signal including status data DATA_1 or read data DATA_2 to a memory controller MC 100 through a plurality of data lines.

[0057] Figure 5 is a timing diagram for describing an operation of a storage device according to an exemplary embodiment of the inventive concept.

[0058] Referring to Figure 5, when the storage device 120 receives a read enable signal RE with a changed level at a first time ta, the storage device 120 can generate a data strobe signal DQS synchronized with the read enable signal RE, and the level of the data strobe signal DQS can change at a second time tb. In Figure 5 , assuming the wait period is 2, the period between the second time tb and the third time tc can be defined as a wait period LP. The data strobe signal DQS in the wait period LP can be referred to as an initial data strobe signal, and the number of cycles of the initial data strobe signal in the wait period LP can be two. The storage device 120 can send a data signal DQx including status data SD to the memory controller 110 during the wait period LP. Thereafter, the storage device can send a data signal DQx including read data D0 to D3 to the memory controller in a cycle after the wait period LP.

[0059] Figure 5 This is only an exemplary embodiment and is not limited thereto. In the exemplary embodiment, the length of the wait period LP can vary according to the wait cycle, the wait cycle can be other than 2, and the transmission method of the status data SD can vary according to the wait cycle. As described above, the wait cycle and the transmission method of the status data SD can be set (or preset) as setting feature information.

[0060] Figures 6A to 6C is a timing diagram showing a method of sending status data executed by a storage device according to an exemplary embodiment of the inventive concept. Hereinafter, redundant descriptions between Figure 5 and Figures 6A to 6C are omitted. Figures 6A to 6C The configuration of the status data shown in is only an exemplary embodiment and is not limited thereto. The configuration of the status data can be differently implemented to include data for determining whether to perform a retraining operation on the storage device.

[0061] Referring to Figure 6A, the storage device 120 may transmit a data signal DQx including status data to the memory controller 110 through a data line. In the status data, various types of data are continuous during a waiting period LP between a second time tb and a third time tc. In an exemplary embodiment, the status data may include write training result data WT P / F, data DCM regarding duty cycle modulation of a signal of the storage device, data DQS OSC regarding oscillation of a data strobe signal DQS, and a ZQ code. Additionally, the storage device may transmit the status data to the memory controller 110 at the same or a similar transmission rate during the waiting period LP and transmit read data D1 to D3 to the memory controller 110 during a period after the waiting period LP. However, this is only an exemplary embodiment, and the inventive concept is not limited thereto. The storage device 120 may transmit status data to the memory controller, in which more or fewer types of data are continuous according to the length of the waiting period LP.

[0062] Referring to Figure 6B , the storage device 120 may transmit different types of status data to the memory controller 110 through a data line during the waiting period LP. In an exemplary embodiment, the storage device 120 may transmit a first data signal DQ[0] including write training result data WT P / F, a second data signal DQ[1] including data DCM regarding duty cycle modulation of a signal of the storage device 120, a third data signal DQ[2] including data DQS OSC regarding oscillation of a data strobe signal DQS, and a fourth data signal DQ[3] including a ZQ code during the waiting period LP. Additionally, the storage device 120 may transmit the status data to the memory controller 110 at different transmission rates during the waiting period LP and transmit read data D1 to D3 to the memory controller 110 during a period after the waiting period LP. Specifically, the transmission rate of the status data during the waiting period LP may be lower than the transmission rate of the read data D0 to D3 during a subsequent period. That is, since there is a possibility that the data strobe signal DQS during the waiting period LP does not satisfy a target duty cycle, the storage device 120 may reduce the transmission rate of the status data to be less than the transmission rate of the read data D0 to D3 so that the memory controller 110 can obtain relatively accurate status data. For example, during the waiting period LP, the storage device 120 may transmit the status data to the memory controller in a first frequency domain, and during a subsequent period, transmit the read data D0 to D3 to the memory controller in a second frequency domain. The second frequency domain may be an integer multiple of the frequency of the first frequency domain. For example, the second frequency domain may be twice the frequency of the first frequency domain.

[0063] The storage device 120 may operate at single data rate (SDR) or double data rate (DDR). In an exemplary embodiment, the storage device may operate at SDR during a wait period LP, and may operate at DDR during a subsequent period.

[0064] In another exemplary embodiment, the storage device 120 may send data other than status data (e.g., user data) to the memory controller 110 during the wait period LP. Since the data strobe signal DQS for the data sent during the wait period LP is somewhat unstable, the storage device 120 may reduce the transmission rate of the data sent during the wait period LP to be less than the transmission rate of the read data D0 to D3. Since the storage device sends data at a lower transmission speed than the read data D0 to D3 during the wait period LP, the memory controller 110 may sample and obtain the other data at a lower frequency than the read data D0 to D3. As described above, the storage device 120 may reduce the transmission rate of the data sent during the wait period LP in order to compensate for the somewhat unstable data strobe signal DQS during the wait period LP, and the memory controller 110 may relatively accurately obtain the data sent during the wait period LP.

[0065] With further reference to Figure 6C , the storage device 120 may send the fifth to eighth data signals DQ[4:7] including the memory core status data Core Status to the memory controller 110 during the wait period LP. Compared with Figure 6B , the storage device 120 may send the same type of memory core status data Core Status to the memory controller 110 through multiple data lines. However, this is only an exemplary embodiment, and the inventive concept is not limited thereto. The storage device 120 may send some types of status data to the memory controller 110 through multiple data lines, and send some other types of status data to the memory controller 110 through one data line. As described above, the memory controller 110 may confirm the type of status data sent by the storage device 120 according to the data line with reference to the set characteristic information.

[0066] Figure 7 is a timing diagram showing a method of sending status data SD performed by a storage device according to an exemplary embodiment of the inventive concept. In Figure 7 , it is assumed that the wait cycle during the wait period LP is 2.

[0067] With reference to Figure 7, the storage device 120 may send a data signal DQx including undefined data UD to the memory controller 110 before the status data SD during the wait period LP. Because there is a concern that the data strobe signal DQS does not meet the target duty cycle during the wait period LP and is not recognized as a pulse signal by the memory controller 110, the storage device 120 may send the undefined data UD in the initial period of the wait period LP and then send the status data SD.

[0068] Figure 7 The method of sending the status data SD in is only an exemplary embodiment and is not limited thereto. The transmission period of the undefined data UD may vary according to the length of the wait period LP, the operating environment of the storage device, the type of the status data SD, etc. The memory controller 110 may refer to the set characteristic information to confirm the transmission period of the undefined data UD sent by the storage device 120.

[0069] Figure 8A and Figure 8B are timing diagrams for describing a method of sending status data SD performed by a storage device according to an exemplary embodiment of the inventive concept. Assume Figure 8A and 8B that the number of wait cycles LC in the wait period LP in Figure 8A and 8B is 4.

[0070] Referring to Figure 8A , the storage device 120 may send a data signal DQx including undefined data UD to the memory controller 110 before the status data SD during the wait period LP. In the exemplary embodiment, the storage device 120 may send the undefined data UD and the status data SD to the memory controller 110 during different length periods in the wait period LP. For example, the period of sending the undefined data UD in the wait period LP may be shorter than the period of sending the status data SD. Specifically, in the wait period LP, the storage device 120 may send the undefined data UD to the memory controller 110 within one cycle of the data strobe signal DQS and then send the status data SD to the memory controller 110 within three cycles of the data strobe signal DQS. However, this is only an exemplary embodiment and the inventive concept is not limited thereto. The period of sending the undefined data UD in the wait period LP may be longer than the period of sending the status data SD. That is, in the wait period LP, the periods of sending the undefined data UD and the status data SD according to the exemplary embodiment of the inventive concept may vary according to the operating environment of the storage device 120 that affects the duty cycle of the data strobe signal DQS.

[0071] Referring to Figure 8B , compared with Figure 8AAlternatively, the storage device 120 may transmit undefined data UD and status data SD to the memory controller 110 during periods of the same length within the wait period LP. Specifically, within the wait period LP, the storage device 120 may transmit the undefined data UD to the memory controller 110 within two cycles of the data strobe signal DQS, and may subsequently transmit the status data SD to the memory controller 110 within two cycles of the data strobe signal DQS. However, this is merely an exemplary embodiment, and the inventive concept is not limited thereto. The length of the transmission period for each of the undefined data UD and the status data SD may vary according to the wait cycle LC.

[0072] Figures 9A to 9C FIG. is a diagram illustrating a configuration of data signals transmitted from a storage device to a memory controller according to an exemplary embodiment of the inventive concept.

[0073] Referring to Figure 9A , the data signal may include status data SD transmitted during the wait period LP and read data RD transmitted during a period after the wait period LP. The transmission rate of the status data SD according to the exemplary embodiment may be the same as or similar to the transmission rate of the read data RD. According to some exemplary embodiments, the transmission rate of the status data SD may be different from the transmission rate of the read data RD. Specifically, the transmission rate of the status data SD may be lower than the transmission rate of the read data RD, and the memory controller 110 may sample the status data SD at a frequency lower than that of the read data RD to obtain the status data SD.

[0074] Further referring to Figure 9B , the data signal may include status data SD transmitted during the wait period LP, a cyclic redundancy check (CRC) code CRC for increasing the reliability of the status data SD, and read data RD transmitted during a period after the wait period LP. The CRC code CRC may be used to check and correct errors in the status data SD in the memory controller 110, and according to some exemplary embodiments, may be replaced with a Gray code.

[0075] Further referring to Figure 9C , the data signal may include undefined data UD, status data SD transmitted during the wait period LP, and read data RD transmitted during a period after the wait period LP. The memory controller 110 may skip the undefined data UD and obtain the sampled and obtained status data SD.

[0076] Figures 9A to 9CThe configuration of the data signal shown in [Figure 0] can be determined by the memory controller 110 and the storage device 120 by setting the characteristic information, and the memory controller 110 can obtain the status data SD received from the storage device 120 during the waiting period LP based on the set characteristic information and control the storage device 120 based on the status data SD (e.g., control the retraining operation of the storage device 120).

[0077] Figure 10 is a flowchart showing the operation of a storage system according to an exemplary embodiment of the inventive concept.

[0078] Referring to Figure 10 , in operation S200, the memory controller 110 may send a read enable signal to the storage device 120 to obtain read data.

[0079] In operation S210, the storage device 120 may generate a data strobe signal in response to the read enable signal to send the data strobe signal to the memory controller 110 through the data strobe line and send the status data to the memory controller 110 through the data line during a desired (or alternatively, predetermined) waiting period.

[0080] In operation S220, the storage device 120 may send the read data to the memory controller 110 through the data line during a subsequent period of the waiting period.

[0081] In operation S230, the memory controller 110 may determine whether to perform a retraining operation on the storage device 120 based on the status data. When it is determined to perform the retraining operation (S230, Yes), operation S240 may follow. Otherwise, when it is determined not to perform the retraining operation (S230, No), operation S250 may follow.

[0082] In operation S240, the memory controller 110 may send a desired (or alternatively, predetermined) command for performing the retraining operation to the storage device 120.

[0083] In operation S260, the storage device 120 may perform a retraining operation in response to the received command.

[0084] Conversely, when it is determined not to perform the retraining operation, in operation S250, the memory controller 110 may perform a processing operation on the read data of the storage device 120 and then send the processed read data to the host.

[0085] Figure 11A is a diagram showing the configuration of the data signal sent from the storage device to the memory controller according to an exemplary embodiment of the inventive concept. Figure 11BIt is a flowchart showing a method of a storage system that determines the validity of status data SD using a configuration of an operation data signal.

[0086] Referring to Figure 11A , the data signal may include pattern data PD, status data SD transmitted during a waiting period LP, and read data RD transmitted during a period after the waiting period LP. The pattern data PD may be defined as data having a desired (or alternatively, predetermined) pattern in order to determine the validity of the status data SD. As described above, the data strobe signal during the waiting period LP may have unstable pulses. Thus, the pattern data PD may be used to determine the validity of the status data SD transmitted during the waiting period LP.

[0087] Further referring to Figure 11B , in operation S300, the memory controller 110 may send an Nth (where N is an integer greater than or equal to 1) read enable signal to the storage device 120.

[0088] In operation S310, the memory controller 110 may receive the pattern data PD from the storage device 120 during an initial period of the waiting period LP.

[0089] In operation S320, the memory controller 110 may receive the status data SD from the storage device 120 after receiving the pattern data PD during the waiting period LP.

[0090] In operation S330, the memory controller 110 may determine whether the pattern data PD matches reference data previously stored in the memory controller 110. When the pattern data PD matches the reference data (S330, Yes), operation S340 may follow, and when the pattern data PD does not match the reference data (S330, No), operation S350 may follow.

[0091] In operation S340, the memory controller 110 may confirm the validity of the status data SD and control the storage device 120 based on the status data SD.

[0092] In operation S350, the memory controller 110 may confirm that the status data SD is not valid, skip sampling the received status data SD, and then send a read enable signal for the next read operation to the storage device.

[0093] Figure 12 It is a block diagram showing a solid state drive (SSD) system 1000 according to an exemplary embodiment of the inventive concept.

[0094] Referring to Figure 12, the SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 exchanges signals with the host 1100 through a signal connector and receives power through a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and a plurality of storage devices 1230, 1240, and 1250.

[0095] According to example embodiments of the inventive concept, the plurality of storage devices 1230, 1240, and 1250 may transmit status data to the SSD controller 1210 through channels Ch1, Ch2, and Chn in response to a read enable signal received from the SSD controller 1210 during a waiting period. The plurality of storage devices 1230, 1240, and 1250 may transmit read data through channels Ch1, Ch2, and Chn during a period after the waiting period. The SSD controller 1210 may determine whether to perform a retraining operation on the plurality of storage devices 1230, 1240, and 1250 based on the received status data. As described above, the method of transmitting status data during the waiting period may vary and may be pre-promised between the SSD controller 1210 and the plurality of storage devices 1230, 1240, and 1250. In some example embodiments, the SSD controller 1210 may transmit the status data received from the storage devices 1230, 1240, and 1250 to the host 1100, and the host 1100 may perform a retraining operation on the plurality of storage devices 1230, 1240, and 1250 based on the status data through the memory controller 1210.

[0096] Figure 13 is a block diagram of a storage module 2000 to which a storage device is applied according to an example embodiment of the inventive concept.

[0097] Referring to Figure 13 , the storage module 2000 may include a register clock driver (RCD) 2100 and a plurality of DRAM devices 2210 to 2280. The RCD 2100 may receive a command / address C / A and a clock signal CK from an external device (e.g., a host or a memory controller). The RCD 2100 may transfer the command / address C / A to the plurality of DRAM devices 2210 to 2280 based on the received signals. Each of the DRAM devices 2210 to 2280 may output a plurality of data signals DQ and a data strobe signal DQS. For example, the plurality of DRAM devices 2210 to 2280 may output data signals DQ including status data indicating the status of each of the DRAM devices 2210 to 2280 during a desired (or alternatively, predetermined) waiting period, as described with reference to Figures 1 to 11B .

[0098] Multiple DRAM devices 2210 to 2280 may send status data and user data to an external device (e.g., a host or a memory controller) via multiple data signals DQ based on a data strobe signal DQS. Thereafter, the external device may determine whether to perform a retraining operation on the DRAM devices 2210 to 2280 based on the status data received from the DRAM devices 2210 to 2280. As described above, the method of sending status data during the waiting period may vary and may be predetermined between the external device and the multiple DRAM devices 2210 to 2280.

[0099] The memory controller 110 and the storage device 120 and its sub-components including the enable signal generator 111, the status data generation circuit 121, the data output circuits 123, 124, the control logic 125, and the DQS generator 129 may include a processing circuit, such as hardware including logic circuits; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In addition, the MCA 127 and the latch circuits LAT1-LATn may include non-volatile or volatile memory. The processing circuit may be a dedicated processing circuit such that the storage device 120 uses the waiting period when sending status data, thereby effectively providing status data without a separate command and a separate section, and the memory controller 110 determines whether to perform a retraining operation on the storage device 120 based on the status data. Therefore, the dedicated processing circuit may generally improve the performance of the storage system 100.

[0100] Although example embodiments of the inventive concept have been specifically shown and described with reference to example embodiments of the inventive concept, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: a storage cell array configured to store data; and a data output circuit configured to, in response to a read enable signal received from an external device, send status data to the external device via at least one data line during a waiting period, and send the data stored in the storage cell array to the external device via at least one data line during a period after the waiting period, wherein the transmission method of the status data is based on the length of the waiting period.

2. The storage device according to claim 1, wherein, the waiting period starts from the first transition time of a data strobe signal after the read enable signal until a set number of cycles of the data strobe signal occur, wherein the length of the waiting period corresponds to the set number of cycles.

3. The storage device according to claim 2, wherein, transmission parameters associated with the transmission method of the status data are determined according to the set number of cycles.

4. The storage device according to claim 1, wherein, transmission parameters associated with the transmission method of the status data include at least one of the following: the transmission start timing of the status data, the transmission rate of the status data, and the data type included in the status data.

5. The storage device according to claim 1, wherein, the status data includes data indicating whether a retraining operation needs to be performed on the storage device.

6. The storage device according to claim 1, wherein, the data output circuit is configured to: send undefined data to the external device via at least one data line before the transmission of the status data during the waiting period.

7. The storage device according to claim 1, wherein, the data output circuit is configured to: send both pattern data for determining the reliability of the status data and the status data during the waiting period, such that the pattern data is sent before the status data during the waiting period.

8. The storage device according to claim 1, wherein, the storage device is configured to send the status data at a data transmission rate lower than the data stored in the storage cell array.

9. The storage device according to claim 1, wherein, the at least one data line includes a plurality of data lines, such that the data output circuit is configured to send different status data in the status data via corresponding data lines among the plurality of data lines during the waiting period.

10. The storage device according to claim 1, wherein, the at least one data line includes a plurality of data lines, such that the data output circuit is configured to send the same status data in the status data to the external device via the plurality of data lines during the waiting period.

11. The storage device according to claim 1, wherein, the data output circuit is configured to send the status data based on setup characteristic information determined for communication between the external device and the storage device.

12. A storage system, comprising: a memory controller; and a storage device configured to, in response to a read enable signal received from the memory controller, send status data to the memory controller via a plurality of data lines during a waiting period, and During a period after the waiting period, data stored in the storage device is sent to the memory controller via a plurality of data lines, wherein the status data indicates whether a retraining operation needs to be performed on the storage device.

13. The storage system according to claim 12, wherein, the memory controller is configured to determine whether to perform a retraining operation on the storage device based on the status data, and control the storage device based on whether the memory controller determines to perform the retraining operation.

14. The storage system according to claim 12, wherein, the memory controller is configured to transfer the status data to the host, and control the retraining operation of the storage device in response to a request from the host to retrain the storage device.

15. The storage system according to claim 12, wherein, the status data includes at least one of data (DCM) associated with duty cycle modulation of a signal of the storage device (120), data associated with oscillation of a data strobe signal (DQS), memory core status data, and a ZQ code.

16. The storage system according to claim 12, wherein, the status data indicates the degree of change in the temperature environment or operating voltage environment of the storage device.

17. The storage system according to claim 12, wherein, the storage device is configured to determine parameters associated with sending the status data based on setup characteristic information determined for communication between the memory controller and the storage device.

18. The storage system according to claim 12, wherein, the storage device is configured to send the status data at a first data transfer rate and send the data stored in the storage device at a second data transfer rate, the first data transfer rate being different from the second data transfer rate.

19. A storage device, comprising: a storage cell array configured to store first data and second data; and a data output circuit configured to, in response to a read enable signal received from an external device, send the first data to the external device via a plurality of data lines at a first transfer rate during a waiting period, and send the second data to the external device via a plurality of data lines at a second transfer rate during a period after the waiting period, wherein the first data indicates whether a retraining operation needs to be performed on the storage device.

20. The storage device according to claim 19, wherein, the second data includes user data.

Images