Topological Shader Technology

Abstract

Systems, devices, and methods can provide the following technology: a topology shader in a graphics pipeline receives an object description and generates a set of polygons in the topology shader based on the object description. Additionally, the set of polygons is sent to a vertex shader.

Description

Technical Field

[0001] Embodiments of the present application generally relate to a graphics processing architecture. More specifically, embodiments relate to topology shader technology in a graphics processing architecture. Background Art

[0002] In a traditional graphics processing architecture, a central processing unit (CPU) may determine the complexity and topology of a scene to be rendered and generate a stream of instructions that are further processed by a vertex shader in a graphics pipeline. The stream of instructions may include parameters such as vertex data of a high-order surface, primitives, etc., where the vertex shader may transform the vertex data from an object-based coordinate representation (object space) to an alternatively based coordinate system such as world space or normalized device coordinate (NDC) space. Such architectures may be limited to a fixed topology for each video frame depicting a scene, where the fixed topology may limit quality and / or performance. Additionally, traditional means may use a tessellator later in the graphics pipeline to generate vertex attributes and surface representations for each vertex associated with a geometric primitive. Relying solely on later-stage tessellation to generate surface representations may further limit quality and / or performance. Brief Description of the Drawings

[0003] Various advantages of the embodiments will become apparent to those skilled in the art by reading the following specification and the appended claims and by referring to the following drawings, in which:

[0004] Figure 1 is a block diagram that illustrates a computer system configured to implement one or more aspects of the embodiments described herein;

[0005] Figures 2A - 2D illustrates a parallel processor component according to an embodiment;

[0006] Figures 3A - 3B is a block diagram of a graphics multiprocessor according to an embodiment;

[0007] Figures 4A - 4F illustrates an exemplary architecture in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0008] Figure 5 illustrates a graphics processing pipeline according to an embodiment;

[0009] Figure 6 is a block diagram of an example of a graphics processing pipeline according to another embodiment;

[0010] Figure 7 is an illustration of an example of a topological representation of a sphere with varying levels of detail according to an embodiment;

[0011] Figure 8 is an illustration of an example of a lack of visibility condition according to an embodiment;

[0012] Figure 9A is a flowchart of an example of a method for operating a semiconductor packaging device according to an embodiment;

[0013] Figure 9B is a flowchart of an example of a method for generating a set of polygons according to an embodiment;

[0014] Figure 10A is a block diagram of an example of a computing system according to an embodiment;

[0015] Figure 10B is an illustration of an example of a semiconductor packaging device according to an embodiment;

[0016] Figure 11 is an illustration of an example of a head-mounted display (HMD) system according to an embodiment;

[0017] Figure 12 is included according to an embodiment in Figure 11 a block diagram of an example of a functional component in an HMD system;

[0018] Figure 13 is a block diagram of an example of a general processing cluster included in a parallel processing unit according to an embodiment;

[0019] Figure 14 is a conceptual illustration of an example of a graphics processing pipeline that can be implemented within a parallel processing unit according to an embodiment;

[0020] Figure 15 is a block diagram of an example of a streaming multiprocessor according to an embodiment;

[0021] Figures 16 - 18 is a block diagram of an example of an overview of a data processing system according to an embodiment;

[0022] Figure 19 is a block diagram of an example of a graphics processing engine according to an embodiment;

[0023] Figures 20 - 22 is a block diagram of an example of an execution unit according to an embodiment;

[0024] Figure 23 is a block diagram of an example of a graphics pipeline according to an embodiment;

[0025] Figures 24A - 24B is a block diagram of an example of graphics pipeline programming according to an embodiment;

[0026] Figure 25 is a block diagram of an example of a graphics software architecture according to an embodiment;

[0027] Figure 26 is a block diagram of an example of an intellectual property (IP) core development system according to an embodiment; and

[0028] Figure 27 is a block diagram of an example of a system-on-chip integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0029] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

[0030] System Overview

[0031] Figure 1 is a block diagram that illustrates a computing system configured to implement one or more aspects of the embodiments described herein. Computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104, the one or more processors 102 communicating with the system memory 104 via an interconnect path that may include a memory hub 105. Memory hub 105 may be a separate component within a chipset component or may be integrated within the one or more processors 102. Memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. I / O subsystem 111 includes an I / O hub 107 that may enable computing system 100 to receive input from one or more input devices 108. Additionally, I / O hub 107 may enable a display controller to provide output to one or more display devices 110A, the display controller being included in the one or more processors 102. In one embodiment, the one or more display devices 110A coupled to I / O hub 107 may include local, internal, or embedded display devices.

[0032] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112, which are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols (such as, but not limited to, PCI Express), or can be a vendor-specific communication interface or communication fabric. In one embodiment, the one or more parallel processors 112 form a computationally centralized parallel or vector processing system, which includes a large number of processing cores and / or processing clusters (such as, an integrated many-core (MIC) processor). In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem, which can output pixels to one of the one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 can also include a display controller and a display interface (not shown) to enable a direct connection to one or more display devices 110B.

[0033] Within the I / O subsystem 111, the system storage unit 114 can be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. The I / O switch 116 can be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components (such as, a network adapter 118 and / or a wireless network adapter 119 that can be integrated into the platform, and various other devices that can be added via one or more plug-in devices 120). The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of the following: Wi-Fi, Bluetooth, near field communication (NFC), or another network device that includes one or more wireless radios.

[0034] The computing system 100 can include other components not explicitly shown, including USB or other port connectors, optical storage drives, video capture devices, and the like, which can also be connected to the I / O hub 107. The communication paths interconnecting the various components can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI Express) or any other bus or point-to-point communication interface and / or protocol (such as, NV-Link high-speed interconnect, or an interconnect protocol known in the art). Figure 1

[0035]

[0035] In one embodiment, the one or more parallel processors 112 incorporate circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In another embodiment, the one or more parallel processors 112 incorporate circuitry optimized for general purpose processing while maintaining the underlying computational architecture described in more detail herein. In yet another embodiment, components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processors 112, memory hub 105, processor 102, and I / O hub 107 may be integrated into a system-on-a-chip (SoC) integrated circuit. Alternatively, components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM) that may be interconnected with other multi-chip modules into a modular computing system.

[0036] It will be recognized that the computing system 100 shown herein is illustrative, and variations and modifications are possible. The connection topology can be modified as desired, including the number and arrangement of bridges, the number of processors 102, and the number of parallel processors 112. For example, in some embodiments, system memory 104 is connected directly to the processor(s) 102 rather than through a bridge, while other devices communicate with the processor(s) 102 and system memory 104 via the memory hub 105. In other alternative topologies, the parallel processor(s) 112 are connected to the I / O hub 107 or directly to one of the processor(s) 102 rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 may be integrated into a single chip. Some embodiments may include two or more sets of processors 102 attached via multiple sockets, which may be coupled to two or more instances of the parallel processor(s) 112.

[0037] Some of the specific components shown herein are optional and may not be included in all implementations of the computing system 100. For example, any number of plug-in cards or peripheral devices may be supported, or some components may be eliminated. Additionally, some architectures may use different terms for components similar to those shown Figure 1 herein. For example, in some architectures, the memory hub 105 may be referred to as the north bridge, while the I / O hub 107 may be referred to as the south bridge.

[0038] Figure 2AFIG. 200 shows a parallel processor according to an embodiment. Various components of the parallel processor 200 may be implemented using one or more integrated circuit devices such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). According to an embodiment, the illustrated parallel processor 200 is Figure 1 a variant of one or more of the parallel processors 112 shown in FIG. 112.

[0039] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 that enables communication with other devices, including other instances of the parallel processing unit 202. The I / O unit 204 may be directly connected to other devices. In one embodiment, the I / O unit 204 is connected to other devices via the use of a hub or switch interface such as the memory hub 105. The connection between the memory hub 105 and the I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar 216, where the host interface 206 receives commands for performing processing operations and the memory crossbar 216 receives commands for performing memory operations.

[0040] When the host interface 206 receives a command buffer via the I / O unit 204, the host interface 206 may direct the work operations for performing those commands to a front end 208. In one embodiment, the front end 208 is coupled to a scheduler 210 configured to distribute commands or other work items to an array of processing clusters 212. In one embodiment, the scheduler 210 ensures that the array of processing clusters 212 is properly configured and in an active state before tasks are distributed to the processing clusters of the array of processing clusters 212. In one embodiment, the scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 may be configured to perform complex scheduling and work distribution operations at both a coarse and fine granularity, enabling context switching and rapid preemption of threads executing on the processing array 212. In one embodiment, host software may check the workload scheduled on the processing array 212 via one of a plurality of graphics processing doorbells. The workload may then be automatically distributed across the processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0041] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each of the clusters 214A - 214N of the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may use various scheduling and / or workload distribution algorithms to allocate work to the clusters 214A - 214N of the processing cluster array 212, which may vary depending on the workload generated for each type of program or computation. Scheduling may be handled dynamically by the scheduler 210, or may be assisted in part by compiler logic during the compilation of the program logic configured to be executed by the processing cluster array 212. In one embodiment, different clusters 214A - 214N of the processing cluster array 212 may be assigned to process different types of programs, or to perform different types of computations.

[0042] The processing cluster array 212 may be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, the processing cluster array 212 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations (including physics operations), and performing data transformations.

[0043] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. Additionally, the processing cluster array 212 may be configured to execute graphics processing-related shader programs, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 may transfer data from the system memory via the I / O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing and then written back to the system memory.

[0044] In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better enable distribution of the graphics processing operations across the multiple clusters 214A - 214N in the processing cluster array 212. In some embodiments, multiple portions of the processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of the clusters 214A - 214N may be stored in a buffer to allow transfer of the intermediate data between the clusters 214A - 214N for further processing.

[0045] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, the processing tasks may include commands and status parameters defining how to process the data (e.g., what program to execute) and indices of the data to be processed (e.g., surface (patch) data, primitive data, vertex data, and / or pixel data). The scheduler 210 may be configured to obtain the indices corresponding to the tasks or may receive the indices from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured in an effective state before initiating the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0046] Each of one or more instances of the parallel processing unit 202 may be coupled to the parallel processor memory 222. The parallel processor memory 222 may be accessed via a memory crossbar 216 that may receive memory requests from the array of processing clusters 212 as well as the I / O unit 204. The memory crossbar 216 may access the parallel processor memory 222 via a memory interface 218. The memory interface 218 may include a plurality of partitioning units (e.g., partitioning unit 220A, partitioning unit 220B, up to partitioning unit 220N), each of which may be coupled to a portion (e.g., a memory unit) of the parallel processor memory 222. In one implementation, the number of partitioning units 220A - 220N is configured to be equal to the number of memory units such that the first partitioning unit 220A has a corresponding first memory unit 224A, the second partitioning unit 220B has a corresponding memory unit 224B, and the Nth partitioning unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partitioning units 220A - 220N may not be equal to the number of memory devices.

[0047] In various embodiments, the memory units 224A - 224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A - 224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will recognize that the specific implementation of the memory units 224A - 224N may vary and may be selected from one of a variety of conventional designs. Render targets (such as frame buffers or texture maps) may be stored across the memory units 224A - 224N, allowing the partitioning units 220A - 220N to write multiple portions of each render target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 222. In some embodiments, a local instance of the parallel processor memory 222 may be excluded in favor of a unified memory design that utilizes system memory along with local cache memory.

[0048] In one embodiment, any one of clusters 214A - 214N of processing cluster array 212 can process data to be written into any one of memory units 224A - 224N within parallel processor memory 222. Memory crossbar 216 can be configured to transfer the output of each of clusters 214A - 214N to any partition unit 220A - 220N or another cluster 214A - 214N, which can perform additional processing operations on the output. Each of clusters 214A - 214N can communicate with memory interface 218 via memory crossbar 216 to read from or write to various external memory devices. In one embodiment, memory crossbar 216 has a connection to memory interface 218 to communicate with I / O unit 204, and a connection to a local instance of parallel processor memory 222, enabling processing units within different processing clusters 214A - 214N to communicate with system memory or other memory not local to parallel processing unit 202. In one embodiment, memory crossbar 216 can use virtual channels to separate the traffic flow between clusters 214A - 214N and partition units 220A - 220N.

[0049] Although a single instance of parallel processing unit 202 is shown within parallel processor 200, any number of instances of parallel processing unit 202 can be included. For example, multiple instances of parallel processing unit 202 can be provided on a single plug - in card, or multiple plug - in cards can be interconnected. Different instances of parallel processing unit 202 can be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example and in one embodiment, some instances of parallel processing unit 202 can include higher - precision floating - point units relative to other instances. Systems incorporating one or more instances of parallel processing unit 202 or parallel processor 200 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0050] Figure 2B is a block diagram of partition unit 220 according to an embodiment. In one embodiment, partition unit 220 is Figure 2AAn example of one of the partition units 220A - 220N. As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar 216 and the ROP 226. Read misses and urgent writeback requests are output from the L2 cache 221 to the frame buffer interface 225 for processing. Updates can also be sent via the frame buffer interface 225 to the frame buffer for processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory units in the parallel processor memory, such as the memory units 224A - 224N of FIG. 2 (e.g., within the parallel processor memory 222).

[0051] In a graphics application, the ROP 226 is a processing unit that performs raster operations such as stencil, z-test, blending, and the like. Subsequently, the ROP 226 outputs the processed graphics data stored in the graphics memory. In some embodiments, the ROP 226 includes compression logic for compressing depth or color data written to the memory and decompressing depth or color data read from the memory. The compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by the ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0052] In some embodiments, the ROP 226 is included within each processing cluster (e.g., clusters 214A - 214N of FIG. 2) rather than within the partition unit 220. In such embodiments, read and write requests for pixel data, rather than pixel fragment data, are conveyed through the memory crossbar 216. The processed graphics data can be displayed on a display device (such as Figure 1 one of the one or more display devices 110), routed for further processing by the (one or more) processors 102, or routed for further processing by Figure 2A one of the processing entities within the parallel processor 200.

[0053] Figure 2CIt is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A - 214N of FIG. 2. The processing cluster 214 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific set of input data. In some embodiments, without providing multiple independent instruction units, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads. In other embodiments, a common instruction unit configured to issue instructions to a set of processing engines within each of the processing clusters is used, and single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronized threads. Different from the SIMD execution regime where all processing engines typically execute the same instruction, SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that the SIMD processing regime represents a functional subset of the SIMT processing regime.

[0054] The operation of the processing cluster 214 can be controlled via a pipeline manager 232, which distributes processing tasks to SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2 and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures can be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included within the processing cluster 214. The graphics multiprocessor 234 can process data, and a data crossbar 240 can be used to distribute the processed data to one of multiple possible destinations, including other shader units. The pipeline manager 232 can facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 240.

[0055] Each graphics multiprocessor 234 within the processing cluster 214 can include the same set of functional execution logic (e.g., arithmetic logic units, load - store units, etc.). The functional execution logic can be configured in a pipelined manner, in which new instructions can be issued before the previous instruction is completed. The functional execution logic supports a wide variety of operations, including integer and floating - point arithmetic, comparison operations, boolean operations, bit - shifting, and the calculation of various algebraic functions. In one embodiment, different operations can be performed using the same functional unit hardware, and any combination of functional units can exist.

[0056] The instructions transmitted to processing cluster 214 form threads. A set of threads that execute across a group of parallel processing engines is a thread group. The thread group executes the same program on different input data. Each thread within the thread group can be assigned to a different processing engine within graphics multiprocessor 234. The thread group can include fewer threads than the number of processing engines within graphics multiprocessor 234. When the thread group includes fewer threads than the number of processing engines, one or more of the processing engines can be idle during the cycle in which the thread group is being processed. The thread group can also include more threads than the number of processing engines within graphics multiprocessor 234. When the thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be executed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor 234.

[0057] In one embodiment, graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, graphics multiprocessor 234 can forgo the internal cache and use the cache memory (e.g., L1 cache 308) within processing cluster 214. Each graphics multiprocessor 234 also has access to an L2 cache within a partition unit (e.g., partition units 220A - 220N of FIG. 2) that is shared across all processing clusters 214 and can be used to transfer data between threads. Graphics multiprocessor 234 also has access to off - chip global memory, which can include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 202 can be used as global memory. Embodiments in which processing cluster 214 includes multiple instances of graphics multiprocessor 234 can share common instructions and data, which can be stored in L1 cache 308.

[0058] Each processing cluster 214 can include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of MMU 245 can reside within memory interface 218 of FIG. 2. MMU 245 includes: a set of page table entries (PTEs) for mapping the virtual addresses of tiles (more discussion on tiling) to physical addresses; and optionally a cache line index. MMU 245 can include a translation lookaside buffer (TLB) or cache that can reside within graphics multiprocessor 234 or L1 cache or processing cluster 214. The physical addresses are processed to distribute surface data access locality, allowing for efficient request interleaving within the partition unit. The cache line index can be used to determine whether a request for a cache line is a hit or a miss.

[0059] In graphics and computing applications, the processing cluster 214 may be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. As needed, texture data is read from an internal texture L1 cache (not shown) or in some embodiments from an L1 cache within the graphics multiprocessor 234, and the texture data is fetched from an L2 cache, local parallel processor memory, or system memory. Each graphics multiprocessor 234 outputs the processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. The preROP 242 (e.g., pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234 and direct the data to a ROP unit, which may be co-located with a partitioning unit (e.g., partitioning units 220A-220N of FIG. 2) as described herein. The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0060] It will be appreciated that the core architectures described herein are illustrative and that variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessors 234, texture units 236, preROP 242, etc.) may be included within the processing cluster 214. Additionally, although only one processing cluster 214 is shown, the parallel processing units as described herein may include any number of instances of the processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0061] Figure 2D A graphics multiprocessor 234 according to one embodiment is shown. In such embodiments, the graphics multiprocessor 234 is coupled to a pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to: an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0062] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. The instructions are cached in the instruction cache 252 and dispatched by the instruction unit 254 for execution. The instruction unit 254 may dispatch instructions as thread groups (e.g., warps), where each thread of a thread group is assigned to a different execution unit within the GPGPU core 262. Instructions can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 may be used to translate an address in the unified address space into a distinct memory address that can be accessed by the load / store unit 266.

[0063] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for the operands of the data paths connected to the functional units (e.g., GPGPU core 262, load / store unit 266) of the graphics multiprocessor 324. In one embodiment, the register file 258 is partitioned among each of the functional units such that each functional unit is allocated a dedicated portion of the register file 258. In one embodiment, the register file 258 is partitioned among different warps executed by the graphics multiprocessor 324.

[0064] The GPGPU cores 262 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing the instructions of the graphics multiprocessor 324. According to an embodiment, the GPGPU cores 262 may be architecturally similar or may be architecturally different. For example and in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or be capable of implementing variable-precision floating-point arithmetic. The graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units to perform specific functions (such as copy rectangle or pixel blend operations). In one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0065] In one embodiment, the GPGPU core 262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 262 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time or can be automatically generated when executing a program written and compiled for a single-program multiple-data (SPMD) or SIMT architecture. Multiple threads of a program configured for the SIMT execution model can be executed via a single SIMD instruction. For example and in one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logical unit.

[0066] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 234 to the register file 258 and to the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to implement load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, whereby data transfer between the GPGPU core 262 and the register file 258 is very low latency. The shared memory 270 can be used to enable communication between the threads executing on the functional units within the graphics multiprocessor 234. The cache memory 272 can be used as, for example, a data cache to cache texture data communicated between the functional units and the texture unit 236. The shared memory 270 can also be used as a program-managed cache. Threads executing on the GPGPU core 262 can programmatically store data in the shared memory other than the automatically cached data stored in the cache memory 272.

[0067] Figures 3A - 3B Additional graphics multiprocessors according to embodiments are shown. The graphics multiprocessors 325, 350 shown are Figure 2C variants of the graphics multiprocessor 234. The graphics multiprocessors 325, 350 shown can be configured as streaming multiprocessors (SMs) capable of simultaneously executing a large number of execution threads.

[0068] Figure 3A A graphics multiprocessor 325 according to an additional embodiment is shown. The graphics multiprocessor 325 relative to Figure 2DThe graphics multiprocessor 234 includes multiple additional instances of execution resource units. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A - 332B, register files 334A - 334B, and texture units 344A - 344B. The graphics multiprocessor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A - 336B, GPGPU cores 337A - 337B, GPGPU cores 338A - 338B) and multiple sets of load / store units 340A - 340B. In one embodiment, the execution resource units have a common instruction cache 330, a texture and / or data cache memory 342, and a shared memory 346.

[0069] The various components may communicate via an interconnect structure 327. In one embodiment, the interconnect structure 327 includes one or more crossbar switches to enable communication between the various components of the graphics multiprocessor 325. In one embodiment, the interconnect structure 327 is a separate high - speed network structure layer on which each component of the graphics multiprocessor 325 is stacked. The components of the graphics multiprocessor 325 communicate with remote components via the interconnect structure 327. For example, the GPGPU cores 336A - 336B, 337A - 337B, and 338A - 338B may each communicate with the shared memory 346 via the interconnect structure 327. The interconnect structure 327 may arbitrate communication within the graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0070] Figure 3B A graphics multiprocessor 350 is shown according to an additional embodiment. The graphics processor includes multiple sets of execution resources 356A - 356D, where each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load - store units, as Figure 2D and Figure 3A shown. The execution resources 356A - 356D may work in concert with the texture units 360A - 360D for texture operations while sharing an instruction cache 354 and a shared memory 362. In one embodiment, the execution resources 356A - 356D may share the instruction cache 354 and the shared memory 362 as well as multiple instances of texture and / or data cache memories 358A - 358B. The various components may communicate via an interconnect structure 352 similar to Figure 3A the interconnect structure 327.

[0071] Those skilled in the art will understand that Figure 1 、 2AThe architectures described in 2D and 3A-3B are illustrative rather than restrictive with respect to the scope of this embodiment. Thus, without departing from the scope of the embodiments described herein, the techniques described herein may be implemented on any properly configured processing unit, including but not limited to one or more mobile application processors, one or more desktop computer or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (such as the parallel processing unit 202 of FIG. 2), and one or more graphics processors or dedicated processing units.

[0072] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of the manner in which the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0073] Techniques for GPU - to - Host Processor Interconnection

[0074] Figure 4A An exemplary architecture is shown in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 440-443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, depending on the implementation, the high-speed links 440-443 support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the present invention are not limited to any particular communication protocol or throughput.

[0075] Additionally, in one embodiment, two or more of the GPUs 410-413 are interconnected via high-speed links 444-445, which may be implemented using the same or different protocols / links as those used for the high-speed links 440-443. Similarly, two or more of the multi-core processors 405-406 may be connected via a high-speed link 433, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4AAll communication between the various system components shown may be achieved using the same protocol / link (e.g., via a common interconnect structure). However, as mentioned, the fundamental principles of the present invention are not limited to any specific type of interconnect technology.

[0076] In one embodiment, each multi-core processor 405 - 406 is communicatively coupled to a processor memory 401 - 402 via a memory interconnect 430 - 431 respectively, and each GPU 410 - 413 is communicatively coupled to a GPU memory 420 - 423 via a GPU memory interconnect 450 - 453 respectively. The memory interconnects 430 - 431 and 450 - 453 may utilize the same or different memory access technologies. By way of example and not limitation, the processor memories 401 - 402 and the GPU memories 420 - 423 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics double data rate SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using two-level memory (2LM) layering).

[0077] As described below, although the various processors 405 - 406 and GPUs 410 - 413 may be physically coupled to specific memories 401 - 402, 420 - 423 respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as the "effective address" space) is distributed across all individual physical memories. For example, each of the processor memories 401 - 402 may include 64 GB of system memory address space, and each of the GPU memories 420 - 423 may include 32 GB of system memory address space (resulting in a total of 256 GB of addressable memory in this example).

[0078] Figure 4B Additional details of the interconnect between the multi-core processor 407 and the graphics acceleration module 446 are shown in accordance with one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card, and the line card is coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0079] The illustrated processor 407 includes a plurality of cores 460A - 460D, each having a translation lookaside buffer 461A - 461D and one or more caches 462A - 462D. The cores may include various other components for executing instructions and processing data (e.g., instruction fetch unit, branch prediction unit, decoder, execution unit, reorder buffer, etc.), and such other components are not shown to avoid obscuring the fundamental principles of the present invention. The caches 462A - 462D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 426 may be included in the cache hierarchy and shared by multiple sets of cores 460A - 460D. For example, one embodiment of processor 407 includes 24 cores, each having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. Processor 407 and graphics accelerator integration module 446 are connected to system memory 441, which may include processor memories 401 - 402.

[0080] Consistency of data and instructions stored in the various caches 462A - 462D, 456, and system memory 441 is maintained through inter - core communication via coherence bus 464. For example, each cache may have cache coherence logic / circuit associated therewith to communicate via coherence bus 464 in response to a detected read or write to a specific cache line. In one implementation, a cache snooping protocol is implemented via coherence bus 464 to snoop on cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the fundamental principles of the present invention.

[0081] In one embodiment, proxy circuit 425 communicatively couples graphics acceleration module 446 to coherence bus 464, thereby allowing graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the cores. Specifically, interface 435 provides connectivity to proxy circuit 425 via high - speed link 440 (e.g., PCIe bus, NVLink, etc.), and interface 437 connects graphics acceleration module 446 to link 440.

[0082] In one implementation, the accelerator integrated circuit 436 represents multiple graphics processing engines 431, 432, N of the graphics acceleration module 446 to provide cache management, memory access, context management, and interrupt management services. The graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N may include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and block blit engines. In other words, the graphics acceleration module can be a GPU with multiple graphics processing engines 431 - 432, N, or the graphics processing engines 431 - 432, N can be individual GPUs integrated on a common package, line card, or chip.

[0083] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and a memory access protocol for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431 - 432, N. In one embodiment, the data stored in the cache 438 and the graphics memories 433 - 434, N is kept consistent with the core caches 462A - 462D, 456, and the system memory 411. As mentioned, this can be achieved via the proxy circuit 425, which participates in the cache coherence mechanism on behalf of the cache 438 and the memories 433 - 434, N (e.g., sending updates related to modifications / accesses of cache lines on the processor caches 462A - 462D, 456 to the cache 438, and receiving updates from the cache 438).

[0084] A set of registers 445 stores context data for the threads executed by the graphics processing engines 431 - 432, N, and the context management circuit 448 manages the thread contexts. For example, the context management circuit 448 may perform save and restore operations during context switching to save and restore the contexts of various threads (e.g., where the first thread is saved and the second thread is stored so that the second thread can be executed by the graphics processing engine). For example, during context switching, the context management circuit 448 may store the current register values into a region in memory (e.g., identified by a context pointer). Then, it may restore the register values when returning to the context. In one embodiment, the interrupt management circuit 447 receives and processes interrupts received from system devices.

[0085] In one implementation, the MMU 439 converts the virtual / valid addresses from the graphics processing engine 431 into real / physical addresses in the system memory 411. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator modules 446 may be dedicated to a single application executing on the processor 407 or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, in which the resources of the graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). The resources may be further divided into "slices" that are allocated to the VMs and / or applications based on the processing requirements and priorities associated with different VMs and / or applications.

[0086] Thus, the accelerator integrated circuit acts as a bridge to the system of the graphics accelerator modules 446 and provides address translation and system memory cache services. Additionally, the accelerator integrated circuit 436 may provide virtualization facilities for the host processor to manage the virtualization, interrupts, and memory management of the graphics processing engine.

[0087] Since the hardware resources of the graphics processing engines 431-432, N are explicitly mapped to the real address space seen by the host processor 407, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431-432, N such that they appear to the system as independent units.

[0088] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are respectively coupled to each of the graphics processing engines 431-432, N. The graphics memories 433-434, M store the instructions and data being processed by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M may be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D XPoint or Nano-Ram.

[0089] In one embodiment, to reduce data traffic on link 440, a biasing technique is used to ensure that the data stored in graphics memories 433 - 434, M is the data that will be most frequently used by graphics processing engines 431 - 432, N and preferably not used (at least not frequently) by cores 460A - 460D. Similarly, the biasing mechanism attempts to keep the data required by the cores (and preferably not by graphics processing engines 431 - 432, N) in system memory 411 and in caches 462A - 462D, 456 of the cores.

[0090] Figure 4C Another embodiment is shown where accelerator integrated circuit 436 is integrated within processor 407. In this embodiment, graphics processing engines 431 - 432, N communicate directly to accelerator integrated circuit 436 via interface 437 and interface 435 (again, which can utilize any form of bus or interface protocol) over high - speed link 440. Accelerator integrated circuit 436 can perform the same operations as those described with respect to Figure 4B but potentially at a higher throughput considering its close proximity to coherence bus 462 and caches 462A - 462D, 426.

[0091] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter can include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0092] In one embodiment of the dedicated process model, graphics processing engines 431 - 432, N are dedicated to a single application or process under a single operating system. A single application can funnel requests from another application to graphics engines 431 - 432, N, thus providing virtualization within a VM / partition.

[0093] In the dedicated process programming model, graphics processing engines 431 - 432, N can be shared by multiple VM / application partitions. The shared model requires a hypervisor to virtualize graphics processing engines 431 - 432, N to allow access by each operating system. For a non - hypervisor single - partition system, graphics processing engines 431 - 432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431 - 432, N to provide access to each process or application.

[0094] For a shared programming model, the graphics acceleration module 446 or individual graphics processing engines 431 - 432, N use a process handle to select a process element. In one embodiment, the process elements are stored in the system memory 411 and are addressable using the effective address to real address translation techniques described herein. The process handle can be an implementation - specific value provided to the host process when it registers its context with the graphics processing engines 431 - 432, N (i.e., calls system software to add the process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0095] Figure 4D An exemplary accelerator integration slice 490 is shown. As used herein, a "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 436. The application effective address space 482 within the system memory 411 stores process elements 483. In one embodiment, the process elements 483 are stored in response to a GPU call 481 from an application 480 executing on the processor 407. The process element 483 contains the process state of the corresponding application 480. The work descriptor (WD) 484 contained within the process element 483 can be a single job requested by the application or can contain a pointer to a job queue. In the latter case, the WD 484 is a pointer to a job request queue within the application's address space 482.

[0096] The graphics acceleration module 446 and / or individual graphics processing engines 431 - 432, N can be shared by all processes or a subset of processes in the system. Embodiments of the present invention include infrastructure for setting the process state and sending the WD 484 to the graphics acceleration module 446 to start a job in a virtualized environment.

[0097] In one implementation, the dedicated process programming model is implementation - specific. In this model, a single process owns the graphics acceleration module 446 or an individual graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, when the graphics acceleration module 446 is assigned, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition and the operating system initializes the accelerator integrated circuit 436 for the owning process.

[0098] In operation, the WD fetch unit 491 in the accelerator integrated slice 490 fetches the next WD 484, which includes an indication of work to be completed by one of the graphics processing engines of the graphics acceleration module 446. Data from the WD 484 can be stored in the register 445 and used by the MMU 439, interrupt management circuit 447, and / or context management circuit 446 as shown. For example, one embodiment of the MMU 439 includes a segment / page walk circuitry for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can process the interrupt events 492 received from the graphics acceleration module 446. When performing a graphics operation, the MMU 439 converts the effective address 493 generated by the graphics processing engines 431 - 432, N into a real address.

[0099] In one embodiment, the same set of registers 445 is replicated for each of the graphics processing engines 431 - 432, N and / or the graphics acceleration module 446, and it can be initialized by the hypervisor or the operating system. Each of these replicated registers can be included in the accelerator integrated slice 490. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0100] Table 1 - Hypervisor Initialized Registers

[0101] 1 Slice Control Register 2 Real Address (RA) Scheduled Process Region Pointer 3 Permission Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Descriptor Register

[0102] Exemplary registers that can be initialized by the operating system are shown in Table 2.

[0103] Table 2 - Operating System Initialized Registers

[0104] 1 Process and Thread Identification 2 Effective Address (EA) Context Save / Recovery Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Permission Mask 6 Work Descriptor

[0105] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engines 431 - 432, N. It contains all the information required for the graphics processing engines 431 - 432, N to complete their work, or it can be a pointer to a memory location of a command queue where the application has set up work to be done.

[0106] Figure 4E Additional details of an embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 498 in which a list of process elements 499 is stored. The hypervisor real address space 498 can be accessed via the hypervisor 496, which virtualizes the graphics acceleration module engine for the operating system 495.

[0107] The shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time slice sharing and graphics directed shared.

[0108] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. To enable the graphics acceleration module 446 to support virtualization by the hypervisor 496, the graphics acceleration module 446 may comply with the following requirements: 1) The job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The graphics acceleration module 446 is guaranteed to complete the job requests of the application (including any translation faults) within a specified amount of time, or the graphics acceleration module 446 provides the ability to handle preempted jobs. 3) When operating in the directed shared programming model, fairness between processes must be guaranteed for the graphics acceleration module 446.

[0109] In one embodiment, for the shared model, the application 480 needs to make an operating system 495 system call with the graphics acceleration module 446 type, work descriptor (WD), access mask register (AMR) value, and context save / restore area pointer (CSRP). The graphics acceleration module 446 type describes the acceleration function targeted for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is specifically formatted for the graphics acceleration module 446 and can be in the form of a graphics acceleration module 446 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure used to describe the work to be done by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state to be used for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the accelerator integrated circuit 436 and the graphics acceleration module 446 implementation do not support the user access mask override register (UAMOR), then the operating system may apply the current UAMOR value to the AMR value and then pass the AMR in the hypervisor call. Optionally, the hypervisor 496 may apply the current access mask override register (AMOR) value and then place the AMR in the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the valid address of a region in the application's address space 482 for the graphics acceleration module 446 to save and restore the context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. The context save / restore area can be pinned system memory.

[0110] Upon receiving a system call, the operating system 495 may verify that the application 480 is registered and has been granted permission to use the graphics acceleration module 446. The operating system 495 then invokes the hypervisor 496 with the information shown in Table 3.

[0111] Table 3 – OS to Hypervisor Call Parameters

[0112] 1 Work Descriptor (WD) 2 Permission Mask Register (AMR) Value (Potentially Masked) 3 Effective Address (EA) Context Save / Recovery Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0113] Upon receiving a hypervisor call, the hypervisor 496 verifies that the operating system 495 is registered and has been granted permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into the linked list of process elements of the corresponding graphics acceleration module 446 type. The process element may include the information shown in Table 4.

[0114] Table 4 - Process Element Information

[0115] 1 Work Descriptor (WD) 2 Permission Mask Register (AMR) Value (Potentially Masked) 3 Effective Address (EA) Context Save / Recovery Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt Vector Table Derived from Hypervisor Call Parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 12 Storage Descriptor Register (SDR)

[0116] In one embodiment, the hypervisor initializes the registers 445 of the plurality of accelerator integrated slices 490.

[0117] As Figure 4F shown, one embodiment of the present invention employs a unified memory addressable via a common virtual memory address space for accessing the physical processor memories 401 - 402 and the GPU memories 420 - 423. In such an implementation, operations executed on the GPUs 410 - 413 utilize the same virtual / effective memory address space to access the processor memories 401 - 402 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to the processor memory 401, a second portion is allocated to the second processor memory 402, a third portion is allocated to the GPU memory 420, and so on. Thus, the entire virtual / effective memory space (sometimes referred to as the effective address space) is distributed across each of the processor memories 401 - 402 and the GPU memories 420 - 423, allowing any processor or GPU to access any physical memory (using the virtual address mapped to that memory).

[0118] In one embodiment, the bias / coherency management circuits 494A - 494E within one or more of the MMUs 439A - 439E ensure cache coherency between the host processor (e.g., 405) and the caches of the GPUs 410 - 413, and implement a bias technique for the physical memory indicating where certain types of data should be stored. While Figure 4FMultiple instances of bias / coherence management circuits 494A - 494E are shown, but the bias / coherence circuits may be implemented within the MMU of one or more host processors 405 and / or within the accelerator integrated circuit 436.

[0119] One embodiment allows the use of shared virtual memory (SVM) technology to access GPU - attached memories 420 - 423 and map them as part of the system memory without suffering the typical performance penalties associated with full system cache coherence. The ability to access GPU - attached memories 420 - 423 as system memory without heavy cache coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows host processor 405 software to set operands and access computed results without the overhead of traditional I / O DMA data copies. Such traditional copies involve driver calls, interrupts, and memory - mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. At the same time, the ability to access GPU - attached memories 420 - 423 without cache coherence overhead can be critical to the runtime of offloaded computations. In cases with substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410 - 413. The efficiency of operand setting, result access, and GPU computation all play a role in determining the effectiveness of GPU offloading.

[0120] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. A bias table may be used, for example, which can be a page - granularity structure (i.e., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU - attached memory page. The bias table may be implemented in the stolen memory ranges of one or more GPU - attached memories 420 - 423, with or without a bias cache in GPUs 410 - 413 (e.g., for caching frequently / most recently used entries of the bias table). Alternatively, the entire bias table may be maintained within the GPU.

[0121] In one implementation, the bias table entries associated with each access to the GPU-attached memories 420-423 are accessed before actually accessing the GPU memory, thereby causing the following operations. First, local requests from the GPUs 410-413 that look for their pages in the host bias are directly forwarded to the corresponding GPU memories 420-423. Local requests from the GPUs are forwarded to the processor 405 (e.g., via the high-speed link as discussed above). In one embodiment, a request from the processor 405 (which looks for the requested page in the host processor bias) completes a request similar to a normal memory read. Alternatively, a request for a page in the GPU bias can be forwarded to the GPUs 410-413. Then, if the GPU is not currently using the page, the GPU can transition the page to the host processor bias.

[0122] The bias state of a page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or a purely hardware-based mechanism for a limited set of cases.

[0123] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the device driver of the GPU, which in turn sends a message (or enqueues a command descriptor) to the GPU to direct it to change the bias state and perform a cache dump flush operation in the host for some transitions. The cache dump flush operation is required for transitioning from the host processor 405 bias to the GPU bias, but not for the reverse transition.

[0124] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that are not cacheable by the host processor 405. To access these pages, the processor 405 can request access from the GPU 410, which may or may not immediately grant access depending on the implementation. Therefore, to reduce communication between the processor 405 and the GPU 410, ensure that the GPU bias pages are those that are needed by the GPU but not by the host processor 405 and vice versa.

[0125] Graphics Processing Pipeline

[0126] Figure 5 Illustrates a graphics processing pipeline 500 according to an embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included within a parallel processing subsystem as described herein (such as the parallel processor 200 of FIG. 2), which in one embodiment is Figure 1Variants of the (one or more) parallel processors 112. Various parallel processing systems may implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., the parallel processing unit 202 of FIG. 2) as described herein. For example, shader units (e.g., the graphics multiprocessor 234 of FIG. 3) may be configured to perform the functions of one or more of the vertex processing unit 504, the tessellation control processing unit 508, the tessellation evaluation processing unit 512, the geometry processing unit 516, and the fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be performed by other processing engines and corresponding partitioning units (e.g., the partitioning units 220A - 220N of FIG. 2) within a processing cluster (e.g., the processing cluster 214 of FIG. 3). The graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general - purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on - chip memory (e.g., the parallel processor memory 222 as in FIG. 2) via a memory interface 528, which may be an instance of the memory interface 218 of FIG. 2.

[0127] In one embodiment, the data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. The data assembler 502 then outputs the vertex data, including vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes a vertex shader program to light and transform the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in a cache, local, or system memory for use in processing the vertex data, and the vertex processing unit 504 may be programmed to transform the vertex data from an object - based coordinate representation to a world - space coordinate space or a normalized device coordinate space.

[0128] A first instance of the primitive assembler 506 receives vertex attributes from the vertex processing unit 504. The primitive assembler 506 reads stored vertex attributes as needed and constructs graphics primitives for processing by the tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0129] The tessellation control processing unit 508 treats the input vertices as control points for geometric patches. The control points are transformed from an input representation from a patch (e.g., the basis of the patch) to a representation suitable for use by the tessellation evaluation processing unit 512 in surface evaluation. The tessellation control processing unit 508 may also compute tessellation factors for the edges of the geometric patch. The tessellation factors are applied to individual edges and quantify the view-dependent level of detail associated with that edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and to tessellate the patch surface into a plurality of geometric primitives such as line, triangle, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0130] A second instance of the primitive assembler 514 receives vertex attributes from the tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphics primitives received from the primitive assembler 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide the graphics primitive into one or more new graphics primitives and to compute parameters for rasterizing the new graphics primitives.

[0131] In some embodiments, the geometry processing unit 516 may add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying the new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for use in processing geometric data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling and outputs the processed graphics primitives to the rasterizer 522.

[0132] The rasterizer 522 may perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 may be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels output to the raster operations unit 526. The fragment / pixel processing unit 524 may read data stored in the parallel processor memory or the system memory for use in processing fragment data. The fragment or pixel shader program may be configured to shade at the sample, pixel, tile, or other granularity (depending on the sampling rate configured for the processing unit).

[0133] The raster operations unit 526 is a processing unit that performs raster operations including but not limited to stencil printing, z-testing, blending, and the like, and outputs pixel data as processed graphics data to be stored in the graphics memory (e.g., the parallel processor memory 222 as shown in FIG. 2 and / or the system memory 104 as shown in Figure 1 ), for display on the one or more display devices 110 or for further processing by one of the (one or more) parallel processors 112 or the one or more processors 102. In some embodiments, the raster operations unit 526 is configured to compress z or color data written to the memory and decompress z or color data read from the memory.

[0134] Topology Shader Techniques

[0135] Now turning to Figure 6, shows a graphics pipeline 600, where a topology shader 602 receives an object description 604 from, for example, a host processor (e.g., a central processing unit / CPU), an application programming interface (API), a driver, etc. The object description 604 may contain general information about the type of object to be rendered (e.g., a sphere with a determined center and radius, a person with a determined skeleton shape, etc.) without specifying the topology of the object to be displayed. The topology shader 602 may receive the object description 604, generate a set of polygons 606 (e.g., triangles, primitives) based on the object description, and send the set of polygons 606 to a vertex shader 608 ("VS"). Thus, the topology shader 602 can determine the appropriate topology of the outer surface of a sphere given only the center coordinates and radius of the sphere. Similarly, the topology shader 602 can determine the appropriate topology of the skin of a person / character given only the skeleton shape and depth of the person / character in the scene.

[0136] As will be discussed in more detail, the generation of the set of polygons 606 may involve detecting the lack of visibility conditions with respect to one or more polygons and excluding polygons sent from the set of polygons 606 to the VS 608. The lack of visibility conditions may include, for example: occlusion state (e.g., in a three-dimensional / 3D scene, a polygon is behind another polygon), off-screen state (e.g., a polygon is outside the viewport), etc. Generating the set of polygons 606 may also involve determining a level of detail (LOD) associated with the object description based on depth information (e.g., the z coordinate of the sphere center). The depth information may be obtained from one or more visibility samples associated with the polygon and / or the object description.

[0137] Regarding LOD, the topological data of the scene can be subdivided into an octree data structure, where each internal node has eight child nodes (e.g., partitioning the 3D space / model by recursively subdividing the 3D space / model into eight octants). In such cases, the topology shader 602 may be called for an identified sub-octree (e.g., LOD). Enabling the graphics pipeline 600 to determine the topology of the object being rendered can increase flexibility (e.g., through variable topology), improve efficiency, enhance performance, and reduce power consumption by reducing the number of memory transactions associated with transferring topological data from the host processor to the graphics pipeline 600.

[0138] The vertex shader 608 can process the vertices of the set of polygons 606 by performing operations such as transformation, skinning, and lighting. The vertex shader 608 can produce the same number of vertices that it takes as input. Additionally, the hull shader 610 ("HS") can process control points that define lower-order surfaces such as lines, triangles, or quadrilaterals. As output, the HS 610 can produce higher-order geometry "patches" and patch constants, which are passed to the fixed-function tessellator 612. The tessellator 612 can preprocess the domain represented by the output of the HS 610. As output, the tessellator 612 can create a sampling pattern for the domain and a set of small primitives (e.g., points, lines, triangles) that connect the samples. The illustrated pipeline 600 also includes a domain shader 614 ("DS"), which processes the higher-order geometry patches from the HS 610 along with the tessellation factors from the tessellator 612. The tessellation factors can include both the tessellator input factors and the output factors. As output, the DS 614 can compute the vertex positions of points on the output patches that conform to the tessellation factors.

[0139] Additionally, the geometry shader 616 ("GS") can process entire primitives (e.g., points, lines, or triangles) along with optional vertex data for edge-adjacent primitives. Unlike the VS 608, the GS 616 can produce more or fewer primitives than it takes as input. The pipeline 600 can also include a pixel shader 618 ("PS"), which processes rasterized primitives along with interpolated vertex data to generate per-pixel values (such as color and depth). The illustrated pipeline 600 thus does not rely solely on the tessellator 612 to generate a surface representation of the scene to be rendered.

[0140] Figure 7 Illustrated is what can be done by a topology shader 602 such as those already discussed ( Figure 6LOD analysis processed by a topological shader as described in (). In the illustrated example, at a relatively high LOD (e.g., a high-fidelity topology including a relatively large number of polygons), a sphere is represented at the first level 700 of the octree ("level_0"). If the sphere has, for example, a short distance to the camera and / or the user (e.g., a foreground object), the first level 700 can be selected. In contrast, the second level 702 of the octree ("level_1") can represent the sphere at an intermediate LOD (e.g., including an intermediate number of polygons). Thus, if the sphere has, for example, an intermediate distance to the camera and / or the user, the second level 702 can be selected. Additionally, the sphere can be represented at a relatively low LOD (e.g., a low-fidelity topology including a relatively small number of polygons) at the third level 704 ("level_2"). If the sphere has, for example, a long distance to the camera and / or the user (e.g., a background object), the third level 704 can be selected. The topological shader can thus be invoked mainly based on depth information in the selected sub-octree. As already noted, the topological shader can determine the appropriate LOD based on the restricted / basic information in the object description.

[0141] Determining the LOD can also involve interpolation between two LODs. For example, the object description can indicate support for the three illustrated levels 700, 702, 704, where the topological shader selects a level between the first level 700 and the second level 702 based on the distance of the sphere to the camera / user. In such cases, the selected LOD can include more polygons compared to the second level 702 and fewer polygons compared to the first level 700 in proportion to the actual distance.

[0142] Figure 8 The field of view 800 relative to the scene to be rendered is shown. In the illustrated example, an object 802 (e.g., a sphere) in the scene is only partially within the field of view. In such cases, since one or more polygons 804 of the object 802 are outside the field of view 800 (e.g., in an "off-screen state"), one or more polygons 804 of the object 802 can be considered to lack visibility conditions. Similarly, even if one or more other polygons 806 are within the field of view 800, but they are occluded by polygons closer to the camera / user, so one or more other polygons 806 can be considered to lack visibility conditions. Again, the topological shader can detect the lack of visibility conditions based on, for example, the restricted / basic information in the object description obtained from the host processor.

[0143] Figure 9ADisclosed is a method 900 for operating a semiconductor packaging device. The method 900 can be implemented as one or more modules in a set of logical instructions stored in a non-transitory machine or computer-readable storage medium, such as random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc.; stored in configurable logic, such as, for example, a programmable logic array (PLA), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD); stored in fixed-functional hardware logic using circuit technologies, such as, for example, an application-specific integrated circuit (ASIC), complementary metal oxide semiconductor (CMOS), or transistor-transistor logic (TTL) technology, or any combination thereof.

[0144] For example, the computer program code for implementing the operations shown in the method 900 can be written in any combination of one or more programming languages, the one or more programming languages including object-oriented programming languages, such as JAVA, SMALLTALK, C++, or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. In addition, the logical instructions can include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, status setting data, configuration data for integrated circuits, state information of personalized electronic circuits and / or other structural components native to hardware (such as host processors, central processing units / CPUs, microcontrollers, etc.).

[0145] The illustrated processing block 902 receives an object description in a topology shader. The object description can provide a general description of the object without describing or specifying the topology of the object. Block 904 can generate a set of polygons in the topology shader based on the object description, and the set of polygons can be sent to a vertex shader at block 906.

[0146] Figure 9B Disclosed is a method 910 for generating a set of polygons. The method 910 can thus generally be incorporated into block 904 ( Figure 9A ) already discussed. More specifically, the method 910 can be implemented as one or more modules in a set of logical instructions stored in a non-transitory machine or computer-readable storage medium, such as RAM, ROM, PROM, firmware, flash memory, etc.; stored in configurable logic, such as, for example, PLA, FPGA, CPLD; stored in fixed-functional hardware logic using circuit technologies, such as, for example, ASIC, CMOS, or TTL technology, or any combination thereof.

[0147] The illustrated processing block 912 determines a level of detail associated with an object description based on depth information. Block 912 may, for example, include identifying a sub-octree corresponding to the object description, where a topology shader is invoked for the identified sub-octree. As already discussed, determining the level of detail may also involve interpolating between two levels of detail. The lack of a visibility condition may be detected in block 914 with respect to one or more polygons, where the (one or more) polygons may be excluded from the set of polygons in block 916 in response to the lack of the visibility condition. The lack of a visibility condition may include, for example, a culling state, an off-screen state, etc., or any combination thereof.

[0148] Figure 10A A computing system 100 showing performance improvement. In the illustrated example, the host processor 1002 includes an integrated memory controller (IMC) 1004 that communicates with a system memory 1006 (e.g., DRAM). The host processor 1002 may be coupled to a graphics processor 1008 and an input / output (IO) module 1010 that may include a graphics pipeline 1016. The illustrated graphics processor 1008 is also coupled to a dedicated graphics memory 1022. The IO module 1010 may be coupled to a network controller 1012 (e.g., wireless and / or wired), a display 1014 (e.g., a fixed or head-mounted liquid crystal display / LCD, a light-emitting diode / LED display, etc., for visually presenting video of a 3D scene), and a mass storage device 1018 (e.g., flash memory, an optical disk, a solid state drive / SSD).

[0149] The system memory 1006 and / or the mass storage device 1018 may include instructions 1020 that, when executed by the host processor 1002, cause the host processor 1002 to generate an object description associated with visual content to be presented by the display 1014. Additionally, the graphics pipeline 1016 of the graphics processor 1008 may include a topology shader that performs one or more aspects of method 900 ( Figure 9A ), and / or method 910 ( Figure 9B ). Thus, the graphics pipeline 1016 may be configured to receive an object description at the topology shader, generate a set of polygons at the topology shader based on the object description, and send the set of polygons to a vertex shader. The illustrated solution thus reduces the number of memory transfers between the system memory 1006 / mass memory 1018 and the graphics memory 1022. Thus, higher efficiency and performance may be achieved while improving quality in the system 1000.

[0150] Figure 10BA semiconductor package device 1030 (e.g., a chip) is shown that includes a substrate 1032 (e.g., silicon, sapphire, gallium arsenide) and logic 1034 (1034a - 1034c, e.g., a transistor array and other integrated circuit / IC components) coupled to the substrate 1032. The logic 1034, which can be implemented in configurable logic and / or fixed - functional logic hardware, includes a graphics processor 1034a, a host processor 1034b, and an IO module 1034c. The logic 1034 can generally implement one or more aspects of method 900 ( Figure 9A ), and / or method 910 ( Figure 9B ). Thus, the logic 1034 can receive an object description at a topology shader (e.g., of a graphics pipeline), generate a set of polygons at the topology shader based on the object description, and send the set of polygons to a vertex shader.

[0151] In one example, the logic 1034 detects a lack of visibility conditions (e.g., culling state, off - screen state) with respect to one or more polygons and excludes the one or more polygons from the set of polygons in response to the lack of visibility conditions. Additionally, the logic 1034 can be configured to determine a level of detail associated with an object description, e.g., by identifying a sub - octree corresponding to the object description. The logic 1034 can also interpolate between two levels of detail.

[0152] Head - Mounted Display System Overview

[0153] Figure 11 A head - mounted display (HMD) system 1100 being worn by a user while experiencing an immersive environment is shown, the immersive environment such as, for example, a virtual reality (VR) environment, an augmented reality (AR) environment, a multi - player three - dimensional (3D) game, etc. In the example shown, one or more straps 1120 hold the frame 1102 of the HMD system 1100 in front of the user's eyes. Accordingly, a left - eye display 1104 is positioned to be viewed by the user's left eye and a right - eye display 1106 is positioned to be viewed by the user's right eye. In some examples, such as a smart phone worn by the user, the left - eye display 1104 and the right - eye display 1106 can alternatively be integrated into a single display. In the case of AR, the displays 1104, 1106 can be see - through displays that allow the user to view the physical environment while other rendered content (e.g., virtual characters, informational annotations, heads - up display / HUD) is presented above a live feed of the physical environment.

[0154] In one example, the frame 1102 includes a left-look-down camera 1108 to capture images (e.g., left hand gestures) from an area generally located in front of the user and below the left eye. Additionally, a right-look-down camera 1110 can capture images from an area generally located in front of the user and below the right eye (e.g., right hand gestures). The illustrated frame 1102 also includes a left-front-look camera 1112 and a right-front-look camera 1114 to capture images in front of the user's left and right eyes, respectively. The frame 1102 can also include a left-side-look camera 1116 to capture images from an area to the left of the user and a right-side-look camera 1118 to capture images from an area to the right of the user.

[0155] Images captured by the cameras 1108, 1110, 1112, 1114, 1116, 1118, which may have overlapping fields of view, can be used to detect gestures made by the user and to analyze and / or reproduce the external environment on the displays 1104, 1106. In one example, the detected gestures are used by a (e.g., internal and / or external) graphics processing architecture to render and / or control the virtual representation of the user in a 3D game. In fact, the overlapping fields of view can enable the capture of gestures made by other individuals (e.g., in a multi-player game), where the gestures of the other individuals can also be used to render / control the immersive experience. The overlapping fields of view can also enable the HMD system 1100 to automatically detect obstructions or other hazards near the user. Such methods are particularly advantageous in advanced driver assistance system (ADAS) applications.

[0156] In one example, the left-look-down camera 1108 and the right-look-down camera 1110 with overlapping fields of view provide a stereoscopic view with increased resolution. The increased resolution can in turn enable very similar user movements to be distinguished from each other (e.g., with sub-millimeter accuracy). The result can be improved performance of the HMD system 1100 in terms of reliability. In fact, the illustrated solution is useful in a variety of applications such as, for example, coloring information in an AR setting, exchanging virtual tools / devices between users in a multi-user environment, rendering virtual items (e.g., weapons, swords, people), etc. The gestures of other objects, limbs, and / or body parts can also be detected and used to render / control the virtual environment. For example, signals such as myelogram signals, electroencephalogram signals, eye tracking, breathing or panting, hand movements, etc., can be tracked in real time, whether from the wearer or from another individual in the shared environment. The images captured by the cameras 1108, 1110, 1112, 1114, 1116, 1118 can also be used as context input. For example, it may be determined that the user is indicating a specific word to be edited or a specific key to be pressed in a word processing application, a specific weapon to be deployed or a direction of travel in a game, etc.

[0157] In addition, images captured by cameras 1108, 1110, 1112, 1114, 1116, 1118 can be used to implement shared communication or networked interaction in equipment operation, medical training, and / or remote / telestration applications. A task-specific pose library or neural network machine learning can enable tool identification and feedback on tasks. For example, virtual tools that can be converted into remote, real actions can be enabled. In yet another example, the HMD system 1100 converts the manipulation of a virtual drill bit within a virtual scene into the remote operation of a drill bit on a robotic device deployed to search for collapsed buildings. Moreover, the HMD system 1100 can be programmable to the extent that it includes, for example, a protocol that enables a user to add new poses to a list of identifiable poses associated with the user's actions.

[0158] In addition, the various cameras in the HMD 1100 can be configurable to detect spectral frequencies outside the visible wavelengths of the spectrum. The multispectral imaging capabilities in the input cameras allow for the tracking of the position of the user and / or object by eliminating non-essential image features (e.g., background noise). For example, in an augmented reality (AR) application such as surgery, instruments and equipment can be tracked by their infrared reflectivity without the need for additional tracking aids. Moreover, the HMD 1100 can be employed in low visibility situations where the "live feeds" from the various cameras can be enhanced or augmented by computer analysis and presented to the user as visual or audio cues.

[0159] The HMD system 1100 can also forego performing any type of data communication with a remote computing system or that requires a power line (e.g., stand-alone operation mode). In this regard, the HMD system 1100 can be a "cordless" device having a power unit that enables the HMD system 1100 to operate independently of an external power system. Accordingly, a user can play full-featured games without being tethered to another device (e.g., a game console) or power supply. In a word processing example, the HMD system 1100 presents a virtual keyboard and / or virtual mouse on the displays 1104 and 1106 to provide a virtual desktop or word processing scenario. Thus, the pose recognition data captured by one or more of the cameras can represent user typing activities on the virtual keyboard or the movement of the virtual mouse. Advantages include, but are not limited to: portability and the comfort of the virtual desktop isolating the privacy of nearby individuals. The underlying graphics processing architecture can support the compression and / or decompression of video and audio signals. Moreover, providing separate images to the user's left and right eyes can facilitate the rendering, generation, and / or perception of 3D scenes. The relative positions of the left-eye display 1104 and the right-eye display 1106 can also be adjustable to match variations in the interocular spacing between different users.

[0160] Figure 11The number of cameras shown is for discussion purposes only. In fact, depending on the environment, the HMD system 1100 may include fewer than six or more than six cameras.

[0161] Functional Components of the HMD System

[0162] Figure 12 The HMD system is shown in more detail. In the example shown, the frame 1102 includes a power unit 1200 (e.g., battery power, adapter) that supplies power to the HMD system. The frame 1102 shown also includes a motion tracking module 1220 (e.g., accelerometer, gyroscope), where the motion tracking module 1220 provides motion tracking data, orientation data, and / or position data to the processor system 1204. The processor system 1204 may include a network adapter 1224 coupled to an I / O bridge 1206. The I / O bridge 1206 enables communication between the network adapter 1224 and various components such as, for example, an audio input module 1210, an audio output module 1208, a display device 1207, an input camera 1202, and so on.

[0163] In the example shown, the audio input module 1210 includes a right audio input 1218 and a left audio input 1216, which detect sounds that can be processed to identify voice commands of the user and nearby individuals. The voice commands identified in the captured audio signal can enhance gesture recognition during mode switching and other applications. Moreover, the captured audio signal can provide 3D information used to enhance the immersive experience.

[0164] The audio output module 1208 may include a right audio output 1214 and a left audio output 1212. The audio output module 1208 can deliver sound to the ears of the user and / or other nearby individuals. The audio output module 1208 can be in the form of earbuds, on-ear speakers, over-ear speakers, speakers, etc. or any combination thereof, and the audio output module 1208 can deliver stereo and / or 3D audio content to the user (e.g., spatial localization). The frame 1102 shown also includes a wireless module 1222, which can facilitate communication between the HMD system and various other systems (e.g., computers, wearable devices, game consoles). In one example, the wireless module 1222 communicates with the processor system 1204 via the network adapter 1224.

[0165] The display device 1207 shown includes a left-eye display 1104 and a right-eye display 1106, where the visual content presented on the displays 1104, 1106 can be obtained from the processor system 1204 via the I / O bridge 1206. The input cameras 1202 may include the left-looking camera 1116, right-looking camera 1118, lower-left-looking camera 1108, front-left-looking camera 1112, front-right-looking camera 1114, and lower-right-looking camera 1110 that have been discussed.

[0166] Turning now to Figure 13 , a general processing cluster (GPC) 1300 is shown. The GPC 1300 shown may be incorporated into a processing system such as, for example, the processor system 1204 ( Figure 12 ). The GPC 1300 may include a pipeline manager 1302 that communicates with a scheduler. In one example, the pipeline manager 1302 receives tasks from the scheduler and distributes the tasks to one or more streaming multiprocessors (SMs) 1304. Each SM 1304 may be configured to process a thread group, where a thread group may be considered multiple related threads that perform the same or similar operations on different input data. Thus, each thread in the thread group may be assigned to a specific SM 1304. In another example, the number of threads may be greater than the number of execution units in the SM 1304. In this regard, the threads in the thread group may operate in parallel. The pipeline manager 1302 may also specify the destination of the processed data to a work distribution crossbar 1308 that communicates with a memory crossbar.

[0167] Thus, when each SM 1304 transfers the processed task to the work distribution crossbar 1308, the processed task may be provided to another GPC 1300 for further processing. The output of the SM 1304 may also be sent to a pre-raster operation (preROP) unit 1314 that in turn directs the data to one or more raster operation units or performs other operations (e.g., performing address translation, organizing picture color data, blending colors, etc.). The SM 1304 may include an internal level-one (L1) cache (not shown) in which the SM 1304 may store data. The SM 1304 may also have access to a one-and-a-half-level (L1.5) cache 1306 and to a level-two (L2) cache (not shown) via a memory management unit (MMU) 1310. The MMU 1310 may map virtual addresses to physical addresses. In this regard, the MMU 1310 may include page table entries (PTEs) that are used to map virtual addresses to the physical addresses of tiles, memory pages, and / or cache line indices. The GPU 1300 shown also includes a texture unit 1312.

[0168] Graphics Pipeline Architecture

[0169] Now turning to Figure 14 , a graphics pipeline 1400 is shown. In the example shown, the world space pipeline 1420 includes a primitive distributor (PD) 1402. The PD 1402 can collect vertex data associated with high-level services, graphics primitives, triangles, etc., and transmit the vertex data to a vertex attribute fetcher (VAF) 1404. The VAF 1404 can retrieve the vertex attributes associated with each incoming vertex from shared memory and store the vertex data and the associated vertex attributes together in the shared memory.

[0170] The world space pipeline 1420 shown also includes a vertex, tessellation, geometry processing unit (VTG) 1406. The VTG 1406 can include, for example, a vertex processing unit, a tessellation initialization processing unit, a task distributor, a task generator, a topology generator, a geometry processing unit, a tessellation processing unit, etc. or any combination thereof. In one example, the VTG 1406 is a programmable execution unit configured to execute geometry programs, tessellation programs, and vertex shader programs. The programs executed by the VTG 1406 can process the vertex data and vertex attributes received from the VAF 1404. Moreover, the programs executed by the VTG 1406 can generate graphics primitives, color values, surface normal factors, and transparency values at each vertex of the graphics primitives for further processing within the graphics processing pipeline 1400.

[0171] The vertex processing unit of the VTG 1406 can be a programmable execution unit that executes a vertex shader program to lighten and transform the vertex data as specified by the vertex shader program. For example, the vertex processing unit can be programmed to transform the vertex data from an object-based coordinate representation (e.g., object space) to an alternative coordinate system such as world space or normalized device coordinate (NDC) space. In addition, the vertex processing unit can read the vertex data and vertex attributes stored in the shared memory by the VAF 1404 and process the vertex data and vertex attributes. In one example, the vertex processing unit stores the processed vertices in the shared memory.

[0172] The tessellation initialization processing unit (e.g., hull shader, tessellation control shader) can execute a tessellation initialization shader program. In one example, the tessellation initialization processing unit processes vertices generated by the vertex processing unit and generates graphics primitives sometimes referred to as "patches". The tessellation initialization processing unit can also generate various patch attributes, where the patch data and patch attributes are stored in shared memory. The task generation unit of the VTG 1406 can retrieve the data and attributes of vertices and patches from the shared memory. In one example, the task generation unit generates tasks for processing vertices and patches for later stages in the graphics processing pipeline 1400.

[0173] Tasks generated by the task generation unit can be redistributed by the task distributor of the VTG 1406. For example, tasks generated by various instances of the vertex shader program and the tessellation initialization program can vary significantly between one graphics processing pipeline 1400 and another. Accordingly, the task distributor can redistribute these tasks so that each graphics processing pipeline 1400 has an almost equal workload during later pipeline stages.

[0174] As already noted, the VTG 1406 can also include a topology generation unit. In one example, the topology generation unit retrieves the tasks distributed by the task distributor, indexes the vertices including those associated with the patches, and calculates the coordinates (UV) of the tessellation vertices and the indices that connect the tessellation vertices to form graphics primitives. The indexed vertices can be stored in the shared memory by the topology generation unit. The tessellation processing unit of the VTG 1406 can be configured to execute a tessellation shader program (e.g., domain shader, tessellation evaluation shader). The tessellation processing unit can read input data from the shared memory and write output data to the shared memory. The output data can be passed from the shared memory to the geometry processing unit (e.g., the next shader stage) as input data.

[0175] The geometry processing unit of the VTG 1406 can execute a geometry shader program to transform graphics primitives (e.g., triangles, line segments, points, etc.). In one example, vertices are grouped to construct graphics primitives, where the geometry processing unit divides the graphics primitives into one or more new graphics primitives. The geometry processing unit can also compute parameters that can be used to rasterize the new graphics primitives, such as, for example, plane equation coefficients.

[0176] The world space pipeline 1420 shown also includes a viewport scaling, culling, and clipping unit (VPC) 1408 that receives parameters and vertices specifying new graphical primitives from the VTG 1406. In one example, the VPC 1408 performs clipping, flanging, perspective correction, and viewport transformation to identify graphical primitives that are potentially visible in the final rendered image. The VPC 1408 may also identify graphical primitives that may not be visible.

[0177] The graphics processing pipeline 1400 may also include a tiling unit 1410 coupled to the world space pipeline 1420. The tiling unit 1410 may be a graphical primitive classification engine where graphical primitives are processed in the world space pipeline 1420 and then transmitted to the tiling unit 1410. In this regard, the graphics processing pipeline 1400 may also include a screen space pipeline 1422 where the screen space may be divided into cache tiles. Each cache tile may thus be associated with a portion of the screen space. For each graphical primitive, the tiling unit 1410 may identify a set of cache tiles that intersect (e.g., "tile") the graphical primitive. After tiling multiple graphical primitives, the tiling unit 1410 may process the graphical primitives tile by cache tile. In one example, the graphical primitives associated with a particular cache tile are transmitted one tile at a time to a setup unit 1412 in the screen space pipeline 1422. Graphical primitives that intersect multiple cache tiles may be processed once in the world space pipeline 1420 and transmitted to the screen space pipeline 1422 multiple times.

[0178] In one example, the setup unit 1412 receives vertex data from the VPC 1408 via the tiling unit 1410 and computes parameters associated with the graphical primitive. The parameters may include, for example, edge equations, bias plane equations, and depth plane equations. The screen space pipeline 1422 may also include a rasterizer 1414 coupled to the setup unit 1412. The rasterizer may scan convert new graphical primitives and transmit fragment and coverage data to a pixel shader unit (PS) 1416. The rasterizer 1414 may also perform Z culling and other Z-based optimizations.

[0179] The PS 1416, which has access to shared memory, may execute a fragment shader program that transforms the fragments received from the rasterizer 1414. More specifically, the fragment shader program may shade the fragments at a pixel-level granularity (e.g., operate as a pixel shader program). In another example, the fragment shader program shades the fragments at a sample-level granularity where each pixel includes multiple samples and each sample represents a portion of the pixel. Also, depending on the environment (e.g., sampling rate), the fragment shader program may shade the fragments at any other granularity. The PS 1416 may perform blending, shading, perspective correction, texture mapping, etc. to generate shaded fragments.

[0180] The screen space pipeline 1422 shown also includes a raster operation unit (ROP) 1418, which can perform operations such as stencil printing, Z-testing, blending, and so on. The ROP 1418 can then transfer pixel data as processed graphics data to one or more rendered targets (e.g., graphics memory). The ROP 1418 can be configured to compress Z or color data written to memory and decompress Z or color data read from memory. The location of the ROP 1418 can vary depending on the environment.

[0181] The graphics processing pipeline 1400 can be implemented by one or more processing elements. For example, the VTG 1406 and / or the PS 1416 can be implemented in one or more SMs, and the PD 1402, VAF 1404, VPC 1408, tile unit 1410, setup unit 1412, rasterizer 1414, and / or the ROP 1418 can be implemented in the processing elements of a specific GPC along with the corresponding partition units. The graphics processing pipeline 1400 can also be implemented in fixed functional hardware logic. In fact, the graphics processing pipeline 1400 can be implemented in a PPU.

[0182] Thus, the world space pipeline 1420 shown processes graphical objects in 3D space, where the position of each graphical object relative to other graphical objects and relative to the 3D coordinate system is known. In contrast, the screen space pipeline 1422 can process graphical objects that have been projected from the 3D coordinate system onto a 2D planar surface representing the surface of a display device. Additionally, the world space pipeline 1420 can be divided into an alpha stage pipeline and a beta stage pipeline, where the alpha stage pipeline includes the pipeline stages from the PD 1402 until the task generation unit. The beta stage pipeline can include the pipeline stages from the topology generation unit until the VPC 1408. In such cases, the graphics processing pipeline 1400 can perform a first set of operations (e.g., a single thread, a thread group, multiple thread groups acting in concert) in the alpha stage pipeline and a second set of operations (e.g., a single thread, a thread group, multiple thread groups acting in concert) in the beta stage pipeline.

[0183] If multiple graphics processing pipelines 1400 are in use, the vertex data and vertex attributes associated with a set of graphics objects can be partitioned such that each graphics processing pipeline 1400 has a similar workload throughout the alpha stage. Accordingly, the alpha stage processing can substantially expand the number of vertex data and vertex attributes such that the number of vertex data and vertex attributes generated by the task generation unit is significantly greater than the number of vertex data and vertex attributes processed by the PD 1402 and VAF 1404. Moreover, even when starting the alpha stage with the same number of attributes, task generation units associated with different graphics processing pipelines 1400 can generate vertex data and vertex attributes with different levels of quality. In such cases, the task distributor can redistribute the attributes generated by the alpha stage pipelines such that each graphics processing pipeline 1400 has a substantially equal workload at the start of the beta stage pipeline.

[0184] Turning now to Figure 15 , a streaming multiprocessor (SM) 1500 is shown. The illustrated SM 1500 includes K scheduler units 1504 coupled to an instruction cache 1502, where each scheduler unit 1504 receives an array of thread blocks from a pipeline manager (not shown) and manages the instruction scheduling for one or more thread blocks in each active array of thread blocks. The scheduler units 1504 can schedule threads for execution in groups of parallel threads, where each group can be referred to as a "warp". Thus, each warp may include, for example, sixty-four threads. Additionally, the scheduler units 1504 can manage multiple different thread blocks, allocating the thread blocks to warps for execution. The scheduler units can then schedule instructions from multiple different warps on various functional units during each clock cycle. Each scheduler unit 1504 can include one or more instruction dispatch units 1522, where each dispatch unit 1522 transmits instructions to one or more of the functional units. The number of dispatch units 1522 can vary depending on the environment. In the illustrated example, the scheduler unit 1504 includes two dispatch units 1522 that enable two different instructions from the same warp to be dispatched during each clock cycle.

[0185] The SM 1500 may also include a register file 1506. The register file 1506 may include a set of registers that are partitioned among the functional units such that each functional unit is assigned a dedicated portion of the register file 1506. The register file 1506 may also be partitioned among different warps being executed by the SM 1500. In one example, the register file 1506 provides temporary storage for operands of data paths connected to the functional units. The illustrated SM 1500 also includes L processing cores 1508, where L may be a relatively large number (e.g., 192). Each core 1508 may be a single-precision processing unit including a pipelined floating-point arithmetic logic unit (e.g., IEEE 754-2008) and an integer arithmetic logic unit.

[0186] The illustrated SM 1500 also includes M double-precision units (DPUs) 1510, N special function units (SFUs) 1512, and P load / store units (LSUs) 1514. Each DPU 1510 may implement double-precision floating-point arithmetic and each SFU 1512 may perform special functions such as, for example, rectangle copy pixel blend. Additionally, each LSU 1514 may perform load and store operations between the shared memory 1518 and the register file 1506. In one example, the load and store operations are performed via J texture units / L1 caches 1520 and an interconnect network 1516. In one example, the J texture units / L1 caches 1520 are also coupled to a crossbar (not shown). Thus, the interconnect network 1516 may connect each of the functional units to the register file 1506 and the shared memory 1518. In one example, the interconnect network 1516 acts as a crossbar connecting any of the functional units to any register in the register file 1506.

[0187] The SM 1500 may be implemented within a graphics processor (e.g., a graphics processing unit / GPU), where the texture unit / L1 cache 1520 may access texture maps from memory and sample the texture maps to produce sampled texture values for use in shader programs. Texture operations performed by the texture unit / L1 cache 1520 include, but are not limited to, mipmap-based anti-aliasing.

[0188] Additional System Overview Example

[0189] Figure 16is a block diagram of a processing system 1600 according to an embodiment. In various embodiments, system 1600 includes one or more processors 1602 and one or more graphics processors 1608, and can be a server system with a large number of processors 1602 or processor cores 1607, a single-processor desktop system, or a multi-processor workstation system. In one embodiment, system 1600 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0190] Embodiments of system 1600 may include or may be incorporated within the following: server-based game platforms, game consoles (including game and media consoles, mobile game consoles, handheld game consoles, or online game consoles). In some embodiments, system 1600 is a mobile phone, smartphone, tablet computing device, or mobile Internet device. Data processing system 1600 may also include, be coupled to, or be integrated within the following: wearable devices, such as smartwatch wearable devices, smart eyewear devices, augmented reality devices, or virtual reality devices. In some embodiments, data processing system 1600 is a television or set-top box device having one or more processors 1602 and a graphical interface generated by one or more graphics processors 1608.

[0191] In some embodiments, each of the one or more processors 1602 includes one or more processor cores 1607 for processing instructions that, when executed, perform the operations of system and user software. In some embodiments, each of the one or more processor cores 1607 is configured to process a particular instruction set 1609. In some embodiments, instruction set 1609 may facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 1607 may each process a different instruction set 1609, which may include instructions for facilitating the emulation of other instruction sets. Processor cores 1607 may also include other processing devices, such as digital signal processors (DSPs).

[0192] In some embodiments, the processor 1602 includes a cache memory 1604. Depending on the architecture, the processor 1602 may have a single internal cache or multiple levels of internal caches. In some embodiments, the cache memory is shared among various components of the processor 1602. In some embodiments, the processor 1602 also uses an external cache (e.g., a level 3 (L3) cache or a last-level cache (LLC)) (not shown), which may be shared among the processor cores 1607 using known cache coherence techniques. A register file 1606 is further included in the processor 1602, and the register file may include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers). Some registers may be general-purpose registers, while other registers may be specific to the design of the processor 1602.

[0193] In some embodiments, the processor 1602 is coupled to a processor bus 1610 component for transferring communication signals (such as address, data, or control signals) between the processor 1602 and other components in the system 1600. In one embodiment, the system 1600 uses an exemplary 'hub' system architecture, including a memory controller hub 1616 and an input / output (I / O) controller hub 1630. The memory controller hub 1616 facilitates communication between the memory device and other components of the system 1600, while the I / O controller hub (ICH) 1630 provides connections to I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 1616 is integrated within the processor.

[0194] The memory device 1620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable performance to act as a process memory. In one embodiment, the memory device 1620 may operate as the system memory of the system 1600 to store data 1622 and instructions 1621 for use when the one or more processors 1602 execute an application or a process. The memory controller hub 1616 is also coupled to an optional external graphics processor 1612, which may communicate with one or more graphics processors 1608 in the processor 1602 to perform graphics and media operations.

[0195] In some embodiments, the ICH 1630 enables peripheral devices to be connected to the memory device 1620 and the processor 1602 via a high-speed I / O bus. The I / O peripherals include but are not limited to: an audio controller 1646, a firmware interface 1628, a wireless transceiver 1626 (e.g., Wi-Fi, Bluetooth), a data storage device 1624 (e.g., a hard disk drive, flash memory, etc.), and a legacy I / O controller 1640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1642 connect input devices such as a keyboard and mouse 1644 combination. A network controller 1634 may also be coupled to the ICH 1630. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 1610. It will be appreciated that the system 1600 shown is exemplary and not restrictive, as other types of data processing systems configured in different ways may also be used. For example, the I / O controller hub 1630 may be integrated within the one or more processors 1602, or the memory controller hub 1616 and the I / O controller hub 1630 may be integrated into a discreet external graphics processor such as the external graphics processor 1612.

[0196] Figure 17 is a block diagram of an embodiment of a processor 1700 having one or more processor cores 1702A - 1702N, an integrated memory controller 1714, and an integrated graphics processor 1708. Figure 17 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to the manner described elsewhere herein, but are not limited thereto. The processor 1700 may include additional cores up to and including the additional core 1702N represented by the dashed box. Each of the processor cores 1702A - 1702N includes one or more internal cache units 1704A - 1704N. In some embodiments, each processor core is also capable of accessing one or more shared cache units 1706.

[0197] The internal cache units 1704A - 1704N and the shared cache units 1706 represent a cache memory hierarchy within the processor 1700. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared intermediate-level cache (such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache), where the highest-level cache in front of the external memory is classified as the LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 1706 and 1704A - 1704N.

[0198] In some embodiments, the processor 1700 may further include a set of one or more bus controller units 1716 and a system agent core 1710. The one or more bus controller units 1716 manage a set of peripheral buses, such as one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express). The system agent core 1710 provides management functionality for various processor components. In some embodiments, the system agent core 1710 includes one or more integrated memory controllers 1714 to manage access to various external memory devices (not shown).

[0199] In some embodiments, one or more of the processor cores 1702A - 1702N include support for simultaneous multithreading. In such embodiments, the system agent core 1710 includes components for coordinating and operating the cores 1702A - 1702N during multithreaded processing. The system agent core 1710 may additionally include a Power Control Unit (PCU), which includes logic and components for regulating the power states of the processor cores 1702A - 1702N and the graphics processor 1708.

[0200] In some embodiments, the processor 1700 additionally includes a graphics processor 1708 for performing graphics processing operations. In some embodiments, the graphics processor 1708 is coupled to a set of shared cache units 1706 and the system agent core 1710 (including the one or more integrated memory controllers 1714). In some embodiments, a display controller 1711 is coupled to the graphics processor 1708 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 1711 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 1708 or the system agent core 1710.

[0201] In some embodiments, a ring - based interconnect unit 1712 is used to couple the internal components of the processor 1700. However, alternative interconnect units, such as point - to - point interconnects, switched interconnects, or other techniques, including those well - known in the art, can be used. In some embodiments, the graphics processor 1708 is coupled to the ring interconnect 1712 via an I / O link 1713.

[0202] The exemplary I / O link 1713 represents at least one of a variety of I / O interconnects, including on - package I / O interconnects that facilitate communication between various processor components and a high - performance embedded memory module 1718, such as an eDRAM module. In some embodiments, each of the processor cores 1702 - 1702N and the graphics processor 1708 uses the embedded memory module 1718 as a shared last - level cache.

[0203] In some embodiments, the processor cores 1702A - 1702N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 1702A - 1702N are heterogeneous in terms of instruction set architecture (ISA), where one or more of the processor cores 1702A - N execute a first instruction set, and at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 1702A - 1702N are heterogeneous in terms of microarchitecture, where one or more cores with relatively higher power consumption are coupled with one or more power cores with lower power consumption. Additionally, the processor 1700 can be implemented on one or more chips or as a System - on - Chip (SoC) integrated circuit with the components shown in addition to other components.

[0204] Figure 18 is a block diagram of a graphics processor 1800, which can be a discrete graphics processing unit or can be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via a memory - mapped I / O interface to registers on the graphics processor and with commands placed in the processor memory. In some embodiments, the graphics processor 1800 includes a memory interface 1814 for accessing memory. The memory interface 1814 can be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0205] In some embodiments, the graphics processor 1800 further includes a display controller 1802 for driving display output data to a display device 1820. The display controller 1802 includes hardware for one or more overlapping planes of the display and the composition of multi - layer video or user interface elements. In some embodiments, the graphics processor 1800 includes a video codec engine 1806 for encoding, decoding, or transcoding media to, from, or between one or more media coding formats, the formats including but not limited to: Moving Picture Experts Group (MPEG) formats (such as MPEG - 2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG - 4 AVC), and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC - 1, and Joint Photographic Experts Group (JPEG) formats (such as JPEG and Motion JPEG (MJPEG) formats).

[0206] In some embodiments, the graphics processor 1800 includes a block transfer (BLIT) engine 1804 for performing two-dimensional (2D) rasterizer operations, such as bit boundary block transfers. However, in one embodiment, one or more components of the graphics processing engine (GPE) 1810 are used to perform 2D graphics operations. In some embodiments, the graphics processing engine 1810 is a computing engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0207] In some embodiments, the GPE 1810 includes a 3D pipeline 1812 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions for 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 1812 includes programmable and fixed function elements that perform various tasks within the element and / or generate execution threads for the 3D / media subsystem 1815. Although the 3D pipeline 1812 can be used to perform media operations, embodiments of the GPE 1810 also include a media pipeline 1816 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0208] In some embodiments, the media pipeline 1816 includes fixed function or programmable logic units for performing one or more specialized media operations (such as video decoding acceleration, video deinterlacing, and video encoding acceleration) instead of or on behalf of the video codec engine 1806. In some embodiments, the media pipeline 1816 further includes a thread generation unit to generate threads for execution on the 3D / media subsystem 1815. The generated threads perform calculations for media operations on one or more graphics execution units included in the 3D / media subsystem 1815.

[0209] In some embodiments, the 3D / media subsystem 1815 includes logic for executing the threads generated by the 3D pipeline 1812 and the media pipeline 1816. In one embodiment, the pipeline sends thread execution requests to the 3D / media subsystem 1815, which includes thread dispatch logic for arbitrating and dispatching various requests for available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 1815 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and store output data.

[0210] 3D / Media Processing

[0211] Figure 19 is a block diagram of a graphics processing engine 1910 of a graphics processor according to some embodiments. In one embodiment, GPE 1910 is Figure 18 a version of GPE 1810 as shown in Figure 19 Elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to the manner described elsewhere herein, but are not limited thereto.

[0212] In some embodiments, GPE 1910 is coupled to a command streamer 1903 that provides a command stream to GPE 3D and media pipelines 1912, 1916. In some embodiments, command streamer 1903 is coupled to a memory, which may be a system memory, or one or more of an internal cache memory and a shared cache memory. In some embodiments, command streamer 1903 receives commands from the memory and sends the commands to 3D pipeline 1912 and / or media pipeline 1916. The commands are indications fetched from a ring buffer that stores commands for 3D and media pipelines 1912, 1916. In one embodiment, the ring buffer may additionally include a batch command buffer that stores multiple batches of multiple commands. 3D and media pipelines 1912, 1916 process the commands by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to execution unit array 1914. In some embodiments, execution unit array 1914 is scalable such that the array includes a variable number of execution units based on the target power and performance levels of GPE 1910.

[0213] In some embodiments, sampling engine 1930 is coupled to a memory (e.g., cache memory or system memory) and execution unit array 1914. In some embodiments, sampling engine 1930 provides a memory access mechanism for execution unit array 1914 that allows the execution array 1914 to read graphics and media data from the memory. In some embodiments, sampling engine 1930 includes logic for performing specialized image sampling operations for media.

[0214] In some embodiments, the specialized media sampling logic in the sampling engine 1930 includes a denoising / deinterleaving module 1932, a motion estimation module 1934, and an image scaling and filtering module 1936. In some embodiments, the denoising / deinterleaving module 1932 includes logic for performing one or more of a denoising or deinterleaving algorithm on the decoded video data. The deinterleaving logic combines the alternating fields of the interleaved video content into a single frame of the video. The denoising logic reduces or removes data noise from the video and image data. In some embodiments, the denoising logic and the deinterleaving logic are motion adaptive and use spatial or temporal filtering based on the amount of motion detected in the video data. In some embodiments, the denoising / deinterleaving module 1932 includes dedicated motion detection logic (e.g., within the motion estimation engine 1934).

[0215] In some embodiments, the motion estimation engine 1934 provides hardware acceleration for video operations by performing video acceleration functions (such as motion vector estimation and prediction) on the video data. The motion estimation engine determines motion vectors that describe the transformation of the image data between consecutive video frames. In some embodiments, the graphics processor media codec uses the video motion estimation engine 1934 to perform operations on the video at the macroblock level, which otherwise could be too computationally intensive to perform with a general-purpose processor. In some embodiments, the motion estimation engine 1934 can generally be used by graphics processor components to assist in video decoding and processing functions that are sensitive or adaptive to the direction or magnitude of motion within the video data.

[0216] In some embodiments, the image scaling and filtering module 1936 performs image processing operations to improve the visual quality of the resulting images and videos. In some embodiments, the scaling and filtering module 1936 processes the image and video data during the sampling operation before providing the data to the execution unit array 1914.

[0217] In some embodiments, GPE 1910 includes a data port 1944 that provides an additional mechanism for the graphics subsystem to access memory. In some embodiments, data port 1944 facilitates memory access for operations including render target writes, constant buffer reads, scratch memory space reads / writes, and media surface access. In some embodiments, data port 1944 includes a cache memory space for caching access to memory. The cache memory can be a single data cache or separated into multiple caches for multiple subsystems accessing memory via the data port (e.g., render buffer cache, constant buffer cache, etc.). In some embodiments, threads executing on execution units in execution unit array 1914 communicate with the data port by exchanging messages via a data distribution interconnect that couples each subsystem of GPE 1910.

[0218] Execution Unit

[0219] Figure 20 is a block diagram of another embodiment of graphics processor 2000. Figure 20 Elements having the same reference numbers (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto.

[0220] In some embodiments, graphics processor 2000 includes a ring interconnect 2002, a pipeline front end 2004, a media engine 2037, and graphics cores 2080A - 2080N. In some embodiments, ring interconnect 2002 couples the graphics processor to other processing units, including other graphics processors or one or more general - purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated within a multi - core processing system.

[0221] In some embodiments, the graphics processor 2000 receives multiple batches of commands via the ring interconnect 2002. The incoming commands are interpreted by the command streamer 2003 in the pipeline front end 2004. In some embodiments, the graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via the graphics cores 2080A - 2080N. For 3D geometry processing commands, the command streamer 2003 supplies the commands to the geometry pipeline 2036. For at least some media processing commands, the command streamer 2003 supplies the commands to the video front end 2034, which is coupled to the media engine 2037. In some embodiments, the media engine 2037 includes a Video Quality Engine (VQE) 2030 for video and image post - processing and a Multi - Format Encoding / Decoding (MFX) 2033 engine for providing hardware - accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2036 and the media engine 2037 each generate execution threads for the thread execution resources provided by at least one graphics core 2080A.

[0222] In some embodiments, the graphics processor 2000 includes scalable thread execution resources characterized by modular cores 2080A - 2080N (sometimes referred to as core slices), each modular core having multiple sub - cores 2050A - 2050N, 2060A - 2060N (sometimes referred to as core sub - slices). In some embodiments, the graphics processor 2000 can have any number of graphics cores 2080A through 2080N. In some embodiments, the graphics processor 2000 includes a graphics core 2080A that has at least a first sub - core 2050A and a second core sub - core 2060A. In other embodiments, the graphics processor is a low - power processor having a single sub - core (e.g., 2050A). In some embodiments, the graphics processor 2000 includes multiple graphics cores 2080A - 2080N, each graphics core including a set of first sub - cores 2050A - 2050N and a set of second sub - cores 2060A - 2060N. Each sub - core in the set of first sub - cores 2050A - 2050N includes at least a first set of execution units 2052A - 2052N and media / texture samplers 2054A - 2054N. Each sub - core in the set of second sub - cores 2060A - 2060N includes at least a second set of execution units 2062A - 2062N and samplers 2064A - 2064N. In some embodiments, each sub - core 2050A - 2050N, 2060A - 2060N shares a set of shared resources 2070A - 2070N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0223] Figure 21Illustrates thread execution logic 2100, including an array of processing elements employed in some embodiments of the GPE. Figure 21 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto.

[0224] In some embodiments, thread execution logic 2100 includes a pixel shader 2102, a thread dispatcher 2104, an instruction cache 2106, a scalable execution unit array (including multiple execution units 2108A - 2108N), a sampler 2110, a data cache 2112, and a data port 2114. In one embodiment, the components included are interconnected via an interconnect structure that links to each of the components. In some embodiments, thread execution logic 2100 includes one or more connections to memory (such as system memory or cache memory) via the instruction cache 2106, the data port 2114, the sampler 2110, and one or more of the execution unit arrays 2108A - 2108N. In some embodiments, each execution unit (e.g., 2108A) is a separate vector processor capable of executing multiple simultaneous threads and processing multiple data elements in parallel for each thread. In some embodiments, the execution unit array 2108A - 2108N includes any number of separate execution units.

[0225] In some embodiments, the execution unit array 2108A - 2108N is primarily used to execute "shader" programs. In some embodiments, the execution units in the array 2108A - 2108N execute an instruction set that includes native support for many standard 3D graphics shader instructions, enabling shader programs from graphics libraries (e.g., Direct 3D and OpenGL) to be executed with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute and media shaders).

[0226] Each execution unit in the execution unit array 2108A - 2108N operates on an array of data elements. The number of data elements is the "execution size" or the number of channels for the instruction. Execution channels are logical units for flow control, data element access, and mask execution within an instruction. The number of channels can be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) of a particular graphics processor. In some embodiments, the execution units 2108A - 2108N support integer and floating-point data types.

[0227] The execution unit instruction set includes single instruction multiple data (SIMD) instructions. Various data elements can be stored in registers as packed data types, and the execution unit will process the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four separate 64-bit packed data elements (quad-word (QW) sized data elements), eight separate 32-bit packed data elements (double-word (DW) sized data elements), sixteen separate 16-bit packed data elements (word (W) sized data elements), or thirty-two separate 8-bit data elements (byte (B) sized data elements). However, different vector widths and register sizes are possible.

[0228] One or more internal instruction caches (e.g., 2106) are included in the thread execution logic 2100 to cache the thread instructions of the execution unit. In some embodiments, one or more data caches (e.g., 2112) are included to cache the thread data during thread execution. In some embodiments, a sampler 2110 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2110 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution unit.

[0229] During execution, the graphics and media pipeline sends thread initiation requests to the thread execution logic 2100 via the thread generation and dispatch logic. In some embodiments, the thread execution logic 2100 includes a local thread dispatcher 2104 that arbitrates the thread initiation requests from the graphics and media pipeline and instantiates the requested threads on one or more execution units 2108A - 2108N. For example, the geometry pipeline (e.g., Figure 20 2036) dispatches vertex processing, tessellation, or geometry processing threads to the thread execution logic 2100 ( Figure 21 ). In some embodiments, the thread dispatcher 2104 can also process execution-time thread generation requests from executing shader programs.

[0230] Once a group of geometric objects has been processed and rasterized into pixel data, the pixel shader 2102 is called to further compute output information and cause the results to be written to an output surface (e.g., a color buffer, a depth buffer, a stencil buffer, etc.). In some embodiments, the pixel shader 2102 interpolates values of various vertex attributes that are to be interpolated across the rasterized objects. In some embodiments, the pixel shader 2102 then executes a pixel shader program supplied by an application programming interface (API). To execute the pixel shader program, the pixel shader 2102 dispatches threads to execution units (e.g., 2108A) via a thread dispatcher 2104. In some embodiments, the pixel shader 2102 uses texture sampling logic in a sampler 2110 to access texture data in a texture map stored in memory. Arithmetic operations performed on the texture data and the input geometric data compute pixel color data for each geometric fragment or discard one or more pixels from further processing.

[0231] In some embodiments, the data port 2114 provides a memory access mechanism for outputting processed data to memory for processing on the graphics processor output pipeline for the thread execution logic 2100. In some embodiments, the data port 2114 includes or is coupled to one or more cache memories (e.g., a data cache 2112) to cache data for memory access via the data port.

[0232] Figure 22 is a block diagram illustrating a graphics processor instruction format 2200 in accordance with some embodiments. In one or more embodiments, the graphics processor execution units support an instruction set having instructions in multiple formats. The solid boxes show components that are typically included in the execution unit instructions, while the dashed boxes include optional or components that are only included in a subset of the instructions. In some embodiments, the instruction formats 2200 described and shown are macro-instructions because they are the instructions supplied to the execution units, as opposed to micro-operations derived from instruction decoding (once the instructions are processed).

[0233] In some embodiments, the graphics processor execution units natively support instructions in a 128-bit format 2210. A 64-bit compact instruction format 2230 is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit format 2210 provides access to all instruction options, while some options and operations are limited in the 64-bit format 2230. The native instructions available in the 64-bit format 2230 vary by embodiment. In some embodiments, a set of index values in an index field 2213 is used to partially compact the instruction. The execution unit hardware references a set of compact tables based on the index values and uses the compact table outputs to reconstruct the native instruction in the 128-bit format 2210.

[0234] For each format, the instruction opcode 2212 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an addition instruction, the execution unit performs a simultaneous addition operation across each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 2214 enables control of certain execution options such as channel selection (e.g., predication) and data channel ordering (e.g., shuffling). For a 128-bit instruction 2210, the execution size field 2216 limits the number of data channels to be executed in parallel. In some embodiments, the execution size field 2216 is not available for use in the 64-bit compact instruction format 2230.

[0235] Some execution unit instructions have up to three operands, including two source operands src0 2220, src1 2222, and one destination 2218. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2224), where the instruction opcode 2212 determines the number of source operands. The last source operand of the instruction may be an immediate (e.g., hard-coded) value passed by the instruction.

[0236] In some embodiments, the 128-bit instruction format 2210 includes access / address mode information 2226 that specifies, for example, whether to use direct register addressing mode or indirect register addressing mode. When using direct register addressing mode, the register addresses of one or more operands are provided directly by bits in the instruction 2210.

[0237] In some embodiments, the 128-bit instruction format 2210 includes an access / address mode field 2226 that specifies the address mode and / or access mode for the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte alignment access mode and a 1-byte alignment access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction 2210 may use byte-aligned addressing for source and destination operands, and when in a second mode, the instruction 2210 may use 16-byte-aligned addressing for all source and destination operands.

[0238] In one embodiment, the address mode portion of the access / address mode field 2226 determines whether the instruction will use direct or indirect addressing. When using the direct register addressing mode, the bits in the instruction 2210 directly provide the register addresses of one or more operands. When using the indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address immediate field and the address register value in the instruction.

[0239] In some embodiments, the instructions are grouped based on the opcode 2212 bit field to simplify opcode decoding 2240. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of the opcode. The exact opcode grouping shown is merely an example. In some embodiments, the move and logic opcode group 2242 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2242 shares the five most significant bits (MSB), where the move (mov) instruction takes the form of 0000xxxxb, and the logic instruction takes the form of 0001xxxxb. The flow control instruction group 2244 (e.g., call, jump (jmp)) includes instructions that take the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2246 includes a mix of instructions, which includes synchronization instructions (e.g., wait, send) that take the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 2248 includes component arithmetic instructions (e.g., add, multiply (mul)) that take the form of 0100xxxxb (e.g., 0x40). The parallel math group 2248 performs arithmetic operations in parallel across data channels. The vector math group 2250 includes arithmetic instructions (e.g., dp4) that take the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as a dot product operation on vector operands.

[0240] Graphics Pipeline

[0241] Figure 23 is a block diagram of another embodiment of the graphics processor 2300. Figure 23 Elements with the same reference numbers (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto.

[0242] In some embodiments, the graphics processor 2300 includes a graphics pipeline 2320, a media pipeline 2330, a display engine 2340, thread execution logic 2350, and a render output pipeline 2370. In some embodiments, the graphics processor 2300 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued via a ring interconnect 2302 to the graphics processor 2300. In some embodiments, the ring interconnect 2302 couples the graphics processor 2300 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2302 are interpreted by a command streamer 2303, which supplies instructions to individual components of the graphics pipeline 2320 or the media pipeline 2330.

[0243] In some embodiments, the command streamer 2303 directs the operation of a vertex fetcher 2305, which reads vertex data from memory and executes vertex processing commands provided by the command streamer 2303. In some embodiments, the vertex fetcher 2305 provides vertex data to a vertex shader 2307, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex fetcher 2305 and the vertex shader 2307 execute vertex processing instructions by dispatching execution threads to execution units 2352A, 2352B via a thread dispatcher 2331.

[0244] In some embodiments, the execution units 2352A, 2352B are an array of vector processors having instruction sets for performing graphics and media operations. In some embodiments, the execution units 2352A, 2352B have attached L1 caches 2351 that are specific to each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0245] In some embodiments, the graphics pipeline 2320 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 2311 configures the tessellation operation. A programmable domain shader 2317 provides backend evaluation of the tessellation output. The tessellator 2313 operates in the direction of the hull shader 2311 and includes dedicated logic for generating a set of detailed geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 2320. In some embodiments, if tessellation is not used, the tessellation components 2311, 2313, 2317 can be bypassed.

[0246] In some embodiments, a complete geometric object can be processed by the geometry shader 2319 via one or more threads dispatched to execution units 2352A, 2352B, or can proceed directly to the clipper 2329. In some embodiments, the geometry shader operates on an entire geometric object rather than a patch or vertex of a vertex as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 2319 receives input from the vertex shader 2307. In some embodiments, if the tessellation unit is disabled, the geometry shader 2319 can be programmed by a geometry tessellation shader program to perform geometric tessellation.

[0247] Before rasterization, the clipper 2329 processes vertex data. The clipper 2329 can be a programmable clipper with clipping and geometry shader functionality or a fixed-function clipper. In some embodiments, the rasterizer 2373 (e.g., depth test component) in the render output pipeline 2370 dispatches pixel shaders to transform geometric objects into their per-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 2350. In some embodiments, an application can bypass the rasterizer 2373 and access the un-rasterized vertex data via the stream out unit 2323.

[0248] The graphics processor 2300 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and messages to be passed among the major components of the processor. In some embodiments, the execution units 2352A, 2352B and the associated cache(s) 2351, texture and media sampler 2354, and texture / sampler cache 2358 are interconnected via a data port 2356 to perform memory accesses and communicate with the render output pipeline components of the processor. In some embodiments, the sampler 2354, caches 2351, 2358, and execution units 2352A, 2352B each have separate memory access paths.

[0249] In some embodiments, the rendering output pipeline 2370 includes a rasterizer 2373 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. Associated render cache 2378 and depth cache 2379 are also available in some embodiments. Pixel operation component 2377 performs pixel-based operations on the data, although in some examples, pixel operations associated with 2D operations (e.g., bit blit with blending for transfer) are performed by 2D engine 2341, or at display time by display controller 2343 using an overlay display plane instead. In some embodiments, shared L3 cache 2375 is available to all graphics components, allowing data to be shared without using main system memory.

[0250] In some embodiments, the graphics processor media pipeline 2330 includes a media engine 2337 and a video front end 2334. In some embodiments, the video front end 2334 receives pipeline commands from command streamer 2303. In some embodiments, the media pipeline 2330 includes a separate command streamer. In some embodiments, the video front end 2334 processes the commands before sending the media commands to media engine 2337. In some embodiments, media engine 2337 includes thread generation functionality for generating threads for dispatch to thread execution logic 2350 via thread dispatcher 2331.

[0251] In some embodiments, the graphics processor 2300 includes a display engine 2340. In some embodiments, the display engine 2340 is external to the processor 2300 and is coupled to the graphics processor via ring interconnect 2302, or some other interconnect bus or fabric. In some embodiments, the display engine 2340 includes a 2D engine 2341 and a display controller 2343. In some embodiments, the display engine 2340 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 2343 is coupled to a display device (not shown), which may be a system-integrated display device (such as in a laptop computer), or may be an external display device attached via a display device connector.

[0252] In some embodiments, the graphics pipeline 2320 and the media pipeline 2330 may be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, the driver software for the graphics processor converts API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL) and Open Computing Language (OpenCL) from the Khronos Group, the Direct3D library from Microsoft Corporation, or support may be provided for both OpenGL and D3D. Support may also be provided for the open source computer vision library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if a mapping can be made from the pipelines of the future APIs to the pipelines of the graphics processor.

[0253] Graphics Pipeline Programming

[0254] Figure 24A is a block diagram of a graphics processor command format 2400 according to some embodiments. Figure 24B is a block diagram of a graphics processor command sequence 2410 according to an embodiment. Figure 24A The solid boxes in show components generally included in a graphics command, while the dashed boxes include optional or components included only in a subset of graphics commands. Figure 24A An exemplary graphics processor command format 2400 includes a data field for identifying a target client 2402 for the command, a command operation code (opcode) 2404, and associated data 2406 for the command. A sub-opcode 2405 and a command size 2408 are also included in some commands.

[0255] In some embodiments, the client 2402 specifies the client unit of the graphics device that processes the command data. In some embodiments, the graphics processor command parser examines the client field of each command to adjust further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once the command is received by the client unit, the client unit reads the opcode 2404 and (if present) the sub-opcode 2405 to determine the operation to perform. The client unit uses the information in the data field 2406 to execute the command. For some commands, an explicit command size 2408 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands in the command based on the command opcode. In some embodiments, commands are aligned by multiples of a double word length.

[0256] Figure 24B The flow diagram in Figure 24B illustrates an exemplary graphics processor command sequence 2410. In some embodiments, software or firmware of a data processing system characterized by an embodiment of a graphics processor uses a version of the illustrated command sequence to initiate, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for illustrative purposes only, as embodiments are not limited to these particular commands or this command sequence. Additionally, the commands may be issued in a batch in the command sequence such that the graphics processor will process the sequence of commands at least partially concurrently.

[0257] In some embodiments, the graphics processor command sequence 2410 may begin with a pipeline flush clear command 2412 to cause any active graphics pipeline to complete the current outstanding commands of the pipeline. In some embodiments, the 3D pipeline 2422 and the media pipeline 2424 do not operate concurrently. The pipeline flush clear is executed to cause the active graphics pipeline to complete any outstanding commands. In response to the pipeline flush clear, the command parser for the graphics processor will pause command processing until the active rendering engine has completed the outstanding operations and the associated read caches are invalidated. Optionally, any data marked as 'dirty' in the render cache may be flushed to memory. In some embodiments, the pipeline flush clear command 2412 may be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0258] In some embodiments, a pipeline select command 2413 is used when the command sequence requires the graphics processor to make an explicit switch between pipelines. In some embodiments, the pipeline select command 2413 is only required once within an execution context before issuing pipeline commands, unless the context is to issue commands for two pipelines. In some embodiments, the pipeline flush clear command 2412 is required immediately before the pipeline switch via the pipeline select command 2413.

[0259] In some embodiments, a pipeline control command 2414 configures the graphics pipeline for operation and is used to program the 3D pipeline 2422 and the media pipeline 2424. In some embodiments, the pipeline control command 2414 configures the pipeline state for the active pipeline. In one embodiment, the pipeline control command 2414 is used for pipeline synchronization and for clearing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0260] In some embodiments, the return buffer status command 2416 is used to configure a set of return buffers for enabling the corresponding pipeline to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers, which write intermediate data into the one or more return buffers during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, the return buffer status 2416 includes selecting the size and number of return buffers for a set of pipeline operations.

[0261] The remaining commands in the command sequence differ based on the active pipeline for the operation. Based on the pipeline determination 2420, the command sequence is customized for the 3D pipeline 2422 or the media pipeline 2424, where the 3D pipeline 2422 starts with the 3D pipeline state 2430 and the media pipeline 2424 starts with the media pipeline state 2440.

[0262] The commands for the 3D pipeline state 2430 include 3D state setting commands for: vertex buffer status, vertex element status, constant color status, depth buffer status, and other state variables to be configured before processing 3D primitive commands. The values of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, the 3D pipeline state 2430 commands can also selectively disable or bypass certain pipeline elements if those elements will not be used.

[0263] In some embodiments, the 3D primitive command 2432 is used to submit 3D primitive commands to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive command 2432 are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive command 2432 data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, the 3D primitive command 2432 is used to perform vertex operations on 3D primitives via the vertex shader. To process the vertex shader, the 3D pipeline 2422 dispatches shader execution threads to the graphics processor execution units.

[0264] In some embodiments, the 3D pipeline 2422 is triggered by executing a 2434 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, a pipeline synchronization command is used to trigger command execution to dump a clear command sequence through the graphics pipeline. The 3D pipeline will perform geometric processing on 3D primitive primitives. Once the operation is complete, the resulting geometric object is rasterized and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0265] In some embodiments, when performing media operations, the graphics processor command sequence 2410 follows the media pipeline 2424 path. Generally, the specific use and manner of programming for the media pipeline 2424 depends on the media or compute operation to be performed. During media decoding, specific media decoding operations may be offloaded to the media pipeline. In some embodiments, the media pipeline may also be bypassed and media decoding may be performed in whole or in part (using resources provided by one or more general-purpose processing cores). In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using a compute shader program that does not explicitly involve the rendering of graphics primitive primitives.

[0266] In some embodiments, the media pipeline 2424 is configured in a manner similar to the 3D pipeline 2422. A set of media pipeline state commands 2440 are dispatched or placed into the command queue before the media object command 2442. In some embodiments, the media pipeline state commands 2440 include data for configuring media pipeline elements that will be used to process media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline (such as encoding or decoding formats). In some embodiments, the media pipeline state commands 2440 also support using one or more pointers for "indirect" state elements that contain a batch of state settings.

[0267] In some embodiments, the media object command 2442 supplies a pointer to a media object for processing by a media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before the media object command 2442 is issued. Once the pipeline state is configured and the media object command 2442 is queued, the media pipeline 2424 is triggered via an execute command 2444 or an equivalent execution event (e.g., a register write). The output from the media pipeline 2424 can then be post-processed by operations provided by the 3D pipeline 2422 or the media pipeline 2424. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0268] Graphics Software Architecture

[0269] Figure 25 FIG. shows an exemplary graphics software architecture for a data processing system 2500 according to some embodiments. In some embodiments, the software architecture includes a 3D graphics application 2510, an operating system 2520, and at least one processor 2530. In some embodiments, the processor 2530 includes a graphics processor 2532 and one or more general-purpose processor cores 2534. The graphics application 2510 and the operating system 2520 each execute in the system memory 2550 of the data processing system.

[0270] In some embodiments, the 3D graphics application 2510 includes one or more shader programs that include shader instructions 2512. The shader language instructions can be in a high-level shader language such as High-Level Shading Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 2514 in machine language suitable for execution by the general-purpose processor cores 2534. The application also includes a graphics object 2516 defined by vertex data.

[0271] In some embodiments, the operating system 2520 is the Microsoft® Windows® operating system from Microsoft Corporation, a proprietary UNIX-like operating system, or an open-source UNIX-like operating system (using a variant of the Linux kernel). When the Direct3D API is in use, the operating system 2520 uses a front-end shader compiler 2524 to compile any shader instructions 2512 in HLSL into a lower-level shader language. The compilation can be Just-In-Time (JIT) compilation, or the application can perform shader pre-compilation. In some embodiments, during compilation of the 3D graphics application 2510, high-level shaders are compiled into low-level shaders.

[0272] In some embodiments, the user-mode graphics driver 2526 includes a backend shader compiler 2527 that is used to convert shader instructions 2512 into a hardware-specific representation. When the OpenGL API is in use, shader instructions 2512 in the GLSL high-level language are passed to the user-mode graphics driver 2526 for compilation. In some embodiments, the user-mode graphics driver 2526 uses the operating system kernel-mode functionality 2528 to communicate with the kernel-mode graphics driver 2529. In some embodiments, the kernel-mode graphics driver 2529 communicates with the graphics processor 2532 to dispatch commands and instructions.

[0273] IP Core Implementation

[0274] One or more aspects of at least one embodiment can be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium can include instructions that represent various logic within the processor. When read by the machine, the instructions can cause the machine to fabricate logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of logic for an integrated circuit and can be stored on a tangible machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model can be supplied to various consumers or manufacturing facilities that load the hardware model on a fabrication machine for fabricating the integrated circuit. The integrated circuit can be fabricated such that the circuit performs operations described in association with any of the embodiments described herein.

[0275] Figure 26 is a block diagram showing an IP core development system 2600 according to an embodiment, which can be used to fabricate an integrated circuit to perform operations. The IP core development system 2600 can be used to generate modular, reusable designs that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., an SOC integrated circuit). A design facility 2630 can generate a software simulation 2610 of an IP core design using a high-level programming language (e.g., C / C++). The software simulation 2610 can be used to design, test, and verify the behavior of the IP core. Then a register transfer level (RTL) design can be created or synthesized from the simulation model 2600. The RTL design 2615 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers (including the associated logic performed using the modeled digital signals). In addition to the RTL design 2615, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation can vary.

[0276] The RTL design 2615 or equivalent can be further synthesized by a design facility into a hardware model 2620, which can be in a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. A non-volatile memory 2640 (e.g., a hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a third-party fabrication facility 2665. Alternatively, the IP core design can be transmitted (e.g., via the Internet) through a wired connection 2650 or a wireless connection 2660. The fabrication facility 2665 can then fabricate an integrated circuit that is at least partially based on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

[0277] Figure 27 is a block diagram showing an exemplary system-on-chip integrated circuit 2700 according to an embodiment. The system-on-chip integrated circuit 2700 can be fabricated using one or more IP cores. The exemplary integrated circuit includes one or more application processors 2705 (e.g., CPUs), at least one graphics processor 2710, and can additionally include an image processor 2715 and / or a video processor 2720, any of which can be a modular IP core from the same or multiple different design facilities. The integrated circuit includes peripheral or bus logic, which includes a USB controller 2725, a UART controller 2730, an SPI / SDIO controller 2735, I 2 S / I 2 C controller 2740. Additionally, the integrated circuit can include a display device 2745 that is coupled to one or more of a high-definition multimedia interface (HDMI) controller 2750 and a mobile industry processor interface (MIPI) display interface 2755. Storage can be provided by a flash memory subsystem 2760 (including flash memory and a flash memory controller). A memory interface can be provided via a memory controller 2765 for accessing SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 2770.

[0278] Additionally, other logic and circuitry can be included in the processors of the integrated circuit 2700, including additional graphics processors / kernels, peripheral interface controllers, or general-purpose processor cores.

[0279] In one example, as described with respect to Figures 6 - 10B and in the following examples, the graphics processing pipeline 1400 ( Figure 14 ) includes a topology shader.

[0280] The present disclosure / application provides the following technical solutions:

[0281] 1. A system, comprising:

[0282] A display for presenting visual content;

[0283] A memory for storing a set of instructions; and

[0284] A semiconductor packaging device coupled to the display and the memory, the semiconductor packaging device comprising:

[0285] A substrate;

[0286] A host processor coupled to the substrate, wherein when executed by the host processor, the set of instructions causes the host processor to generate an object description associated with the visual content, and

[0287] A graphics processor coupled to the substrate, wherein the graphics processor includes logic for performing the following operations:

[0288] Receiving the object description at a topology shader,

[0289] Generating a set of polygons at the topology shader based on the object description, and

[0290] Sending the set of polygons to a vertex shader.

[0291] 2. The system according to claim 1, wherein the logic will:

[0292] Detect a lack of visibility conditions with respect to one or more polygons, and

[0293] Exclude the one or more polygons from the set of polygons in response to the lack of visibility conditions.

[0294] 3. The system according to claim 2, wherein the lack of visibility conditions will include one or more of a occluded state or an off-screen state.

[0295] 4. The system according to claim 1, wherein the logic will determine a level of detail associated with the object description based on depth information.

[0296] 5. The system according to claim 4, wherein the logic will identify a sub-octree corresponding to the object description, and wherein the topology shader will be called for the identified sub-octree.

[0297] 6. The system according to claim 4, wherein the logic will interpolate between two levels of detail.

[0298] 7. A device, comprising:

[0299] A substrate; and

[0300] Logic coupled to the substrate, where the logic is implemented in one or more of configurable logic or fixed functional hardware logic, and the logic is for:

[0301] Receiving an object description at a topology shader,

[0302] Generating a set of polygons at the topology shader based on the object description, and

[0303] Sending the set of polygons to a vertex shader.

[0304] 8. The apparatus according to claim 7, wherein the logic will:

[0305] Detect a lack of visibility conditions with respect to one or more polygons, and

[0306] Exclude the one or more polygons from the set of polygons in response to the lack of visibility conditions.

[0307] 9. The apparatus according to claim 8, wherein the lack of visibility conditions will include one or more of an occlusion state or an off-screen state.

[0308] 10. The apparatus according to claim 7, wherein the logic will determine a level of detail associated with the object description based on depth information.

[0309] 11. The apparatus according to claim 10, wherein the logic will identify a sub-octree corresponding to the object description, and wherein the topology shader will be called for the identified sub-octree.

[0310] 12. The apparatus according to claim 10, wherein the logic will interpolate between two levels of detail.

[0311] 13. A method, comprising:

[0312] Receiving an object description at a topology shader;

[0313] Generating a set of polygons at the topology shader based on the object description; and

[0314] Sending the set of polygons to a vertex shader.

[0315] 14. The method according to claim 13, wherein generating the set of polygons includes:

[0316] Detecting a lack of visibility conditions with respect to one or more polygons; and

[0317] Exclude the one or more polygons from the set of polygons in response to the lack of the visibility condition.

[0318] 15. The method according to claim 14, wherein the lack of the visibility condition will include one or more of a occluded state or an off - screen state.

[0319] 16. The method according to claim 13, wherein generating the set of polygons includes determining a level of detail associated with the object description based on depth information.

[0320] 17. The method according to claim 16, wherein determining the level of detail includes identifying a sub - octree corresponding to the object description, and wherein the topology shader will be invoked for the identified sub - octree.

[0321] 18. The method according to claim 16, wherein determining the level of detail includes interpolating between two levels of detail.

[0322] 19. At least one computer - readable storage medium, comprising a set of instructions that, when executed by a computing system, cause the computing system to:

[0323] Receive an object description at a topology shader;

[0324] Generate a set of polygons at the topology shader based on the object description; and

[0325] Send the set of polygons to a vertex shader.

[0326] 20. The at least one computer - readable storage medium according to claim 19, wherein the instructions, when executed, cause the computing system to:

[0327] Detect a lack of a visibility condition with respect to one or more polygons; and

[0328] Exclude the one or more polygons from the set of polygons in response to the lack of the visibility condition.

[0329] 21. The at least one computer - readable storage medium according to claim 20, wherein the lack of the visibility condition will include one or more of a occluded state or an off - screen state.

[0330] 22. The at least one computer - readable storage medium according to claim 19, wherein the instructions, when executed, cause the computing system to determine a level of detail associated with the object description based on depth information.

[0331] 23. At least one computer-readable storage medium as described in technical solution 22, wherein the instructions, when executed, cause the computing system to identify a sub-octree corresponding to the object description, and wherein the topology shader will be called for the identified sub-octree.

[0332] 24. At least one computer-readable storage medium as described in technical solution 22, wherein the instructions, when executed, cause the computing system to interpolate between two levels of detail.

[0333] Additional Notes and Examples

[0334] Example 1 may include a computing system with improved performance, including: a display for presenting visual content; a memory for storing a set of instructions; and a semiconductor packaging device coupled to the display and the memory, the semiconductor packaging device including: a substrate; a host processor coupled to the substrate, wherein when executed by the host processor, the set of instructions causes the host processor to generate an object description associated with the visual content; and a graphics processor coupled to the substrate, wherein the graphics processor includes logic for performing the following operations: receiving the object description at a topology shader, generating a set of polygons at the topology shader based on the object description, and sending the set of polygons to a vertex shader.

[0335] Example 2 may include the system described in Example 1, wherein the logic will detect the lack of visibility conditions with respect to one or more polygons and exclude the one or more polygons from the set of polygons in response to the lack of visibility conditions.

[0336] Example 3 may include the system described in Example 2, wherein the lack of visibility conditions will include one or more of a occlusion state or an off-screen state.

[0337] Example 4 may include the system described in any one of Examples 1 to 3, wherein the logic will determine a level of detail associated with the object description based on depth information.

[0338] Example 5 may include the system described in Example 4, wherein the logic will identify a sub-octree corresponding to the object description, and wherein the topology shader will be called for the identified sub-octree.

[0339] Example 6 may include the system described in Example 4, wherein the logic will interpolate between two levels of detail.

[0340] Example 7 may include a semiconductor packaging device, including: a substrate; and logic coupled to the substrate, where the logic is implemented in one or more of configurable logic or fixed functional hardware logic, and the logic is for: receiving an object description at a topology shader, generating a set of polygons at the topology shader based on the object description, and sending the set of polygons to a vertex shader.

[0341] Example 8 may include the device of Example 7, where the logic detects a lack of visibility conditions with respect to one or more polygons and excludes the one or more polygons from the set of polygons in response to the lack of visibility conditions.

[0342] Example 9 may include the device of Example 8, where the lack of visibility conditions includes one or more of a occlusion state or an off-screen state.

[0343] Example 10 may include the device of any one of Examples 7 to 9, where the logic determines a level of detail associated with the object description based on depth information.

[0344] Example 11 may include the device of Example 10, where the logic identifies a sub-octree corresponding to the object description, and where the topology shader will be called for the identified sub-octree.

[0345] Example 12 may include the device of Example 10, where the logic interpolates between two levels of detail.

[0346] Example 13 may include a method of operating a semiconductor packaging device, including: receiving an object description at a topology shader, generating a set of polygons at the topology shader based on the object description, and sending the set of polygons to a vertex shader.

[0347] Example 14 may include the method of Example 13, where generating the set of polygons includes detecting a lack of visibility conditions with respect to one or more polygons and excluding the one or more polygons from the set of polygons in response to the lack of visibility conditions.

[0348] Example 15 may include the method of Example 14, where the lack of visibility conditions includes one or more of a occlusion state or an off-screen state.

[0349] Example 16 may include the method of any one of Examples 13 to 15, where generating the set of polygons includes determining a level of detail associated with the object description based on depth information.

[0350] Example 17 may include the method described in Example 16, wherein determining the level of detail includes identifying a sub-octree corresponding to the object description, and wherein the topology shader will be called for the identified sub-octree.

[0351] Example 18 may include the method described in Example 16, wherein determining the level of detail includes interpolating between two levels of detail.

[0352] Example 19 may include at least one computer-readable storage medium including a set of instructions that, when executed by a computing system, cause the computing system to: receive an object description at a topology shader, generate a set of polygons at the topology shader based on the object description, and send the set of polygons to a vertex shader.

[0353] Example 20 may include the at least one computer-readable storage medium described in Example 19, wherein the instructions, when executed, cause the computing system to detect a lack of visibility conditions with respect to one or more polygons and exclude the one or more polygons from the set of polygons in response to the lack of visibility conditions.

[0354] Example 21 may include the at least one computer-readable storage medium described in Example 20, wherein the lack of visibility conditions will include one or more of a culled state or an off-screen state.

[0355] Example 22 may include the at least one computer-readable storage medium described in any of Examples 19 to 21, wherein the instructions, when executed, cause the computing system to determine a level of detail associated with the object description based on depth information.

[0356] Example 23 may include the at least one computer-readable storage medium described in Example 22, wherein the instructions, when executed, cause the computing system to identify a sub-octree corresponding to the object description, and wherein the topology shader will be called for the identified sub-octree.

[0357] Example 24 may include the at least one computer-readable storage medium described in Example 22, wherein the instructions, when executed, cause the computing system to interpolate between two levels of detail.

[0358] Example 25 may include a semiconductor packaging device including: components for receiving an object description at a topology shader; components for generating a set of polygons at the topology shader based on the object description; and components for sending the set of polygons to a vertex shader.

[0359] Example 26 may include the apparatus described in Example 25, wherein the component for generating the set of polygons includes a component for detecting a lack of visibility conditions relative to one or more polygons, and a component for excluding the one or more polygons from the set of polygons in response to the lack of visibility conditions.

[0360] Example 27 may include the apparatus described in Example 26, wherein the lack of visibility conditions will include one or more of an occlusion state or an off-screen state.

[0361] Example 28 may include the apparatus described in any one of Examples 25 to 27, wherein the component for generating the set of polygons includes a component for determining a level of detail associated with the object description based on depth information.

[0362] Example 29 may include the apparatus described in Example 28, wherein the component for determining the level of detail includes a component for identifying a sub-octree corresponding to the object description, and wherein the topology shader will be called for the identified sub-octree.

[0363] Example 30 may include the apparatus described in Example 28, wherein the component for determining the level of detail includes interpolating between two levels of detail.

[0364] The techniques described herein may thus determine the complexity / quality of the topology to be rendered when running on a graphics processor using a new stage in the graphics pipeline between calls to the vertex shader. Thus, the graphics processor can generate the topology without transferring unnecessary data from the host processor memory to the dedicated graphics memory. Geometry can be generated programmatically while minimizing the amount of data called upon in generating polygons.

[0365] The term "coupled" may be used herein to refer to any type of direct or indirect relationship between the components being discussed, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electro-mechanical, or other connections. Additionally, the terms "first", "second", etc. may be used herein solely to facilitate discussion and do not carry any specific significance of time or temporal order unless otherwise indicated. Moreover, it should be understood that the indefinite articles "a" or "an" carry the meaning of "one or more" or "at least one".

[0366] As used in this application and the claims, a list of items joined by the term "one or more" may mean any combination of the listed items. For example, the phrase "one or more of A, B, or C" may mean A, B, C; A and B; A and C; B and C; or A, B, and C.

[0367] The embodiments have been described above with reference to specific embodiments. However, those skilled in the art will understand that various modifications and changes can be made thereto without departing from the broader spirit and scope of the embodiments as set forth in the appended claims. Accordingly, the foregoing description and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A semiconductor packaging device, comprising: a substrate; and logic coupled to the substrate, wherein the logic is implemented in one or more of the following: configurable logic or fixed functional hardware logic, and the logic is configured to: generate a set of polygons at a graphics processor by a topology shader based on an object description to create a topology of a scene rather than generating topology primitive data at a host processor, wherein generating the set of polygons includes the following operations: detect a lack of visibility of one or more polygons, in response to the lack of visibility, exclude the one or more polygons from the set of polygons, and determine a level of detail associated with one or more objects in the scene based on the object description, wherein the set of polygons contains a first number of polygons at a first level of detail and a different second number of polygons at a second level of detail; and provide the scene for display based on the set of polygons generated by the topology shader at the graphics processor.

2. The device according to claim 1, wherein the lack of visibility will include one or more of the following: occlusion state or off-screen state.

3. The device according to claim 1, wherein generating the set of polygons includes the following operations: receiving, at the graphics processor by the topology shader, the object description from the host processor, wherein the object description identifies the type of object to be rendered without specifying the topology primitive data of the object.

4. The device according to claim 3, wherein generating the set of polygons includes the following operations: determining the level of detail associated with the object description based on depth information.

5. The device according to claim 4, wherein generating the set of polygons includes the following operations: interpolating between two levels of detail.

6. The device according to claim 4, wherein generating the set of polygons includes the following operations: identifying a sub-octree corresponding to the object description, and wherein the topology shader will be called for the identified sub-octree.

7. A system, comprising: a display for presenting visual content; a memory; and a semiconductor packaging device coupled to the display and the memory, wherein the semiconductor packaging device includes: a substrate; and a graphics processor coupled to the substrate, wherein the graphics processor includes logic configured to: generate a set of polygons at a graphics processor by a topology shader based on an object description to create a topology of a scene rather than generating topology primitive data at a host processor, wherein generating the set of polygons includes the following operations: detect a lack of visibility of one or more polygons, in response to the lack of visibility, exclude the one or more polygons from the set of polygons, and determine a level of detail associated with one or more objects in the scene based on the object description, wherein the set of polygons contains a first number of polygons at a first level of detail and a different second number of polygons at a second level of detail, and Provide the scene to the display based on the set of polygons generated by the topology shader at the graphics processor.

8. The system according to claim 7, wherein, The lack of visibility will include one or more of the following: occlusion state or off-screen state.

9. The system according to claim 7, wherein, The generating the set of polygons includes the following operations: At the graphics processor, receive the object description from the host processor by the topology shader, wherein the object description identifies the type of object to be rendered without specifying the topological primitive metadata of the object.

10. The system according to claim 9, wherein, The generating the set of polygons includes the following operations: Determine the level of detail associated with the object description based on depth information.

11. The system according to claim 10, wherein, The generating the set of polygons includes the following operations: Interpolate between two levels of detail.

12. The system according to claim 10, wherein, The generating the set of polygons includes the following operations: Identify the sub-octree corresponding to the object description, and wherein the topology shader will be called for the identified sub-octree.

13. At least one computer-readable storage medium including an instruction set, the instruction set when executed by a computing device causes the computing device to: At the graphics processor, generate a set of polygons by the topology shader based on the object description to create the topology of the scene rather than generating topological primitive metadata at the host processor, wherein the generating the set of polygons includes the following operations: Detect the lack of visibility of one or more polygons, In response to the lack of visibility, exclude the one or more polygons from the set of polygons, and Determine the level of detail associated with one or more objects in the scene based on the object description, wherein the set of polygons contains a first number of polygons at a first level of detail and a different second number of polygons at a second level of detail; and Provide the scene for display based on the set of polygons generated by the topology shader at the graphics processor.

14. The at least one computer-readable storage medium according to claim 13, wherein, The lack of visibility will include one or more of the following: occlusion state or off-screen state.

15. The at least one computer-readable storage medium according to claim 13, wherein, The generating the set of polygons includes the following operations: At the graphics processor, receive the object description from the host processor by the topology shader, wherein the object description identifies the type of object to be rendered without specifying the topological primitive metadata of the object.

16. The at least one computer-readable storage medium according to claim 15, wherein, The generating the set of polygons includes the following operations: Determine the level of detail associated with the object description based on depth information.

17. The at least one computer-readable storage medium according to claim 16, wherein, Generating the set of polygons includes the following operations: interpolating between two levels of detail.

18. The at least one computer-readable storage medium according to claim 16, wherein, generating the set of polygons includes the following operations: identifying a sub-octree corresponding to the object description, and wherein a topology shader will be called for the identified sub-octree.

19. A method of operating a semiconductor packaging device, comprising: at a graphics processor, generating, by a topology shader, a set of polygons based on an object description to create a topology of a scene rather than generating topology primitive data at a host processor, wherein generating the set of polygons includes the following operations: detecting a lack of visibility of one or more polygons, in response to the lack of visibility, excluding the one or more polygons from the set of polygons, and determining, based on the object description, a level of detail associated with one or more objects in the scene, wherein the set of polygons contains a first number of polygons at a first level of detail and a different second number of polygons at a second level of detail; and providing the scene for display based on the set of polygons generated by the topology shader at the graphics processor.

20. The method according to claim 19, wherein, the lack of visibility will include one or more of the following: occlusion state or off-screen state.

21. The method according to claim 19, wherein, generating the set of polygons includes the following operations: at the graphics processor, receiving, by the topology shader, the object description from the host processor, wherein the object description identifies the type of object to be rendered without specifying the topology primitive data of the object.

22. The method according to claim 21, wherein, generating the set of polygons includes the following operations: determining the level of detail associated with the object description based on depth information.

23. The method according to claim 22, wherein, generating the set of polygons includes the following operations: interpolating between two levels of detail.

24. The method according to claim 22, wherein, generating the set of polygons includes the following operations: identifying a sub-octree corresponding to the object description, and wherein a topology shader will be called for the identified sub-octree.

25. A semiconductor packaging device, comprising: means for generating, at a graphics processor, by a topology shader, a set of polygons based on an object description to create a topology of a scene rather than generating topology primitive data at a host processor, wherein the means for generating the set of polygons includes: means for detecting a lack of visibility of one or more polygons, means for excluding the one or more polygons from the set of polygons in response to the lack of visibility, and A component for determining a level of detail associated with one or more objects in the scene based on the object description, wherein the set of polygons includes a first number of polygons at a first level of detail and a different second number of polygons at a second level of detail; and A component for providing the scene for display based on the set of polygons generated by the topology shader at the graphics processor.

26. The apparatus according to claim 25, wherein, The lack of visibility will include one or more of the following: occlusion state or off-screen state.

27. The apparatus according to claim 25, wherein, The component for generating the set of polygons includes: A component for receiving the object description from the host processor by the topology shader at the graphics processor, wherein the object description identifies the type of object to be rendered without specifying the topological primitive metadata of the object.

28. The apparatus according to claim 27, wherein, The component for generating the set of polygons includes a component for determining the level of detail associated with the object description based on depth information.

29. The apparatus according to claim 28, wherein, The component for generating the set of polygons includes a component for interpolating between two levels of detail.

30. The apparatus according to claim 28, wherein, The component for generating the set of polygons includes a component for identifying a sub-octree corresponding to the object description, and wherein the topology shader will be called for the identified sub-octree.

31. A computer-readable medium having instructions stored thereon that, when executed, cause a computing device to perform the method according to any one of claims 19-24.

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