Integrated circuit device

Abstract

An integrated circuit device includes a peripheral circuit structure, a memory stack including a plurality of gate lines on the peripheral circuit structure overlapping the peripheral circuit structure in a vertical direction, an upper substrate between the peripheral circuit structure and the memory stack, the upper substrate including a via under a memory cell region of the memory stack, a word line cut region extending lengthwise across the memory stack and the via in a first lateral direction, and a common source line in the word line cut region, the common source line including a first portion extending lengthwise on the upper substrate in the first lateral direction and a second portion integrally connected to the first portion, the second portion penetrating the upper substrate from an upper portion of the upper substrate through the via and extending into the peripheral circuit structure.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0117491, filed on September 24, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to an integrated circuit (IC) device, and more specifically, to a non-integrated circuit comprising a cell over periphery (COP) structure.

[0004] IC devices with volatile memory. Background Technology

[0005] With the increasing multifunctionality of information and communication devices, the demand for high-capacity, highly integrated IC devices, including memory devices, is growing. The size of memory cells is gradually shrinking, while the operational circuits and interconnect structures within memory devices for implementing memory operation and electrical connections are becoming more complex. Therefore, there is a need for IC devices that include memory devices.

[0006] The device is configured to increase integration density and have good electrical characteristics. Summary of the Invention

[0007] The disclosed embodiments provide an integrated circuit (IC) device having increased integration density and reduced chip size, and configured to increase the freedom of layout design and improve the reliability of interconnect structures.

[0008] According to one aspect of the present invention, an IC device is provided, the IC device comprising: a peripheral circuit structure; a memory stack including a plurality of gate lines on the peripheral circuit structure that overlap with the peripheral circuit structure in a vertical direction; an upper substrate located between the peripheral circuit structure and the memory stack, the upper substrate including a via located below a memory cell region of the memory stack; a word line dicing region extending longitudinally across the memory stack and the via in a first lateral direction; and a common source line located in the word line dicing region, the common source line including a first portion and a second portion, the first portion extending longitudinally in the first lateral direction on the upper substrate, the second portion being integrally connected to the first portion, the second portion penetrating the upper substrate through the via from the upper part of the upper substrate and extending into the peripheral circuit structure.

[0009] According to one aspect of the present invention, an IC device is provided, the IC device comprising: a peripheral circuit structure including a plurality of circuits, a plurality of peripheral circuit conductive interconnect layers connected to the plurality of circuits, and a floating conductive interconnect layer laterally spaced from the plurality of peripheral circuit conductive interconnect layers; an upper substrate located on the peripheral circuit structure, the upper substrate including a first via formed at a position overlapping the floating conductive interconnect layer in a vertical direction; a memory stack having a memory cell region covering the first via and a connection step region located on one side of the memory cell region, the memory stack including a plurality of gate lines spaced vertically from the peripheral circuit structure, the upper substrate being interposed between the plurality of gate lines and the peripheral circuit structure; a plurality of word line dicing regions extending longitudinally across the memory stack and the first via in a first lateral direction, each of the plurality of word line dicing regions including a portion penetrating the upper substrate in a vertical direction through the first via; and a plurality of first through electrodes penetrating the plurality of gate lines in a vertical direction in the memory cell region and extending through the first via to the plurality of peripheral circuit conductive interconnect layers.

[0010] According to one aspect of the present invention, an IC device is provided, the IC device comprising: a peripheral circuit structure including a lower substrate, and a plurality of peripheral circuit conductive interconnect layers and a floating conductive interconnect layer formed on the lower substrate; a memory cell region including a plurality of gate lines disposed on the peripheral circuit structure; an upper substrate located between the peripheral circuit structure and the memory cell region, and including a via formed at a location within the memory cell region; a common source electrode line including a first portion and a second portion, the first portion extending longitudinally in a first lateral direction across the memory cell region and the via, the first portion contacting the upper substrate, the second portion integrally connected to the first portion, and extending from the upper portion of the upper substrate through the via to the floating conductive interconnect layer; an insulating structure passing through the plurality of gate lines in the memory cell region and extending in a vertical direction; a buried insulating film filling the via; and at least one through electrode passing through the insulating structure and the buried insulating film and extending longitudinally in a vertical direction to at least one peripheral circuit conductive interconnect layer selected from the plurality of peripheral circuit conductive interconnect layers. Attached Figure Description

[0011] The embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram of an integrated circuit (IC) device according to an embodiment;

[0013] Figure 2 This is a schematic perspective view of an IC device according to an embodiment;

[0014] Figure 3This is an equivalent circuit diagram of the memory cell array of an IC device according to an embodiment;

[0015] Figure 4 This is a schematic plan view of an IC device according to an embodiment;

[0016] Figure 5A It is along Figure 4 A cross-sectional view of some components cut by line X1-X1';

[0017] Figure 5B It is along Figure 4 A cross-sectional view of some components cut by line Y1-Y1';

[0018] Figure 5C yes Figure 4 A plan view of some components of the IC device shown;

[0019] Figure 6 This is a schematic plan view of an IC device according to an embodiment;

[0020] Figure 7 yes Figure 6 A plan view of some components of the IC device shown;

[0021] Figure 8 This is a cross-sectional view of an IC device according to an embodiment;

[0022] Figure 9 This is a plan view of an IC device according to an embodiment;

[0023] Figure 10 yes Figure 9 A plan view of some components of the IC device shown;

[0024] Figure 11 This is a plan view of an IC device according to an embodiment;

[0025] Figure 12 yes Figure 11 A plan view of some components of the IC device shown;

[0026] Figure 13 This is a plan view of an IC device according to an embodiment;

[0027] Figure 14 yes Figure 13 A plan view of some components of the IC device shown; and Figures 15A to 19A and Figures 15B to 19B This is a cross-sectional view illustrating the process sequence of a method for manufacturing an IC device according to an embodiment, wherein, Figures 15A to 19A It is with along Figure 4 The cross-sectional view of some components in the corresponding part of the section cut by line X1-X1' according to the process sequence, and Figures 15B to 19BIt is with along Figure 4 A cross-sectional view of some components in the process sequence corresponding to the section cut by line Y1-Y1'. Detailed Implementation

[0028] The embodiments will now be described more fully with reference to the accompanying drawings, which illustrate some embodiments. Throughout the drawings, the same reference numerals are used to denote the same elements, and repeated descriptions thereof will be omitted.

[0029] Figure 1 This is a block diagram of an integrated circuit (IC) device 10 according to an embodiment.

[0030] Reference Figure 1 The IC device 10 may include a memory cell array 20 and peripheral circuitry 30. The memory cell array 20 may include multiple memory cell blocks BLK1, BLK2, ..., and BLKn. Each of the multiple memory cell blocks BLK1, BLK2, ..., and BLKn may include multiple memory cells. The memory cell blocks BLK1, BLK2, ..., and BLKn may be connected to the peripheral circuitry 30 via bit lines BL (e.g., multiple bit lines), word lines WL (e.g., multiple word lines), serial select lines SSL (e.g., multiple serial select lines), and ground select lines GSL (e.g., multiple ground select lines).

[0031] The peripheral circuitry 30 may include a line decoder 32, a page buffer 34, data input / output (I / O) circuitry 36, and control logic 38. Although Figure 1 Although not shown in the diagram, the peripheral circuitry 30 may also include an input / output (I / O) interface, column logic, a voltage generator, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and an amplifier circuit.

[0032] The memory cell array 20 can be connected to the page buffer 34 via bit lines BL and to the row decoder 32 via word lines WL, string select lines SSL, and ground select lines GSL. In the memory cell array 20, each of the plurality of memory cells included in each of the plurality of memory cell blocks BLK1, BLK2, ..., and BLKn can be a flash memory cell. The memory cell array 20 can be a three-dimensional (3D) memory cell array. A 3D memory cell array can include a plurality of NAND strings, each of which can include memory cells respectively connected to a plurality of word lines WL stacked vertically on a substrate. In an example embodiment, the memory cell array 20 can include, as will be referred to below... Figure 4 and Figure 5B The memory stack described is MS.

[0033] The peripheral circuit 30 can receive address ADDR, command CMD, and control signal CTRL from outside the IC device 10, and can send data DATA to and receive data DATA from devices located outside the IC device 10. For example, the IC device can be a semiconductor chip, such as a memory chip.

[0034] The row decoder 32 can select at least one of a plurality of memory cell blocks BLK1, BLK2, ..., and BLKn in response to an address ADDR received from an external source, and select the word line WL, serial select line SSL, and ground select line GSL of the selected memory cell block. The row decoder 32 can send a voltage for performing memory operations to the word line WL of the selected memory cell block.

[0035] Page buffer 34 can be connected to memory cell array 20 via bit line BL. During programming operations, page buffer 34 can operate as a write driver, applying a voltage corresponding to the data DATA to be stored in memory cell array 20 to bit line BL. During read operations, page buffer 34 can operate as a sense amplifier, sensing the data DATA stored in memory cell array 20. Page buffer 34 can operate in response to control signal PCTL provided from control logic 38.

[0036] Data I / O circuit 36 ​​can be connected to page buffer 34 via data line DL. During programming operations, data I / O circuit 36 ​​can receive data DATA from the memory controller (not shown) and can provide programming data DATA to page buffer 34 based on the column address C_ADDR provided from control logic 38. During read operations, data I / O circuit 36 ​​can provide read data DATA stored in page buffer 34 to the memory controller based on the column address C_ADDR provided from control logic 38.

[0037] The data I / O circuit 36 ​​can send the received address or instruction to the control logic 38 or the line decoder 32. The peripheral circuit 30 of the IC device 10 may also include an electrostatic discharge (ESD) circuit and a pull-up / pull-down driver.

[0038] Control logic 38 can receive commands CMD and control signals CTRL from the memory controller. Control logic 38 can provide the row address R_ADDR to the row decoder 32 and the column address C_ADDR to the data I / O circuit 36. Control logic 38 can generate various internal control signals used in the IC device 10 in response to the control signal CTRL. For example, control logic 38 can adjust the voltage levels supplied to the word line WL and bit line BL during memory operations such as programming or erasing operations.

[0039] Figure 2 This is a perspective view of the IC device 10 according to an embodiment.

[0040] Reference Figure 2 The IC device 10 may include a cell array structure CAS and a peripheral circuit structure PCS that overlap (e.g., stack) each other in the vertical direction (Z direction). The cell array structure CAS may include reference... Figure 1 The memory cell array 20 is described. The peripheral circuitry PCS may include references... Figure 1 The peripheral circuit 30 is described. The cell array structure CAS can be described as a cell array layer, and the peripheral circuit structure PCS can be described as a peripheral circuit layer. The cell array layer can be formed on the peripheral circuit layer (e.g., stacked on the peripheral circuit layer in the vertical direction), and each of the cell array layer and the peripheral circuit layer can include various components forming a sublayer.

[0041] The cell array structure CAS may include at least one pad MAT, each of which may include multiple memory cell blocks BLK1, BLK2, ..., and BLKn. Each of the multiple memory cell blocks BLK1, BLK2, ..., and BLKn may include memory cells arranged in three dimensions.

[0042] Figure 3 This is an equivalent circuit diagram of the memory cell array (MCA) of an IC device according to an embodiment. Figure 3 An equivalent circuit diagram of a vertical NAND (V-NAND) flash memory device with a vertical channel structure is shown as an example. Figure 2 Each of the multiple memory cell blocks BLK1, BLK2, ..., and BLKn shown may include Figure 3 The memory cell array MCA shown is shown.

[0043] Reference Figure 3 A memory cell array (MCA) may include multiple memory cell strings (MS). The MCA may include multiple bit lines BL (or BL1, BL2, ..., and BLm), multiple word lines WL (or WL1, WL2, ..., WLn-1 and WLn), at least one string select line SSL, at least one ground select line GSL, and a common-source line CSL. Multiple memory cell strings (MS) may be formed between the multiple bit lines BL (or BL1, BL2, ..., and BLm) and the common-source line CSL.

[0044] Each of the multiple memory cell strings MS may include a string select transistor SST, a ground select transistor GST, and multiple memory cell transistors MC1, MC2, ..., MCn-1 and MCn. The drain regions of the multiple string select transistors SST may be connected to bit lines BL (or BL1, BL2, ..., and BLm), and the source regions of the multiple ground select transistors GST may be connected to the common-source line CSL. The common-source line CSL may be the region to which the source regions of the multiple ground select transistors GST are commonly connected.

[0045] The serial select transistor SST can be connected to the serial select line SSL, and the ground select transistor GST can be connected to the ground select line GSL. Multiple memory cell transistors MC1, MC2, ..., MCn-1 and MCn can be connected to multiple word lines WL (or WL1, WL2, ..., WLn-1 and WLn), respectively.

[0046] Figure 4 This is a plan view of the IC device 100 according to an embodiment. Figure 5A It is along Figure 4 A cross-sectional view of some components cut off by line X1-X1'. Figure 5B It is along Figure 4 A cross-sectional view of some components cut by line Y1-Y1'. Figure 5C yes Figure 4 The diagram shows a plan view of the upper substrate 110, multiple word line cut regions (WLC), and multiple through-hole electrodes (THV) of the IC device 100.

[0047] Reference Figure 4 and Figures 5A to 5C IC device 100 can constitute a reference Figure 1 and Figure 2 This describes a portion of an IC device 10. The IC device 100 may include a peripheral circuit structure PCS and a cell array structure CAS, the cell array structure CAS being disposed on the peripheral circuit structure PCS and overlapping the peripheral circuit structure PCS in the vertical direction (Z direction). The cell array structure CAS may include an upper substrate 110 formed on the peripheral circuit structure PCS and a memory stack MS located on the upper substrate 110. In an example embodiment, the upper substrate 110 may include a semiconductor film. For example, the upper substrate 110 may include a polycrystalline silicon film.

[0048] The memory stack MS may include memory cell areas (see reference) Figure 4 and Figure 5C (120 in the middle). Memory cell area 120 may include references Figure 2The description includes multiple memory cell blocks BLK1, BLK2, ..., and BLKn. The memory stack MS may include multiple gate stacks GS. Each of the multiple gate stacks GS may include multiple gate lines 130 extending laterally parallel to each other and overlapping each other in the vertical direction (Z direction) within the memory cell region 120. Each of the multiple gate lines 130 may include a metal, a metal silicide, a doped semiconductor, or a combination thereof. For example, each of the multiple gate lines 130 may include a metal (such as tungsten, nickel, cobalt, and tantalum), a metal silicide (such as tungsten silicide, nickel silicide, cobalt silicide, and tantalum silicide), doped polysilicon, or a combination thereof.

[0049] An insulating film 134 can be disposed between the upper substrate 110 and the plurality of gate lines 130, as well as between adjacent gate lines 130 among the plurality of gate lines 130. The top surface of the uppermost gate line 130 among the plurality of gate lines 130 can also be covered by the insulating film 134. For example, the insulating film 134 may comprise silicon oxide.

[0050] like Figure 5B As shown, a plurality of common source regions 172 can be formed in the upper substrate 110. The plurality of common source regions 172 can extend longitudinally in a first lateral (X-direction). In an example embodiment, the plurality of common source regions 172 can be impurity regions heavily doped with n-type impurities. The plurality of common source regions 172 can be used as source regions configured to supply current to vertical memory cells. An item, layer, or portion thereof described as extending “longitudinally” in a particular direction has a length in that particular direction and a width perpendicular to that direction, wherein the length is greater than the width.

[0051] Multiple word line cut regions (WLCs) (also described as word line separation regions) may intersect with memory stacks MS on the upper substrate 110 and extend in a first lateral direction (X direction). The width of multiple gate stacks GS in a second lateral direction (Y direction) may be defined by the multiple word line cut regions WLCs. Multiple gate lines 130 may be separated from each other (e.g., in the Y direction) by the multiple word line cut regions WLCs and may be arranged at regular intervals.

[0052] Each of the multiple word line cut regions (WLCs) may be filled with a common source electrode structure 140. The common source electrode structure 140 may include a common source electrode CSL and insulating spacers 144 covering the sidewalls of the common source electrode CSL within the word line cut region (WLC). Each of the multiple common source electrode CSLs may include a metal (such as tungsten, copper, or aluminum), a conductive metal nitride (such as titanium nitride and tantalum nitride), a transition metal (such as titanium and tantalum), or a combination thereof. The insulating spacers 144 may include silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. For example, the insulating spacers 144 may include a silicon oxide film, a silicon nitride film, silicon oxynitride (SIN), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), or a combination thereof.

[0053] Multiple gate lines 130, including in a gate stack GS, can be stacked on the upper substrate 110 to overlap each other in the vertical direction (Z direction) between two adjacent word line cut regions (WLCs). Multiple gate lines 130 including in a gate stack GS can form a reference. Figure 3 The description includes the ground select line GSL, multiple word lines WL, and string select line SSL. From the multiple gate lines 130 included in a gate stack GS, each of the two uppermost gate lines 130 can be divided into two parts in a second lateral (Y direction) direction, and has a string select line cut-off region SSLC between these two parts. In the gate stack GS, the two separate parts of each of the two uppermost gate lines 130, each having a string select line cut-off region SSLC between them, can each constitute a reference. Figure 3 The described string select line is SSL. Although Figure 4 and Figure 5B An example is shown in which a string select line cut region (SSLC) is formed in a gate stack GS, but the inventive concept is not limited thereto. For example, at least two SSLCs may be formed in a gate stack GS. The SSLC may be filled with an insulating film 150. The insulating film 150 may include an oxide film, a nitride film, or a combination thereof. In the example embodiment, at least a portion of the SSLC may be filled with an air gap.

[0054] Multiple channel structures 160 can pass through multiple gate lines 130 and extend in the vertical direction (Z direction) in the memory cell region 120 on the upper substrate 110. The multiple channel structures 160 can be arranged at predetermined distances from each other in the first lateral direction (X direction) and the second lateral direction (Y direction).

[0055] Each of the plurality of channel structures 160 may include a gate dielectric film 162, a channel region 164, a buried insulating film 166, and a drain region 168. The gate dielectric film 162 may have a structure in which a tunneling dielectric film, a charge storage film, and a barrier dielectric film are sequentially formed on the channel region 164. The channel region 164 may include doped or undoped polysilicon. The channel region 164 may be cylindrical. The interior space of the channel region 164 may be filled with the buried insulating film 166. The buried insulating film 166 may include an insulating material. For example, the buried insulating film 166 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the buried insulating film 166 may be omitted.

[0056] In this configuration, the channel region 164 can have a pillar structure without internal space. The drain region 168 may comprise a doped polysilicon film. Multiple drain regions 168 may be insulated from each other by an upper insulating film 169. The upper insulating film 169 may comprise an oxide film, a nitride film, or a combination thereof.

[0057] like Figure 4 As shown, in the CAS cell array structure, the memory cell area 120 may include multiple normal cell areas 120N and one pseudo cell area 120D. Figure 4 An example is shown in which a memory cell region 120 includes two normal cell regions 120N and one pseudo cell region 120D. The pseudo cell region 120D may extend in a second lateral direction (Y direction) between the two normal cell regions 120N. The two normal cell regions 120N may be spaced apart from each other and have the pseudo cell region 120D between them. However, the number and arrangement of the normal cell regions 120N and the pseudo cell regions 120D are not limited to this. Figure 4 The example shown is not representative of the inventive concept and can be modified and changed in various ways.

[0058] In the normal cell region 120N, multiple bit lines BL are arranged on multiple channel structures 160. The multiple bit lines BL can be arranged parallel to each other and extend longitudinally in the second lateral (Y direction). In the normal cell region 120N, each of the multiple channel structures 160 can be connected to a corresponding bit line BL via a contact pad (not shown). Among the multiple channel structures 160, the multiple channel structures 160 arranged between the string select line cut-out region SSLC and the word line cut-out region WLC in the normal cell region 120N can be normal channel structures. Among the multiple channel structures 160, the channel structure (not shown) overlapping with the string select line cut-out region SSLC and the channel structure 160 arranged in the pseudo cell region 120D can be a pseudo channel structure. Pseudo channel structures, as discussed herein, can have a similar or identical physical structure to normal channel structures, but they are not used as channels. For example, those discussed above and Figure 4As shown, in some embodiments, the pseudo-channel structures are not connected to any bit lines, so that bit line voltages can not be applied to these structures, and these structures cannot be used to store data in the same way as normal channel structures.

[0059] like Figures 5A to 5C As shown, the upper substrate 110 may include a via 110H. The via 110H of the upper substrate 110 may be located below the memory cell region 120. The via 110H may be located below the dummy cell region 120D in the memory cell region 120. The via 110H may be filled with a buried insulating film 112. In an example embodiment, the buried insulating film 112 may include a silicon oxide film.

[0060] In the pseudo-cell region 120D, an insulating structure 170 may be disposed on the upper substrate 110. The insulating structure 170 may pass through multiple gate lines 130 and multiple insulating films 134 included in the gate stack GS, and extend in the vertical direction (Z direction). In an example embodiment, the insulating structure 170 may include a silicon oxide film.

[0061] At least one of the multiple word line cut regions (WLCs) may intersect with the memory stack MS and the via 110H, and extend longitudinally in the first lateral direction (X direction). At least one word line cut region (WLC) may include a portion extending longitudinally in the first lateral direction (X direction) on the main surface 110M of the upper substrate 110 and a portion penetrating the upper substrate 110 in the vertical direction (Z direction) through the via 110H formed in the upper substrate 110.

[0062] like Figure 5A and Figure 5B As shown, at least one of the multiple common-source lines (CSLs) filling multiple word line cut regions (WLCs) may include a first portion CSL1 and a second portion CSL2. The first portion CSL1 may extend longitudinally in a first lateral direction (X direction) on the main surface 110M of the upper substrate 110. The second portion CSL2 may be integrally connected to the first portion CSL1, for example, to form a continuous material. The second portion CSL2 may penetrate the upper substrate 110 through a via 110H in the vertical direction (Z direction) and extend into the peripheral circuit structure (PCS). In the common-source line CSL, the length of the second portion CSL2 in the vertical direction (Z direction) may be greater than the length of the first portion CSL1 in the vertical direction (Z direction).

[0063] The second portion CSL2 of the common source line CSL may not overlap with the upper substrate 110 in the vertical direction (Z direction). The second portion CSL2 of the common source line CSL may pass through the upper insulating film 169, the insulating structure 170 and the buried insulating film 112, and extend into the peripheral circuit structure PCS in the vertical direction (Z direction).

[0064] Figure 4 and Figures 5A to 5C An exemplary configuration is shown in which each of the two word line cut regions (WLCs) includes a portion extending across a via 110H formed in the upper substrate 110, and each of the two common source lines (CSLs) filling the two word line cut regions (WLCs) includes a second portion (CSL2) penetrating the upper substrate 110 through the via 110H. However, the inventive concept is not limited thereto. In an example embodiment, only one of the plurality of word line cut regions (WLCs) may extend across the via 110H formed in the upper substrate 110, and only one common source line (CSL) filling one word line cut region (WLC) may include a second portion (CSL2) penetrating the upper substrate 110 through the via 110H and extending into the peripheral circuit structure (PCS). In other example embodiments, at least three of the plurality of word line cut regions (WLCs) may extend across vias 110H formed in the upper substrate 110, and at least three common source lines (CSLs) filling the at least three word line cut regions (WLCs) may include a second portion (CSL2) extending through the vias 110H through the upper substrate 110 and into the peripheral circuit structure (PCS). The second portion (CSL2) of the common source line (CSL) may be laterally spaced from the upper substrate 110 and have a buried insulating film 112 between them.

[0065] In the pseudo-cell region 120D, multiple through-electrodes THV can pass through the gate stack GS of the cell array structure CAS, penetrate the upper substrate 110 through via 110H, and extend longitudinally in the vertical direction (Z direction) into the peripheral circuit structure PCS. Each of the multiple through-electrodes THV can be surrounded by the upper insulating film 169 and the insulating structure 170 in the cell array structure CAS and by the buried insulating film 112 in the via 110H of the upper substrate 110.

[0066] Although Figure 5C Only one via 110H formed in the upper substrate 110 is shown, but multiple vias 110H can be formed in the upper substrate 110. Although Figure 4 and Figure 5C An example is shown in which five through-electrode THVs pass through an insulating structure 170 and a via 110H, but the number of through-electrode THVs passing through an insulating structure 170 and a via 110H is not limited to this. Figure 4 and Figure 5C As shown in the example, and within the scope of the inventive concept, the number and size of the through-electrode THV can vary.

[0067] As the number of gate lines 130 stacked in the vertical direction (Z direction) in the memory stack MS formed on the upper substrate 110 increases, the design rules for ensuring a minimum separation distance between the plurality of through-electrodes THV penetrating the upper substrate 110 through vias 110H and the upper substrate 110 may become more stringent. A stable separation distance greater than or equal to the minimum separation distance required by the design rules can be ensured between the plurality of through-electrodes THV penetrating the upper substrate 110 through vias 110H and the upper substrate 110. In an example embodiment, a separation distance selectable in the range of about 0.01 μm to about 1.5 μm can exist between the plurality of through-electrodes THV penetrating the upper substrate 110 through vias 110H and the upper substrate 110.

[0068] According to a specific embodiment, the second portion CSL2 of the common source line CSL that intersects with the via 110H and penetrates the upper substrate 110 through the via 110H does not overlap with the upper substrate 110 in the vertical direction (Z direction).

[0069] like Figure 5A and Figure 5B As shown, the peripheral circuit structure PCS may include a lower substrate 52, a plurality of circuit CTs formed on the main surface 52M of the lower substrate 52, and a multilayer interconnect structure MWS. Each of the plurality of through electrodes THV can be connected to at least one of the plurality of circuit CTs through the multilayer interconnect structure MWS included in the peripheral circuit structure PCS, and can be connected between those circuits and circuits or wiring above the cell array structure CAS of the integrated circuit device 10 (e.g., connected to a controller).

[0070] The lower substrate 52 may include a semiconductor substrate. For example, the lower substrate 52 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). An active region AC may be defined by a device isolation film 54 in the lower substrate 52. Multiple circuit CTs may be included in the reference... Figure 1 Various circuits in the described peripheral circuitry 30. In an example embodiment, the plurality of circuits CT may include unit elements such as resistors and capacitors. A plurality of transistors TR5 included in the plurality of circuits CT may be formed on the active region AC. Each of the plurality of transistors TR5 may include a gate PG and a source / drain region PSD formed on both sides of the gate PG in the active region AC.

[0071] The multilayer interconnect structure (MWS) may include multiple peripheral circuit interconnect layers (e.g., ML60, ML61, ML62, and ML66) connected to multiple circuit CTs, multiple peripheral circuit contacts (e.g., MC60, MC61, and MC62), and a floating interconnect layer ML68 spaced apart from the peripheral circuit interconnect layers ML60, ML61, ML62, and ML66 and the peripheral circuit contacts MC60, MC61, and MC62. The floating interconnect layer ML68 may be formed at the same level as the uppermost peripheral circuit interconnect layers ML62 and ML66 closest to the upper substrate 110 among the peripheral circuit interconnect layers ML60, ML61, ML62, and ML66. Here, the term "level" refers to the distance relative to the top surface of the lower substrate 52 in the vertical direction (Z-direction or -Z-direction). The peripheral circuit interconnect layers ML60, ML61, ML62, and ML66 may be referred to as peripheral circuit conductive interconnect patterns, and the floating interconnect layer ML68 may be referred to as a floating conductive interconnect pattern. Peripheral circuit conductive interconnect patterns and floating conductive interconnect patterns can be formed in the same vertical layer in a multilayer interconnect structure (MWS).

[0072] Some of the peripheral circuit interconnect layers ML60, ML61, ML62, and ML66 are electrically connected to multiple transistors TR5. Peripheral circuit contacts MC60, MC61, and MC62 can connect to some of the peripheral circuit interconnect layers selected from ML60, ML61, ML62, and ML66 (e.g., ML60, ML61, ML62, and ML66). The lower end of each of the through electrodes THV can connect to some of the outermost peripheral circuit interconnect layers ML62 and ML66 closest to the upper substrate 110 (e.g., ML66). The second portion CSL2 of the common source line CSL, which penetrates the upper substrate 110 through via 110H and extends to the peripheral circuit structure PCS, can be connected to the floating interconnect layer ML68. The floating interconnect layer ML68 may not be connected to any conductive material other than the common source line CSL that contacts the top surface of the floating interconnect layer ML68. The floating interconnect layer ML68 may be part of the peripheral circuit structure PCS, but may not contact any other conductive components of the peripheral circuit structure PCS. The floating interconnect layer ML68 may be electrically isolated from the circuitry disposed in the peripheral circuit structure PCS. During operation of the IC device 100, the floating interconnect layer ML68 may have the same electrical bias as a common source line CSL in contact with the top surface of the floating interconnect layer ML68.

[0073] Each of the plurality of peripheral circuit interconnect layers ML60, ML61, ML62 and ML66, the plurality of peripheral circuit contacts MC60, MC61 and MC62, and the floating interconnect layer ML68 may include a conductive material, such as a metal, a conductive metal nitride, a metal silicide, or a combination thereof. For example, each of the plurality of peripheral circuit interconnect layers ML60, ML61, ML62 and ML66, the plurality of peripheral circuit contacts MC60, MC61 and MC62, and the floating interconnect layer ML68 may include a conductive material, such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, nickel silicide, etc. Although Figure 5A and Figure 5B An example of a multilayer interconnect structure (MWS) comprising three interconnect layers in the vertical direction (Z direction) is shown, but the inventive concept is not limited thereto. Figure 5A and Figure 5B The example shown. For instance, a multilayer interconnect structure (MWS) may include two, four, or more interconnect layers.

[0074] Multiple circuit CTs, peripheral circuit interconnect layers ML60, ML61, ML62 and ML66, peripheral circuit contacts MC60, MC61 and MC62, and floating interconnect layer ML68 may be covered by interlayer insulating film 70. Multiple through-hole electrodes THV may pass through a portion of interlayer insulating film 70 and contact the top surface of peripheral circuit interconnect layer ML66. The term "contact" or "in contact with" as used herein refers to a direct connection (e.g., touching). A second portion CSL2 of the common source line CSL, penetrating the upper substrate 110 via via 110H and extending into the peripheral circuit structure PCS, may pass through a portion of interlayer insulating film 70 and contact the top surface of floating interconnect layer ML68. Interlayer insulating film 70 may include silicon oxide, SiON, SiOCN, etc.

[0075] Figure 6 This is a plan view of the IC device 100A according to an embodiment. Figure 7 yes Figure 6 The diagram shows the upper substrate 110, multiple word line cut regions (WLC), and multiple through electrodes (THV) of the IC device 100A.

[0076] Reference Figure 6 and Figure 7 IC device 100A may have the same characteristics as the reference. Figure 4 and Figures 5A to 5CThe IC device 100 described has a substantially identical construction. However, the IC device 100A may include a pair of connection step regions 122C located on opposite sides of the memory cell region 120 in a first lateral direction (X direction) and a pair of pseudo step regions 122D located on opposite sides of the memory cell region 120 in a second lateral direction (Y direction). In the pair of connection step regions 122C and the pair of pseudo step regions 122D, the width of the plurality of gate lines 130 in the first lateral direction (X direction) and the second lateral direction (Y direction) may gradually decrease in a direction away from the upper substrate 110. Each of the plurality of gate stacks GS may include a plurality of gate lines 130 that extend horizontally parallel above the memory cell region 120 and the connection step regions 122C and overlap each other in the vertical direction (Z direction).

[0077] Figure 8 This is a cross-sectional view of the IC device 200 according to an embodiment. Figure 8 It shows the relationship with along Figure 4 The cross-sectional structure of some components in the area corresponding to the section cut by line Y1-Y1'.

[0078] Reference Figure 8 IC device 200 may have the same characteristics as referenced Figure 4 and Figures 5A to 5C The IC device 100 described has a substantially the same construction. However, the IC device 200 may include an insulating structure 270 instead of the insulating structure 170. The insulating structure 270 may overlap with the buried insulating film 112 filling the via 110H of the substrate 110 in the vertical direction (Z direction). The insulating structure 270 may be... Figure 8 The dashed area 2Y corresponds to this. The insulating structure 270 may have a multilayer structure, comprising a plurality of first insulating films 272 and a plurality of second insulating films 274 alternately stacked on the embedded insulating film 112. The plurality of first insulating films 272 may comprise the same material as that included in the insulating film 134. The plurality of second insulating films 274 may comprise a different material than that included in the insulating film 134. For example, the plurality of first insulating films 272 may comprise a silicon oxide film, and the plurality of second insulating films 274 may comprise a silicon nitride film. The top surface of the insulating structure 270 may be covered by the upper insulating film 169.

[0079] Figure 9 This is a plan view of the IC device 300 according to an embodiment. Figure 10 yes Figure 9 The diagram shows the upper substrate 110, multiple word line cut regions (WLC), and multiple through electrodes (THV3) of the IC device 300.

[0080] Reference Figure 9 and Figure 10IC device 300 may have the same characteristics as referenced. Figure 6 and Figure 7 The IC device 100A described has a substantially the same structure. However, a via 310H may be formed at the location of the dummy cell region 120D of the memory cell region 120 having the IC device 300 in the upper substrate 110. The via 310H may intersect with at least two gate stacks GS and extend in the second lateral direction (Y direction).

[0081] The insulating structure 370 may be located on the upper substrate 110 at a position overlapping the via 310H in the vertical direction (Z direction). The insulating structure 370 may have the same characteristics as the reference. Figure 4 and Figure 5B The insulation structure described is 170 or as referenced. Figure 8 The insulation structure described is the same as that of 270.

[0082] Three of the multiple word line cut regions WLC can intersect with the via 310H formed in the upper substrate 110 and extend in the first lateral direction (X direction).

[0083] IC device 300 may include a plurality of through electrodes THV3 extending vertically (Z direction) through via 310H. Figure 5B Similar to the punch-through electrodes THV shown, each of the plurality of punch-through electrodes THV3 can pass through multiple gate lines 130 in the dummy cell region 120D, penetrate the upper substrate 110 through via 310H, and extend longitudinally in the vertical direction (Z direction) into the peripheral circuit structure PCS. The upper substrate 110 may not be located between the corresponding punch-through electrodes THV3. Some of the plurality of punch-through electrodes THV3 may be spaced apart from each other and have a word line cut-out region WLC between them.

[0084] Each of the multiple through-electrodes THV3 can be surrounded by an insulating structure 370 in the unit array structure CAS. Figure 5B Similar to the punch-through electrode THV shown, multiple punch-through electrodes THV3 can be connected to at least one of multiple circuit CTs through the peripheral circuit interconnect layer ML66 in the peripheral circuit structure PCS.

[0085] The plurality of through-electrodes THV3 may include two through-electrodes THV3 spaced apart from each other and having a word line cut region WLC intersecting the via 310H between them. Some of the plurality of through-electrodes THV3 passing through the via 310H may be spaced apart from the other through-electrodes THV3 and have a second portion of a common source line CSL intersecting the via 310H between the plurality of through-electrodes THV3 and the other through-electrodes THV3 (see reference). Figure 5A(CSL2 in the via). Since the second part of the common source electrode line CSL2 does not overlap with the upper substrate 110 in the vertical direction (Z direction), a stable separation distance greater than or equal to the minimum separation distance required by the design rules can be easily ensured between the upper substrate 110 and the multiple through electrodes THV3. Therefore, the degree of freedom in the layout design of the multiple through electrodes THV3 passing through a via 310H can be increased.

[0086] Although Figure 10 An example is shown in which a single via 310H is formed in the upper substrate 110, but multiple vias 310H can be formed in the upper substrate 110. The number of through electrodes THV3 passing through a single via 310H is not limited to this. Figure 9 and Figure 10 The example shown is not representative of the inventive concept and can be modified in various ways.

[0087] Figure 11 This is a plan view of the IC device 400 according to an embodiment. Figure 12 yes Figure 11 The diagram shows a plan view of the upper substrate 110, multiple word line cut regions (WLC), and multiple through electrodes (THV4) of the IC device 400.

[0088] Reference Figure 11 and Figure 12 IC device 400 may have the same characteristics as referenced. Figure 6 and Figure 7 The IC device 100A described has a substantially the same structure. However, a via 410H can be formed in the upper substrate 110 of the dummy cell region 120D in the memory cell region 120 of the IC device 400. The via 410H can extend longitudinally across the memory cell region 120 in a second lateral (Y direction). The memory cell region 120 can include two normal cell regions 120N separated from each other by the via 410H.

[0089] The insulating structure 470 can be arranged on the upper substrate 110 in the vertical direction (Z direction) at a position overlapping with the through-hole 410H. The insulating structure 470 can have the same characteristics as the reference. Figure 4 and Figure 5B The insulation structure described is 170 or as referenced. Figure 8 The insulation structure described is the same as that of 270.

[0090] The multiple word line cut regions WLC located on the upper substrate 110 can all intersect with the vias 410H formed in the upper substrate 110 and extend in the first lateral direction (X direction).

[0091] IC device 400 may include a plurality of through electrodes THV4 extending in the vertical direction (Z direction) via through-hole 410H. Figure 5B Similar to the punch-through electrodes THV shown, each of the plurality of punch-through electrodes THV4 can pass through multiple gate lines 130 in the dummy cell region 120D, penetrate the upper substrate 110 through via 410H, and extend longitudinally in the vertical direction (Z direction) into the peripheral circuit structure PCS. The upper substrate 110 may not be located between each of the plurality of punch-through electrodes THV4.

[0092] Each of the multiple through-electrodes THV4 can be surrounded by an insulating structure 470 in the unit array structure CAS. Figure 5B Similar to the punch-through electrode THV shown, multiple punch-through electrodes THV4 can be connected to at least one of multiple circuits via a peripheral circuit interconnect layer ML66 included in the peripheral circuit structure PCS.

[0093] The plurality of through-electrodes THV4 may include two through-electrodes THV4 spaced apart from each other and having a word line cut region WLC intersecting the via 410H between them. Some of the plurality of through-electrodes THV4 passing through the via 410H may be spaced apart from the other through-electrodes THV4, and some of the plurality of through-electrodes THV4 have a second portion of a common source line CSL intersecting the via 410H between them (see [link to documentation]). Figure 5A (CSL2 in the via). Since the second part of the common source electrode line CSL2 does not overlap with the upper substrate 110 in the vertical direction (Z direction), a stable separation distance greater than or equal to the minimum separation distance required by the design rules can be easily ensured between the upper substrate 110 and the multiple through electrodes THV4. Therefore, the degree of freedom in the layout design of the multiple through electrodes THV4 passing through a via 410H can be increased.

[0094] The number of through electrodes THV4 passing through insulating structure 470 and through hole 410H is not limited to Figure 11 and Figure 12 The example shown, and the number and size of the through electrodes THV4 can be varied within the scope of the inventive concept.

[0095] Figure 13 This is a plan view of the IC device 500 according to an embodiment. Figure 14 yes Figure 13 The diagram shows the upper substrate 110, multiple word line cut regions (WLC), multiple first through-electrodes THV51, and multiple first through-electrodes THV52 of the IC device 300.

[0096] Reference Figure 13 and Figure 14 IC device 500 may have the same characteristics as referenced Figure 6 and Figure 7The IC device 100A described has a substantially the same construction. However, the IC device 500 may include a pair of connecting step regions 522C located on opposite sides of the memory cell region 120 in the first lateral (X direction).

[0097] A first via 510H1 can be formed at the location of the dummy cell region 120D facing the memory cell region 120 in the upper substrate 510. A plurality of second vias 510H2 can be formed in at least one of a pair of connecting step regions 522C in the upper substrate 510. Although Figure 13 and Figure 14 An example is shown in which a plurality of second through holes 510H2 are formed in only one of a pair of connecting step regions 522C, but the inventive concept is not limited thereto, and a plurality of second through holes 510H2 may be formed in each of the pair of connecting step regions 522C.

[0098] A first insulating structure 572 can be provided on the upper substrate 510 at a position overlapping with the first via 510H1 in the vertical direction (Z direction), and a second insulating structure 574 can be provided at each of a plurality of positions on the upper substrate 510 overlapping with a plurality of second vias 510H2 in the vertical direction (Z direction). In an example embodiment, the upper substrate 510, the first insulating structure 572, and the second insulating structure 574 may have the same characteristics as a reference. Figure 4 and Figures 5A to 5C The upper substrate 110 and insulating structure 170 described are identical in construction. In other example embodiments, each of the first insulating structure 572 and the second insulating structure 574 may have the same construction as described above. Figure 8 The insulation structure described is the same as that of 270.

[0099] The IC device 500 may include a plurality of first through-electrodes THV51, which pass through multiple gate lines 130 in the dummy cell region 120D, penetrate the upper substrate 510 through a first via 510H1, and extend vertically (Z-direction) into the peripheral circuit structure PCS. Additionally, the IC device 500 may include a plurality of second through-electrodes THV52, which pass through multiple gate lines 130 in the connecting step region 522C, penetrate the upper substrate 510 through a second via 510H2, and extend longitudinally (Z-direction) into the peripheral circuit structure PCS.

[0100] Each of the plurality of first through-electrodes THV51 may be surrounded by a first insulating structure 572 in the unit array structure CAS. Each of the plurality of second through-electrodes THV52 may be surrounded by a second insulating structure 574 in the connecting step region 522C. Figure 5BSimilar to the punch-through electrodes THV shown, each of the plurality of first punch-through electrodes THV51 and the plurality of second punch-through electrodes THV52 can be connected to at least one of the plurality of circuit CTs via a peripheral circuit interconnect layer ML66 included in the peripheral circuit structure PCS.

[0101] The number of first through electrodes THV51 passing through a first through hole 510H1 is not limited to Figure 13 and Figure 14 The example shown, and the number and size of the first through-electrode THV51 can be varied within the scope of the inventive concept.

[0102] According to reference Figures 4 to 14 The described IC devices 100, 100A, 200, 300, 400, and 500, in IC devices with a COP structure, even with an increase in the number of gate lines 130 in the memory stack MS stacked on the peripheral circuit structure PCS and an increase in the height of the memory stack MS, can easily ensure a stable separation distance greater than or equal to the minimum separation distance required by the design rules between the upper substrate 110 and the through-electrode THV, THV3, or THV4, or between the upper substrate 510 and the first through-electrode THV51. The distance between the through electrodes THV, THV3, THV4, or THV51 passing through the upper substrate 110 or 510 allows for greater freedom in layout design. The upper substrate 110 is situated between the peripheral circuit structure PCS and the memory stack MS. The through electrodes THV, THV3, or THV4 pass through the memory stack MS and the upper substrate 110 and extend into the peripheral circuit structure PCS. The first through electrode THV51 passes through the memory stack MS and the upper substrate 510 and extends into the peripheral circuit structure PCS. Therefore, the integration density of IC devices with a COP structure can be increased, the chip size can be reduced, and the reliability of the IC device can be improved.

[0103] As can be seen, the through-electrodes THV, THV3, THV4, and THV51 described herein have the following structure: continuous material extends from the bottom of the through-electrode (e.g., where the through-electrode connects and contacts with the conductive layer in the peripheral circuit structure) to the top of the through-electrode (e.g., where the through-electrode connects with components above and outside the unit array structure). These through-electrodes may have continuous sidewalls from bottom to top and may be formed from a single integral structure.

[0104] Figures 15A to 19A and Figures 15B to 19B This is a cross-sectional view illustrating the process sequence of a method for manufacturing an IC device according to an embodiment. Specifically, Figures 15A to 19A It is with along Figure 4A cross-sectional view of some components in the process sequence corresponding to the section cut by line X1-X1'. Figure 15B To the diagram Figure 19B It is with along Figure 4 The cross-sectional view of some components in the corresponding portion of the section cut by line Y1-Y1' according to the process sequence. In this embodiment, the manufacturing process will be described. Figure 4 and Figures 5A to 5C The method of the IC device 100 shown is used as an example.

[0105] Reference Figure 15A and Figure 15B This forms a peripheral circuit structure PCS that includes a lower substrate 52, multiple circuit CTs, a multilayer interconnect structure MWS, and an interlayer insulating film 70.

[0106] The multilayer interconnect structure (MWS) may include multiple peripheral circuit interconnect layers (e.g., ML60, ML61, ML62, and ML66) and a floating interconnect layer ML68, which is formed at the same level as the uppermost peripheral circuit interconnect layers ML62 and ML66 closest to the upper substrate 110 among the peripheral circuit interconnect layers ML60, ML61, ML62, and ML66. Each of these layers may be part of the same vertical layer of the multilayer interconnect structure (MWS). For example, they may be formed as a single layer (e.g., a layer with a consistent material and formed at the same vertical level in the same process).

[0107] Reference Figure 16A and Figure 16B The upper substrate 110 can be formed on the peripheral circuit structure PCS. A via 110H can be formed in the upper substrate 110, and the buried insulating film 112 can be formed to fill the via 110H.

[0108] Reference Figure 17A and Figure 17B Multiple insulating films 134 and multiple sacrificial films PL can be stacked alternately on the upper substrate 110 and the buried insulating film 112. The multiple sacrificial films PL can include silicon nitride, silicon carbide, or polysilicon. The multiple sacrificial films PL can each ensure space for forming multiple gate lines 130 during subsequent processes.

[0109] Next, a portion of each of the plurality of insulating films 134 and a portion of each of the plurality of sacrificial films PL can be replaced by an insulating structure 170, and an upper insulating film 169 can be formed. The upper insulating film 169 can be formed to cover the uppermost insulating film 134 and the insulating structure 170 of the plurality of insulating films 134. Then, a plurality of channel structures 160 can be formed to pass through the upper insulating film 169, the plurality of insulating films 134 and the plurality of sacrificial films PL, and a string selection wire cut region SSLC and an insulating film 150 filling the string selection wire cut region SSLC can be formed.

[0110] Then, multiple word line cut regions (WLCs) can be formed to pass through the upper insulating film 169, multiple insulating films 134, and multiple sacrificial films PL. A portion of the multiple word line cut regions (WLCs) can pass through a portion of the buried insulating film 112 filling the via 110H and the interlayer insulating film 70 of the peripheral circuit structure PCS. The top surface of the upper substrate 110 and the top surface of the floating interconnect layer ML68 can be exposed through the multiple word line cut regions (WLCs). Doped ions can be implanted into the portions of the upper substrate 110 exposed through the multiple word line cut regions (WLCs) to form multiple common source regions 172.

[0111] Reference Figure 18A and Figure 18B ,use Figure 17A and Figure 17B In the resulting structure, multiple word line cleaving regions (WLCs) replace multiple sacrificial films (PLs) with multiple gate lines (130). In some embodiments, in order to replace multiple sacrificial films (PLs) (refer to...) Figure 17B The gate lines 130 can be replaced by multiple gate lines, and multiple sacrificial films PL exposed through multiple word line cut regions WLC can be selectively removed to reserve empty spaces between the corresponding insulating films 134. The empty spaces can be filled with conductive material to form multiple gate lines 130.

[0112] Reference Figure 19A and Figure 19B A common-source electrode structure 140, including insulating spacer 144 and common-source electrode CSL, can be formed in each of the plurality of word line cut regions WLC. A plurality of through electrodes THV can be formed to pass through upper insulating film 169, insulating structure 170, buried insulating film 112 and interlayer insulating film 70 to contact the top surface of peripheral circuit interconnect layer ML66.

[0113] Then, multiple bit lines BL can be formed on multiple channel structures 160 to manufacture Figure 4 and Figures 5A to 5C The IC device 100 is shown. Additionally, extra lines can be formed on the top surface of the cell array structure CAS to electrically connect to the through-hole electrode THV.

[0114] Can be used as a reference Figures 15A to 19B The method for manufacturing the IC device 100 described is similar to the method for manufacturing IC devices. Figure 8 The IC device 200 is shown. However, it can be seen from the reference... Figure 17A and Figure 17B The process described omits the process for forming the insulating structure 170. Additionally, when referring to... Figure 18A and Figure 18B The described process involves multiple sacrificial membranes PL (refer to...) Figure 17B When the gate line is replaced with multiple gate lines 130, some of the multiple sacrificial films PL can be retained without being replaced by the multiple gate lines 130. As a result, an insulating structure 270 with a multilayer structure including some of the multiple sacrificial films PL and some of the multiple insulating films 134 can be obtained. In this case, Figure 8 The plurality of first insulating films 272 shown can be the resulting structure obtained using some of the plurality of insulating films 134, and Figure 8 The plurality of second insulating films 274 shown can be the resulting structure obtained using some of the plurality of sacrificial films PL.

[0115] Although it has been referenced Figures 15A to 19B Described Figure 4 and Figures 5A to 5C The IC device 100 shown and its manufacturing process Figure 8 The method of the IC device 200 shown is illustrated, but it should be understood that various modifications and changes can be made within the scope of the inventive concept. Figure 6 , Figure 7 and Figures 9 to 14 The IC devices 100A, 300, 400 and 500 shown are IC devices with different modified and altered structures.

[0116] Although the inventive concept has been clearly shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, comprising: Peripheral circuit structure; A memory stack comprising a plurality of gate lines located on the peripheral circuit structure and overlapping the peripheral circuit structure in the vertical direction; An upper substrate is located between the peripheral circuit structure and the memory stack, and the upper substrate includes a via located below the memory cell area of ​​the memory stack; The word line cutting area extends longitudinally in the first lateral direction, spanning the memory stack and the through-hole; as well as A common source electrode line is located in the word line cutting area. The common source electrode line includes a first part and a second part. The first part extends longitudinally in the first transverse direction on the upper substrate. The second part is integrally connected to the first part. The second part penetrates the upper substrate through the via from the upper part of the upper substrate and extends into the peripheral circuit structure.

2. The integrated circuit device according to claim 1, wherein, The peripheral circuit structure includes multiple peripheral circuit conductive interconnect layers and a floating conductive interconnect layer. The floating conductive interconnect layer is laterally spaced from the multiple peripheral circuit conductive interconnect layers and is connected to the common source line.

3. The integrated circuit device according to claim 1, wherein, The peripheral circuit structure includes: Lower substrate; Multiple circuits are formed on the lower substrate; Multiple peripheral circuit conductive interconnect layers connected to the multiple circuits; and A floating conductive interconnect layer is formed at the same vertical level as the uppermost peripheral circuit conductive interconnect layer closest to the upper substrate among the plurality of peripheral circuit conductive interconnect layers, wherein the floating conductive interconnect layer contacts the common source electrode line.

4. The integrated circuit device of claim 1, further comprising a through electrode that passes through the plurality of gate lines and the upper substrate, and extends longitudinally in the vertical direction into the peripheral circuit structure.

5. The integrated circuit device according to claim 1, further comprising: An insulating structure disposed on the upper substrate, the insulating structure passing through the plurality of gate lines in the memory cell region and extending in the vertical direction; An insulating film is embedded to fill the through-hole; as well as Through-electrode, which passes through the insulating structure and the embedded insulating film, and extends longitudinally in the vertical direction into the peripheral circuit structure.

6. The integrated circuit device according to claim 1, wherein, The memory cell area includes a normal cell area and a pseudo cell area. The through-hole is located below the pseudo-cell region.

7. The integrated circuit device according to claim 1, further comprising: Multiple through-electrodes pass through the multiple gate lines in the memory cell region and extend longitudinally in the vertical direction. Each of the plurality of through electrodes penetrates the upper substrate through the through-hole and is connected to the multilayer interconnect structure of the peripheral circuit structure.

8. The integrated circuit device according to claim 1, wherein, The peripheral circuit structure includes: Lower substrate; Multiple circuits are formed on the lower substrate; Multiple peripheral circuit conductive interconnect layers connected to the multiple circuits; and A floating conductive interconnect layer is formed at the same vertical level as the uppermost peripheral circuit conductive interconnect layer closest to the upper substrate among the plurality of peripheral circuit conductive interconnect layers, wherein the floating conductive interconnect layer contacts a second portion of the common source electrode line. The floating conductive interconnect layer has the same electrical bias as the common source electrode.

9. The integrated circuit device according to claim 1, further comprising: Through-hole electrodes penetrate the upper substrate through vias in the memory cell region and connect to the multilayer interconnect structure of the peripheral circuitry. The separation distance between the through electrode and the upper substrate is between 0.01 μm and 1.5 μm.

10. The integrated circuit device according to claim 1, wherein, The first portion overlaps with the upper substrate in the vertical direction. In the vertical direction, the length of the second part is greater than the length of the first part.

11. An integrated circuit device, comprising: The peripheral circuit structure includes multiple circuits, multiple peripheral circuit conductive interconnect layers connected to the multiple circuits, and floating conductive interconnect layers laterally spaced from the multiple peripheral circuit conductive interconnect layers. An upper substrate located on the peripheral circuit structure, the upper substrate including a first via formed at a position that overlaps with the floating conductive interconnect layer in the vertical direction; A memory stack having a memory cell region covering the first through-hole and a connection step region located on one side of the memory cell region, the memory stack including a plurality of gate lines spaced apart from the peripheral circuit structure in the vertical direction, and an upper substrate between the plurality of gate lines and the peripheral circuit structure; Multiple word line cut regions extend longitudinally across the memory stack and the first via in a first lateral direction, each of the multiple word line cut regions including a portion penetrating the upper substrate through the first via in the vertical direction; as well as Multiple first through electrodes penetrate the multiple gate lines in the vertical direction within the memory cell region and extend through the first vias to the multiple peripheral circuit conductive interconnect layers.

12. The integrated circuit device according to claim 11, wherein, The plurality of first through electrodes includes two first through electrodes that are laterally spaced apart from each other, and a selected word line cutting area from the plurality of word line cutting areas is located between the two first through electrodes.

13. The integrated circuit device according to claim 11, further comprising: Multiple common-source polar lines are respectively arranged within the multiple word line cutting regions. Each of the plurality of common source electrode lines includes a first portion and a second portion, the first portion extending longitudinally in the first transverse direction on the upper substrate, and the second portion integrally connected to the first portion and extending from the upper part of the upper substrate through the first via to the floating conductive interconnect layer.

14. The integrated circuit device according to claim 13, wherein, In the vertical direction, the second part has a longer length than the first part.

15. The integrated circuit device according to claim 11, wherein, The upper substrate is not laterally located between any two of the plurality of first through electrodes.

16. The integrated circuit device of claim 11, further comprising: The second through hole is formed at a location within the connection step region in the upper substrate; as well as At least one second through electrode penetrates the upper substrate through the second through hole in the vertical direction and extends to at least one peripheral circuit conductive interconnect layer selected from the plurality of peripheral circuit conductive interconnect layers.

17. The integrated circuit device of claim 11, further comprising: An insulating structure that passes through the plurality of gate lines in the memory cell region and extends in the vertical direction; as well as An insulating film is embedded, which fills the first through-hole. The plurality of first through electrodes pass through the insulating structure and the buried insulating film in the vertical direction and extend to the plurality of peripheral circuit conductive interconnect layers.

18. An integrated circuit device, comprising: The peripheral circuit structure includes a lower substrate and a plurality of peripheral circuit conductive interconnect layers and floating conductive interconnect layers formed on the lower substrate; The memory cell region includes multiple gate lines arranged on the peripheral circuit structure; An upper substrate is located between the peripheral circuit structure and the memory cell region, and includes a via formed at a location within the memory cell region; A common-source electrode includes a first portion and a second portion. The first portion extends longitudinally in a first lateral direction across the memory cell region and the via. The first portion contacts the upper substrate. The second portion is integrally connected to the first portion and extends from the upper part of the upper substrate through the via to the floating conductive interconnect layer. An insulating structure that passes through the plurality of gate lines in the memory cell region and extends in the vertical direction; An insulating film is embedded to fill the through-hole; as well as At least one through electrode passes through the insulating structure and the buried insulating film, and extends longitudinally in the vertical direction to at least one peripheral circuit conductive interconnect layer selected from the plurality of peripheral circuit conductive interconnect layers.

19. The integrated circuit device according to claim 18, wherein, The at least one peripheral circuit conductive interconnect layer and the floating conductive interconnect layer extend laterally at the same vertical level on the lower substrate. The floating conductive interconnect layer is configured to have the same electrical bias as the common source electrode.

20. The integrated circuit device according to claim 18, wherein, The at least one through-electrode includes two through-electrodes that are laterally spaced apart from each other, the common source electrode is located between the two through-electrodes, and the two through-electrodes extend longitudinally through the through-hole in the vertical direction. The upper substrate is not located laterally between the two through electrodes.

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