Rotary transformer calibration device and method for calibrating a rotary transformer calibration device

Abstract

Various embodiments of the present invention relate to a rotary transformer calibration apparatus and a method for calibrating the rotary transformer calibration apparatus. This calibration method and the rotary transformer calibration apparatus can reduce the detection error of rotation angle (rotation speed) caused by the rotary transformer. During normal operation, the excitation signal supply circuit provides an excitation signal with an excitation frequency to the rotary transformer, and during calibration operation, it provides an excitation signal with multiple frequencies, including the excitation frequency, to a first phase shifter or a second phase shifter. During calibration operation, the offset search circuit, while referencing the detection result of the phase difference detection circuit, searches for a first offset setting value that makes the first offset 45 degrees for each frequency of the excitation signal; and searches for a second offset setting value that makes the second offset 135 degrees for each frequency of the excitation signal, and stores these values ​​in a calibration table.

Description

[0001] Cross-references to related applications

[0002] The disclosure of Japanese Patent Application No. 2019-185406, filed on October 8, 2019, is incorporated herein by reference in its entirety, including the specification, drawings and abstract. Technical Field

[0003] This invention relates to a resolver calibration device and a calibration method for the resolver calibration device, for example, to a technique for correcting errors occurring in an RDC (Resolver to Digital Converter) circuit. Background Technology

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication 2017-32480

[0006] [Patent Document 2] Japanese Unexamined Patent Application Publication 2018-31619

[0007] Patent Document 1 discloses a signal converter comprising: a first phase shifter for shifting the phase of a first phase signal from a resolver; and a second phase shifter for shifting the phase of a second phase signal from the resolver, operating with a phase difference between the offsets of the first and second phase shifters, the phase difference being set to a predetermined difference (90 degrees). Patent Document 2 discloses a resolver correction device that corrects the offset setting of the phase shifters to be proportional to the rotational speed of a motor. Summary of the Invention

[0008] It is known that resolvers use the rotation angle (rotational speed) of a motor as a detection sensor. The detection signal from the resolver is processed in an RDC circuit. As a processing method for the RDC circuit, a method is known, as shown in Patent Document 1, which generates a predetermined phase difference (90 degrees) by using two phase shifter circuits. If such a scheme is used, since the offset of the two phase shifters changes with the signaling frequency to the same degree, a predetermined phase difference (90 degrees) can be created in a certain frequency band.

[0009] However, the signal frequency is a value modulated based on factors such as the motor's rotational speed. Therefore, in the system of Patent Document 1, for example, when the frequency modulation amount is large, it is difficult to maintain the phase difference at a predetermined phase difference (90 degrees). Errors in this predetermined phase difference (90 degrees) lead to detection errors in the rotation angle (rotational speed). Therefore, as shown in Patent Document 2, it is possible to consider correcting the offset setting value of the phase shifter to be proportional to the motor's rotational speed. However, the required offset setting value compensation is not necessarily proportional to the motor's rotational speed.

[0010] The embodiments described below were made in view of these circumstances, and other problems and novel features will become apparent from the description and drawings in this specification.

[0011] A rotary transformer calibration apparatus according to one embodiment includes: a first phase shifter for outputting a first phase signal by shifting the phase of a first detection signal by a first offset amount according to a first offset amount setting value, the first detection signal being one of the quadrature detection signals of the rotary transformer; a second phase shifter for outputting a second phase signal by shifting the phase of a second detection signal by a second offset amount according to a second offset amount setting value, the second detection signal being another of the quadrature detection signals; an adder circuit for outputting a third phase signal by adding the first phase signal and the second phase signal; and an excitation signal supply circuit for providing an excitation signal having an excitation frequency to the rotary transformer during normal operation, and for providing excitation signals of multiple frequencies including the excitation frequency to the first phase shifter during calibration operation. Or a second phase shifter; a phase difference detection circuit for detecting the rotation angle of the resolver during normal operation by detecting the phase difference between the excitation signal from the excitation signal supply circuit and the third phase signal from the adder circuit, and for detecting a first offset or a second offset during calibration operation; an offset search circuit for searching, during calibration operation, a first offset setting value such that the first offset becomes a first specified amount for each frequency of the excitation signal, while referring to the detection result of the phase difference detection circuit, and a second offset setting value such that the second offset becomes a second specified amount differing from the first specified amount by 90 degrees; and a storage circuit for storing the first offset setting value and the second offset setting value for each frequency of the excitation signal obtained by the search results of the offset search circuit as a calibration table.

[0012] According to the above embodiments, the detection errors of the rotation angle and rotation speed of the rotary transformer can be reduced. Attached Figure Description

[0013] Figure 1 This is a schematic diagram illustrating an example configuration of a motor system including a rotary transformer correction device according to a first embodiment.

[0014] Figure 2 It is shown Figure 1 A circuit diagram illustrating an example configuration of a phase shifter.

[0015] Figure 3 It is shown Figure 1 A schematic diagram illustrating an example configuration of the calibration table in the diagram.

[0016] Figure 4 It is shown in Figure 1 A flowchart illustrating the exemplary process content of the calibration operation in the rotary transformer calibration device [1].

[0017] Figure 5 It is shown in Figure 1 A flowchart illustrating the exemplary process content of the normal operation of the rotary transformer correction device [1].

[0018] Figure 6A This is a schematic diagram illustrating an example configuration of a motor system including a rotary transformer correction device according to a second embodiment.

[0019] Figure 6B It is shown Figure 6A A schematic diagram of the modified example.

[0020] Figure 7 It is shown Figure 6A A schematic diagram illustrating an example configuration of the calibration table in the diagram.

[0021] Figure 8 It is used to explain in Figure 6A A graph of the arithmetic expressions used in the detection result corrector.

[0022] Figure 9 It is illustrated in Figure 6A A flowchart of an example of the processing content during the calibration operation in the rotary transformer calibration device [2].

[0023] Figure 10 It is illustrated in Figure 6A A flowchart of an example of the processing content during normal operation[2] of a rotary transformer correction device.

[0024] Figure 11 This shows the use of Figure 6A An example of simulation results comparing the detection error of the motor rotation angle with and without correction by the rotary transformer correction device.

[0025] Figure 12A This is a schematic diagram illustrating an example configuration of a microcomputer in a rotary transformer correction apparatus according to a third embodiment.

[0026] Figure 12B It is shown Figure 12A A schematic diagram of the modified example.

[0027] Figure 13 It is shown Figure 12A A schematic diagram illustrating an example configuration of the calibration table in the diagram.

[0028] Figure 14 It is shown in Figure 12A A flowchart illustrating the exemplary process content of the calibration operation in the rotary transformer calibration device [3].

[0029] Figure 15 It is shown in Figure 12A A flowchart illustrating the exemplary process content during normal operation of the rotary transformer correction device [3].

[0030] Figure 16A This is a schematic diagram illustrating an example configuration of a microcomputer in a rotary transformer correction apparatus according to a fourth embodiment.

[0031] Figure 16B It is shown Figure 16A A schematic diagram of the modified example.

[0032] Figure 17 It is shown Figure 16A A flowchart illustrating the exemplary process of determining the correction necessity circuit.

[0033] Figure 18A It is shown Figure 1 A diagram illustrating the characteristics of a phase shifter in a given context.

[0034] Figure 18B It is shown Figure 1 A diagram illustrating the characteristics of a phase shifter in a given context. Detailed Implementation

[0035] In the following embodiments, for convenience, the embodiments are described by dividing them into multiple parts or embodiments. However, unless otherwise stated, they are not unrelated to each other, and one embodiment is related to some or all of other embodiments (such as modified examples, details, supplementary descriptions, etc.). In the following embodiments, except where specifically specified or where it is obvious that the principle is limited to a specific number, the number of elements, etc. (including quantity, number, amount, range, etc.) is not limited to a specific number and may be a specific number or more or less.

[0036] Furthermore, in the following embodiments, it is obvious that, except in specifically designated cases and cases deemed obviously necessary in principle, constituent elements (including element steps, etc.) are not necessarily required. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is assumed that the shape, etc., is substantially approximate or similar to the shape, etc., except in specifically designated cases and cases deemed obviously necessary in principle. The same applies to the numerical values ​​and ranges described above.

[0037] The circuit elements constituting the functional blocks of the embodiments are formed on a semiconductor substrate such as single-crystal silicon using integrated circuit technology (such as, but not limited to, known CMOS, complementary MOS transistors).

[0038] In the following, embodiments of the invention will be described in detail with reference to the accompanying drawings. In principle, the same elements are denoted by the same reference numerals in all the drawings used to explain the embodiments, and repeated descriptions thereof are omitted.

[0039] (First Embodiment)

[0040] <Schematic diagram of rotary transformer correction device>

[0041] Figure 1 This is a schematic diagram illustrating an exemplary configuration of a motor system including a rotary transformer correction device according to a first embodiment. Figure 1 The illustrated motor system includes a motor MT, a driver unit DVU that drives the motor MT, a resolver RSV, a shaft angle digital converter RDC, and a microcontroller MCU (hereinafter referred to as a microcomputer). The resolver correction device of the first embodiment corresponds to the shaft angle digital converter RDC and the microcomputer MCU.

[0042] Each device in the axis-angle digital converter (RDC) and microcomputer MCU consists of, for example, a separate semiconductor chip or IC chip. However, the installation mode is not limited to this and can be changed as needed. Some or all of the various circuit blocks included in the microcomputer MCU can be replaced with FPGA (Field Programmable Gate Array), ASIC (Application-Specific Integrated Circuit), etc. That is, the various circuit blocks can be appropriately implemented using hardware processing, software processing, or a combination thereof.

[0043] The driver unit DVU includes, for example, a driver circuit DV (such as a three-phase inverter) and a pre-driver circuit PDV for driving each switching element (not shown) in the driver circuit DV. For example, based on three-phase PWM (pulse width modulation) signals PWMu, PWMv, and PWMw output from a microcomputer MCU, the pre-driver circuit PDV controls the switching of the corresponding switching elements in the driver circuit DV.

[0044] A resolver (RSV) is mounted, for example, on the rotating shaft of a motor (MT). It detects the rotation angle θ of the motor MT and outputs detection signals E1 and E2. Detection signals E1 and E2 are orthogonal detection signals with a 90-degree phase difference, reflecting the rotation angle θ. A shaft angle digital converter (RDC) processes the detection signals E1 and E2 from the resolver (RSV). Specifically, in addition to the excitation circuit (EXC), differential amplifiers (AMP1 and AMP2), phase shifters (PSF1 and PSF2), and adder circuit (ADDU), the shaft angle digital converter (RDC) also includes a selection switch (SSW).

[0045] The excitation circuit EXC, in response to the excitation clock signal CKe with excitation frequency fexc provided by the microcomputer MCU, performs filtering processes and outputs a sine wave with excitation frequency fexc (angular velocity ω = 2π × fexc) as the excitation signal VIN (∝sin(ωt)). The rotary transformer RSV receives the excitation signal VIN via the selection switch SSW and outputs detection signals E1 and E2. At this time, according to the rotation angle and electrical angle θ of the motor MT, the detection signal E1 becomes "E1∝sin(θ)×sin(ωt)", and the detection signal E2 becomes "E2∝cos(θ)×sin(ωt)".

[0046] Amplifiers AMP1 and AMP2 differentially amplify the detection signals E1 and E2 from the resolver RSV, respectively, and output phase signals V1 and V2. Phase shifter PSF1 outputs phase signal V1' by shifting the phase of phase signal V1 (and therefore the phase of detection signal E1) by a predetermined offset based on the offset setting value SS1 from the microcomputer MCU. Phase shifter PSF2 outputs phase signal V2' by shifting the phase of phase signal V2 (and therefore the phase of detection signal E2) by a predetermined offset based on the offset setting value SS2 from the microcomputer MCU.

[0047] The offset of phase shifter PSF2 is set to be 90 degrees (π / 2) different from the offset of phase shifter PSF1. As a result, when the phase signal V1' is "V1∝sin(θ)×sin(ωt)", the phase signal V2' is, for example, "V2'∝cos(θ)×sin(ωt-π / 2)=-cos(θ)×cos(ωt)".

[0048] The adder circuit ADDU outputs a phase signal by adding the phase signal V1' from phase shifter PSF1 to the phase signal V2' from phase shifter PSF2, and detects the clock signal CKd. Specifically, the adder circuit ADDU includes: an adder ADD for adding the phase signals V1' and V2'; and a comparator CMP for converting the phase signal V3' (=V1'+V2') as the addition result into a square wave, and outputting the phase signal V3' as the detection clock signal CKd via the comparator CMP. As a result, the phase signal V3' (=V1'+V2') becomes "V3'∝cos(ωt+θ)", and the detection clock signal CKd becomes a signal synchronized with the phase signal V3'.

[0049] In addition to the offset search circuit SSR, the offset correction circuit SCR, and the storage circuit MEM of the calibration table CTBLa, the microcomputer MCU also includes a PWM signal generator PWMG, an analog-to-digital converter ADC, an excitation signal supply circuit ESS, a timer TMR including a phase difference detection circuit PHD, and a processor CPU. The processor CPU includes a position detector PDET, a speed detector SDET, and a current controller PIC, all implemented through software processing by the processor CPU. The offset search circuit SSR, the offset correction circuit SCR, and the calibration table CTBLa will be described below.

[0050] The excitation signal supply circuit ESS uses a timer, for example, to generate an excitation clock signal CKe, which serves as the basis for the excitation signal VIN and is provided to the excitation circuit EXC of the shaft angle digital converter RDC. The phase difference detection circuit PHD detects the phase difference between the excitation clock signal CKe and the detection clock signal CKd from the adder circuit ADDU, using it as a counter for the timer TMR. The position detector PDET detects the rotation angle θ of the resolver RSV by converting the count value detected by the phase difference detection circuit PHD into an angle. Therefore, in essence, the phase difference detection circuit PHD can detect the rotation angle θ of the resolver RSV (and thus the motor MT) by detecting the phase difference between the excitation signal VIN (∝sin(ωt)) from the excitation signal supply circuit ESS and the phase signal V3' (∝cos(ωt+θ)) from the adder circuit ADDU.

[0051] The speed detector SDET detects the rotational speed (dθ / dt) of the resolver RSV based on the rate of change of its rotational angle θ, which is detected by the position detector PDET and essentially by the phase difference detection circuit PHD. The analog-to-digital converter ADC converts the drive current Imt of the motor MT, detected, for example, via a current sensor (not shown) in the driver circuit DV, into a digital value.

[0052] The current controller PIC is, for example, a PI (proportional (P)·integral (I)) controller. This current controller determines the target current based on the error between the target rotational speed and the rotational speed detected by the speed detector SDET. The target current is used to limit the duty cycle of the PWM signal based on the error between the drive current Imt converted by the analog-to-digital converter ADC. For example, a PWM signal generator PWMG, which is composed of a timer, generates PWM signals PWMu, PWMv, and PWMw based on the duty cycle limited by the current controller PIC.

[0053] <Phase Shifter Configuration>

[0054] Figure 2 It is shown Figure 1 A circuit diagram illustrating an exemplary configuration of the phase shifter. The phase shifter PSF1 is, for example, an all-pass filter (APF) and includes resistor unit RU1, capacitor C11, multiple resistors R13 to R16, switch SW12, and amplifier AMP11. Resistor unit RU1 and capacitor C11 form an RC circuit and transmit the phase signal V1 to the (+) input terminal of amplifier AMP11. Resistors R13 and R14 are input resistors and transmit the phase signal V1 to the (-) input terminal of amplifier AMP11 via switch SW12. Resistors R15 and R16 are feedback resistors and negatively feedback the output terminal of amplifier AMP11 to the (-) input terminal of amplifier AMP11 via switch SW12.

[0055] Resistor unit RU1 includes, for example, multiple resistors R11 and R12 connected in parallel, and a switch SW11 for switching the enable and disable of resistor R11. The effective resistor of resistor unit RU1 is controlled by turning switch SW11 on or off at a predetermined time ratio based on an offset setting value SS1. That is, in this case, the offset setting value SS1 is the duty cycle PWMD1 of a PWM signal, and the on or off of switch SW11 is controlled by a PWM signal having a duty cycle PWMD1. As described above, phase shifter PSF1 controls the RC circuit delay by switching a portion of the multiple resistors R11 and R12 in the RC circuit, and the enable and disable of resistor unit RU1, via a PWM signal, thereby controlling the offset.

[0056] Similarly, the phase shifter PSF2 is, for example, an all-pass filter APF, and includes resistor unit RU2, capacitor C21, multiple resistors R23 to R26, switches SW22 to SW24, and amplifier AMP21. Resistor unit RU2 and capacitor C21 form an RC circuit and transmit the phase signal V2 to the (+) input terminal of amplifier AMP21. Resistors R23 to R26 are input resistors or feedback resistors for the (-) input terminal of amplifier AMP21. The ratio between the input resistors and the feedback resistors can be variably set by switches SW22 to SW24.

[0057] Similar to resistor unit RU1, unit RU2 includes multiple resistors R21 and R22 connected in parallel and a switch SW21 for switching the enable and disable of resistor R21. The offset setting value SS2 is the duty cycle PWMD2 of the PWM signal, and the on or off state of switch SW21 is controlled by the PWM signal with the duty cycle PWMD2. As described above, phase shifter PSF2 also controls the offset by switching a portion of the multiple resistors R21 and R22 in the RC circuit, and the enable or disable state of resistor unit RU2, via the PWM signal.

[0058] Incidentally, the multiple resistors in the resistor unit can be connected in series, not just in parallel. In this case, a switch can be provided to bypass a portion of the series-connected resistors. Additionally, although the effective resistor of the resistor unit is controlled by a PWM signal, it is not limited to this, and various variable resistor schemes can be used. However, by using PWM control methods, the resolution of the effective resistor can be improved without complicating the hardware. That is, the higher the duty cycle setting resolution of the PWM signal of the microcomputer MCU (and therefore the higher the clock frequency), the higher the resolution of the effective resistor. Additionally, although the resistors in the RC circuit here are variablely controlled, the capacitors can also be variablely controlled.

[0059] <Prerequisites>

[0060] Figure 18A and Figure 18B It is shown Figure 1 A diagram illustrating the characteristics of a phase shifter in a given context. Figure 18A and Figure 18B In the diagram, the horizontal axis represents the output frequencies fres [kHz] of the detection signals E1 and E2 from the rotary transformer RSV, and the vertical axis represents the phase difference [degrees] between the offsets of the two phase shifters PSF1 and PSF2. Figure 18AThe characteristics are shown when, for the excitation frequency fexc (20 kHz in this case), the offset setting value SS1 of phase shifter PSF1 is defined to have an offset of 45 degrees and the offset setting value SS2 of phase shifter PSF2 is defined to have an offset of 135 degrees (i.e., a phase difference of 90 degrees). Figure 18B The characteristics are shown when, for the excitation frequency fexc (20 kHz in this case), the offset setting value SS1 of phase shifter PSF1 is defined as having an offset of 55 degrees and the offset setting value SS2 of phase shifter PSF2 is defined as having an offset of 145 degrees (i.e., a phase difference of 90 degrees).

[0061] exist Figure 18A and Figure 18B For example, when the rotational speed fm [rpm] of the motor MT (resolver transformer RSV) is zero, the output frequency fres is equal to the excitation frequency fexc (=ω / 2π) of the excitation signal VIN (20kHz). In this case, as... Figure 18A and Figure 18B As shown, if the offset settings SS1 and SS2 of phase shifters PSF1 and PSF2 are determined such that the phase difference between the two phase shifters PSF1 and PSF2 is 90 degrees, then the set phase difference (90 degrees) is obtained.

[0062] On the other hand, if the rotational speed fm [rpm] of the motor MT (resolver RSV) is not zero, the output frequency fres is a value modulated according to the rotational speed fm of the motor MT. Therefore, the output frequency fres is the value of equation (1), which uses the excitation frequency fexc (=ω / 2π), the rotational speed fm, and the number of poles Np of the resolver RSV. Thus, for example, when the excitation frequency fexc is 20kHz, the output frequency fres is higher than 20kHz when the motor MT rotates in the forward direction, and lower than 20kHz when the motor MT rotates in the reverse direction.

[0063] fres=fexc+(fm / 60)×Np: Equation (1)

[0064] Here, firstly, the use of the method described in Patent Document 1 above is presented. For example... Figure 18AAs shown, when two phase shifters, PSF1 and PSF2, are used as in Patent Document 1, the phase difference can be maintained at approximately 90 degrees near the excitation frequency fexc (20 kHz). Therefore, when the rotational speed fm of the motor MT is low or the number of poles Np of the resolver RSV is small, and only ±2 kHz modulation is applied to 20 kHz, the phase difference setting error (approximately 0.2 degrees in this example) is acceptable. However, if the rotational speed fm of the motor MT is high or the number of poles Np of the resolver RSV is large (e.g., 50 poles, etc.), and approximately ±5 kHz modulation is applied to 20 kHz, the phase difference setting error (approximately 1.4 to 2.2 degrees in this example) may be unacceptable.

[0065] like Figure 18A and Figure 18B As shown, in phase shifters PSF1 and PSF2, the characteristics of the setting error of the phase difference relative to the output frequency fres vary depending on the values ​​of the offset setting values ​​SS1 and SS2 relative to phase shifters PSF1 and PSF2, respectively. Therefore, in order to determine the characteristics of the setting error of the phase difference as designed, it is necessary to accurately determine the offset setting values ​​SS1 and SS2. However, when the predetermined offset setting values ​​SS1 and SS2 are set in the corresponding phase shifters PSF1 and PSF2, it is difficult to verify that the actual offset is in the offset setting value state. Therefore, there is a concern that the phase difference setting error cannot be sufficiently reduced if the designed characteristics cannot be obtained.

[0066] Next, the use of the method described in Patent Document 2 will be described. In the method of Patent Document 2, for example, in... Figure 18A In this configuration, if the output frequency fres varies according to the rotation of the motor MT, then one of the offset settings SS1 and SS2 of the phase shifters PSF1 and PSF2 is proportional to the rotational speed fm of the motor MT. For example, by correcting one of the offset settings SS1 and SS2 using linear characteristics, the linearity becomes zero at 20kHz and -1.4 degrees at 25kHz, so that the phase difference can be maintained at approximately 90 degrees even when the output frequency changes.

[0067] However, the corrected amount of the initially required offset setting is not necessarily proportional to the rotational speed fm of the motor MT. That is, as Figure 18A and Figure 18B As shown, the relationship between the rotational speed fm of the motor MT (and therefore the output frequency fres) and the corrected amount of the required offset setting value also varies depending on the magnitude of the original offset setting value. Therefore, for example, when... Figure 18A The correction amount of the offset setting value in the range of 20kHz to 15kHz is applied to Figure 18B At that time, due to Figure 18A and Figure 18B The polarity of the initial required correction amount differs; conversely, the phase difference setting error will increase.

[0068] Additionally, in the method of Patent Document 2, after the rotational speed fm of the motor MT is detected, the offset setting values ​​of phase shifters PSF1 and PSF2 must be controlled and corrected. In this case, a control delay occurs. This control delay may not be sufficient to reduce the phase difference setting error.

[0069] <Offset Correction Method>

[0070] therefore, Figure 1 The resolver calibration device includes an offset search circuit SSR, an offset correction circuit SCR, and a calibration table CTBLa. The offset search circuit SSR and the offset correction circuit SCR are implemented, for example, through software processing by the processor CPU, but can be implemented in other ways. The selection switch SSW, based on instructions from the offset search circuit SSR, selects which of the following should be supplied to the resolver RSV, phase shifter PSF1, and phase shifter PSF2, based on the excitation signal VIN provided from the excitation signal supply circuit ESS via the excitation circuit EXC:

[0071] Here, Figure 1 The resolver calibration device performs a calibration operation to correct the offset of phase shifters PSF1 and PSF2 by increasing the rotation angle θ when the motor MT is rotated to detect normal operation. The offset search circuit SSR is activated during the calibration operation. In normal operation, the excitation signal supply circuit ESS provides the excitation clock signal CKe (and therefore the excitation signal VIN) with the excitation frequency fexc to the resolver RSV via the selection switch SSW. On the other hand, when performing the calibration operation, based on the instruction from the offset search circuit SSR, the excitation signal supply circuit ESS provides the excitation signal VIN with multiple frequencies, including the excitation frequency fexc, to either phase shifter PSF1 or phase shifter PSF2 via the selection switch SSW.

[0072] like Figure 1 The phase difference detection circuit PHD detects the phase difference between the excitation clock signal CKe (and therefore the excitation signal VIN) from the excitation signal supply circuit ESS and the detection clock signal CKd (and therefore the phase signal V3') from the adder circuit ADDU. Therefore, the phase difference detection circuit PHD detects the rotation angle θ of the resolver RSV during normal operation and detects the offset of phase shifter PSF1 or phase shifter PSF2 during calibration operation.

[0073] During calibration, if the excitation signal VIN is provided to the phase shifter PSF1 via the selection switch SSW, the phase signal V2' from the phase shifter PSF2 to the adder circuit ADDU is null. Therefore, the phase difference detection circuit PHD can detect the offset of the phase shifter PSF1 by switching to detecting the phase difference between the detection clock signal CKd and the excitation clock signal CKe corresponding to the phase signal V1' from the adder circuit ADDU. This also applies when the excitation signal VIN is provided to the phase shifter PSF2 via the selection switch SSW.

[0074] During calibration, the offset search circuit SSR indicates the frequency of the excitation signal VIN to the excitation signal supply circuit ESS. Simultaneously with the detection results from the reference phase difference detection circuit PHD for each frequency, it searches for an offset setting value SS1 that causes the offset of phase shifter PSF1 to become a specified amount (e.g., 45 degrees). Similarly, at each frequency of the excitation signal VIN, the offset search circuit SSR searches for an offset setting value SS2 that causes the offset of phase shifter PSF2 to become a specified amount (e.g., 135 degrees). The offset search circuit SSR stores the search results in the calibration table CTBLa.

[0075] Figure 3 It is shown Figure 1 A schematic diagram illustrating an exemplary configuration of the correction table in the diagram. For example... Figure 3 As shown, the calibration table CTBLa stores offset setting values ​​SS1 and SS2 for each frequency of the excitation signal VIN. These offset setting values ​​SS1 and SS2 are obtained through the search results of the offset search circuit SSR. In this case, as... Figure 2 As shown, the offset settings SS1 and SS2 are the duty cycles PWMD1 and PWMD2 of the PWM signal, respectively.

[0076] During calibration, the frequency of the excitation signal VIN can be considered as... Figure 18A and Figure 18B The output frequency fres is described in the text. The maximum value of the frequency of the excitation signal VIN is a value corresponding to "excitation frequency fexc + number of poles Np × maximum forward rotation speed [rps]" (e.g., 25kHz when the excitation frequency fexc is 20kHz). Similarly, the minimum value of the frequency of the excitation signal VIN is a value corresponding to "excitation frequency fexc - number of poles Np × maximum reverse rotation speed [rps]" (e.g., 15kHz). Additionally, the frequency of the excitation signal VIN is set here to increase by 1kHz between the maximum and minimum values.

[0077] exist Figure 1In normal operation, the offset correction circuit SCR uses the rotational speed (dθ / dt = fm) detected by the speed detector SDET, the excitation frequency fexc of the excitation signal VIN, and the number of poles Np of the resolver RSV to calculate the output frequency fres based on equation (1). The offset correction circuit SCR uses the output frequency fres as a search keyword to refer to the correction table CTBLa to obtain the offset setting values ​​SS1 and SS2, and sets the offset setting values ​​SS1 and SS2 in the phase shifters PSF1 and PSF2, respectively. In this case, when the calculated output frequency fres is located among the multiple output frequencies fres (i.e., discrete values) stored in the correction table CTBLa, the offset correction circuit SCR determines the corresponding offset setting values ​​SS1 and SS2 by, for example, linear interpolation between the output frequencies fres.

[0078] exist Figure 1 In this configuration, calibration is performed via a selection switch SSW, but it can also be performed in a configuration without the selection switch SSW. Specifically, when the excitation signal supply circuit ESS provides the excitation signal VIN to the resolver RSV, the rotation of the motor MT (resolver RSV) can be controlled to a stopped state. In this case, the output frequency fres of the detection signals E1 and E2 is equal to the frequency of the excitation signal VIN.

[0079] In this scenario, for example, by deactivating one of the phase shifters PSF1, PSF2, etc., the offset search circuit SSR disables one of the phase signals V1' and V2'. Therefore, the adder circuit ADDU can output one of the phase signals V1' and V2' as the phase signal V3'. However, in this case, the offsets of the phase shifters PSF1 and PSF2 detected by the phase difference detection circuit PHD may include errors related to the configuration of the resolver RSV. From the perspective of eliminating such errors, it is desirable to provide a selection switch SSW.

[0080] Operation of the Rotary Transformer Correction Device

[0081] Figure 4 It is shown in Figure 1 A flowchart illustrating the exemplary process content of the calibration operation [1] in a rotary transformer calibration device. Figure 4In step S102, the excitation signal supply circuit ESS, in response to the instruction from the offset search circuit SSR, provides an excitation clock signal CKe with frequency f[k] (and therefore the excitation signal VIN) at k=0 (step S101). Subsequently, the selection switch SSW, in response to the instruction from the offset search circuit SSR, selects the calibration path[1] for providing the excitation signal VIN to the phase shifter PSF1 (step S103).

[0082] Next, the offset search circuit SSR searches for the following offset setting value SS1 while sequentially changing the offset setting value SS1 (duty cycle PWMD1). Under this offset setting value SS1, the offset detected by the phase difference detection circuit PHD becomes a specified amount (45 degrees in this case) (S104). Then, the offset search circuit SSR stores the correspondence between the frequency f[k] in step S102 and the offset setting value SS1 (duty cycle PWMD1) as the search result in step S104 in the correction table CTBLa (step S105).

[0083] Subsequently, in steps S106 to S108, the same process as steps S103 to S105 is performed for the calibration path [2] used to provide the excitation signal VIN to the phase shifter PSF2. That is, the selection switch SSW selects the calibration path [2] (step S106), and the offset search circuit SSR searches (step S107) for the offset setting value SS2 (duty cycle PWMD2) as follows, under which the offset detected by the phase difference detection circuit PHD becomes a specified amount (here, 135 degrees). Then, the offset search circuit SSR stores the correspondence between the frequency f [k] and the offset setting value SS2 (duty cycle PWMD2) in the calibration table CTBLa (step S108).

[0084] Subsequently, the offset search circuit SSR repeats steps S102 to S108 while sequentially changing k, until k = kmax (steps S109 and S110). As a result, in Figure 3 In the calibration table CTBLa, the frequency f[k] in step S102 is changed from 15kHz to 25kHz in increments of 1kHz, and offset setting values ​​SS1 and SS2 (duty cycles PWMD1 and PWMD2) for each frequency f[k] are registered.

[0085] Figure 5 It is shown in Figure 1 A flowchart illustrating the exemplary process content during normal operation [1] of a rotary transformer correction device. Figure 5In step S201, the excitation signal supply circuit ESS provides an excitation clock signal CKe (and therefore excitation signal VIN) with an excitation frequency fexc (e.g., 20kHz) to the resolver RSV via a selection switch SSW. Subsequently, the phase difference detection circuit PHD (position detector PDET) detects the phase difference between the excitation clock signal CKe and the detection clock signal CKd to detect the rotation angle θ of the resolver RSV (and therefore the motor MT) (step S202). The speed detector SDET detects (step S203) the rotational speed (dθ / dt = fm) of the motor MT based on the rate of change of the rotation angle θ.

[0086] Then, the offset correction circuit SCR calculates (step S204) the output frequencies fres of the detection signals E1 and E2 based on the above equation (1), using the excitation frequency fexc, the rotational speed fm detected in step S203, and the predetermined number of poles Np of the rotary transformer RSV. The offset correction circuit SCR obtains the offset setting values ​​SS1 and SS2 (duty cycles PWMD1 and PWMD2) by using the output frequency fres calculated in step S204 as the search keyword and referring to the correction table CTBLa (step S205). The offset correction circuit SCR sets the offset setting values ​​SS1 and SS2 obtained in step S205 to the phase shifters PSF1 and PSF2 (step S206).

[0087] Here, the resolver correction device, while performing normal operation, repeats steps S202 to S206 (step S207) during each control period of the speed detector SDET. In step S205, the offset correction circuit SCR linearly interpolates, for example, offset setting values ​​SS1 and SS2 based on the value of the output frequency fres. Figure 3 Taking the correction table CTBLa as an example, if the output frequency fres is 15.5KHz, the offset correction circuit SCR defines the duty cycle PWMD1 as "(0.9+0.55) / 2" and the duty cycle PWMD2 as "(0.8+0.7) / 2".

[0088] <Main Effects of the First Embodiment>

[0089] As described above, by using the resolver calibration device of the first embodiment, during calibration operations, offset setting values ​​SS1 and SS2 for each output frequency fres can be obtained in advance to maintain the specified offsets (45 degrees and 135 degrees) of the phase shifters PSF1 and PSF2. This allows the phase difference between the phase shifters PSF1 and PSF2 to be maintained at 90 degrees with high precision, regardless of the rotational speed fm of the motor MT or the pole count Np of the resolver RSV. Therefore, the detection error of the resolver RSV for the rotation angle θ (rotational speed dθ / dt) can be reduced, thereby enabling high-precision control of the motor MT.

[0090] Additionally, by using an existing phase difference detection circuit (PHD) to detect the offset of phase shifters PSF1 and PSF2, the area overhead associated with detecting the offset can be reduced. That is, for example, a pseudo-phase shifter for detecting the offset is not required. Furthermore, compared to the system in Patent Document 2, an appropriate correction amount can be determined even if the relationship between the output frequency fres and the correction amount of the offset setting value is not proportional but has any characteristics. Moreover, in normal operation, since referring to the correction table CTBLa defined during calibration is sufficient, the control delay associated with calibration can be reduced.

[0091] (Second Embodiment)

[0092] <Schematic diagram of rotary transformer correction device>

[0093] Figure 6A This is a schematic diagram illustrating an example configuration of a motor system including a rotary transformer correction device according to a second embodiment. Figure 6A The rotary transformer calibration device shown includes an offset error detection circuit SED, an offset setting circuit SST, a calibration table CTBLb, and a detection result calibrator RTC, but does not include... Figure 1 The offset search circuit (SSR), offset correction circuit (SCR), and calibration table (CTBLa) in the microcontroller unit (MCU) are described. The detection result corrector (RTC) is implemented, for example, through software processing by the processor (CPU). The offset error detection circuit (SED) and offset setting circuit (SST) are also implemented, for example, through software processing by the processor (CPU). However, they can be implemented in other ways.

[0094] In the second embodiment, unlike the first embodiment, the offset settings SS1 and SS2 of phase shifters PSF1 and PSF2 are set to fixed values ​​during normal operation. Instead, during calibration, for each output frequency fres, the offset error from a specified amount (e.g., 45 degrees, 135 degrees) in phase shifters PSF1 and PSF2 is detected. If the offset error for each output frequency fres is known in advance, the offset error corresponding to the current output frequency fres can be corrected using an arithmetic expression during normal operation, and the rotation angle θ and rotation speed (dθ / dt) can be calculated.

[0095] During calibration, the offset error detection circuit SED detects the offset error contained in the offset of the phase shifter PSF1 detected in the phase difference detection circuit PHD at each frequency of the excitation signal VIN, using a reference specified amount (e.g., 45 degrees). Similarly, the offset error detection circuit SED detects the offset error contained in the offset of the phase shifter PSF2 detected in the phase difference detection circuit PHD at each frequency of the excitation signal VIN, using a reference specified amount (e.g., 135 degrees).

[0096] The calibration table CTBLb stores the offset errors of phase shifters PSF1 and PSF2 for each frequency of the excitation signal VIN, and these offset errors are detected by the offset error detection circuit SED. Figure 7 It is shown Figure 6A A schematic diagram illustrating an exemplary configuration of the correction table in the diagram. For example... Figure 7 As shown, the calibration table CTBLb and Figure 3 The difference between the calibration table CTBLa and the standard table is that, for each frequency of the excitation signal VIN (and therefore the output frequency fres), it stores the offset error detected by the offset error detection circuit SED. and Offset error This indicates the error generated by the phase shifter PSF1, and the offset error. This indicates the error generated by the phase shifter PSF2.

[0097] During calibration, the offset setting circuit SST, while referencing the detection results of the phase difference detection circuit PHD, searches for offset setting values ​​SS1 and SS2 that cause the phase shifters PSF1 and PSF2 to be offset by specified amounts (45 degrees and 135 degrees), where, as an initial operation, the excitation signal VIN is set to the excitation frequency fexc (e.g., 20 kHz). During calibration and normal operation, the offset setting circuit SST sets the offset setting values ​​SS1 and SS2 obtained from the search results to the phase shifters PSF1 and PSF2.

[0098] During normal operation, the detection result corrector RTC corrects the rotation angle of the resolver RSV detected by the phase difference detection circuit PHD based on the reserved contents of the correction table CTBLb and a predetermined arithmetic expression. Specifically, the detection result corrector RTC first calculates the output frequencies fres of the detection signals E1 and E2 based on the rotational speed (apparent rotational speed (dθ0 / dt = fm)) detected in the speed detector SDET, the excitation frequency fexc of the excitation signal VIN, and the number of poles Np of the resolver RSV.

[0099] Subsequently, the detection result corrector RTC obtains the offset errors of phase shifters PSF1 and PSF2 by using the output frequency fres as the search keyword and referencing the correction table CTBLb. and The detection result corrector RTC is based on an arithmetic expression and uses offset error. The rotation angle of the resolver RSV (apparent rotation angle θ0) detected by the phase difference detection circuit PHD (position detector PDET) is used as a parameter to correct the rotation angle of the resolver RSV and calculate the true rotation angle θ. The current controller PIC determines the duty cycle based on the true rotation speed (dθ / dt) obtained from the true rotation angle θ and instructs the PWM signal generator PWMG.

[0100] Figure 6B It shows Figure 6A A schematic diagram of the modified example. Figure 6A In this configuration, the current controller PIC determines the duty cycle based on the actual rotational speed (dθ / dt) obtained from the actual rotational angle θ, and instructs the PWM signal generator PWMG. However, as Figure 6B As shown, since the error in rotational speed (dθ / dt) is much smaller than the error in rotational angle θ, the current controller PIC can determine the duty cycle based on the apparent rotational speed (dθ0 / dt) before correction. In this case, since the rotational speed is calculated from the rotational angle only once, the computational load on the control is reduced. Incidentally, in Figure 6B (also applicable to) Figure 6A The actual rotation angle θ calculated by the detection result corrector RTC is used, for example, as position information associated with the vector control of the motor MT.

[0101] <Arithmetic expression used to correct offset errors>

[0102] Figure 8 It is used to explain in Figure 6AThe graph shows the arithmetic expression used in the detection result corrector. First, the actual rotation angle (electrical angle) θ of the rotary transformer RSV and the frequency-modulated angular velocity ω (=ω0+ω) accompanying the rotation of the rotary transformer RSV are used. m The phase signals V1 and V2 obtained from the detection results of the rotary transformer RSV are expressed by equations (2) and (3). “ω0” is the angular velocity based on the excitation frequency fexc, and “ω m "This is the angular velocity (electric angle) of the rotary transformer RSV."

[0103] V1=sinθ×sinωt: Equation (2)

[0104] V2=cosθ×sinωt: Equation (3)

[0105] Now assume that phase shifters PSF1 and PSF2 shift phase signal V1 by 45 degrees (=π / 4) and phase signal V2 by 135 degrees (=3π / 4). At this time, as... Figure 8 As shown, the offset error generated on the phase signal V1 side is defined as And the offset error generated on the phase signal V2 side is defined as The phase signal V1' after the phase signal V1 is shifted is given by equation (4). On the other hand, the phase signal V2' after the phase signal V2 is shifted is represented by equation (5), and it is assumed that... Small enough to use and An approximate expression for is obtained, which leads to equation (6).

[0106]

[0107]

[0108]

[0109] The adder circuit ADDU outputs the phase signal V3' (=V1'+V2') of equation (7) by adding the phase signal V1' of equation (4) to the phase signal V2' of equation (6).

[0110]

[0111] The adder circuit ADDU converts the phase signal V3' from equation (7) into a rectangular wave (detecting the clock signal CKd) using the comparator CMP. Since the comparator CMP detects the phase at the midpoint (amplitude center) of the phase signal V3', it determines the phase to satisfy... of The error ΔV3' of the phase signal V3' when detecting the phase is expressed by equation (8).

[0112]

[0113] When comparator CMP detects phase At that time, the time derivative of the phase signal V3' in equation (7) becomes Therefore, using equation (8), the time conversion error Δt when the phase is detected by the comparator CMP becomes equation (9).

[0114]

[0115] As the frequency f (=ω / 2π) after frequency modulation, when the time conversion error Δt of equation (9) is converted into the electrical angle conversion error Δθ, the electrical angle conversion error Δθ when the phase is detected by the comparator CMP is equation (10).

[0116]

[0117] On the other hand, the phase difference detection circuit PHD detects the phase difference by comparing the electrical angle conversion error Δθ with the phase detected by the comparator CMP. The apparent rotation angle θ0 is obtained by adding the two sides. Therefore, the actual rotation angle θ is obtained through equation (11).

[0118]

[0119] Based on equations (10) and (11), the final electrical angle conversion error Δθ is given by equation (12), and the actual rotation angle θ is given by equation (13).

[0120]

[0121]

[0122] As shown in equation (13), the actual rotation angle θ can be based on the apparent rotation angle θ0 of the rotary transformer RSV detected by the phase difference detection circuit PHD (position detector PDET), and the offset error that occurs in the phase shifters PSF1 and PSF2 during detection. and The detection result corrector RTC obtains the offset error corresponding to the current output frequency fres from the correction table CTBLb. and Therefore, the actual rotation angle θ is calculated based on equation (13).

[0123] Operation of the Rotary Transformer Correction Device

[0124] Figure 9 It is illustrated in Figure 6A A flowchart of an exemplary process performed in the calibration operation [2] of a rotary transformer calibration device. Figure 9 In steps S201 to S206, an initial operation is performed as a prerequisite for the calibration operation, and in subsequent steps S301 to S310, a calibration operation for generating the calibration table CTBLb is performed. In step S201, the excitation signal supply circuit ESS provides an excitation clock signal CKe (and therefore an excitation signal VIN) having an excitation frequency fexc (e.g., 20kHz).

[0125] Subsequently, the selection switch SSW responds to the instruction from the offset setting circuit SST and selects the calibration path [1] (the path to the phase shifter PSF1) (step S202). Then, while the offset setting circuit SST sequentially changes the offset setting value SS1 (duty cycle PWMD1), it searches for the offset setting value SS1 under which the offset detected by the phase difference detection circuit PHD becomes a specified amount (45 degrees in this case).

[0126] Then, the calibration path [2] (the path to phase shifter PSF2) is processed in the same way as steps S202 and S203. Specifically, the selection switch SSW selects the calibration path [2] (step S204), and the offset setting circuit SST searches (step S205) for the offset setting value SS2 (duty cycle PWMD2) as follows, under which the offset detected by the phase difference detection circuit PHD is quantitative (here, 135 degrees). The offset setting circuit SST sets the offset setting values ​​SS1 and SS2 (PWMD1 and PWMD2) as the search results of steps S203 and S205 to phase shifters PSF1 and PSF2 (step S206).

[0127] Subsequently, in response to the instruction from the offset error detection circuit SED, the excitation signal supply circuit ESS provides an excitation clock signal CKe with frequency f[k] (and therefore an excitation signal VIN) at k=0 (step S301) (step S302). Then, the selection switch SSW selects the calibration path according to the instruction from the offset error detection circuit SED [1] (step S303). The offset error detection circuit SED detects the offset error based on the detection result of the phase difference detection circuit PHD (step S304). (That is, an error of 45 degrees). In step S305, the offset error detection circuit SED compares the frequency f[k] from step S302 with the offset error, which is the detection result of step S304. The correspondence between them is stored in the correction table CTBLb.

[0128] Next, in steps S306 to S308, the same process as in steps S303 to S305 is performed for the calibration path [2]. The selection switch SSW selects the calibration path [2] (step S306), and the offset error detection circuit SED detects the offset error. (That is, an error of 135 degrees) to detect offset error (Step S307). Then, the offset error detection circuit SED compares the frequency f[k] with the offset error. The correspondence between them is stored in the correction table CTBLb (step S308).

[0129] Subsequently, the offset error detection circuit SED repeats steps S302 to S308 while sequentially changing k, until k = kmax (steps S309 and S310). As a result, in Figure 7 In the calibration table CTBLb, the frequency f[k] in step S302 changes from 15kHz to 25kHz in increments of 1kHz, and the offset error for each frequency f[k] is... and It was stored.

[0130] Figure 10 It is illustrated in Figure 6A A flowchart illustrating the exemplary process content during normal operation [2] of a rotary transformer correction device. Figure 10 In step S400, the offset setting circuit SST sets offset setting values ​​SS1 and SS2 (PWMD1 and PWMD2) in phase shifters PSF1 and PSF2. These offset setting values ​​SS1 and SS2 (PWMD1 and PWMD2) are... Figure 9 The search results for steps S203 and S205. The excitation signal supply circuit ESS also supplies the excitation clock signal CKe (and therefore the excitation signal VIN) with the excitation frequency fexc (e.g., 20kHz) to the rotary transformer RSV via the selection switch SSW (step S401).

[0131] Subsequently, in steps S402 to S404, as in Figure 5In steps S202 to S204, the phase difference detection circuit PHD (position detector PDET) detects the apparent rotation angle θ0 of the resolver RSV (and therefore the motor MT), and the speed detector SDET detects the apparent rotational speed (dθ0 / dt = fm) of the motor MT. Then, the detection result corrector RTC uses the excitation frequency fexc, the rotational speed fm detected in step S403, and the predetermined number of poles Np of the resolver RSV to calculate the output frequency fres based on the above equation (1) (step S404).

[0132] Subsequently, the detection result corrector RTC obtains the offset error by using the output frequency fres calculated in step S404 as the search keyword to refer to the correction table CTBLb. and (Step S405). The detection result corrector RTC uses the offset error obtained in step S405. and And the apparent rotation angle θ0 detected by step S402 is corrected based on equation (13) to calculate the true rotation angle θ (and therefore the true rotation speed dθ / dt) (step S406).

[0133] Then, during normal operation, such as during each control period of the speed detector SDET, the resolver correction device repeats the process of steps S402 to S406 (step S407). In step S405, with Figure 5 The same as step S205 in the previous step, the detection result corrector RTC adjusts the offset error based on the value of the output frequency fres. and Appropriate linear interpolation.

[0134] <Main Effects of the Second Embodiment>

[0135] Using the rotary transformer correction device of the second embodiment can achieve the same effect as the first embodiment. Specifically, the detection error of the rotary transformer RSV for the rotation angle θ (rotation speed dθ / dt) can be reduced, thereby enabling high-precision control of the motor MT. Figure 11 This is a diagram illustrating an example of simulation results, in which... Figure 6A The detection error of the motor's rotation angle is compared between the case where the rotary transformer correction device performs correction and the case where it does not perform correction. Here, the excitation frequency fexc is assumed to be 20kHz, and the number of poles Np of the rotary transformer RSV is assumed to be 50 poles.

[0136] like Figure 11As shown, for example, when the rotational speed of the motor MT is in the range of 0 rpm to ±3000 rpm and no calibration is performed, a detection error of approximately -5.3 degrees to +5.3 degrees may occur. However, by performing calibration, the detection error can be reduced to approximately +0.3 degrees to +1.2 degrees. When the rotational speed of the motor MT is 0 rpm to ±6000 rpm and the MT is not calibrated, a detection error of approximately -11.8 degrees to +10.5 degrees may occur. However, by calibrating the MT, the detection error can be reduced to approximately -1.6 degrees to +1.2 degrees.

[0137] Furthermore, compared to the method of the first embodiment, for example, since it is not necessary to variably control the offset setting values ​​SS1 and SS2 (duty cycles PWMD1 and PWMD2) during normal operation, the effects of switching timing associated with variable control need not be considered. Moreover, in the method of the first embodiment, the detection error is related to the setting resolution of, for example, the duty cycles PWMD1 and PWMD2, but such a correlation is less likely to occur in the method of the second embodiment.

[0138] (Third Embodiment)

[0139] <Overview of Rotary Transformer Correction Device>

[0140] Figure 12A This is a schematic diagram illustrating an exemplary configuration of a microcomputer in a resolver correction apparatus according to a third embodiment. The third embodiment method is a combination of the first and second embodiment schemes. In the second embodiment method, the offset setting values ​​SS1 and SS2 of phase shifters PSF1 and PSF2 are fixed values, but in the third embodiment method, the offset setting values ​​SS1 and SS2 of phase shifters PSF1 and PSF2 are variably controlled in the same manner as in the first embodiment method. However, strictly speaking, depending on the setting resolution of the offset setting values ​​SS1 and SS2 (duty cycles PWMD1 and PWMD2), offset error remains in the offset of phase shifters PSF1 and PSF2. The third embodiment method uses the second embodiment method to correct the residual error.

[0141] Figure 12A The microcomputer MCU shown includes the table generation circuit TBG, Figure 1 The offset correction circuit SCR shown Figure 6A The detection result corrector RTC and the correction table CTBLc shown are included, and the table generation circuit TBG includes... Figure 1 The offset search circuit SSR shown is Figure 6AThe offset error detection circuit SED is shown. As described in the first embodiment, during the calibration operation, the offset search circuit SSR searches for the offset setting values ​​SS1 and SS2 for each frequency of the excitation signal VIN, and registers the searched offset setting values ​​SS1 and SS2 in the calibration table CTBLc.

[0142] During calibration, the offset error detection circuit SED reflects the offset setting values ​​SS1 and SS2 as the search results of the offset search circuit SSR, and then, for each frequency of the excitation signal VIN, the offset error remaining in the offsets of the phase shifters PSF1 and PSF2 is detected by the phase difference detection circuit PHD. and Then, the offset error detection circuit SED will detect the offset error for each frequency of the excitation signal VIN. Registered in calibration table CTBLc.

[0143] Figure 13 It shows Figure 12A A schematic diagram illustrating an exemplary configuration of the correction table in the diagram. For example... Figure 13 As shown, the calibration table CTBLc has the function of... Figure 3 The correction table CTBLa and Figure 7 The calibration table CTBLb is configured. The calibration table CTBLc stores the offset settings SS1, SS2 (duty cycles PWMD1, PWMD2) and offset error for each frequency of the excitation signal VIN (and therefore the output frequency fres).

[0144] Similar to the first embodiment, during normal operation, the offset correction circuit calculates the output frequency fres based on the rotational speed detected by the speed detector SDET, and obtains the corresponding duty cycles PWMD1 and PWMD2 from the calibration table CTBLc, setting them in the phase shifters PSF1 and PSF2. During normal operation, the detection result corrector RTC calculates the output frequency fres in the same manner as the RTC in the second embodiment, based on the rotational speed (apparent rotational speed (dθ0 / dt)) detected by the speed detector SDET, and obtains the corresponding offset error from the calibration table CTBLc. and The detection result corrector RTC uses offset error. The rotation angle (apparent rotation angle θ0) detected by the phase difference detection circuit PHD (position detector PDET) is corrected based on the arithmetic expression of equation (13) to calculate the true rotation angle θ (and thus calculate the true rotation speed (dθ / dt)).

[0145] Figure 12BIt shows Figure 12A A schematic diagram of the modified example. Figure 12B In the configuration example, with Figure 12A The configuration examples differ, such as in Figure 6B In the aforementioned case, the current controller PIC defines the duty cycle based on the apparent rotational speed (dθ0 / dt) before correction. Because the rotational speed from the rotational angle only needs to be calculated once, this reduces the computational burden of control.

[0146] Operation of the Rotary Transformer Correction Device

[0147] Figure 14 It is illustrated in Figure 12A A flowchart of an exemplary process performed in the calibration operation [3] of a rotary transformer calibration device. Figure 14 In response to a command from the offset search circuit SSR, the excitation signal supply circuit ESS provides an excitation clock signal CKe (and therefore an excitation signal VIN) with frequency f[k] at k=0 (step S501) (step S502). Subsequently, the selection switch SSW selects the calibration path [1] (the path to the phase shifter PSF1) in response to a command from the offset search circuit SSR (step S503).

[0148] Next, the offset search circuit SSR searches for the following offset setting value SS1 (duty cycle PWMD1) while sequentially changing the offset setting value SS1 (S504). Under this offset setting value SS1, the offset detected by the phase difference detection circuit PHD becomes a specified amount (45 degrees in this case). The offset search circuit SSR sets the offset setting value SS1, which is the search result, to the phase shifter PSF1.

[0149] In this case, the offset error detection circuit SED detects the offset error of the phase shifter PSF1 based on the detection results of the phase difference detection circuit PHD. (i.e., error from 45 degrees) (step S505). The table generation circuit TBG takes the frequency f[k] from step S502, the offset setting value SS1 (duty cycle PWMD1) as the search result from step S504, and the offset error as the detection result from step S505. The correspondence between them is stored in the correction table CTBLc (step S506).

[0150] Subsequently, in steps S507 to S510, the same process as steps S503 to S506 is performed for the calibration path [2] (the path to phase shifter PSF2). That is, the selection switch SSW selects the calibration path [2] (step S507), and the offset search circuit SSR searches (step S508) for the offset setting value SS2 (duty cycle PWMD2) as follows, under which the offset detected by the phase difference detection circuit PHD becomes a specified amount (here, 135 degrees).

[0151] Reflecting the search result, based on the detection results of the phase difference detection circuit PHD, the offset error detection circuit SED detects the offset error of the phase shifter PSF2 (the "offset error" of the phase shifter PSF2). (i.e., an error of 135 degrees) to detect offset error (Step S509). Then, the table generation circuit TBG sets the frequency f[k] from step S502, the offset setting value SS2 (duty cycle PWMD2) as the search result from step S508, and the offset error as the detection result from step S509. The correspondence between them is stored in the correction table CTBLc (step S510).

[0152] Subsequently, the offset search circuit SSR repeats steps S502 to S510 while sequentially changing k, until k = kmax (steps S511 and S512). As a result, the following is generated: Figure 13 The calibration table CTBLc is shown.

[0153] Figure 15 It is shown in Figure 12A A flowchart illustrating the exemplary process content during normal operation [3] of a rotary transformer correction device. Figure 15 In step S601, the excitation signal supply circuit ESS provides the excitation clock signal CKe (and thus the excitation signal VIN) with an excitation frequency fexc (e.g., 20kHz) to the rotary transformer RSV via the selection switch SSW.

[0154] Subsequently, in steps S602 to S604, as in Figure 5In steps S202 to S204, the phase difference detection circuit PHD (position detector PDET) detects the apparent rotation angle θ0 of the resolver RSV, thereby detecting the apparent rotation angle of the motor MT, and the speed detector SDET detects the apparent rotation speed of the motor MT (dθ0 / dt = fm). Then, the offset correction circuit SCR and the detection result corrector RTC use the excitation frequency fexc, the rotation speed fm detected in step S603, and the predetermined number of poles Np of the resolver RSV to calculate (step S604) the output frequency fres based on the above equation (1).

[0155] Subsequently, the offset correction circuit SCR obtains the offset setting values ​​SS1 and SS2 (duty cycles PWMD1 and PWMD2) corresponding to the calculated output frequency fres from the calibration table CTBLc (step S605), and sets the phase shifters PSF1 and PSF2 (step S606). The detection result corrector RTC obtains the offset error corresponding to the calculated output frequency fres from the calibration table CTBLc. and (Step S607). Then, the detection result corrector RTC uses the obtained offset error. and The apparent rotation angle θ0 detected in step S602 is corrected based on equation (13), and the true rotation angle θ is calculated (step S608) (thereby calculating the true rotation speed dθ / dt).

[0156] Then, while performing normal operation, the rotary transformer correction device repeats steps S602 to S608 (step S609) for each control period of the speed detector SDET. In step S605, specifically, the offset correction circuit SCR linearly interpolates the offset setpoints SS1 and SS2 based on the value of the output frequency fres. Similarly, in step S607, the detection result corrector RTC adjusts the offset error as needed based specifically on the value of the output frequency fres. and Linear interpolation.

[0157] <Main Effects of the Third Embodiment>

[0158] The resolver calibration device of the third embodiment produces the same effect as the first and second embodiments. Additionally, compared to the first and second embodiments, the detection error of the resolver RSV for the rotation angle θ (rotation speed dθ / dt) can be further reduced, thereby enabling higher precision control of the motor MT. Specifically, for the first embodiment method, as described above, in order to reduce the detection error, it is necessary to increase the setting resolution of the duty cycle associated with the offset setting value (and therefore increase the clock frequency).

[0159] On the other hand, in the second embodiment system, for example, in the above equation (6), because it is assumed Small enough to use an approximate expression Therefore, when the offset error As the offset error increases, the correction error also increases. As a specific example, when the offset error... At approximately 20 degrees Celsius, There is an approximation error of approximately 2% relative to 0.342.

[0160] Therefore, by combining the first embodiment with the second embodiment, the offset error can be reduced. Reduce to, for example, below 5 degrees. In this case, for The approximation error can be suppressed to approximately 0.1%. On the other hand, by combining the second embodiment with the first embodiment, even if the duty cycle setting resolution (clock frequency) associated with the offset setting value is low, the detection error of the rotation angle θ (rotation speed dθ / dt) can be sufficiently reduced using a correction equation. Satisfactory detection accuracy can be obtained even when the performance of the microcomputer MCU is low.

[0161] (Fourth Embodiment)

[0162] <Overview of Rotary Transformer Correction Device>

[0163] Figure 16A This is a schematic diagram illustrating an exemplary configuration of a microcomputer in a rotary transformer correction apparatus according to a fourth embodiment. (For...) Figure 12A An example configuration, Figure 16AThe microcomputer MCU also includes a calibration necessity determination circuit CJG. The calibration necessity determination circuit CJG is implemented, for example, through software processing by the processor CPU, but can be implemented in other ways. For example, the calibration necessity determination circuit CJG operates before the motor MT starts, provided by the excitation signal supply circuit ESS to the phase shifters PSF1 and PSF2 with an excitation frequency fexc, and the offset correction circuit SCR sets offset setting values ​​SS1 and SS2 corresponding to the excitation frequency fexc based on the correction table CTBLc.

[0164] In this case, the correction necessity determination circuit CJG enables the offset error detection circuit SED to detect the offset error corresponding to the excitation frequency fexc in phase shifters PSF1 and PSF2. and Then, the correction necessity determination circuit CJG will take the offset error of the detection result as the basis for its determination. Offset error stored in calibration table CTBLc A comparison is performed. Based on the comparison results, the correction necessity determination circuit CJG selects to execute. Figure 14 The calibration operation shown [3] is still performed. Figure 15 The normal operation is shown [3]. Specifically, when the comparison results are consistent, the calibration necessity determination circuit CJG performs normal operation [3], while when the comparison results are inconsistent, a calibration operation is performed [3]. At this time, for example, the criteria for judging consistency or inconsistency are determined according to the required accuracy of the motor system.

[0165] Figure 16B It is shown Figure 16A A schematic diagram of the modified example. Figure 16B In the configuration example, with Figure 16A The configuration examples are different, such as Figure 6B In the aforementioned scenario, the current controller PIC defines the duty cycle based on the apparent rotational speed (dθ0 / dt) before correction. Because the rotational speed from the rotational angle only needs to be calculated once, this reduces the computational burden on the control.

[0166] Operation of the Rotary Transformer Correction Device

[0167] Figure 17 It's a diagram. Figure 16A A flowchart illustrating an exemplary process for determining the necessity of correction in a circuit. For example, this process may be performed before the motor MT starts, after the microcomputer MCU and shaft angle digital converter RDC are powered on, during the waiting period of the motor MT, or when an instruction is received from the user. Figure 17 The process. In Figure 17In step S700, the calibration necessity determination circuit CJG determines whether a calibration table CTBLc has been generated in the storage circuit MEM. The storage circuit MEM can be, for example, a non-volatile memory.

[0168] If the calibration table CTBLc is not generated in step S700, the calibration necessity determination circuit CJG begins. Figure 14 The calibration operation in [3] (step S706). On the other hand, if the calibration table CTBLc has been generated in step S700, the calibration necessity determination circuit CJG causes the excitation signal supply circuit ESS to provide an excitation clock signal CKd with an excitation frequency fexc (and an excitation signal VIN) (step S701).

[0169] Subsequently, the correction necessity determination circuit CJG sends a command to the offset correction circuit SCR, and in response, the offset correction circuit SCR sets the offset setting values ​​SS1 and SS2 corresponding to the excitation frequency fexc obtained from the correction table CTBLc to the phase shifters PSF1 and PSF2 (step S702). Then, the correction necessity determination circuit CJG causes the offset error detection circuit SED to detect the offset error. (Step S703). Specifically, as follows: Figure 9 As shown in steps S303, S304, S306, and S307, the offset error detection circuit SED detects the offset error while switching calibration paths. and

[0170] Then, in step S704, the correction necessity determination circuit CJG will determine the offset error detected in step S703. and And the offset error corresponding to the excitation frequency fexc in the calibration table CTBLc and A comparison is performed. When the comparison results in step S704 are consistent, the correction necessity determination circuit CJG begins. Figure 15 The normal operation in step S704 [3] (step S705) is initiated, but when the comparison results in step S704 are inconsistent, the correction necessity determination circuit CJG starts. Figure 14 The calibration operation in [3] (step S706).

[0171] Here, the calibration necessity determination circuit CJG has automatically started normal operation[3] or calibration operation[3], but the calibration necessity determination circuit CJG can perform a process that leaves the activation to the user. Specifically, the calibration necessity determination circuit CJG assigns flags to the "no" case in step S700 and the "yes" and "no" cases in step S704, and notifies the user of these flags. The user instructs the resolver calibration device to perform normal operation[3] or calibration operation[3] based on the flags.

[0172] <Main Benefits of the Fourth Embodiment>

[0173] In addition to the various advantages described in the third embodiment, the resolver calibration apparatus of the fourth embodiment can reduce the number of calibration operations while also reducing the detection error of the rotation angle θ (rotation speed dθ / dt) caused by the resolver RSV. More specifically, frequent calibration operations may reduce system utilization. On the other hand, when the results of calibration operations are used for a long time, for example, changes in the system environment (temperature, etc.) and due to the aging of circuit components may increase the detection error.

[0174] When using the method of the fourth embodiment, the necessity of the calibration operation can be determined such that it is performed only when truly needed. Furthermore, since the necessity of the calibration operation is determined via a single excitation frequency fexc, the time required for the necessity determination is not a particular issue. In this example, although the calibration necessity determination circuit CJG is added... Figure 12A The configuration example is shown, but in the same way, the correction necessity determination circuit CJG can be added. Figure 6A Configuration example.

[0175] Although the present invention has been specifically described based on embodiments, it is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention. For example, the foregoing embodiments have been described in detail for ease of illustration, and the foregoing embodiments are not necessarily limited to embodiments including all the described configurations. Additionally, a portion of the configuration of one embodiment may be replaced by the configuration of another embodiment, and the configuration of another embodiment may be added to the configuration of one embodiment. Configurations of corresponding embodiments may also be added, deleted, or replaced.

Claims

1. A rotary transformer calibration device, comprising: A first phase shifter is used to output a first phase signal by shifting the phase of a first detection signal by a first offset amount according to a first offset amount setting value. The first detection signal is one of the orthogonal detection signals of the rotary transformer. The second phase shifter is used to output a second phase signal by shifting the phase of the second detection signal by a second offset amount according to a second offset amount setting value, wherein the second detection signal is another detection signal in the quadrature detection signals; An adder circuit is used to output a third phase signal by adding the first phase signal to the second phase signal; An excitation signal supply circuit is used to provide an excitation signal with an excitation frequency to the rotary transformer during normal operation, and to provide the excitation signal with multiple frequencies, including the excitation frequency, to the first phase shifter or the second phase shifter during calibration operation. The phase difference detection circuit detects the rotation angle of the rotary transformer during normal operation and detects the first offset or the second offset during the calibration operation by detecting the phase difference between the excitation signal from the excitation signal supply circuit and the third phase signal from the adder circuit. An offset search circuit is used, during the calibration operation, while referring to the detection result of the phase difference detection circuit, to search for a first offset setting value that makes the first offset become a first specified amount for each frequency of the excitation signal, and to search for a second offset setting value that makes the second offset become a second specified amount for each frequency of the excitation signal, wherein the second specified amount differs from the first specified amount by 90 degrees. as well as A storage circuit is used to store the first offset setting value and the second offset setting value for each frequency of the excitation signal, obtained by the search results obtained by the offset search circuit, as a calibration table.

2. The rotary transformer correction device according to claim 1, further comprising: A speed detector is used to detect the rotational speed of the rotary transformer during the normal operation, based on the rate of change of the rotational angle of the rotary transformer detected by the phase difference detection circuit. as well as An offset correction circuit is configured to, during normal operation, calculate the output frequency of the first detection signal or the output frequency of the second detection signal based on the rotational speed detected by the speed detector and the excitation frequency of the excitation signal; obtain the first offset setting value and the second offset setting value by referring to the correction table using the output frequency as a search keyword; set the first offset setting value to the first phase shifter and the second offset setting value to the second phase shifter.

3. The rotary transformer correction device according to claim 2, The first phase shifter and the second phase shifter each include an RC circuit, wherein the RC circuit includes a capacitor and multiple resistors. The first phase shifter controls the offset by switching a portion of the plurality of resistors in the RC circuit of the first phase shifter on or off by a first PWM signal. The second phase shifter controls the offset by switching a portion of the plurality of resistors in the RC circuit of the second phase shifter on or off by a second PWM signal. Wherein the first offset setting value is the duty cycle of the first PWM signal, and The second offset setting value is the duty cycle of the second PWM signal.

4. The rotary transformer correction device according to claim 1, During the calibration operation, the excitation signal supply circuit provides the excitation signal to the rotary transformer, the rotation of the rotary transformer is controlled to stop, and either the second phase signal or the first phase signal is disabled. The adder circuit outputs either the first phase signal or the second phase signal as the third phase signal.

5. The rotary transformer correction device according to claim 1, further comprising: A selection switch is used to select whether the excitation signal from the excitation signal supply circuit is provided to any one of the rotary transformer, the first phase shifter, or the second phase shifter.

6. The rotary transformer correction device according to claim 1, further comprising: An offset error detection circuit is configured, during the calibration operation, to detect, for each frequency of the excitation signal, the remaining first offset error in the first offset and the remaining second offset error in the second offset detected by the phase difference detection circuit, after reflecting the first offset setting value and the second offset setting value as the search results of the offset search circuit; and Test result corrector The calibration table of the storage circuit further stores the first offset error and the second offset error detected by the offset error detection circuit for each frequency of the excitation signal, and During normal operation, the detection result corrector corrects the rotation angle of the rotary transformer detected by the phase difference detection circuit based on the stored contents of the correction table and a predetermined arithmetic expression.

7. The rotary transformer correction device according to claim 6, further comprising: A speed detector is used to detect the rotational speed of the rotary transformer during the normal operation, based on the rate of change of the rotational angle of the rotary transformer detected by the phase difference detection circuit. as well as An offset correction circuit is configured to, during normal operation, calculate the output frequency of the first detection signal or the output frequency of the second detection signal based on the rotational speed detected by the speed detector and the excitation frequency of the excitation signal; obtain the first offset setting value and the second offset setting value by referring to the correction table using the output frequency as a search keyword; set the first offset setting value to the first phase shifter and the second offset setting value to the second phase shifter.

8. The rotary transformer correction device according to claim 7, The detection result corrector calculates the output frequency of the first detection signal or the output frequency of the second detection signal based on the rotational speed detected by the speed detector and the excitation frequency of the excitation signal; the detection result corrector obtains the first offset error and the second offset error by referring to the correction table using the output frequency as a search keyword; and the detection result corrector corrects the rotation angle of the rotary transformer based on the arithmetic expression, which uses the first offset error, the second offset error, and the rotation angle of the rotary transformer detected by the phase difference detection circuit as parameters.

9. The rotary transformer correction device according to claim 7, further comprising: The calibration necessity determination circuit, in a state where the excitation signal supply circuit provides the excitation signal having the excitation frequency to the first phase shifter or the second phase shifter, and the offset correction circuit sets a first offset setting value and a second offset setting value corresponding to the excitation frequency, is used to detect the first offset error and the second offset error corresponding to the excitation frequency in the offset error detection circuit; and compares the first offset error and the second offset error as detection results with the first offset error and the second offset error stored in the calibration table; And based on the comparison results, it is selected whether to perform the calibration operation or the normal operation.

10. A rotary transformer calibration device, comprising: A first phase shifter is used to output a first phase signal by shifting the phase of a first detection signal by a first offset amount according to a first offset amount setting value. The first detection signal is one of the orthogonal detection signals of the rotary transformer. The second phase shifter is used to output a second phase signal by shifting the phase of the second detection signal by a second offset amount according to a second offset amount setting value, wherein the second detection signal is another detection signal in the quadrature detection signals; An adder circuit is used to output a third phase signal by adding the first phase signal to the second phase signal; An excitation signal supply circuit is used to provide an excitation signal with an excitation frequency to the rotary transformer during normal operation. During calibration, the excitation signal having multiple frequencies is provided to the first phase shifter or the second phase shifter, the multiple frequencies including the excitation frequency; The phase difference detection circuit detects the rotation angle of the rotary transformer during normal operation and detects the first offset or the second offset during the calibration operation by detecting the phase difference between the excitation signal from the excitation signal supply circuit and the third phase signal from the adder circuit. An offset error detection circuit is configured to, during a calibration operation, detect a first offset error contained in the first offset detected by the phase difference detection circuit for each frequency of the excitation signal based on a predetermined first specified amount, and detect a second offset error contained in the second offset detected by the phase difference detection circuit for each frequency of the excitation signal based on a second specified amount that differs from the first specified amount by 90 degrees. A storage circuit is used to store the first offset error and the second offset error detected by the offset error detection circuit for each frequency of the excitation signal as a correction table; as well as A detection result corrector is used, during normal operation, to correct the rotation angle of the rotary transformer detected by the phase difference detection circuit, based on the stored contents of the correction table and a predetermined arithmetic expression.

11. The rotary transformer correction device according to claim 10, further comprising: An offset setting circuit is configured, during the calibration operation, to search for a first offset setting value that makes the first offset change to a first specified amount, and to search for a second offset setting value that makes the second offset change to a second specified amount, while referring to the detection result of the phase difference detection circuit, wherein, as an initial operation, the excitation signal is set to the excitation frequency. During the calibration operation and during the normal operation, the offset setting circuit sets the first offset setting value and the second offset setting value, which are used as search results, to the first phase shifter and the second phase shifter.

12. The rotary transformer correction device according to claim 10, further comprising: A speed detector is used to detect the rotational speed of the rotary transformer during normal operation, based on the rate of change of the rotational angle detected by the phase difference detection circuit. The detection result corrector calculates the output frequency of the first detection signal or the output frequency of the second detection signal based on the rotational speed detected by the speed detector and the excitation frequency of the excitation signal; the detection result corrector obtains the first offset error and the second offset error by referring to the correction table using the output frequency as a search keyword; and the detection result corrector corrects the rotation angle of the rotary transformer based on the arithmetic expression, which uses the first offset error, the second offset error, and the rotation angle of the rotary transformer detected by the phase difference detection circuit as parameters.

13. The rotary transformer correction device according to claim 11, The first phase shifter and the second phase shifter each include an RC circuit, wherein the RC circuit includes a capacitor and multiple resistors. The first phase shifter controls the offset by switching a portion of the plurality of resistors in the RC circuit of the first phase shifter on or off by a first PWM signal. The second phase shifter controls the offset by switching a portion of the plurality of resistors in the RC circuit of the second phase shifter on or off by a second PWM signal. Wherein the first offset setting value is the duty cycle of the first PWM signal, and The second offset setting value is the duty cycle of the second PWM signal.

14. The rotary transformer correction device according to claim 10, During the calibration operation, the excitation signal supply circuit provides the excitation signal to the rotary transformer, the rotation of the rotary transformer is controlled to stop, and either the second phase signal or the first phase signal is disabled. The adder circuit outputs either the first phase signal or the second phase signal as the third phase signal.

15. The rotary transformer correction device according to claim 10, further comprising: A selection switch is used to select whether the excitation signal from the excitation signal supply circuit is provided to any one of the rotary transformer, the first phase shifter, or the second phase shifter.

16. The rotary transformer correction device according to claim 11, further comprising: The calibration necessity determination circuit, in a state where the excitation signal supply circuit provides the excitation signal having the excitation frequency to the first phase shifter or the second phase shifter, and the offset correction circuit sets the first offset setting value and the second offset setting value corresponding to the excitation frequency, is used to detect the first offset error and the second offset error corresponding to the excitation frequency in the offset error detection circuit; and compare the first offset error and the second offset error as detection results with the first offset error and the second offset error stored in the calibration table; And based on the comparison results, it is selected whether to perform the calibration operation or the normal operation.

17. A calibration method for a rotary transformer calibration device, the rotary transformer calibration device comprising: A first phase shifter is used to output a first phase signal by shifting the phase of a first detection signal by a first offset amount according to a first offset amount setting value. The first detection signal is one of the orthogonal detection signals of the rotary transformer. The second phase shifter is used to output a second phase signal by shifting the phase of the second detection signal by a second offset amount according to a second offset amount setting value, wherein the second detection signal is another detection signal in the quadrature detection signals; An adder circuit is used to output a third phase signal by adding the first phase signal to the second phase signal; Storage circuitry, for including a calibration table, The correction method includes the following steps: (a) During normal operation, an excitation signal having an excitation frequency is provided to the rotary transformer; during calibration operation, the excitation signal having multiple frequencies, including the excitation frequency, is provided to the first phase shifter or the second phase shifter. (b) During normal operation, the rotation angle of the resolver is detected by the phase difference detection circuit by detecting the phase difference between the excitation signal provided in step (a) and the third phase signal from the adder circuit, and during the calibration operation, the first offset or the second offset is detected. (c) In the calibration operation, while referring to the detection result of the phase difference detection circuit, for each frequency of the excitation signal, the offset search circuit searches for a first offset setting value that makes the first offset become a first specified value; and for each frequency of the excitation signal, searches for a second offset setting value that makes the second offset become a second specified value, the second specified value differing from the first specified value by 90 degrees. (d) The first offset setting value and the second offset setting value for each frequency of the excitation signal obtained through the search results in step (c) are stored in the calibration table.

18. The correction method according to claim 17, further comprising the following steps: (e) During the normal operation, the rotational speed of the rotary transformer is detected based on the rate of change of the rotational angle detected in step (d); as well as (f) During the normal operation, based on the rotational speed detected in step (e) and the excitation frequency of the excitation signal, calculate the output frequency of the first detection signal or the output frequency of the second detection signal; obtain the first offset setting value and the second offset setting value by referring to the calibration table using the output frequency as a search keyword; set the first offset setting value to the first phase shifter and set the second offset setting value to the second phase shifter.

19. The calibration method according to claim 17, further comprising the following steps: (g) During the calibration operation, after reflecting the first offset setting value and the second offset setting value as the search results of the offset search circuit, for each frequency of the excitation signal, the remaining first offset error in the first offset and the remaining second offset error in the second offset detected by the phase difference detection circuit are detected; and the first offset error and the second offset error detected by the offset error detection circuit for each frequency of the excitation signal are stored. (h) During the normal operation, the rotation angle of the rotary transformer detected in step (b) is corrected based on the stored contents of the correction table and a predetermined arithmetic expression.

20. The calibration method according to claim 19, further comprising the following steps: (i) During the normal operation, the rotational speed of the rotary transformer is detected based on the rate of change of the rotational angle detected in step (b); (j) During the normal operation, based on the rotational speed detected in step (i) and the excitation frequency of the excitation signal, calculate the output frequency of the first detection signal or the output frequency of the second detection signal; obtain the first offset setting value and the second offset setting value by referring to the calibration table using the output frequency as a search keyword; set the first offset setting value to the first phase shifter and set the second offset setting value to the second phase shifter; In step (h), based on the rotational speed detected in step (i) and the excitation frequency of the excitation signal, the output frequency of the first detection signal or the output frequency of the second detection signal is calculated; by referring to the correction table using the output frequency as a search keyword, the first offset error and the second offset error are obtained; and based on the arithmetic expression, the rotation angle of the rotary transformer is corrected, the arithmetic expression taking the first offset error, the second offset error, and the rotation angle of the rotary transformer detected by the phase difference detection circuit as parameters.

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