A loop compensation circuit and its compensation method

Abstract

The present invention provides a loop compensation circuit, which includes a switching circuit, a hysteresis compensation circuit, and a sampling circuit. The switching circuit is used to be controlled by a control signal with a fixed pulse width and a frequency proportional to the switching frequency of the main power switch of the switching power supply, and transmit the error amplified signal output by the feedback network of the switching power supply to the hysteresis compensation circuit; the hysteresis compensation circuit is used to compensate the error amplified signal output by the feedback network of the switching power supply and transmit it to the sampling circuit; the sampling circuit is used to sample the error amplified signal output by the feedback network of the switching power supply and transmit it, together with the compensated error amplified signal, to the duty cycle control circuit of the main power switch of the switching power supply. The present invention also provides a corresponding loop compensation method. The present invention directly adds a zero point to the open-loop transfer function of the loop compensation circuit, without waiting for other circuits to conduct, and without considering, for example, the response time of a buffer, etc., thus accelerating the response of the power supply system.

Description

Technical Field

[0001] The present invention relates to the field of switching converters, and particularly to a loop compensation circuit and a compensation method thereof. Background Art

[0002] A switching converter (also known as a switching power supply) generally maintains the output voltage of the converter stable through a negative feedback control loop. However, for any negative feedback system, there is a problem of loop stability. The stability of a control system is determined by the system structure because a control system generally contains energy storage elements and inertial elements such as capacitors and inductors. Since the energy of such elements cannot change suddenly, when the system is disturbed or there is an input quantity, the control process will not be completed immediately but will have a certain delay. If this delay causes the feedback signal to be added to the original disturbance or input signal in phase, the system will exhibit an oscillation phenomenon. If this oscillation process gradually weakens, the system will eventually tend to be stable; if the oscillation process remains constant or gradually increases, the system will get out of control, that is, an unstable system. According to the "Barkhausen criterion", the criterion for the stability of a control system is that at the frequency where the open-loop loop gain is 1 (i.e., the crossover frequency), the total open-loop phase delay of all the links of the system must be less than 360°. In addition, the difference between the phase angle corresponding to the system at the crossover frequency and -180° is defined as the phase margin. If the phase margin is too small, the system will exhibit damped oscillations; if the phase margin is too large, the response speed of the system will become slow. In order to reduce the oscillation amplitude caused by the step response of the feedback system and provide a fast adjustment speed, the phase margin is generally designed between 45° and 70°.

[0003] In order to meet the requirements of the phase margin, a lag compensation circuit is often used in a switching converter. As Figure 3 shown, a passive lag compensation circuit usually consists of two resistors R1, R2 and a capacitor C1 connected in series in sequence, and its transfer function Gc(s) is given by Equation (1),

[0004]

[0005] In Equation (1), s is the independent variable in the s-domain, also known as the "complex frequency".

[0006] Let T = R2C1, then Equation (1) is transformed into:

[0007]

[0008] According to common general knowledge, the zero frequency fz and the pole frequency fp of the compensation are respectively:

[0009]

[0010]

[0011] The relevant formula derivation of the transfer function of the above lag compensation circuit and its frequency characteristics are analyzed in detail in the first edition of "Principles of Automatic Control" published by Chemical Industry Press, edited by Sun Youxian and Wang Hui. The ISBN number of this book is 978 - 7 - 122 - 11607 - 9. In particular, on pages 253 to 256 of "Principles of Automatic Control", the author describes the steps of designing a lag compensation circuit using the frequency domain method. To ensure that the lag angle of the lag compensation circuit at the system cut-off frequency fc (also known as the crossover frequency in a switching converter) is not greater than -6°, generally, the zero frequency of the compensation is taken as one-tenth of the crossover frequency. In a switching converter system, the crossover frequency is generally designed to be 1 / 6 to 1 / 10 of the switching frequency to meet the stability requirements. The loop stability is analyzed in detail in the first edition of "Mastering Switching Power Supply Design" written by Sanjaya Maniktala and translated by Wang Zhiqiang et al., published by Posts & Telecom Press. The ISBN number of this book is 978 - 7 - 115 - 18500 - 6. In Chapter 7 of the first edition of "Mastering Switching Power Supply Design", especially in Section 7.24 on page 201, the most popular and simplest method for judging loop stability is given.

[0012] If the switching frequency of a power supply system is 100 kHz, then its maximum crossover frequency is 16.7 kHz. So, the zero frequency of the lag compensation design can be taken as 1.67 kHz. From equations (3) and (4), it can be calculated that when R2 = 68 kΩ, C1 ≈ 1.4 nF. If α is taken as 6, then R1 = 340 kΩ.

[0013] If the power supply system uses PFM control, then the switching frequency will decrease during light load, especially the no-load switching frequency will drop to the lowest. Taking the no-load switching frequency as 1 kHz as an example, according to the above lag compensation circuit design method, the specifications of the compensation components R1, R2, and C1 required under full load and light load conditions are calculated as shown in Table 1 below:

[0014] Table 1

[0015]

[0016] Generally, considering the loop stability at no-load, the compensation capacitor C1 should be taken as 140 nF. However, neither a 1.4 nF nor a 140 nF capacitor is easy to integrate in the controller. Moreover, because the compensation capacitor is large, it seriously affects the slew rate of the output signal of the compensation circuit, causing poor and difficult-to-correct dynamic characteristics for the system.

[0017] Although in integrated circuits, resistors can be drawn in a folded manner to reduce the area. Therefore, in integrated circuits, usually on the premise of keeping the RC constant unchanged, larger resistors are used to reduce the capacitance in order to obtain a smaller area. However, even with such an operation, directly extending the existing technology to integrated circuits is still difficult to achieve, as shown in Table II below:

[0018] Table II

[0019]

[0020] As can be seen from Table II, even if the resistor is magnified nearly 44 times, the capacitance C1 can only be reduced to 3.17 nF, which is still not easy to integrate and is not conducive to improving the dynamic characteristics of the system.

[0021] The Chinese invention patent with the patent number CN201510574605.6 discloses a loop compensation circuit, including a switching circuit, a hysteresis compensation circuit, and a sampling circuit. The switching circuit is controlled by a control signal with a preset duty cycle to receive the error amplification signal output by the switching power supply feedback network and transmit it to the hysteresis compensation circuit. The preset duty cycle can amplify the RC constant of the hysteresis compensation circuit; the hysteresis compensation circuit generates a compensated signal and transmits it to the sampling circuit; the sampling circuit is controlled by another control signal with a preset duty cycle to transmit the received compensated signal to the duty cycle control circuit of the switching power supply main power switch tube. The sampling circuit completely preserves the compensated signal and then completely transmits it to the duty cycle control circuit of the switching power supply main power switch tube. The preset duty cycle of the switching circuit is generated based on the driving signal of the switching power supply main power switch tube. The frequency of the control signal is proportional to the switching frequency of the switching power supply main power switch tube. The preset duty cycle of the sampling circuit is the same as that of the switching circuit. The control signal of the sampling circuit and the control signal of the switching circuit are a pair of synchronous signals.

[0022] This patent also discloses the specific circuit structure of the above circuit, such as Figure 1 shown, the loop compensation circuit ( Figure 1 within the dashed box) includes a switching circuit 103, resistors R 101 、R 102 , capacitors C 101 、C 102 , a differential amplifier 104, and a sampling switch 105. Resistors R 101 、R 102 and capacitor C 101 constitute the hysteresis compensation circuit, and the differential amplifier 104, the sampling switch 105, and capacitor C 102A sampling circuit is formed. The feedback pin FB is connected to the inverting input terminal of the transconductance amplifier 102 through an inflection point sampling module 101. The non-inverting input terminal of the transconductance amplifier 102 is connected to the reference voltage VFBR. The output terminal of the transconductance amplifier 102 is connected to the first terminal of the switch circuit 103 to form node ①. The second terminal of the switch circuit 103 is connected to the first terminal of the first resistor R 101 to form node ②. The third terminal of the switch circuit 103 is connected to the pulse generator 107 to form node ③. The second terminal of the first resistor R 101 is connected to the first terminal of the resistor R 102 to form node ④. Node ④ is also connected to the non-inverting input terminal of the differential amplifier 104. The second terminal of the resistor R 102 is grounded (i.e., the negative pole of the input voltage VIN) through the first capacitor C 101 . The inverting input terminal of the differential amplifier 104 is connected to the output terminal of the differential amplifier 104 and the first terminal of the sampling switch 105. The second terminal of the sampling switch 105 is connected to the first terminal of the duty cycle control circuit 106. The second terminal of the sampling switch 105 is also grounded through the second capacitor C 102 . The third terminal of the sampling switch 105 is connected to node ③. The second terminal of the duty cycle control circuit 106 outputs a drive signal to control the main power switch tube SW. The switch circuit 103, as shown in Figure 2 , includes a transmission gate circuit composed of a PMOS transistor PM1 and an NMOS transistor NM1, and a NOT gate 111. The drain of the PMOS transistor PM1 is connected to the source of the NMOS transistor NM1 to form the first terminal of the switch circuit, which is used to connect to the output terminal of the transconductance amplifier of the flyback converter. The source of the PMOS transistor PM1 is connected to the drain of the NMOS transistor NM1 to form the second terminal of the switch circuit, which is connected to the compensation circuit after connection. The input terminal of the NOT gate 111 is connected to the gate of the NMOS transistor NM1 to form the third terminal of the switch circuit, which is used to connect to the pulse generator of the flyback converter. The output terminal of the NOT gate 111 is connected to the gate of the PMOS transistor PM1.

[0023] This patent can achieve lag compensation by using relatively small passive devices such as capacitors and resistors. The control circuit can be fully integrated into the controller, reducing the number of peripheral components and lowering the power supply cost. In the application scenarios of pulse frequency modulation (PFM) control mode, dynamic zero and pole compensation can also be achieved, and only a relatively small capacitor is required to meet the switching power supply loop stability requirements under full load (higher switching frequency) and no load (lower switching frequency) conditions.

[0024] However, the above disclosed circuit has the following problems:

[0025] Only when the switching circuit 103 is turned on can the signal be transmitted normally. That is, the zeros and poles compensated by the loop compensation circuit can be completely added to the open-loop transfer function only when the switching circuit 103 is turned on. Therefore, it is necessary to save the signal at node ④ during the conduction time of the switching circuit 103. Wait for the switching circuit 103 to turn on, and it also needs to pass through the differential amplifier 104. The differential amplifier 104 also requires a certain response time, and the effect of accelerating the response speed of the power supply system by the zero is delayed. During the load jump of the power supply system, such as from light load to full load, the operating frequency of the power supply system is low under light load. When the system load changes, it is necessary to wait for at least one switching period, plus the response time of the differential amplifier 104, to respond to the change of the load. The response time of the power supply system is delayed due to the delay of the zero point effect.

[0026] In addition, in the actual use of the above circuit, in order to reliably transmit the zero point to the open-loop transfer function, the pulse width of the control signal of the switching circuit is limited by the response time of the differential amplifier 104. If the pulse width of the control signal is less than the response time of the differential amplifier 104, the differential amplifier 104 cannot completely add the zero point to the open-loop transfer function during the conduction period of the switching circuit 103, and the response of the power supply system lags more behind the load change. The pole is to slow down the response of the power supply system. If the fixed value is less than the response time of the differential amplifier 104, the pole cannot be completely added to the open-loop transfer function through the differential amplifier 104 during the conduction period of the switching circuit 103, and the "slow down the response of the power supply system" will slow down, but instead promote the response of the power supply system. Summary of the Invention

[0027] In view of the above-mentioned disadvantages and limitations of the prior art, the present invention aims to provide a loop compensation circuit and its compensation method to reduce the influence of the response time of the differential amplifier on accelerating the response speed of the power supply system.

[0028] A loop compensation circuit for a switching power supply includes a switching circuit, a lag compensation circuit, and a sampling circuit. The switching circuit, the lag compensation circuit, and the sampling circuit are connected in series in sequence. The switching circuit is used to be controlled by a control signal and transmit the error amplified signal output by the feedback network of the switching power supply to the lag compensation circuit; the pulse width of the control signal is an adjustable fixed value, and the frequency of the control signal is proportional to the switching frequency of the main power switch tube of the switching power supply; the lag compensation circuit is used to compensate the error amplified signal output by the feedback network of the switching power supply to obtain a compensated error amplified signal, and then transmit it to the sampling circuit. The RC constant of the lag compensation circuit is amplified by the preset duty cycle of the control signal; the sampling circuit is used to sample the error amplified signal output by the feedback network of the switching power supply to obtain a sampled error amplified signal, and transmit the sampled error amplified signal and the compensated error amplified signal to the duty cycle control circuit of the main power switch tube of the switching power supply.

[0029] Preferably, the RC constant of the lag compensation circuit generates a pole during the operation of the circuit, and the sampling error amplification signal of the sampling circuit generates a zero during the operation of the circuit.

[0030] As a specific implementation of the sampling circuit, it includes a buffer, resistor R103, resistor R104, and capacitor C102. The input end of the buffer 104 is connected to the lag compensation circuit, the output end of the buffer 104 is connected to one end of the resistor R104, one end of the resistor R103 is connected to the output end of the switching power supply feedback network, the other end of the resistor R103 is connected to the other end of the resistor R104, the input end of the duty cycle control circuit of the switching power supply, and one end of the capacitor C102, and the other end of the capacitor C102 is connected to the reference potential.

[0031] Preferably, the buffer is a differential amplifier. The positive input terminal of the differential amplifier is the input terminal of the buffer, and the negative input terminal of the differential amplifier is connected to the output terminal of the differential amplifier to form the output terminal of the buffer.

[0032] As a specific implementation of the lag compensation circuit, it includes a resistor device and capacitor C101. One end of the resistor device is connected to the switching circuit, the other end of the resistor device is connected to the first end of the capacitor C101 and the sampling circuit, and the second end of the capacitor C101 is connected to the reference potential.

[0033] Preferably, the resistor device is composed of multiple resistors connected in series.

[0034] Preferably, the loop compensation circuit further includes a fast response circuit, and the fast response circuit is connected in parallel with some of the multiple resistors.

[0035] Preferably, the fast response circuit includes at least two bipolar transistors of the same or different types, or two MOS transistors of the same or different types, or two diodes.

[0036] As a specific implementation of the fast response circuit, it includes NMOS transistor NM2 and NMOS transistor NM3. The gate and drain of NMOS transistor NM2 are connected to the drain of NMOS transistor NM3 to form the first end of the fast response circuit, which is connected to the first end of resistor R101. The source of NMOS transistor NM2 is connected to the gate and source of NMOS transistor NM3 to form the second end of the fast response circuit, which is connected to the second end of resistor R101.

[0037] The present invention also provides a loop compensation method for a switching power supply, including the following steps:

[0038] A switching control step, controlled by a control signal with a pulse width of an adjustable fixed value and a frequency proportional to the switching frequency of the main power switch tube of the switching power supply, and transmitting the error amplification signal output by the switching power supply feedback network to the next step;

[0039] A hysteresis compensation step, after compensating the error amplification signal output by the feedback network of the switching power supply, transmits it to the next step;

[0040] A sampling step, after sampling the error amplification signal output by the feedback network of the switching power supply, transmits it together with the compensated error amplification signal to the duty cycle control circuit of the main power switch tube of the switching power supply.

[0041] In the specific embodiment part, the principles, functions, etc. of the technical solutions and technical features of the circuits of the present invention are analyzed. Now, the beneficial effects of the present invention are summarized as follows:

[0042] 1. The zero point is directly added to the open-loop transfer function of the loop compensation circuit, without waiting for other circuits to conduct, and without considering, for example, the response time of a buffer, etc., which speeds up the response of the power supply system;

[0043] 2. The zero point is directly added to the open-loop transfer function of the loop compensation circuit, without considering the size of the preset duty cycle of the switching circuit, reducing the requirement for the response time of the buffer;

[0044] 3. To meet the requirements of the fast dynamic response of the power supply system, it is only necessary to flexibly set the resistor devices in the hysteresis compensation circuit. To meet the load-carrying capacity of the buffer, set the resistors R 103 、R 104 in the sampling circuit, and the circuit debugging is simple and easy to operate. Description of the Drawings

[0045] Figure 1 is a circuit schematic diagram of a loop compensation circuit of the prior art;

[0046] Figure 2 is a circuit schematic diagram of a switching circuit in a loop compensation circuit of the prior art;

[0047] Figure 3 is a schematic diagram of a prior art passive hysteresis compensation circuit;

[0048] Figure 4 is a circuit schematic diagram of the first embodiment of the present invention;

[0049] Figure 5 is a circuit schematic diagram of the second embodiment of the present invention;

[0050] Figure 6 is a circuit schematic diagram of a fast response circuit in the loop compensation circuit of the present invention. Detailed Description of the Invention

[0051] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0052] The first embodiment

[0053] As Figure 4 shown is the circuit schematic diagram of the first embodiment of the present invention. In the controller, the feedback pin FB is connected to the inverting input terminal of the transconductance amplifier 102 through an inflection point sampling module 101, and the non-inverting input terminal of the transconductance amplifier 102 is connected to the reference voltage V FBR , the output terminal of the transconductance amplifier 102, the first terminal of the resistor R 103 , and the first terminal of the switch circuit 103 are connected to form node ①. The second terminal of the switch circuit 103 is connected to the first terminal of the resistor R 101 to form node ②. The third terminal of the switch circuit 103 is connected to the pulse generator 106 to form node ③. The second terminal of the resistor R 101 is connected to the first terminal of the resistor R 102 . The second terminal of the resistor R 102 is connected to the first terminal of the capacitor C 101 to form node ④. Node ④ is also connected to the non-inverting input terminal of the differential amplifier 104. The second terminal of the capacitor C 101 is connected to the reference potential. The inverting input terminal of the differential amplifier 104 is connected to the output terminal of the differential amplifier 104 and the second terminal of the resistor R 104 . The first terminal of the resistor R 104 , and the second terminal of the resistor R 103 are connected, and the connection point is connected to the first terminal of the duty cycle control circuit 105 and the first terminal of the capacitor C 102 . The second terminal of the capacitor C 102 is connected to the reference potential. The second terminal of the duty cycle control circuit 106 outputs a drive signal to control the main power switch tube SW.

[0054] The loop compensation circuit of the present invention ( Figure 4 within the dashed box) includes the switch circuit 103, the resistors R 101 , R 102 , R 103 , R 104 , the capacitors C 101 , C 102 , and the differential amplifier 104. The resistors R 101 , R 102 and the capacitor C 101 form a lag compensation circuit. The differential amplifier 104, the resistors R 103 , the resistor R 104 and the capacitor C 102 form a sampling circuit. The switch circuit 103 adopts the structure as shown in Figure 2 .

[0055] The switch circuit 103 has a pulse width of T p , and a period of Tsw is controlled by a control signal, and the pulse width T p is a fixed value, that is, the duty cycle of the switching circuit 103 is T p / T sw <1. When the error amplification signal at node ① changes, since at node ④, the voltage across the capacitor C 101 cannot change suddenly, the differential amplifier 104 transmits the compensated error amplification signal voltage at node ④ to the output terminal of the differential amplifier 104 and the second terminal of the resistor R 104 . The change of the error amplification signal at node ① is sampled through the resistors R 103 , R 104 and stored in the capacitor C 102 to form a zero-point effect. The pole signal at node ④ is stored in the capacitor C 103 through the differential amplifier 104, the resistors R 104 . Therefore, the transfer function of the loop compensation circuit of the present invention is: 102 Among them

[0056]

[0057] Therefore, the compensated zero-point frequency f

[0058] and the pole frequency f z and f p are respectively:

[0059]

[0060]

[0061] By selecting the resistors R103 and R104, a ratio α is formed, and the ratio of the pole signal to the zero signal is also α.

[0062] First, in order to improve the attenuation effect on high-frequency noise signals, the ratio coefficient α is set to 1 / 6. Then, according to the general design experience of switching power supply loop compensation and lag compensation, we set the zero-point frequency of the loop compensation circuit at 1 / 60 of the switching frequency. Now, taking the control signal period T sw of the switching circuit to be consistent with the switching period, and the control signal pulse width T p to be 200 ns. Then, calculated according to the full-load switching frequency of 100 kHz (that is, the period T sw is also 100 kHz), the compensated zero-point frequency f z is 1.67 kHz. According to Equation (6), it can be obtained that (R 101 +R 102 )*C 101 =0.318×10 -6 . If the capacitor C 101Take 6.4 pF, and the resistance (R 101 +R 102 ) is 49.7 kΩ, where R 101 , R 102 can be flexibly set according to the requirements of the fast dynamic response of the power supply system. In addition, R 103 , R 104 are set to meet the ratio α and the load-carrying capacity of the buffer 104. From Equation (7), the pole frequency f P is 0.278 kHz. At this parameter, calculated according to the no-load switching frequency of 1 kHz, the compensated zero frequency becomes 0.0167 kHz, which is still 1 / 60 of 1 kHz and also meets the stability requirements of no-load.

[0063] Analyze the parameters obtained in this embodiment in combination with Table II as shown in Table III below:

[0064] Table III

[0065]

[0066] As can be seen from the above table, compared with the existing passive lag compensation circuit technology, the present invention only needs to reduce the compensation resistors R 101 , R 102 by 0.73 times, and the compensation capacitor C 101 can be reduced by 4 orders of magnitude, greatly reducing the difficulty of integration.

[0067] Second Embodiment

[0068] As Figure 5 shown is the circuit schematic diagram of the second embodiment of the present invention. Compared with the first embodiment, the difference is that it further includes a fast response circuit 205, which is connected in parallel across the resistor R 201 (R 101 ).

[0069] The fast response circuit 205 is as Figure 6 shown and consists of two NMOS transistors. The gate and drain of NMOS transistor NM2, and the drain of NMOS transistor NM3 are connected to node ②. The source of NMOS transistor NM2, and the gate and source of NMOS transistor NM3 are connected to node ⑤.

[0070] The fast response circuit 205 only works when the load of the converter suddenly changes. When the load of the converter suddenly changes, the error amplifier outside the controller will respond instantaneously and change the error amplification signal V EA . For example, when the load of the converter suddenly increases, the output voltage decreases, and the error amplification signal V EA increases. Then when the switching circuit 203 is turned on, the voltage at node ② will be much greater than that at node ⑤. At this time, NMOS transistor NM2 is turned on, and the resistor R 201The short circuit improves the response speed of the lag compensation circuit, effectively avoiding problems such as poor dynamic performance caused by a low pole frequency and improving the dynamic response characteristics of the loop. Similarly, if the load suddenly becomes smaller, the error amplification signal V EA becomes smaller, and the NMOS transistor NM3 conducts, also improving the response speed of the loop compensation circuit.

[0071] The dynamic response circuit in the second embodiment is combined with the present invention to jointly accelerate the response speed of the loop compensation circuit, thereby accelerating the response speed of the system.

[0072] The above are only the preferred embodiments of the present invention. It should be noted that the above preferred embodiments should not be regarded as a limitation of the present invention. It should also be recognized that the present invention can be applied to other broader ranges. According to the above content of the present invention, using the ordinary technical knowledge and conventional means in the art, without departing from the above basic technical idea of the present invention, the present invention can also be modified, replaced or changed in various other forms, all of which fall within the scope of the protection of the present invention.

Claims

1. A loop compensation circuit for a switching power supply, comprising a switching circuit, a hysteresis compensation circuit, and a sampling circuit. The switching circuit, the hysteresis compensation circuit, and the sampling circuit are connected in series in sequence. It is characterized in that: The switching circuit is used to be controlled by a control signal and transmit the error amplified signal output by the feedback network of the switching power supply to the hysteresis compensation circuit; The pulse width of the control signal is an adjustable fixed value, and the frequency of the control signal is proportional to the switching frequency of the main power switch tube of the switching power supply; The hysteresis compensation circuit is used to compensate the error amplified signal output by the feedback network of the switching power supply to obtain a compensated error amplified signal and then transmit it to the sampling circuit. The RC constant of the hysteresis compensation circuit is amplified by the preset duty ratio of the control signal; The sampling circuit is used to sample the error amplified signal output by the feedback network of the switching power supply to obtain a sampled error amplified signal and transmit the sampled error amplified signal and the compensated error amplified signal to the duty ratio control circuit of the main power switch tube of the switching power supply; The sampling circuit described above includes a buffer, resistor R 103 , resistor R 104 and capacitor C 102 . The input end of the buffer 104 is connected to the hysteresis compensation circuit, and the output end of the buffer 104 is connected to one end of the resistor R 104 . One end of the resistor R 103 is used to be connected to the output end of the switching power supply feedback network. The other end of the resistor R 103 is connected to the other end of the resistor R 104 , the input end of the duty cycle control circuit of the switching power supply, and one end of the capacitor C 102 . The other end of the capacitor C 102 is connected to the reference potential.

2. The loop compensation circuit according to claim 1, wherein: The RC constant of the said hysteresis compensation circuit generates a pole during the operation of the circuit, and the sampled error amplified signal of the sampling circuit generates a zero point during the operation of the circuit.

3. The loop compensation circuit according to claim 1, wherein: The said buffer is a differential amplifier. The non-inverting input terminal of the differential amplifier is the input terminal of the buffer, and the inverting input terminal of the differential amplifier is connected to the output terminal of the differential amplifier to form the output terminal of the buffer.

4. The loop compensation circuit according to claim 1, wherein: The said hysteresis compensation circuit includes a resistive device and a capacitor C101. One end of the resistive device is connected to the switching circuit, and the other end of the resistive device is connected to the first end of the capacitor C101 and the sampling circuit. The second end of the capacitor C101 is connected to a reference potential.

5. The loop compensation circuit according to claim 4, wherein: The said resistive device is composed of multiple resistors connected in series.

6. The loop compensation circuit according to claim 5, wherein: It further includes a fast response circuit, and the fast response circuit is connected in parallel with some of the multiple resistors.

7. The loop compensation circuit according to claim 6, characterized in that: The said fast response circuit includes at least two bipolar transistors of the same or different types, or two MOS transistors of the same or different types, or two diodes.

8. The loop compensation circuit according to claim 6, wherein: The said fast response circuit includes an NMOS transistor NM2 and an NMOS transistor NM3. The gate and drain of the NMOS transistor NM2 are connected to the drain of the NMOS transistor NM3 to form the first end of the fast response circuit and connect to the first end of the resistor R101. The source of the NMOS transistor NM2 is connected to the gate and source of the NMOS transistor NM3 to form the second end of the said fast response circuit and connect to the second end of the resistor R101.

9. A loop compensation method for a switching power supply, characterized in that, It includes the following steps: A switching control step, controlled by a control signal with a fixed pulse width and a frequency proportional to the switching frequency of the main power switch tube of the switching power supply, and transmit the error amplified signal output by the feedback network of the switching power supply to the next step; A hysteresis compensation step, after compensating the error amplified signal output by the feedback network of the switching power supply, transmit it to the next step; A sampling step, after sampling the error amplified signal output by the feedback network of the switching power supply, and transmit it together with the compensated error amplified signal to the duty ratio control circuit of the main power switch tube of the switching power supply; The sampling step is implemented by a sampling circuit, and the sampling circuit includes a buffer, resistor R 103 , resistor R 104 and capacitor C 102 . The input end of the buffer 104 is connected to the hysteresis compensation circuit, and the output end of the buffer 104 is connected to one end of the resistor R 104 . One end of the resistor R 103 is used to be connected to the output end of the switching power supply feedback network. The other end of the resistor R 103 is connected to the other end of the resistor R 104 , the input end of the duty cycle control circuit of the switching power supply, and one end of the capacitor C 102 . The other end of the capacitor C 102 is connected to the reference potential.

Images