storage device

Abstract

A storage device is provided. The storage device includes a substrate, a stack structure including a plurality of gate layers and a plurality of interlayer insulating layers alternately stacked in a vertical direction on the substrate, the stack structure including rows of cutouts each extending in a first horizontal direction and configured to divide the plurality of gate layers, the cutouts being separated from each other and arranged in a cell region of the stack structure in the first horizontal direction, and rows of channel structures arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.

Description

[0001] Cross-references to related applications

[0002] The entire contents of Korean Patent Application No. 10-2019-0125694 entitled "Memory Device", which was filed with the Korean Intellectual Property Office on October 10, 2019, are incorporated herein by reference. Technical Field

[0003] The embodiments relate to semiconductor memory devices. Background Technology

[0004] Electronic devices with smaller size, larger data processing capacity, and lower cost are being developed. For example, storage devices with higher integration can be formed. Summary of the Invention

[0005] An embodiment relates to a memory device, comprising: a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers alternately stacked on the substrate in a vertical direction, the stacked structure including rows of cutouts, each of the cutouts extending in a first horizontal direction and configured to divide the plurality of gate layers, the cutouts being separated from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and rows of channel structures arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.

[0006] An embodiment relates to a memory device, comprising: a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers alternately stacked on the substrate in a vertical direction; and a channel structure arranged in a cell region of the stacked structure as a first row channel structure, a second row channel structure, and a third row channel structure, the rows extending in a first horizontal direction, and the channel structures all extending in the vertical direction to penetrate the plurality of gate layers. The stacked structure may include: a first row of discontinuous cuts that discontinuously divide the plurality of gate layers in the cell region between the first row channel structure and the second row channel structure in the first horizontal direction; and a continuous cut that continuously divides the plurality of gate layers in the cell region in the first horizontal direction. The second row channel structure and the third row channel structure may be located between the first row of discontinuous cuts and the continuous cuts.

[0007] Embodiments relate to a storage device including a substrate, a stack structure including a plurality of gate layers and a plurality of interlayer insulating layers alternately stacked in a vertical direction on the substrate, and a plurality of channel structures located in a cell region of the stack structure and extending in the vertical direction to penetrate the plurality of gate layers. The stack structure can include a plurality of cell region cutouts in a row, each of the cell region cutouts extending in a first horizontal direction and dividing the plurality of gate layers, the cell region cutouts can be spaced apart from each other and arranged in the first horizontal direction in the cell region, the stack structure can include a plurality of connection region cutouts in a row, each of the connection region cutouts extending in the first horizontal direction and dividing the plurality of gate layers, and the connection region cutouts can be spaced apart from each other and arranged in the first horizontal direction in a connection region of the stack structure. BRIEF DESCRIPTION OF DRAWINGS

[0008] Features will become apparent to those of ordinary skill in the art upon examination of the following details description of example embodiments in conjunction with the accompanying drawings, in which:

[0009] FIG. 1 is a circuit diagram illustrating a storage device according to an example embodiment;

[0010] FIG. 2 is a circuit diagram schematically illustrating one of memory blocks constituting a memory cell array included in a storage device according to an example embodiment;

[0011] FIG. 3 is a top view schematically illustrating a storage device according to an example embodiment;

[0012] FIG. 4A is a top view schematically illustrating FIG. 3 the first region A1 illustrated in FIG. 1A;

[0013] FIG. 4B is a cross-sectional view taken along FIG. 4A the line B4-B4' illustrated in FIG. 1B;

[0014] FIG. 4C is a cross-sectional view taken along FIG. 4A the line C4-C4' illustrated in FIG. 1C;

[0015] FIG. 4D is a cross-sectional view taken along FIG. 4A the line D4-D4' illustrated in FIG. 1D;

[0016] FIG. 5 is a cross-sectional view schematically illustrating FIG. 4B the cell region discontinuous cutout and a row of channel structures at the first height illustrated in FIG. 1E according to an example embodiment;

[0017] FIG. 6 is a cross-sectional view schematically showing a unit region discontinuous cut at a second height less than the first height shown in FIG. 6B according to an example embodiment. FIG. 4B

[0018] FIG. 7 is a cross-sectional view schematically showing a unit region discontinuous cut at a second height less than the first height shown in FIG. 6B according to an example embodiment. FIG. 4B

[0019] FIG. 8A is a plan view schematically showing the second region A2 shown in FIG. 6B. FIG. 3

[0020] FIG. 8B is a cross-sectional view taken along the line B8-B8' shown in FIG. 6B. FIG. 8A

[0021] FIG. 8C is a cross-sectional view taken along the line C8-C8' shown in FIG. 6B. FIG. 8A

[0022] FIG. 9 is a cross-sectional view schematically showing a connection region discontinuous cut at a first height shown in FIG. 7B according to an example embodiment. FIG. 8B

[0023] FIG. 10 is a cross-sectional view schematically showing a connection region discontinuous cut at a second height less than the first height shown in FIG. 7B according to an example embodiment. FIG. 8B

[0024] FIG. 11 is a cross-sectional view schematically showing a connection region discontinuous cut at a second height less than the first height shown in FIG. 7B according to an example embodiment. FIG. 8B

[0025] FIG. 12 is a cross-sectional view schematically showing a storage device according to an example embodiment.

[0026] FIG. 13 is a cross-sectional view schematically showing a storage device according to an example embodiment; and

[0027] FIG. 14A to FIG. 14K is a cross-sectional view showing a method of manufacturing a storage device according to an example embodiment. DETAILED DESCRIPTION

[0028] FIG. 1 is a circuit diagram showing a storage device 10 according to an example embodiment.

[0029] Referring to​​​​​​​​FIG. 1 The storage device 10 can include a memory cell array 11 and a peripheral circuit PC. The peripheral circuit PC can include a row decoder 12, an input / output (I / O) circuit 13, and a control logic 14.

[0030] The memory cell array 11 can include first to z-th memory blocks BLK1 to BLKz (z is an integer greater than or equal to 2). Each of the first to z-th memory blocks BLK1 to BLKz can include a plurality of memory cells capable of storing data. The plurality of memory cells included in the memory cell array 11 can be nonvolatile memory cells that retain data stored therein even at power-off. For example, the memory cell array 11 can include an electrically erasable programmable read-only memory (RAM) (EEPROM), a flash memory, a phase-change RAM (PRAM), a resistive RAM (RRAM), and a magnetic RAM (MRAM), or a ferroelectric RAM (FRAM). Hereinafter, an example embodiment will be described with respect to a case in which the plurality of memory cells include NAND flash memory cells.

[0031] The row decoder 12 can be connected to the memory cell array 11 via a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL. The row decoder 12 can select at least one of the first to z-th memory blocks BLK1 to BLKz of the memory cell array 11 in response to an address ADDR provided from a storage controller (not shown). The row decoder 12 can select at least one of the word lines WL, the string selection lines SSL, and the ground selection lines GSL of the memory block selected in response to the address ADDR provided from the storage controller (not shown).

[0032] The I / O circuit 13 can be connected to the memory cell array 11 via a plurality of bit lines BL. The I / O circuit 13 can select at least one of the plurality of bit lines BL. The I / O circuit 13 can store data DATA received from the storage controller in the memory cell array 11. In addition, the I / O circuit 13 can output data DATA read from the memory cell array 11 to the storage controller.

[0033] The control logic 14 can control overall operations of the storage device 10. The control logic 14 can control operations of the row decoder 12 and the I / O circuit 13. For example, the storage device 10 can be controlled to perform a memory operation corresponding to a command CMD provided from the storage controller. In addition, the control logic 14 can generate various internal control signals for the storage device 10 in response to a control signal CTRL provided from the storage controller.

[0034] FIG. 2 is a circuit diagram schematically illustrating a first memory block BLK1 constituting the storage device 10 (refer to FIG. 1) according to an example embodiment.FIG. 1 ) of FIG. 1. FIG. 1 ) of FIG. 1.

[0035] Referring to FIG. 2 , the first memory block BLK1 can include a plurality of NAND strings (NS11 to NS33). In FIG. 2 , one memory block (BLK1) is shown to include nine NAND strings (NS11 to NS33), but the number of NAND strings included in one memory block (BLK1) can vary. Each NAND string (NS11 to NS33) can include at least one string selection transistor SST, a plurality of memory cells (MC1 to MC8), and at least one ground selection transistor GST connected in series. In FIG. 2 , each NAND string (NS11 to NS33) is shown to include one string selection transistor SST, eight memory cells (MC1 to MC8), and one ground selection transistor GST, but the number of string selection transistors SST, memory cells, and ground selection transistors GST included in each NAND string (NS11 to NS33) can vary.

[0036] The NAND strings (NS11 to NS33) can be connected between bit lines (BL1 to BL3) and a common source line CSL. The gates of the string selection transistors SST can be connected to string selection lines (SSL1 to SSL3), the gates of the memory cells (MC1 to MC8) can be connected to word lines (WL1 to WL8), and the gates of the ground selection transistors GST can be connected to ground selection lines (GSL1 to GSL3). The common source line CSL can be commonly connected to the plurality of NAND strings (NS11 to NS33). Also, the word lines (WL1 to WL8) can be commonly connected to the plurality of NAND strings (NS11 to NS33).

[0037] FIG. 3 is a plan view schematically showing the memory device 100 according to an example embodiment.

[0038] Referring to FIG. 3The memory device 100 can include a substrate 110, a memory cell array 11 arranged side by side on the substrate 110, and a peripheral circuit PC. The memory cell array 11 can include a stack structure SS on the substrate 110. The stack structure SS can include a cell region CELL and a connection region EXT. The connection region EXT can be located on one side of the cell region CELL. The connection region EXT can be arranged along with the cell region CELL in a first horizontal direction (X direction). In an example embodiment, the stack structure SS can have another connection region EXT. For example, two connection regions EXT can be located on opposite sides of the cell region CELL, respectively. The two connection regions EXT and the cell region CELL can be arranged along the first horizontal direction (X direction). The two connection regions EXT can be spaced apart from each other in the first horizontal direction (X direction), and the cell region CELL can be located between the two connection regions EXT. In an example embodiment, the stack structure SS can include four connection regions EXT located on four sides of the cell region CELL, respectively.

[0039] FIG. 4A is a plan view schematically showing FIG. 3 a first region A1 shown in FIG. 1A. FIG. 4B is a cross-sectional view taken along FIG. 4A line B4-B4' shown in FIG. 1B. FIG. 4C is a cross-sectional view taken along FIG. 4A line C4-C4' shown in FIG. 1C. FIG. 4D is a cross-sectional view taken along FIG. 4A line D4-D4' shown in FIG. 1D. FIG. 8A is a plan view schematically showing FIG. 3 a second region A2 shown in FIG. 2A. FIG. 8B is a cross-sectional view taken along FIG. 8A line B8-B8' shown in FIG. 2B. FIG. 8C is a cross-sectional view taken along FIG. 8A line C8-C8' shown in FIG. 2C.

[0040] Referring to FIG. 4A to FIG. 4D and FIG. 8A to FIG. 8C , the memory device 100 can include a substrate 110, a stack structure SS on the substrate 110, a plurality of channel structures CH penetrating a cell region CELL of the stack structure SS, and a plurality of dummy channel structures DCH penetrating a connection region EXT of the stack structure SS.

[0041] The substrate 110 can include a semiconductor material such as a Group IV semiconductor material, a Group III-V semiconductor material, a Group II-VI semiconductor material, or a combination thereof. The Group IV semiconductor material can include, for example, silicon (Si), germanium (Ge), Si-Ge, or a combination thereof. The Group III-V semiconductor material can include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), indium gallium arsenide (InGaAs), or a combination thereof. The Group II-VI semiconductor material can include, for example, zinc telluride (ZnTe), cadmium sulfide (CdS), or a combination thereof.

[0042] The stack structure SS can include a plurality of gate layers (150a to 150c) and a plurality of interlayer insulating layers 140 alternately stacked on the substrate 110. Two adjacent gate layers among the plurality of gate layers (150a to 150c) can be spaced apart from each other by one interlayer insulating layer 140. The plurality of gate layers (150a to 150c) can include at least one bottom gate layer 150a, a plurality of middle gate layers 150b located on the at least one bottom gate layer 150a, and at least one top gate layer 150c located on the plurality of middle gate layers 150b. Each gate layer (150a to 150c) can include a conductive material such as tungsten (W), copper (Cu), silver (Ag), gold (Au), aluminum (Al), or a combination thereof. Each interlayer insulating layer 140 can include an insulating material such as silicon oxide, silicon nitride, or a combination thereof.

[0043] As shown in FIG. 1A, a unit region CELL of the stack structure SS can be flat, while a connection region EXT of the stack structure SS can have a stepped shape. FIG. 4B and FIG. 4C As shown in FIG. 1A, a unit region CELL of the stack structure SS can be flat, while a connection region EXT of the stack structure SS can have a stepped shape. FIG. 8C Accordingly, a length of a gate layer in the plurality of gate layers (150a to 150c) located at a lower height in the second horizontal direction (Y direction) can be greater than a length of a gate layer in the plurality of gate layers (150a to 150c) located at a higher height in the second horizontal direction (Y direction). Similarly, a length of an interlayer insulating layer 140 located at a lower height in the second horizontal direction (Y direction) can be greater than a length of an interlayer insulating layer 140 located at a higher height in the second horizontal direction (Y direction).

[0044] The channel structure CH can extend in a direction substantially parallel to the vertical direction (Z-direction) and can penetrate the cell region CELL of the stacked structure SS. The dummy channel structure DCH can extend in a direction substantially parallel to the vertical direction (Z-direction) and can penetrate the connection region EXT of the stacked structure SS. For example, the direction of extension of the channel structure CH and / or the dummy channel structure DCH may not be exactly parallel to the vertical direction (Z-direction) due to internal stress or deformation of the material (e.g., expansion, contraction, or torsion) generated during the process. The description that the direction of extension of the channel structure CH and / or the dummy channel structure DCH is substantially parallel to the vertical direction (Z-direction) can mean that the angle between the direction of extension of the channel structure CH and / or the dummy channel structure DCH and the vertical direction (Z-direction) is about 0° to about 10°, for example, about 0° to about 5°, or about 0° to about 2°.

[0045] Multiple channel structures (CH) can be arranged two-dimensionally in the cell region (CELL) of the stacked structure (SS), and multiple dummy channel structures (DCH) can be arranged two-dimensionally in the connection region (EXT) of the stacked structure (SS). Multiple channel structures (CH) arranged along a first horizontal direction (X direction) can be referred to as a row of channel structures (CH). For example, the storage device 100 may include first to third row channel structures (CH1 to CH3). The first to third row channel structures (CH1 to CH3) may be spaced apart from each other in a second horizontal direction (Y direction).

[0046] Each channel structure CH and each dummy channel structure DCH may include a channel pattern 162, a buried insulating pattern 161, a pad pattern 164, and a gate insulating pattern 163. The channel pattern 162 may penetrate multiple gate layers (150a to 150c) and multiple interlayer insulating layers 140. The channel pattern 162 may contain a semiconductor material. In an example embodiment, the channel pattern 162 may have a cup shape (or a cylinder with a closed bottom and a hollow space). Therefore, the channel pattern 162 may extend along the side and bottom surfaces of the channel structure CH. The hollow space defined by the channel pattern 162 may be filled by the buried insulating pattern 161. The buried insulating pattern 161 may contain an insulating material. FIG. 4B and FIG. 4C As shown, in some embodiments, the channel pattern 162 may be cylindrical or columnar, and the buried insulating pattern 161 may be omitted. The pad pattern 164 may be located on the top surface of the channel structure CH. The pad pattern 164 may contain semiconductor material.

[0047] Gate insulating pattern 163 may be located between channel pattern 162 and stacked structure SS. Gate insulating pattern 163 may extend along the side and bottom surfaces of channel structure CH. In the example embodiment, with FIG. 4B , FIG. 4Cand FIG. 8B As shown, at least a portion of the gate insulating pattern 163 may not be included in the channel structure CH or the dummy channel structure DCH, and may also be located between the interlayer insulating layer 140 and the plurality of gate layers (150a to 150c). The gate insulating pattern 163 may include a barrier insulating layer, a tunnel insulating layer, and a charge storage layer located between the barrier insulating layer and the tunnel insulating layer. The barrier insulating layer may comprise an insulating material such as silicon oxide, hafnium oxide, lanthanum oxide, zirconium oxide, tantalum oxide, or combinations thereof. The charge storage layer may comprise an insulating material such as silicon oxide, silicon nitride, or combinations thereof. The charge storage layer may be trapping type. For example, the charge storage layer may also comprise quantum dots or nanocrystals. Here, quantum dots or nanocrystals may comprise fine particles having a conductive material. The tunnel insulating layer may comprise an insulating material such as silicon oxide, hafnium oxide, lanthanum oxide, zirconium oxide, tantalum oxide, or combinations thereof. In an example embodiment, the barrier insulating layer and the tunnel insulating layer may comprise oxides, and the charge storage layer may comprise nitrides.

[0048] The stacked structure SS can include multiple cutouts, such as cutouts HWC, FW, HS, FS, HGC, HWE, DWE, and HGE. The cutouts (HWC, FW, HS, FS, HGC, HWE, DWE, and HGE) of the stacked structure SS can be openings or recesses formed in the stacked structure SS.

[0049] The stacked structure SS may include discontinuous cell region cutouts (HWC). For example, the stacked structure SS may include a first row of HWC1 and a second row of HWC2 with discontinuous cell region cutouts (HWC). Both the first row of HWC1 and the second row of HWC2 may include multiple discontinuous cell region cutouts (HWC).

[0050] The discontinuous cut in the unit region (HWC) can also be called a discontinuous cut, unit region cut, or cut.

[0051] Each row (HWC1 and HWC2) of the discontinuous cell region cutouts HWC can be spaced apart from each other and can be arranged to extend along a first horizontal direction (X direction) within the cell region of the stacked structure SS. The discontinuous cell region cutouts HWC of the stacked structure SS can extend along the first horizontal direction (X direction) and can divide multiple gate layers (150a to 150c) of the stacked structure SS. Therefore, each row (HWC1 and HWC2) of the discontinuous cell region cutouts HWC can discontinuously divide multiple gate layers (150a to 150c) within the cell region of the stacked structure SS along the first horizontal direction (X direction).

[0052] In example embodiments, such as FIG. 4DAs shown, the bottom surface of at least one discontinuous cut in a unit region HWC can convex upwards, such that the depth D1 of the end of the at least one discontinuous cut in a unit region HWC (in the vertical direction (Z direction)) is greater than the depth D2 of the center of the at least one discontinuous cut in a unit region HWC (in the vertical direction (Z direction)). In another example embodiment, with FIG. 4D As shown, at least one unit region discontinuous cut HWC bottom surface may be convex downwards or may be flat.

[0053] In example embodiments, such as FIG. 5 As shown, the discontinuous cut in the unit region HWC can have end PaC and middle PbC. For example... FIG. 5 As shown, when the maximum width Wa1 of the end PaC of the discontinuous cut HWC in the first height H1 in the second horizontal direction (Y direction) becomes greater than the maximum width Wb1 of the middle PbC of the discontinuous cut HWC in the second horizontal direction (Y direction), the bottom surface of at least one discontinuous cut HWC may tend to convex upward.

[0054] For example, such as FIG. 5 As shown, at the first height H1 in the Z direction (refer to...) FIG. 4B The maximum width Wa1 of the end PaC (in the second horizontal direction (Y direction)) can be greater than the maximum width Wb1 of the middle PbC (in the second horizontal direction (Y direction)).

[0055] Refer again FIG. 4A The first row HWC1 and the second row HWC2 of the discontinuous cut in the cell region HWC can be spaced apart from each other in the second horizontal direction (Y direction). The first row HWC1 of the discontinuous cut in the cell region HWC can be located between the first row CH1 and the second row CH2 of the channel structure CH. The second row HWC2 of the discontinuous cut in the cell region HWC can be located between the second row CH2 and the third row CH3 of the channel structure CH.

[0056] A gap G1 may exist between two adjacent discontinuous cutouts HWC in the first row HWC1. A gap G2 may exist between two adjacent discontinuous cutouts HWC in the second row HWC2. In an example embodiment, the gap G1 in the first row HWC1 and the gap G2 in the second row HWC2 may not be aligned along the same line in the second horizontal direction (Y direction). That is, gaps G1 and G2 may be offset in the X direction. This arrangement can facilitate the operation of removing multiple sacrificial layers (180a to 180c) and then filling multiple gate layers (150a to 150c), such as... FIG. 14I to FIG. 14KAs described in [the document]. Additionally, this arrangement can mitigate the tilting of the stacked structure SS due to internal stresses and tensions in the material that may occur during manufacturing operations (e.g., deformation, expansion, and contraction).

[0057] In the example embodiment, the discontinuous cutout HWC in the cell region can be filled with insulating material IM. In the example embodiment, as... FIG. 4C As shown, at least one discontinuous cutout HWC in a unit region can include voids VD in the insulating material IM. Furthermore, in relation to the above reference... FIG. 5 In a structure similar to the one described in detail, when the maximum width Wa1 of the end PaC of the discontinuous cut HWC in the first height H1 in the second horizontal direction (Y direction) becomes greater than the maximum width Wb1 of the middle PbC of the discontinuous cut HWC in the second horizontal direction (Y direction), the void VD may tend to be formed at the end PaC of the discontinuous cut HWC in the first height H1.

[0058] In another example embodiment, the cell region discontinuity cutout HWC may be filled with a common source line (not shown) and an insulating spacer (not shown), the common source line extending in the vertical direction (Z direction) of the cell region discontinuity cutout HWC, and the insulating spacer located on the side surface of the cell region discontinuity cutout HWC and surrounding the common source line.

[0059] According to an example embodiment, the undivided portion between two adjacent discontinuous cutouts HWC in each row (HWC1 and HWC2) of the cell region CELL of the stacked structure SS can mitigate the tilting of the stacked structure SS caused by internal stresses and deformations (e.g., expansion, contraction, or torsion) of the material that may occur during manufacturing. Therefore, even when the memory device 100 including the stacked structure SS is manufactured with more gate layers (150a to 150c) and interlayer insulating layers 140, the processing difficulties that may arise due to the tilting of the stacked structure can be mitigated. Thus, a memory device 100 with higher integration can be provided.

[0060] In an example embodiment, a continuous notch FW can extend along a first horizontal direction (X direction) above the cell region CELL and the connection region EXT of the stacked structure SS, and can divide multiple gate layers (150a to 150b) of the stacked structure SS. Therefore, the continuous notch FW can continuously divide multiple gate layers (150a to 150b) along the first horizontal direction (X direction) in the cell region CELL and the connection region EXT of the stacked structure SS. The continuous notch FW can be filled with an insulating material.

[0061] The second row CH2 and the third row CH3 of the channel structure CH can be located between the continuous cut FW and the first row HWC1 of the discontinuous cut HWC in the cell region. The third row CH3 of the channel structure CH can be located between the continuous cut FW and the second row HWC2 of the discontinuous cut HWC in the cell region. The second row CH2 of the channel structure CH can be located between the first row HWC1 and the second row HWC2 of the discontinuous cut HWC in the cell region.

[0062] In example embodiments, such as FIG. 4B As shown, due to internal stresses and tensions (e.g., deformation, expansion, or contraction) that may occur during manufacturing, the maximum width Wb1 of the middle portion of the discontinuous cut HWC in the unit region at the first height H1 (in the second horizontal direction (Y direction)) can be smaller than the maximum width W5 of the continuous cut FW at the first height H1 (in the second horizontal direction (Y direction)). The maximum width Wb1 of the middle portion of the discontinuous cut HWC in the unit region (in the second horizontal direction (Y direction)) can decrease with increasing height, while the maximum width W5 of the continuous cut FW (in the second horizontal direction (Y direction)) can increase with increasing height.

[0063] A discontinuous top cut HS can also be referred to as a top cut. A discontinuous top cut HS can be filled with insulating material.

[0064] Discontinuous top cutouts HS can be arranged in a first row HS1 and a second row HS2. The first row HS1 and the second row HS2 of the discontinuous top cutouts HS can be spaced apart from each other in a second horizontal direction (Y direction). The rows (HS1 and HS2) of the discontinuous top cutouts HS can be arranged to extend along a first horizontal direction (X direction) in the cell region CELL of the stacked structure SS. The discontinuous top cutouts HS can extend in the first horizontal direction (X direction) to divide at least one top gate layer 150c, but may not divide the plurality of intermediate gate layers 150b and at least one bottom gate layer 150a. Therefore, each row (HS1 and HS2) of the discontinuous top cutouts HS can only discontinuously divide (one or more) of the top gate layers 150c in the cell region CELL of the stacked structure SS along the first horizontal direction (X direction).

[0065] A discontinuous top cut HS in the first row HS1 of a discontinuous top cut HS can be located between two adjacent discontinuous top cuts HWC in the first row HWC1 of a discontinuous top cut HWC in a cell region. A discontinuous top cut HS in the second row HS2 of a discontinuous top cut HS can extend between two adjacent discontinuous top cuts HWC in the second row HWC2 of a discontinuous top cut HWC in a cell region.

[0066] In the example embodiment, the discontinuous top cut HS in the first row HS1 of the discontinuous top cut HS and the discontinuous top cut HS in the second row HS2 of the discontinuous top cut HS may not be aligned along the same line in the second horizontal direction (Y direction).

[0067] Each consecutive top cut (FS1 to FS3) may extend in the first horizontal direction (X direction) to divide at least one top gate layer 150c, but may not divide the plurality of intermediate gate layers 150b and at least one bottom gate layer 150a. Therefore, each consecutive top cut (FS1 to FS3) may divide only one or more top gate layers 150c consecutively in the cell region CELL of the stacked structure SS along the first horizontal direction (X direction).

[0068] The continuous top cuts (FS1 to FS3) can be spaced apart from each other in the second horizontal direction (Y direction). The second continuous top cut FS2 can be located between the first row HWC1 and the second row HWC2 of the discontinuous cut HWC in the cell region, and the third continuous top cut FS3 can be located between the second row HWC2 of the discontinuous cut HWC in the cell region and the continuous cut FW. The first row HWC1 of the discontinuous cut HWC in the cell region can be located between the first continuous top cut FS1 and the second continuous top cut FS2, and the second row HWC2 of the discontinuous cut HWC in the cell region can be located between the second continuous top cut FS2 and the third continuous top cut FS3. The continuous top cuts (FS1 to FS3) can be filled with insulating material.

[0069] The discontinuous bottom cutout (HGC) of the cell region can also be referred to as a cell region bottom cutout or bottom cutout. Each row (HGC1 and HGC2) of the discontinuous bottom cutout HGC can be spaced apart from each other and can be arranged in the cell region CELL of the stacked structure SS to extend along a first horizontal direction (X direction). The discontinuous bottom cutout HGC can extend in the first horizontal direction (X direction) to divide at least one bottom gate layer 150a, but can leave multiple intermediate gate layers 150b and at least one top gate layer 150c undivided. Therefore, each row (HGC1 and HGC2) of the discontinuous bottom cutout HGC in the cell region CELL of the stacked structure SS can only discontinuously divide (one or more) the bottom gate layer 150a.

[0070] The discontinuous bottom cut HGC in the first row HGC1 of the cell region discontinuous cut HGC can be located between two adjacent discontinuous bottom cut HWCs in the first row HWC1 of the cell region discontinuous cut HWC, and the discontinuous bottom cut HGC in the second row HGC2 of the cell region discontinuous cut HGC can extend between two adjacent discontinuous bottom cut HWCs in the second row HWC2 of the cell region discontinuous cut HWC.

[0071] The first row HGC1 and the second row HGC2 of the discontinuous bottom cutout HGC in the unit region can be spaced apart from each other in the second horizontal direction (Y direction). In an example embodiment, the discontinuous bottom cutout HGC in the first row HGC1 and the discontinuous bottom cutout HGC in the second row HGC2 of the unit region can not be aligned along the same line in the second horizontal direction (Y direction). The discontinuous bottom cutout HGC can be filled with insulating material. In an example embodiment, the discontinuous bottom cutout HGC can overlap with the discontinuous top cutout HS in the vertical direction (Z direction).

[0072] The discontinuous joint feature (HWE) can also be called the joint feature cut.

[0073] For example, such as FIG. 8A As shown, each row (HWE1 and HWE2) of the discontinuous cutouts HWE in the connection region can be spaced apart from each other and can be arranged in the connection region EXT of the stacked structure SS to extend along a first horizontal direction (X direction). The discontinuous cutouts HWE in the connection region can extend along the first horizontal direction (X direction) to divide multiple gate layers (150a to 150c) of the stacked structure SS. Therefore, each row (HWE1 and HWE2) of the discontinuous cutouts HWE in the connection region can be a discontinuous division of multiple gate layers (150a to 150c) in the connection region EXT of the stacked structure SS along the first horizontal direction (X direction).

[0074] In an example embodiment, the gap G3 between two adjacent discontinuous cuts HWE in the first row HWE1 of the connecting region discontinuous cuts HWE and the gap G4 between two adjacent discontinuous cuts HWE in the second row HWE2 of the connecting region discontinuous cuts HWE can be aligned along the same line in the second horizontal direction (Y direction). However, in other embodiments, with FIG. 8AAs shown, the gap G3 between two adjacent discontinuous cuts HWE in the first row HWE1 of the discontinuous cut HWE and the gap G4 between two adjacent discontinuous cuts HWE in the second row HWE2 of the discontinuous cut HWE can not be aligned in the second horizontal direction (Y direction).

[0075] The first row HWE1 and the second row HWE2 of the discontinuous cut in the connecting region HWE can be spaced apart from each other in the second horizontal direction (Y direction). In the example embodiment, the first row HWE1 of the discontinuous cut in the connecting region HWE and the first row HWC1 of the discontinuous cut in the unit region HWC can be aligned in the first horizontal direction (X direction), and the second row HWE2 of the discontinuous cut in the connecting region HWE and the first row HWC1 of the discontinuous cut in the unit region HWC can be aligned in the first horizontal direction (X direction).

[0076] In an example embodiment, the discontinuous cutout HWE in the connection region may be filled with an insulating material. In one example embodiment, at least one discontinuous cutout HWE in the connection region may include voids (not shown) within the insulating material.

[0077] In example embodiments, such as FIG. 9 As shown, when the maximum width Wa3 of the end PaE (in the second horizontal direction (Y direction)) of the discontinuous cut HWE in the connecting region at the first height H1 becomes greater than the maximum width Wb3 of the middle PbE (in the second horizontal direction (Y direction)) of the discontinuous cut HWE in the connecting region at the first height H1, a gap (not shown) may tend to be formed at the end of the discontinuous cut HWE in the connecting region.

[0078] In another example embodiment, the cell region discontinuity cutout HWE may be filled with a common source line (not shown) and an insulating spacer (not shown), the common source line extending in the vertical direction (Z direction) in the connection region discontinuity cutout HWE, and the insulating spacer located on the side surface of the connection region discontinuity cutout HWE and surrounding the common source line (not shown).

[0079] Refer again FIG. 8AThe undivided portion between two adjacent discontinuous cuts HWE in each row (HWE1 and HWE2) of the connection region EXT of the stacked structure SS can mitigate the tilting of the stacked structure SS caused by internal stresses and tensions (e.g., expansion, contraction, or torsion) of the material that may occur during the manufacturing process. Therefore, even when the memory device 100 including the stacked structure SS is manufactured with more stacked gate layers (150a to 150c) and interlayer insulating layers 140, the processing difficulties that may arise due to the tilting of the stacked structure SS can be mitigated. Thus, a memory device 100 with higher integration can be provided.

[0080] Each row (DWE1 to DWE3) of the dummy discontinuous cuts DWE can be spaced apart from each other and can be arranged in the connection region EXT of the stacked structure SS to extend along a first horizontal direction (X direction). The dummy discontinuous cuts DWE can extend in the first horizontal direction (X direction) to divide multiple gate layers (150a to 150c) of the stacked structure SS. Therefore, each row (DWE1 and DWE2) of the dummy discontinuous cuts DWE can discontinuously divide multiple gate layers (150a to 150c) in the connection region EXT of the stacked structure SS along the first horizontal direction (X direction).

[0081] The second row of the dummy discontinuous cut DWE, DWE2, can be located between the first row HWE1 and the second row HWE2 of the connected region discontinuous cut HWE. The third row of the dummy discontinuous cut DWE, DWE3, can be located between the second row HWE2 of the connected region discontinuous cut HWE and the continuous cut FW. The first row HWE1 of the connected region discontinuous cut HWE can be located between the first row DWE1 and the second row DWE2 of the dummy discontinuous cut DWE, and the second row HWE2 of the connected region discontinuous cut HWE can be located between the second row DWE2 and the third row DWE3 of the dummy discontinuous cut DWE.

[0082] The first row DWE1 to the third row DWE3 of the dummy discontinuous cut DWE can be spaced apart from each other in the second horizontal direction (Y direction). In the example embodiment, the first row DWE1 of the dummy discontinuous cut DWE can be aligned with the first continuous top cut FS1 in the first horizontal direction X, the second row DWE2 of the dummy discontinuous cut DWE can be aligned with the second continuous top cut FS2 in the first horizontal direction X, and the third row DWE3 of the dummy discontinuous cut DWE can be aligned with the third continuous top cut FS3 in the first horizontal direction X.

[0083] In an example embodiment, the dummy discontinuous cut (DWE) may be filled with an insulating material. In an example embodiment, at least one dummy discontinuous cut (DWE) may include a void (not shown) in the insulating material. Specifically, voids (not shown) may tend to be formed at the ends of the dummy discontinuous cut (DWE) when the maximum width of the end of the dummy discontinuous cut (DWE) in the second horizontal direction (Y direction) becomes greater than the maximum width of the middle portion of the dummy discontinuous cut (DWE) in the second horizontal direction (Y direction).

[0084] The discontinuous bottom cutout (HGE) of the connection region can also be referred to as the bottom cutout of the connection region. In the example embodiment, the discontinuous bottom cutout (HGE) of the connection region may be filled with an insulating material.

[0085] Each row (HGE1 and HGE2) of the discontinuous bottom cutouts HGE in the connection region can be spaced apart from each other and can be arranged in the connection region EXT of the stacked structure SS to extend along a first horizontal direction (X direction). The discontinuous bottom cutouts HGE in the connection region can extend in the first horizontal direction (X direction) to divide at least one bottom gate layer 150a, but can leave the multiple intermediate gate layers 150b and at least one top gate layer 150c undivided. Therefore, each row (HGE1 and HGE2) of the discontinuous bottom cutouts HGE in the connection region EXT of the stacked structure SS can only discontinuously divide (one or more) the bottom gate layers 150a in the first horizontal direction (X direction).

[0086] The bottom cut of the connecting region discontinuity HGE in the first row HGE1 can be located between two adjacent bottom cuts of the connecting region discontinuity HWE in the first row HWE1 of the connecting region discontinuity HWE, and the bottom cut of the connecting region discontinuity HGE in the second row HGE2 can extend between two adjacent bottom cuts of the connecting region discontinuity HWE in the second row HWE2 of the connecting region discontinuity HWE.

[0087] The first row HGE1 and the second row HGE2 of the discontinuous bottom cutout HGE can be spaced apart from each other in the second horizontal direction (Y direction). In the example embodiment, the discontinuous bottom cutout HGC in the first row HGC1 of the discontinuous bottom cutout HGC and the discontinuous bottom cutout HGC in the second row HGC2 of the discontinuous bottom cutout HGC can be aligned in the second horizontal direction (Y direction).

[0088] In another example embodiment, with FIG. 8AAs shown, the discontinuous bottom cut HGC in the first row HGC1 of the discontinuous bottom cut HGC can be disaligned with the discontinuous bottom cut HGC in the second row HGC2 of the discontinuous bottom cut HGC in the second horizontal direction (Y direction).

[0089] For example, such as FIG. 4B As shown, in the example embodiment, the memory device 100 may further include a first semiconductor layer 132, an etch stop layer 133, and a plurality of support patterns SP located between the substrate 110 and the stacked structure SS. The gate insulating pattern 163 of each of the channel structure CH and the dummy channel structure DCH may expose the bottom of the channel pattern 162, and the first semiconductor layer 132 may contact the exposed portion of the channel pattern 162 of each of the channel structure CH and the dummy channel structure DCH. The etch stop layer 133 may be located between the first semiconductor layer 132 and the stacked structure SS. The etch stop layer 133 may contain a semiconductor material. When removed by removing, such as FIG. 14G and FIG. 14H When the sacrificial layer 181 forms a first gap 181G between the substrate 110 and the first interlayer insulating layer 140a, the etch stop layer 133 can prevent the etching of the first interlayer insulating layer 140a.

[0090] In a top view, multiple support patterns SP can be surrounded by a first semiconductor layer 132. The support patterns SP may contain semiconductor material. The multiple support patterns SP can be arranged two-dimensionally on the substrate 110. In an example embodiment, the etch stop layer 133 and the multiple support patterns SP can be integrally formed. Therefore, the etch stop layer 133 and the multiple support patterns SP can be formed simultaneously using the same material.

[0091] For example, such as FIG. 4B As shown, in the example embodiment, the support pattern SP may overlap with the cell region discontinuity cutout HWC in the vertical direction (Z direction). This prevents the cell region discontinuity cutout HWC from being formed to penetrate the sacrificial layer 181 (e.g., see reference 181). FIG. 14G The operation shown can remove the sacrificial layer 181 (for example, refer to...). FIG. 14G and FIG. 14H (The operation shown).

[0092] In an example embodiment, the support pattern SP can be located between two adjacent discontinuous cut HWCs in each row (HWC1 and HWC2) of the discontinuous cut HWCs, and at least one of the multiple support patterns SP can overlap with two adjacent discontinuous cut HWCs in each row (HWC1 and HWC2) of the discontinuous cut HWCs in the vertical direction (Z direction). As an example embodiment, at least one of the multiple support patterns SP overlaps with two adjacent ends in each row (HWC1 and HWC2) of the discontinuous cut HWCs in the vertical direction. Therefore, when the bottom surface of at least one discontinuous cut HWC is formed to be convex upward (specifically, as an example embodiment, the bottom surface of at least one of the two adjacent ends is formed to be convex upward), it can prevent the discontinuous cut HWC from being formed to penetrate the sacrificial layer 181 (e.g., refer to...). FIG. 14G The operation shown can remove the sacrificial layer 181 (for example, refer to...). FIG. 14G and FIG. 14H (The operation shown).

[0093] The storage device 100 may further include an interlayer insulating layer 140 located on the stacked structure SS. The storage device 100 may also include a plurality of contact plugs CP extending in a vertical direction (Z direction) on the connection region EXT of the stacked structure SS. The plurality of contact plugs CP may be electrically connected to a plurality of gate layers (150a to 150c), respectively. The contact plugs CP may contain a conductive material.

[0094] FIG. 5 According to the example embodiment FIG. 4B The diagram shows a schematic cross-sectional view of the discontinuous cutout HWC in the unit region and the row CH1 of the channel structure CH at the first height H1.

[0095] Reference FIG. 5 The discontinuous cut in the cell region HWC may include end PaCs and a middle PbC arranged in the first horizontal direction (X direction). The discontinuous cut in the cell region HWC may include two end PaCs spaced apart from each other in the first horizontal direction (X direction) and a middle PbC located between the two end PaCs.

[0096] In the example embodiment, at the first height H1, the discontinuous cutout HWC of the unit region can have a dumbbell-shaped cross-section. Therefore, regardless of its position in the X direction, the width of the middle PbC of the discontinuous cutout HWC at the first height H1 in the second horizontal direction (Y direction) can be substantially constant. However, the width of the end PaC of the discontinuous cutout HWC at the first height H1 in the second horizontal direction (Y direction) can increase and then decrease as its position in the X direction moves away from the middle PbC. The maximum width Wa1 of the end PaC of the discontinuous cutout HWC at the first height H1 in the second horizontal direction (Y direction) can be greater than the maximum width Wb1 of the middle PbC of the discontinuous cutout HWC at the first height H1 in the second horizontal direction (Y direction). Therefore, at the first height H1, the distance Da1 from the end PaC of the discontinuous cell region cutout HWC along the second horizontal direction (Y direction) to the row CH1 of the channel structure CH can be smaller than the distance Db1 from the middle PbC of the discontinuous cell region cutout HWC along the second horizontal direction (Y direction) to the row CH1 of the channel structure CH. By forming a maximum width Wa1 at the end PaC of the discontinuous cell region cutout HWC in the second horizontal direction (Y direction) that is larger than the maximum width Wb1 of the middle PbC of the discontinuous cell region cutout HWC, the operations of forming the discontinuous cell region cutout HWC and forming the gate layer (150a to 150c) can be easily performed.

[0097] FIG. 6 According to the example embodiment FIG. 4B The diagram shows a schematic cross-sectional view of a discontinuous cutout HWC in a cell region located at a second height H2 (e.g., closer to the substrate 110) that is lower than the first height H1.

[0098] Reference FIG. 6 At the second height H2, the discontinuous cut in the element region HWC can have a dumbbell-shaped cross-section. Therefore, regardless of its position in the X direction, the width of the central PbC in the second horizontal direction (Y direction) of the discontinuous cut in the element region HWC at the second height H2 can remain essentially constant. However, the width of the end PaC in the second horizontal direction (Y direction) of the discontinuous cut in the element region HWC at the second height H2 can increase and then decrease as its position in the X direction moves away from the central PbC. The maximum width Wa2 of the end PaC in the second horizontal direction (Y direction) of the discontinuous cut in the element region HWC at the second height H2 can be greater than the maximum width Wb2 of the central PbC in the second horizontal direction (Y direction) of the discontinuous cut in the element region HWC at the second height H2.

[0099] Compare FIG. 5 and FIG. 6The maximum width Wa2 of the end PaC of the discontinuous cut HWC in the second horizontal direction (Y direction) at the second height H2 can be smaller than the maximum width Wa1 of the end PaC of the discontinuous cut HWC in the second horizontal direction (Y direction) at the first height H1. The maximum width Wb2 of the middle PbC of the discontinuous cut HWC in the second horizontal direction (Y direction) at the second height H2 can be equal to or smaller than the maximum width Wb1 of the middle PbC of the discontinuous cut HWC in the second horizontal direction (Y direction) at the first height H1.

[0100] FIG. 7 According to the example embodiment FIG. 4B The diagram shows a schematic cross-sectional view of the discontinuous cutout HWC in the unit region located at a second height H2, which is lower than the first height H1.

[0101] Reference FIG. 7 In the example embodiment, regardless of its position in the X direction, the width of the middle PbC of the discontinuous cut HWC in the cell region at the second height H2 in the second horizontal direction (Y direction) can remain substantially constant. However, the width of the end PaC of the discontinuous cut HWC in the second horizontal direction (Y direction) can decrease as its position in the X direction moves away from the middle PbC. The maximum width Wa2 of the end PaC of the discontinuous cut HWC in the second horizontal direction (Y direction) can be equal to or less than the maximum width Wb2 of the middle PbC of the discontinuous cut HWC in the second horizontal direction (Y direction).

[0102] FIG. 9 According to the example embodiment FIG. 8B The diagram shows a schematic cross-sectional view of the discontinuous cut HWE in the connection area located at the first height H1.

[0103] Reference FIG. 9 The discontinuous cut in the connecting region HWE may include an end PaE and a middle PbE arranged in the first horizontal direction (X direction). The discontinuous cut in the connecting region HWE may include two end PaEs spaced apart from each other in the first horizontal direction (X direction) and a middle PbE located between the two end PaEs.

[0104] In the example embodiment, the discontinuous cut HWE in the connecting region at the first height H1 can have a dumbbell-shaped cross-section. Therefore, regardless of its position in the X direction, the width of the middle portion PbE of the discontinuous cut HWE in the second horizontal direction (Y direction) can remain substantially constant. However, the width of the end portion PaE of the discontinuous cut HWE in the second horizontal direction (Y direction) can increase and then decrease as it moves further away from the middle portion PbE in the X direction. The maximum width Wa3 of the end portion PaE of the discontinuous cut HWE in the second horizontal direction (Y direction) can be greater than the maximum width Wb3 of the middle portion PbE of the discontinuous cut HWE in the second horizontal direction (Y direction).

[0105] Compare FIG. 5 and FIG. 9 In some embodiments, the maximum width Wa1 of the end PaC of the discontinuous cut HWC in the unit region at the first height H1 in the second horizontal direction (Y direction) may be smaller than the maximum width Wa3 of the end PaE of the discontinuous cut HWE in the connecting region at the first height H1 in the second horizontal direction (Y direction).

[0106] FIG. 10 According to the example embodiment FIG. 8B The schematic cross-sectional view of the discontinuous cutout HWE of the connection region located at a second height H2 (e.g., closer to the substrate 110) that is lower than the first height H1.

[0107] Reference FIG. 10 In the example embodiment, the discontinuous cut HWE in the connecting region at the second height H2 can have a dumbbell-shaped cross-section. Therefore, regardless of its position in the X direction, the width of the middle portion PbE of the discontinuous cut HWE in the second horizontal direction (Y direction) can remain substantially constant. However, the width of the end portion PaE of the discontinuous cut HWE in the second horizontal direction (Y direction) can increase and then decrease as it moves further away from the middle PbE in the X direction. In the example embodiment, the maximum width Wa4 of the end portion PaE of the discontinuous cut HWE in the second horizontal direction (Y direction) can be greater than the maximum width Wb4 of the middle portion PbE of the discontinuous cut HWE in the second horizontal direction (Y direction).

[0108] Compare FIG. 9 and FIG. 10The maximum width Wa4 of the end PaE of the discontinuous cut HWE in the second horizontal direction (Y direction) at the second height H2 can be less than the maximum width Wa3 of the end PaE of the discontinuous cut HWE in the second horizontal direction (Y direction) at the first height H1. The maximum width Wb4 of the middle PbE of the discontinuous cut HWE in the second horizontal direction (Y direction) at the second height H2 can be equal to or less than the maximum width Wb3 of the middle PbE of the discontinuous cut HWE in the second horizontal direction (Y direction) at the first height H1.

[0109] Compare FIG. 6 and FIG. 10 In some embodiments, the maximum width Wa2 of the end PaC of the discontinuous cut HWC in the unit region at the second height H2 in the second horizontal direction (Y direction) can be greater than the maximum width Wa4 of the end PaE of the discontinuous cut HWE in the connecting region at the second height H2 in the second horizontal direction (Y direction).

[0110] FIG. 11 According to the example embodiment FIG. 8B The schematic cross-sectional view of the discontinuous cutout HWE of the connection region located at a second height H2 (e.g., closer to the substrate 110) that is lower than the first height H1.

[0111] Reference FIG. 11 In the example embodiment, regardless of its position in the X direction, the width of the middle PbE of the discontinuous cut HWE at the second height H2 in the second horizontal direction (Y direction) can remain substantially constant. However, the width of the end PaE of the discontinuous cut HWE at the second height H2 in the second horizontal direction (Y direction) can decrease as its position in the X direction moves away from the middle PbE. The maximum width Wa4 of the end PaE of the discontinuous cut HWE at the second height H2 in the second horizontal direction (Y direction) can be equal to or less than the maximum width Wb4 of the middle PbE of the discontinuous cut HWE at the second height H2 in the second horizontal direction (Y direction).

[0112] FIG. 12 This is a schematic cross-sectional view of the storage device 100a according to an example embodiment.

[0113] Reference FIG. 12The storage device 100a may have a cell-on-peri (COP) structure. Therefore, the peripheral circuit PC may be located between the substrate 110 and the stacked structure SS. The storage device 100a may also include: an interlayer insulating layer 120 covering the top surface of the substrate 110 and the peripheral circuit PC, and a second semiconductor layer 131 located between the interlayer insulating layer 120 and the first semiconductor layer 132.

[0114] FIG. 13 This is a schematic cross-sectional view of the storage device 100b according to an example embodiment.

[0115] Reference FIG. 13 The storage device 100b may have multiple stacked structures. The storage device 100b may include a substrate 110, a first stacked structure SS1 located on the substrate 110, and a second stacked structure SS2 located on the first stacked structure SS1. Multiple first channel structures CH1 may penetrate the first stacked structure SS1, and multiple second channel structures CH2 may penetrate the multiple second stacked structures SS2 and overlap with the first channel structures CH1 in the vertical direction (Z direction).

[0116] The first stacked structure SS1 may include a discontinuous bottom cutout HGC2 that divides only at least one bottom gate layer 150a, and the second stacked structure SS2 may include a continuous top cutout (FS1 to FS3) and a discontinuous top cutout HS2 that divides only at least one top gate layer 150c. The discontinuous bottom cutout HWC1 and the continuous cutout FW can divide the gate layers (150a and 150b) of the first stacked structure SS1 and the gate layers (150b and 150c) of the second stacked structure SS2. A first interlayer insulating layer 170 may be located between the first stacked structure SS1 and the second stacked structure SS2, and a second interlayer insulating layer 171 may be located on the second stacked structure SS2.

[0117] FIG. 14A to FIG. 14K This is a cross-sectional view illustrating a method of manufacturing a storage device according to an example embodiment. FIG. 14A to FIG. 14K The line B4-B4' in the middle corresponds to FIG. 4A Line B4-B4' in the middle.

[0118] Reference FIG. 14A A sacrificial layer 181, a plurality of support patterns SP surrounded by the sacrificial layer 181, and an etch stop layer 133 located on the sacrificial layer 181 can be formed on the substrate 110. The sacrificial layer 181 may contain a material with high etch selectivity relative to the etch stop layer 133. The sacrificial layer 181 may contain, for example, silicon nitride. In an example embodiment, the plurality of support patterns SP and the etch stop layer 133 may be formed simultaneously and integrally.

[0119] ReferenceFIG. 14B A first interlayer insulating layer 140a and a first sacrificial layer 180a can be formed on the etch stop layer 133. For example, the first sacrificial layer 180a may contain a material with high etch selectivity relative to the first interlayer insulating layer 140a, such as silicon nitride. Next, discontinuous bottom cutouts (HGC1 and HGC2, see reference) can be formed to divide the cell regions of the first sacrificial layer 180a. FIG. 4A to FIG. 4C ) and discontinuous bottom cuts in the connecting area (HGE1 and HGE2, see reference) FIG. 8A and FIG. 8B Next, the discontinuous bottom cuts in the cell regions (HGC1 and HGC2, see reference) can be filled with insulating material. FIG. 4A to FIG. 4C ) and discontinuous bottom cuts in the connecting area (HGE1 and HGE2, see reference) FIG. 8A and FIG. 8B ).

[0120] Reference FIG. 14C Multiple interlayer insulating layers 140 and multiple sacrificial layers (180b and 180c) can be alternately formed on the first sacrificial layer 180a. The multiple interlayer insulating layers 140 and multiple sacrificial layers (180b and 180c) can be patterned as follows: FIG. 8C The stepped shape is shown. Then, an interlayer insulating layer 170 can be formed on the top sacrificial layer 180c.

[0121] Reference FIG. 14D Multiple vias CHO and multiple dummy vias (not shown) can be formed that penetrate multiple sacrificial layers (180a to 180c and 181), multiple interlayer insulating layers (140, 140a and 170) and etch stop layer 133.

[0122] Reference FIG. 14E Multiple channel structures CH can be formed in multiple channel holes CHO, and multiple dummy channel structures DCH can be formed in multiple dummy channel holes (not shown) (see reference). FIG. 8A and FIG. 8B For example, a gate insulating layer, a channel layer, and a buried insulating layer can be formed on multiple vias CHO and multiple dummy vias (not shown). Next, a gate insulating pattern 163, a channel pattern 162, and a buried insulating pattern 161 can be formed by planarizing the gate insulating layer, the channel layer, and the buried insulating layer to expose the interlayer insulating layer 170. Next, a recess can be formed by removing the top of the gate insulating pattern 163, the top of the channel pattern 162, and the top of the buried insulating pattern 161. A pad layer can be formed on the recess, and a pad pattern 164 can be formed by planarizing the pad layer.

[0123] Reference FIG. 14FIt is possible to form continuous top cuts (FS1 to FS3) and discontinuous top cuts (HS1 and HS2) that divide at least one top sacrificial layer 180c (see reference). FIG. 4A and FIG. 4B Furthermore, continuous top cuts (FS1 to FS3) and discontinuous top cuts (HS1 and HS2) can be filled with insulating material.

[0124] Reference FIG. 14G This can create discontinuous cuts in the unit region that divide multiple sacrificial layers (180a to 180c) (HWC1 and HWC2, see reference). FIG. 4A to FIG. 4C ), discontinuous cuts in the connecting area (HWE, see reference) FIG. 8A and FIG. 8B ), Dummy Discontinuous Cut (DWE, see FIG. 8B and FIG. 4A to FIG. 4C And continuous cut FW. In the example embodiment, the maximum width Wb1g of the middle part of the discontinuous cut HWC1 in the second horizontal direction (Y direction) of the cell region at the first height H1 can be formed to be substantially the same as the maximum width W5g of the continuous cut FW in the second horizontal direction (Y direction) of the second horizontal direction.

[0125] Although not in FIG. 8A As shown in the image, but refer to... FIG. 8B Discontinuous cuts in unit regions (HWC1 and HWC2, see reference) FIG. 8B ), discontinuous cuts in the connecting area (HWE, see reference) FIG. 4A to FIG. 4C and FIG. 8A ), Dummy Discontinuous Cut (DWE, see 8A and FIG. 8B ) and continuous cut FW can expose a portion of the sacrificial layer 181.

[0126] Next, discontinuous cuts can be made in the cell regions (HWC1 and HWC2, see reference). FIG. 8B Discontinuous incisions in the sidewalls and connecting areas of the ) (HWE, see reference) FIG. 14G and FIG. 4D The sidewalls of the ) and the dummy discontinuous cuts (DWE, see 8A and ) FIG. 14G A covering layer 190 is formed on the sidewalls of the unit region and the sidewalls of the continuous cut FW. The covering layer 190 may not cover the discontinuous cuts (HWC1 and HWC2, see reference 190). FIG. 14H The bottom and connecting area of ​​the discontinuous cut (HWE, see reference) FIG. 4A to FIG. 4C and FIG. 8A The bottom of the ) and the dummy discontinuous cut (DWE, see 8A and ) FIG. 8B The bottom of ) and the bottom of the continuous cut FW. Therefore, although not in FIG. 8B As shown in the image, but refer to... FIG. 8BThe capping layer 190 may expose a portion of the sacrificial layer 181. The capping layer 190 may contain a material with high etch selectivity relative to the sacrificial layer 181, such as a semiconductor material.

[0127] Reference FIG. 8B and FIG. 8B This can be achieved through discontinuous cuts in the unit region (HWC1 and HWC2, see reference). FIG. 14H ), discontinuous cuts in the connecting area (HWE, see reference) FIG. 14I and FIG. 14I ), Dummy Discontinuous Cut (DWE, see 8A and FIG. 14J The first gap 181G is formed between the substrate 110 and the etch stop layer 133 by removing the sacrificial layer 181 using wet or dry etching, along with a continuous notch FW. The channel structure CH and the dummy channel structure DCH (see reference) can be exposed through the first gap 181G. FIG. 14G A portion of the sidewall of the gate insulating pattern 163. Even when the first gap 181G is formed, the etch stop layer 133, the multiple interlayer insulating layers 140 and the multiple sacrificial layers (180a to 180c) can be supported by multiple channel structures CH, multiple dummy channel structures DCH and multiple support patterns SP, which can prevent the collapse of the multiple interlayer insulating layers 140 and the multiple sacrificial layers (180a to 180c).

[0128] Next, the channel structure CH and the dummy channel structure DCH exposed by the first gap 181G can be removed (see reference). FIG. 14G Part of the gate insulating pattern 163, therefore, the channel structure CH and the dummy channel structure DCH (refer to) FIG. 14J A portion of the channel pattern 162 may be exposed to the first gap 181G.

[0129] Reference FIG. 14K and FIG. 14G The first gap 181G can be filled with the first semiconductor layer 132.

[0130] Reference FIG. 14G and FIG. 4A to FIG. 4D Multiple second gaps 180G can be formed between multiple interlayer insulating layers 140 by removing the cover layer 190 and multiple sacrificial layers (180a to 180c). When removing the multiple sacrificial layers (180a to 180c), the sidewalls of the discontinuous cutout HWC1 and the continuous cutout FW in the cell region may become inclined due to the expansion of the multiple interlayer insulating layers 140. For example, the maximum width Wb1j of the middle portion of the discontinuous cutout HWC1 in the cell region at the first height H1 in the second horizontal direction (Y direction) may become greater than that in the second horizontal direction (Y direction). FIG. 8A to FIG. 8CThe operation shown has already formed the discontinuous cut HWC1 in the unit region at the time point where the discontinuous cut HWC1 is located, with a maximum width Wb1g in the second horizontal direction (Y direction). The maximum width W5j of the continuous cut FW at the first height H1 in the second horizontal direction (Y direction) can be smaller than that at the time point where the discontinuous cut HWC1 is located. ​ In the operation shown, the maximum width W5g of the continuous cut FW in the second horizontal direction (Y direction) has been formed at the time point. Therefore, the maximum width Wb1j of the middle part of the discontinuous cut HWC1 in the cell region at the first height H1 in the second horizontal direction (Y direction) can become greater than the maximum width W5j of the continuous cut FW in the second horizontal direction (Y direction) at the first height H1.

[0131] Reference ​ and ​ Multiple second gaps 180G can be filled by multiple gate layers (150a to 150c). When forming multiple gate layers (150a to 150c), the sidewalls of the discontinuous cell region cutout HWC1 and the continuous cutout FW may become inclined due to material shrinkage. For example, the maximum width Wb1k of the middle portion of the discontinuous cell region cutout HWC1 at the first height H1 in the second horizontal direction (Y direction) may become smaller than that at the second horizontal direction (Y direction). ​ The operation shown has already formed the maximum width Wb1g of the discontinuous cut HWC1 in the second horizontal direction (Y direction) at the middle of the unit region discontinuous cut HWC1. However, the maximum width W5k of the continuous cut FW at the first height H1 in the second horizontal direction (Y direction) can become greater than that at the time point. ​ In the operation shown, the maximum width W5g of the continuous cut FW in the second horizontal direction (Y direction) has been formed at the time point. Therefore, the maximum width Wb1k of the middle of the discontinuous cut HWC1 in the unit region at the first height H1 in the second horizontal direction (Y direction) can be smaller than the maximum width W5k of the continuous cut FW in the second horizontal direction (Y direction) at the first height H1.

[0132] Reference ​ and ​ The cell region discontinuity cut HWC, the connection region discontinuity cut HWE, the dummy discontinuity cut DWE, and the continuous cut FW can be filled with insulating material IM. Additionally, multiple contact plugs CP can be formed, each contacting multiple gate layers (150a to 150c). Thus, a memory device 100 can be manufactured.

[0133] By summarizing and reviewing, one method to improve the integration of semiconductor memory devices is to form three-dimensional (3D) semiconductor memory devices with memory cells stacked vertically. Increasing the number of memory cells stacked vertically to improve the integration of 3D semiconductor memory devices may present challenges to the manufacturing of these devices.

[0134] As described above, the embodiments relate to three-dimensional semiconductor memory devices.

[0135] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some cases, it will be apparent to those skilled in the art at the time of filing this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A storage device, comprising: Substrate; A stacked structure comprising a plurality of gate layers and a plurality of interlayer insulating layers alternately stacked on a substrate in a vertical direction, the stacked structure comprising rows of cutouts, each of the cutouts extending in a first horizontal direction and configured to divide the plurality of gate layers, the cutouts being separated from each other and arranged in a cell region of the stacked structure in the first horizontal direction; as well as A row of channel structures, the channel structures being arranged along the first horizontal direction in the cell region, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers. In a cross-sectional view at a first height relative to the substrate, the maximum width of the end of at least one of the row of cuts in a second horizontal direction perpendicular to the first horizontal direction is greater than the maximum width of the middle portion of the at least one cut in the second horizontal direction.

2. The storage device according to claim 1, wherein, In the cross-sectional view at the first height, the distance from the end along the second horizontal direction to the row of channel structures is less than the distance from the middle along the second horizontal direction to the row of channel structures.

3. The storage device according to claim 1, wherein, The maximum width of the end in the cross-sectional view at the second height is less than the maximum width of the end in the cross-sectional view at the first height, the second height being less than the first height relative to the substrate, and the maximum width being determined in the second horizontal direction.

4. The storage device according to claim 1, wherein, In a cross-sectional view at a second height relative to the substrate, which is less than the first height, the maximum width of the end is equal to or less than the maximum width of the middle portion, the maximum width being determined in the second horizontal direction.

5. The storage device according to claim 1, wherein, The plurality of gate layers includes at least one bottom gate layer, a plurality of intermediate gate layers located on the at least one bottom gate layer, and at least one top gate layer located on the plurality of intermediate gate layers. The stacked structure also includes rows of top cutouts spaced apart from each other and arranged along the first horizontal direction in the cell region. Each top cutout extends along the first horizontal direction between two adjacent cutouts in the row, while dividing the at least one top gate layer, but not the plurality of intermediate gate layers and the at least one bottom gate layer.

6. The storage device according to claim 1, wherein, The plurality of gate layers includes at least one bottom gate layer, a plurality of intermediate gate layers located on the at least one bottom gate layer, and at least one top gate layer located on the plurality of intermediate gate layers. The stacked structure further includes rows of bottom cutouts spaced apart from each other and arranged along the first horizontal direction in the cell region. Each bottom cutout extends along the first horizontal direction between two adjacent cutouts in the row, while dividing the at least one bottom gate layer, but not the plurality of intermediate gate layers and the at least one top gate layer.

7. The storage device of claim 1, further comprising a semiconductor layer located between the substrate and the stacked structure, and a plurality of support patterns all surrounded by the semiconductor layer, wherein at least one of the plurality of support patterns overlaps with at least one of the row of cutouts in the vertical direction.

8. The storage device according to claim 7, wherein, At least one of the plurality of support patterns overlaps with two adjacent ends of the row of cuts in the vertical direction.

9. The storage device according to claim 8, wherein, The bottom surface of at least one of the two adjacent ends convexes upward relative to the substrate.

10. A storage device, comprising: Substrate; A stacked structure comprising a plurality of gate layers and a plurality of interlayer insulating layers alternately stacked on the substrate in a vertical direction; as well as The channel structure is arranged in a first row, a second row, and a third row in the cell region of the stacked structure, the rows extending along a first horizontal direction, and the channel structures all extending along the vertical direction to penetrate the plurality of gate layers. in, The stacked structure includes: A first row of discontinuous cuts, wherein the first row of discontinuous cuts discontinuously divides the plurality of gate layers in the cell region between the first row of channel structures and the second row of channel structures along the first horizontal direction, wherein, in a cross-sectional view relative to a first height of the substrate, the maximum width of the end of at least one of the discontinuous cuts in the first row of discontinuous cuts in a second horizontal direction perpendicular to the first horizontal direction is greater than the maximum width of the middle portion of the at least one discontinuous cut in the second horizontal direction; and A continuous cut, wherein the continuous cut continuously divides the plurality of gate layers along the first horizontal direction in the cell region, and The second row of channel structures and the third row of channel structures are located between the first row of discontinuous cuts and the continuous cuts.

11. The storage device according to claim 10, wherein, In the cross-sectional view at the first height relative to the substrate, the maximum width of the middle portion of at least one discontinuous cut is less than the maximum width of the continuous cut, the maximum width being determined in the second horizontal direction.

12. The storage device according to claim 10, wherein, The continuous cuts continuously divide the plurality of gate layers along the first horizontal direction in the connection region of the stacked structure.

13. The storage device according to claim 10, wherein, The stacked structure further includes a second row of discontinuous cuts that discontinuously divide the plurality of gate layers along the first horizontal direction between the second row of channel structures and the third row of channel structures in the cell region.

14. The storage device according to claim 13, wherein, There is a first gap between two adjacent discontinuous cuts in the first row of discontinuous cuts. There is a second gap between two adjacent discontinuous cuts in the second row of discontinuous cuts, and The first gap is not aligned with the second gap in the second horizontal direction.

15. The storage device according to claim 10, wherein, The plurality of gate layers includes at least one bottom gate layer, a plurality of intermediate gate layers located on the at least one bottom gate layer, and at least one top gate layer located on the plurality of intermediate gate layers. The stacked structure further includes a discontinuous top cut, which discontinuously divides the at least one top gate layer along the first horizontal direction without dividing the plurality of intermediate gate layers and the at least one bottom gate layer. Each of the discontinuous top cuts extends between two adjacent discontinuous cuts in the first row of discontinuous cuts.

16. A storage device, comprising: Substrate; A stacked structure comprising a plurality of gate layers and a plurality of interlayer insulating layers alternately stacked on the substrate in a vertical direction; as well as Multiple channel structures are located in the cell regions of the stacked structure and extend along the vertical direction to penetrate the multiple gate layers. in, The stacked structure includes rows of cell region cutouts, each cell region cutout extending along a first horizontal direction and dividing the plurality of gate layers, wherein, in a cross-sectional view relative to a first height of the substrate, the maximum width of the end of at least one of the row of cell region cutouts in a second horizontal direction perpendicular to the first horizontal direction is greater than the maximum width of the middle portion of the at least one cell region cutout in the second horizontal direction. The cuts in the unit regions are spaced apart from each other and arranged along the first horizontal direction in the unit regions. The stacked structure includes rows of connection region cutouts, each of which extends along the first horizontal direction and divides the plurality of gate layers. The cutouts in the connection areas are spaced apart from each other and are arranged along the first horizontal direction in the connection areas of the stacked structure.

17. The storage device according to claim 16, wherein, In the cross-sectional view at the first height, the maximum width of the end of at least one of the row of connecting area cuts in the second horizontal direction is greater than the maximum width of the middle portion of the at least one connecting area cut in the second horizontal direction.

18. The storage device according to claim 17, wherein, In the cross-sectional view at the first height, the maximum width of the end of the at least one unit region cut is less than the maximum width of the end of the at least one connecting region cut.

19. The storage device according to claim 16, wherein, In a cross-sectional view at a second height relative to the substrate, the maximum width of the end of at least one of the row of cell region cutouts is greater than the maximum width of the end of at least one of the row of connection region cutouts, the maximum width being determined in the second horizontal direction.

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