System and method for removing low frequency offset components from a digital data stream

Abstract

A method for eliminating a low-frequency offset component from a digital data stream includes receiving an analog input signal from one or more analog front-end components at the input of an analog-to-digital converter (ADC). The analog input signal has an associated low-frequency offset due, at least in part, to the analog front-end components. The method also includes generating a digital data stream representing the analog input signal at the output of the ADC. The digital data stream has an associated low-frequency offset due, at least in part, to the analog front-end components and the ADC. One or more low-pass finite impulse response (FIR) filters are applied to the digital data stream to detect the low-frequency offset component in the digital data stream and generate a filtered output signal containing only the low-frequency offset component. In response, a corrected digital data stream without the low-frequency offset component is generated, for example, by taking a difference between the digital data stream and the filtered output signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. Provisional Application No. 62 / 912,918, filed on October 9, 2019, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to electrical circuits and, more particularly, to electrical circuits and related systems and methods for removing low-frequency offset components from digital data streams. Background Art

[0004] As is well known, electrical circuits typically include multiple electrical components, such as analog, digital and / or mixed-signal electrical components. It is well known that these electrical components (e.g., analog front-end components) may introduce noise or offset into the electrical signals received by the electrical components. In addition, the signal source coupled to the component may also introduce offset. If not taken into account, the introduced offset (e.g., low-frequency offset) may affect the accuracy of the output of the electrical component, as well as the accuracy of the circuit including the electrical component. For example, a measurement circuit is an example type of electrical circuit that typically includes multiple electrical components (e.g., measurement components) for measuring one or more parameters. For example, the offset introduced by the electrical component and the signal source coupled to the electrical component may affect the accuracy of the measurement circuit output, which may result in energy waste. Therefore, it is important to consider this offset. Summary of the Invention

[0005] Systems and methods are described herein for removing offset, particularly low-frequency offset components, from a digital data stream. The digital data stream may be received from, for example, one or more electrical components and / or signal sources in an electrical / power system. The power system may be associated with, for example, at least one load, process, building, facility, vessel, aircraft, or other type of structure.

[0006] In one aspect of the present disclosure, a method for eliminating a low-frequency offset component from a digital data stream includes receiving an analog input signal from one or more analog front-end components at the input of an analog-to-digital converter (ADC). The analog input signal has an associated low-frequency offset due, at least in part, to the analog front-end components. The method also includes generating, at the output of the ADC, a digital data stream representing the analog input signal. The digital data stream has an associated low-frequency offset due, at least in part, to the analog front-end components and the ADC. The method also includes applying one or more low-pass finite impulse response (FIR) filters to the digital data stream to detect the low-frequency offset component in the digital data stream and generating a filtered output signal containing only the low-frequency offset component. In response, a corrected digital data stream is generated without the low-frequency offset component, for example, by taking the difference between the digital data stream (i.e., the original digital data stream) and the filtered output signal using a summing circuit (e.g., which may take the form of a subtractor or subtraction circuit). In some embodiments, the corrected digital data stream is provided at the output of the circuit. Furthermore, in some embodiments, the corrected digital data stream is provided to one or more circuits, systems, or devices for further processing. For example, the corrected digital data stream may be processed using a field programmable gate array (FPGA), a microprocessor, a digital signal processor, and / or an off-system communication port where filtering may be performed.

[0007] According to some embodiments of the present disclosure, an analog front-end component can be coupled to one or more signal sources (e.g., a utility power source), wherein the analog front-end component is configured to receive one or more signals (e.g., voltage and / or current signals) generated by the one or more signal sources. In some embodiments, the signal sources may contribute to low-frequency offsets in analog signals (e.g., analog input signals) provided by the analog front-end component to the ADC. For example, the signal sources may introduce ground differentials to the signals. Additionally, resistive elements may contribute to offsets due to wire length, corrosion on the connections, and the like.

[0008] In some embodiments, the above methods and other methods (and systems) described below may include one or more of the following features, alone or in combination with other features. In some embodiments, the low-frequency offset components eliminated from the digital data stream include direct current (DC) offset components, such as DC offset components introduced by power supply noise and / or external low-frequency influences in electrical components (e.g., operational amplifiers) or power distribution systems, to name a few. In some embodiments, the one or more low-pass FIR filters configured to detect the low-frequency offset components in the digital data stream and generate a filtered output signal include at least one cascaded integrated comb (CIC) decimation filter (e.g., Figure 4AIn some embodiments, the one or more low-pass FIR filters include at least one recursive moving average filter. In some embodiments, the at least one recursive moving average filter includes at least one CIC decimation filter. As is well known, CIC decimation filters (e.g., 1400, as shown) Figure 4A ) is an effective implementation of a moving average filter. The filter(s) can be implemented using hardware, software, or a combination of hardware and software. CIC decimation filters are well known in the art and will not be described in detail herein.

[0009] In some embodiments, the analog front-end component includes at least one active electrical component (e.g., an operational amplifier, etc.) Additionally, in some embodiments, the analog front-end component includes at least one passive electrical component (e.g., a resistor, a capacitor, an inductor, etc.).

[0010] In some embodiments, the method is implemented in the measurement circuit, for example, using a processor of the measurement circuit or a processor associated with the measurement circuit. For example, the measurement circuit can be provided in a high-speed data acquisition device. As used herein, the term "processor" is used to describe an electronic circuit that performs a function, operation, or sequence of operations. The function, operation, or sequence of operations can be hard-coded into the electronic circuit or soft-coded using instructions stored in a memory device. The processor can use digital values or analog signals to perform the function, operation, or sequence of operations.

[0011] In some embodiments, the processor can be embodied as, for example, a specially programmed microprocessor, a digital signal processor (DSP), or an application specific integrated circuit (ASIC), which can be an analog ASIC or a digital ASIC. Additionally, in some embodiments, the processor can be embodied in configurable hardware such as an FPGA or a programmable logic array (PLA). In some embodiments, the processor can also be embodied in a microprocessor with an associated program memory. Additionally, in some embodiments, the processor can be embodied in a discrete electronic circuit, which can be an analog circuit, a digital circuit, or a combination of an analog circuit and a digital circuit. It should be understood that the terms "processor" and "controller" are sometimes used interchangeably herein. For example, a processor can be used to describe a controller. Additionally, a controller can be used to describe a processor.

[0012] In an embodiment in which the method is implemented using a measurement circuit, the measurement circuit may include, for example, an analog front-end component that receives an analog input signal, an ADC coupled to receive the analog input signal, and a low-pass FIR filter responsive to a digital data stream generated by the ADC. It should be understood that the measurement circuit may additionally or alternatively include other components, for example, depending on the circuit or device in which the measurement circuit is provided. In one embodiment, the measurement circuit is a measurement circuit used in a metering device. For example, the metering device may be a metering device used in a power system (e.g., a high-speed transient data acquisition device).

[0013] In some embodiments, a metering device may correspond to an Intelligent Electronic Device (IED). As used herein, an IED is a computing electronic device optimized to perform a specific function or set of functions. Examples of IEDs include smart meters, power quality meters, microprocessor relays, digital fault recorders, and other metering devices. IEDs may also be embodied in variable speed drives (VSDs), uninterruptible power supplies (UPSs), circuit breakers, relays, transformers, or any other electrical device. IEDs can be used to perform monitoring and control functions in a wide variety of facilities. Facilities may include utility systems, industrial facilities, warehouses, office buildings or other commercial complexes, campus facilities, computing co-location centers, data centers, power distribution networks, or any other system, process, or load that uses electrical energy. For example, if the IED is a power monitoring device, it may be coupled to (or installed in) an electric power transmission system or distribution system and configured to sense / measure and store data representing electrical parameters representing operational characteristics of the distribution system (e.g., voltage, current, waveform distortion, power, etc.). Users can analyze these parameters and characteristics to assess potential performance, reliability, or power quality-related issues. An IED may include at least a controller (which, in some IEDs, may be configured to run one or more applications simultaneously, serially, or both), firmware, memory, a communication interface, and connectors for connecting the IED to external systems, devices, and / or components of any voltage level, configuration, and / or type (e.g., AC, DC). At least some aspects of the monitoring and control functionality of the IED may be included in a computer program accessible to the IED.

[0014] It should be understood that the disclosed methods for eliminating low-frequency components from digital data streams can be implemented additionally or alternatively in circuits and devices other than measurement circuits and metering devices. In particular, the concepts and techniques disclosed herein may be found applicable to virtually any application in which it is desired to eliminate low-frequency components from a digital data stream, as will become more apparent in the discussion below. For example, the disclosed concepts and techniques may be found applicable to virtually any instrumentation application, such as high-voltage applications. In one example embodiment, these concepts and techniques are used in a high-speed transient capture application where a circuit responds to an input data stream where a low-frequency (e.g., DC) offset would result in erroneous behavior (e.g., incorrect event detection due to waveform distortion). The resulting data stream (i.e., after offset elimination) can be recorded, for example, for offline viewing.

[0015] In one aspect, the proposed invention uses a series of CIC decimation filters to detect low-frequency components from a digital data stream as it is received from an ADC. The combination of the CIC decimation filters (which only pass low-frequency signals) and a summation (e.g., subtraction) step removes the low-frequency components from the digital data stream. One example benefit is that the low-frequency components can be continuously removed sample by sample without calibrating the device, ensuring that the sampled digital data only contains the frequencies of interest to the application. This contrasts with traditional elimination methods, which require a calibration step during device manufacturing. As is well known, calibration methods do not account for temperature drift or aging, for example.

[0016] In one aspect, by using a CIC decimation filter as opposed to a traditional FIR filter, the embodiments proposed in the present invention are more computationally efficient and are well suited for implementation on programmable logic devices such as FPGAs. For example, in some embodiments, the low-frequency component occupies a very small portion of the frequency bandwidth of the signal. Applying a traditional FIR high-pass filter to attenuate this small area would result in a filter order that is too high to be properly implemented in typical hardware. By cascading a low-pass filter with decimation after each stage, the requirements for each stage are reduced. As is well known, a CIC decimation filter is a low-pass filter and is very efficient. According to some embodiments of the present disclosure, all frequency components except the low-frequency component are filtered out of the input signal, and then the low-frequency component is subtracted from the original signal to achieve the equivalent function of an FIR high-pass filter, rather than directly filtering the input signal. The act of decimating and cascading each stage allows for even higher efficiency because the sampling rate of each subsequent stage is reduced.

[0017] It will be appreciated that the disclosed systems and methods have numerous other advantages, as will become apparent from the following discussion. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The foregoing features of the present disclosure, as well as the present disclosure itself, may be more fully understood from the following detailed description of the accompanying drawings, in which:

[0019] Figure 1 is a block diagram of an example power system including a signal source and a metering device capable of monitoring one or more parameters of the signal source;

[0020] Figure 2 is a block diagram of an example measurement circuit according to an embodiment of the present disclosure, which can be used, for example, in a metering device;

[0021] Figure 3 is a block diagram of another example measurement circuit according to an embodiment of the present disclosure;

[0022] Figure 4 is a block diagram of a low frequency (LF) offset cancellation circuit according to an embodiment of the present disclosure, which LF offset cancellation circuit can be used, for example, in a measurement circuit;

[0023] Figure 4A An example arrangement of a cascaded integrator-comb (CIC) decimation filter is shown, which may be suitable for use in, for example, Figure 4 LF offset elimination circuit;

[0024] Figure 5 shows an example arrangement of low-pass finite impulse response filters, which may be suitable for use in, for example, Figure 4 LF offset elimination circuit;

[0025] Figure 6 is a flow chart illustrating an example method for removing low-frequency offset components from a digital data stream according to an embodiment of the present disclosure;

[0026] Figure 7 An example sample signal is shown;

[0027] Figure 7A shows an example signal after LF offset cancellation;

[0028] Figure 8 is a block diagram of an example measurement circuit according to a further embodiment of the present disclosure;

[0029] Figure 8A is a block diagram of another example measurement circuit according to further embodiments of the present disclosure;

[0030] Figure 8B is a block diagram of another example measurement circuit according to further embodiments of the present disclosure; and

[0031] Figure 8C is a block diagram of another example measurement circuit according to further embodiments of the present disclosure. DETAILED DESCRIPTION

[0032] The features and other details of the concepts, systems, and techniques for which protection is sought herein will now be described in greater detail. It should be understood that any specific embodiments described herein are shown by way of illustration and not as limitations of the present disclosure and the concepts described herein. Features of the subject matter described herein may be included in various embodiments without departing from the scope of the concepts for which protection is sought.

[0033] refer to Figure 1 , an example power system 100 according to an embodiment of the present disclosure includes a signal source 110 and a metering device 120 capable of monitoring one or more parameters of the signal source 110. The signal source 110 and the metering device 120 can each take various forms. For example, the signal source 110 can take the form of a renewable energy source (e.g., hydroelectric, geothermal, wind, and solar) or a non-renewable energy source (e.g., a fossil fuel power plant). In addition, the metering device 120 can take the form of a device for monitoring the amount of electrical energy consumed by a residence or business, or the form of a specific electric device at the residence or business. The metering device 120 can be coupled to the signal source 110 via one or more connectors and / or media (e.g., a transmission line).

[0034] In some embodiments, the signal source 110 may be provided as, include, or be coupled to one or more loads in the power system 100. The loads may include, for example, machinery or devices associated with a particular application (e.g., an industrial application), application, and / or process(es). For example, the machinery may include electrical or electronic equipment. The machinery may also include controllers and / or auxiliary equipment associated with the electrical or electronic equipment.

[0035] In the illustrated example embodiment, the metering device 120 includes a high-speed data acquisition device 121 and a display device 124. The high-speed data acquisition device 121 is coupled to receive a signal (or signals) 110a generated by the signal source 110 at an input and is configured to generate a signal (or signals) 121a at its output that is indicative of one or more monitored parameters of the signal (or signals) 110a. For example, the high-speed data acquisition device 121 can be configured to capture, sample, or measure the energy-related signal (or signals) (e.g., 110a) generated by the signal source 110 using measurement circuitry 122. Furthermore, the high-speed data acquisition device 121 can be configured to generate a signal (or signals) 121a at its output that is indicative of one or more parameters associated with the energy-related signal (or signals). The energy-related signal (or signals) may include, for example, at least one of a current signal and a voltage signal. Furthermore, the parameters associated with the energy-related signal (or signals) may include, for example, at least one of voltage, current, power, frequency, power factor, demand, energy, and other parameters derived from the current and / or voltage signals. Based on the parameter type, the signal(s) 121a may indicate one or more values (e.g., instantaneous, average maximum, etc.) of the signal(s) 110a. For example, in an embodiment where the signal(s) 110a (i.e., the input signal(s) 110a) are voltage signals, the signal(s) 121a (i.e., the output signal(s) 121a) may indicate the instantaneous and / or maximum average voltage of the signal(s) 110a.

[0036] According to some embodiments of the present disclosure, the measurement circuit 122 is coupled to the processor 123 of the high-speed data acquisition device 121 or a processor 123 associated with the high-speed data acquisition device 121 and includes, for example, one or more sensor devices for capturing, sampling, or measuring the signal(s) 110 a. According to some embodiments of the present disclosure, the processor 123 is coupled to receive the measurement signal and / or measurement data from the measurement circuit 122 and is configured to generate the output signal(s) 121 a.

[0037] In some embodiments, the output signal(s) 121a may be provided to a display device for displaying the monitored parameters (or selected ones of the monitored parameters) or information associated with the monitored parameters (e.g., power quality issues). The display device (e.g., an LCD or LED display) may be the display device 124 of the metering device 120, as shown. Additionally or alternatively, the display device may be, for example, a display device of a remote computing device.

[0038] In some embodiments, the output signal(s) 121a may be provided to a control circuit (not shown) for configuring (or controlling or regulating) one or more of the monitored parameters (or loads in the power system 100) and / or taking one or more actions responsive to the output signal(s) 121a. For example, in embodiments where the output signal(s) 121a indicate a power quality issue (determined by analysis of the output signal(s) 121a), the output signal(s) 121a may be used by the metering device 120 and / or the control circuit to identify event mitigation opportunities or to reduce (or ideally, eliminate) the effects of the power quality issue / event and to install mitigation equipment and / or perform mitigation measures. It should be understood that other actions (e.g., generation of an alarm, such as a transient alarm, etc.) may additionally or alternatively be taken, for example, as further described in co-pending U.S. patent application Ser. No. 16 / 137,603, entitled “Dynamic Tolerance Curves For Power Monitoring Systems,” assigned to the same assignee as the present disclosure. The control circuit may be a control circuit of the metering device 120 and / or a control circuit coupled to the metering device 120 .

[0039] According to embodiments of the present disclosure, measurement circuitry 122 includes multiple electrical components, such as analog, digital, and / or mixed-signal components. It is well known that electrical components may introduce low-frequency offsets into the electrical signals received by the electrical components. For example, DC offset, an example type of low-frequency offset, may be caused by two natural laws: 1. Current in an inductor cannot change instantaneously; and 2. Current necessarily lags the applied voltage by a natural power factor. Electrical components (e.g., operational amplifiers (op amps) and analog-to-digital converters (ADCs)) may have associated input DC offsets, which can be a source of DC offset. For example, an ideal op amp amplifies differential inputs; if the input difference is 0 volts (i.e., both inputs are at the same voltage), the output should be zero. However, due to manufacturing processes, the differential input transistors of actual op amps may not be perfectly matched. This results in a zero output at non-zero differential input values (referred to as input offset voltage). Furthermore, in differential signaling, such as in certain measurement circuits, differences in component values can result in bias voltages applied to the inputs or present in the system, such as ground potential differences. It should be appreciated that low frequency sources coupled to the measurement circuit 122 and / or the interconnects (eg, between various components associated with the measurement circuit 122 ) may also introduce offsets.

[0040] If not accounted for, the introduced offset can affect the accuracy of the measurement circuitry and metering equipment. For example, due to the introduced offset, deviations in the accuracy of measurements performed by the measurement circuitry can affect the accuracy of the measurement circuitry's output, and thus the accuracy of the metering equipment's output. This can lead to inaccurate measurement reports from the metering equipment, which can, for example, result in wasted energy. Therefore, it is important for metering equipment to have a way to compensate for deviations in measurement accuracy caused by, for example, the introduction of low-frequency offset components into the measurement data.

[0041] Example measurement circuits and example systems, devices, and methods for reducing and eliminating low-frequency offset components from measurement data (e.g., as provided in a digital data stream) are discussed below in conjunction with the accompanying drawings. It should be understood that Figure 1 The illustrated power system 100 is only one of many possible configurations of power systems according to embodiments of the present disclosure. For example, although in the illustrated embodiment the power system 100 is shown as including a single signal source 110 and a single metering device 120, it should be understood that in some embodiments the power system 100 may include multiple signal sources and / or multiple metering devices. In embodiments where the signal source(s) are provided as, include, or are coupled to one or more loads in the power system 100, the metering device(s) may be coupled to the corresponding load(s). In addition to capturing energy-related signals (and / or other signals), the metering device(s) may be configured to, for example, monitor, analyze, and / or control one or more parameters associated with the loads (e.g., energy-related parameters). The loads and / or metering devices may be associated with (e.g., installed or located at) one or more specific metering points in the power system, and the energy-related signals and / or parameters may be associated with the metering points to which the loads and / or metering devices are associated. In some embodiments, the metering device(s) may partially or fully perform the aforementioned control functions and / or be coupled to one or more control devices (e.g., in a power system) configured to perform at least some of the control functions. It should be understood that other configurations of the power system are also possible.

[0042] refer to Figure 2, shows an example measurement circuit 200 according to an embodiment of the present disclosure. The measurement circuit 200 has at least one input (here, input 201) and at least one output (here, output 202). Additionally, the measurement circuit 200 includes a signal path 210 (e.g., an analog, digital, and / or mixed signal path) and a low frequency (LF) offset cancellation circuit 220. In the illustrated embodiment, the signal path 210 includes one or more analog front-end components 212 and an analog-to-digital converter (ADC) 214, wherein the analog front-end component 212 has a first terminal coupled to the measurement circuit input 201 and a second terminal coupled to the first terminal of the ADC 220. Additionally, in the illustrated embodiment, the ADC 214 has a second terminal coupled to the first terminal of the LF offset cancellation circuit 220, and the LF offset cancellation circuit 220 has a second terminal coupled to the measurement circuit output 202. In some embodiments, the measurement circuit input 201 is coupled to a metering device (e.g., Figure 1 Additionally, in some embodiments, the measurement circuit output 202 is coupled to a metering device and / or other components of the metering device (e.g., a display device 124, such as Figure 1 As shown above Figure 1 As described, the metering device can be coupled to a signal source (e.g., Figure 1 shown in 110).

[0043] According to one embodiment of the present disclosure, analog front-end component 212 includes at least one component for capturing, sampling, or measuring a parameter (e.g., voltage, current, etc.) of an input signal (here, input signal 200a). In embodiments, the at least one component may take the form of a resistor (e.g., a current sensing resistor), a capacitor, and / or substantially any other type of element (or elements) that may be found suitable for measuring a parameter. It should be understood that the number of the at least one component (e.g., one element, two elements, three elements, etc.) and the arrangement (e.g., series or parallel coupling) of the at least one component may be selected based at least in part on the parameter (s) being measured by the at least one component. For example, in embodiments where the at least one component is configured to measure the voltage level of input signal 200a, the at least one component may include multiple measurement elements. For example, the multiple measurement elements may be coupled in a frequency divider configuration. It should be understood that the analog front-end component may additionally or alternatively include one or more other analog components, such as capacitors, inductors, diodes, transistors, and operational amplifiers. The analog front-end component may take the form of active electrical components and / or passive electrical components.

[0044] During operation of measurement circuit 200, circuit 200 is configured to receive an input signal 200a at input 201 and provide an output signal 210a indicative of input signal 201a at output 202. According to some embodiments, output signal 210a indicates the level or value of one or more parameters (e.g., voltage, current, etc.) associated with input signal 200a. More specifically, in some embodiments, analog front-end component 212 is coupled to input signal 200a and configured to provide an analog signal 212a (i.e., an initial measurement signal) indicative of the corresponding one or more parameters. In some embodiments, analog signal 212a is associated with a value of the analog front-end component (e.g., a measured resistance value or charge). Additionally, in some embodiments, analog signal 212a is associated with an output of analog front-end component 212 or an output of a node near analog front-end component 212.

[0045] ADC 214 responds to analog signal 212a (e.g., an analog input signal to the ADC) and provides a corresponding converted digital signal 210a at the output of signal path 210. In some embodiments, digital signal 210a may take the form of a digital data stream representing analog signal 212a. For simplicity, digital signal 212a is referred to as digital data stream 210a hereinafter.

[0046] In some embodiments, the LF offset cancellation circuit 220 may be provided as, include, or be implemented in a computer processor, and the LF offset cancellation circuit 220 generates a corrected digital data stream 220a without a low frequency offset component in response to the digital data stream 210a. More specifically, as described above in conjunction with Figure 1For example, a measurement circuit (here, measurement circuit 200) may include multiple electrical components that can introduce a low-frequency offset into an electrical signal received by the components. In the illustrated embodiment, for example, analog front-end component 212 and ADC 214 can introduce a low-frequency offset into the electrical signal received by the components. For example, analog front-end component 212 can introduce a low-frequency offset into input signal 200a received by analog front-end component 212. To this end, analog signal 212a generated by analog front-end component 212 can have an associated low-frequency offset at least in part due to analog front-end component 212. Similarly, ADC 214 can introduce a low-frequency offset into analog signal 212a received by ADC 214. To this end, digital data stream 210a generated by ADC 210 can have an associated low-frequency offset at least in part due to analog front-end component 212 and ADC 214. In other words, the low-frequency offset can be synthesized on signal path 210 (here, the signal path includes analog front-end component 212 and ADC 214). It should be understood that many ADC configurations (and other means for converting analog signals into digital signals) are possible. For example, other means of conversion may take the form of or include a slope comparator. It should also be understood that in some embodiments, signal path 210 may include additional (or alternative) electrical components. For example, signal path 210 may include an operational amplifier, a transistor-based amplification circuit, a demodulation circuit, etc.

[0047] The LF offset cancellation circuit 220 is configured to generate a corrected digital data stream 220a without the low-frequency offset component in real time or substantially real time (i.e., without affecting the operation of the measurement circuit 200) by detecting the low-frequency offset component in the digital data stream 210a received by the LF offset cancellation circuit 220 and canceling the low-frequency offset component. For example, in one example embodiment of the LF offset cancellation circuit 220, the LF offset cancellation circuit 220 is configured to apply one or more low-pass finite impulse response (FIR) filters to the digital data stream to detect the low-frequency offset component in the digital data stream and generate a filtered output signal containing only the low-frequency offset component. Additionally, in an example embodiment, the LF offset cancellation circuit 220 is configured to obtain a difference between the digital data stream and the filtered output signal to generate the corrected digital data stream 220a without the low-frequency offset component. Further aspects and examples of low-frequency offset cancellation circuits according to embodiments of the present disclosure are discussed further below in conjunction with the accompanying figures.

[0048] In the illustrated embodiment, the corrected digital data stream 220a (e.g., the corrected measurement signal) corresponds to the output signal of the measurement circuit 200. However, it should be understood that in some embodiments, the corrected digital data stream 220a may be received by additional circuitry (not shown) of the measurement circuit 200, and the output signal of the measurement circuit 200 may be associated with an output signal generated or otherwise provided by the additional circuitry. Additionally, it should be understood that in some embodiments, the corrected digital data stream 220a (or a signal associated with the corrected measurement signal) may correspond to only one of many output signals of the measurement circuit 200. For simplicity and clarity, Figure 2 One output signal is shown in FIG, but this is not intended to be limiting.

[0049] In some embodiments, an indication of the detected offset can be provided to a circuit or system internal or external to measurement circuit 200. For example, the detected offset can be indicated in the form of a light-emitting diode or other visual indicator of measurement circuit 200, or as a signal provided at a dedicated output pin of measurement circuit 200. Additionally, an indication of the detected offset can be provided to a metering device (e.g., a computer) that uses measurement circuit 200. Figure 1 A user viewing the display device may respond to an abnormal detected offset (e.g., due to a component failure), for example, by replacing one or more components associated with the detected offset (e.g., analog front end component 212).

[0050] In some embodiments, the detected offset may also be stored in a memory device (e.g., a memory device of or associated with LF offset cancellation circuit 220) for later analysis. For example, the detected offset may be analyzed to determine or verify component lifetime and / or to track offset introduced into the signal by electrical components in measurement circuit 200. For example, the determined component lifetime and / or tracked offset may be reported via a display device (of or external to measurement circuit 200) or an output signal. In embodiments, the output signal (which may be provided at an output of measurement circuit 200) may be received by control circuitry (or other circuitry) associated with measurement circuit 200, for example, to control one or more parameters associated with a signal source from which input signal 200a is received. By way of example, the one or more parameters may be associated with a state of the signal source (e.g., on / off state(s), open / closed state(s), high / low state(s)) and / or a signal generated by the signal source or other associated device (e.g., a signal level of the signal). As another example, the one or more parameters may also be associated with at least one of temperature, pressure, volume, space, velocity, humidity, and any other representative physical representation signal.

[0051] While measurement circuit 200 may be provided in the illustrated form of a circuit having an analog front-end portion and a digital portion, it should be understood that the specific description of the circuit functionality of measurement circuit 200 may vary, whether implemented in analog fashion or using digital circuits and signals. For example, one or more portions of signal path 210 (e.g., analog front-end component 212, ADC 214) may take forms other than those shown. For example, in some embodiments, analog front-end component 212 may take the form of digital and / or mixed-signal components. Additionally, in some embodiments, ADC 214 may take the form of a digital-to-analog converter (DAC). The same principles of removing low-frequency offset components from the signal still apply.

[0052] It should also be understood that one or more portions of the measurement circuit 200 may be provided as part of, or implemented by, a controller (not shown) (e.g., a synchronous digital controller or an analog controller). The controller may, for example, execute the functions, operations, or sequences of operations of one or more portions of the signal path 210. The controller may include offset cancellation circuitry (e.g., as provided by the LF offset cancellation circuit 220) and / or software.

[0053] It should also be understood that, for example, in addition to eliminating low-frequency components from the signal, the measurement circuit 200 (and other measurement circuits described throughout this disclosure) can provide correction for temperature drift or aging. It is well known that electrical components (e.g., measurement elements) may drift from their initial or baseline values over time due to external factors such as aging and stress conditions (e.g., humidity, chemical interactions, and temperature). For example, for the measurement element, this drift may cause inaccurate measurements performed by the measurement element and the circuits and devices associated with the measurement element. According to various aspects of the present disclosure, the measurement circuit disclosed herein provides correction for component drift by continuously evaluating the signal from the component's offset and eliminating the detected offset. Example types of drift that can be corrected are DC drift caused by changes in component value (e.g., measurement element resistance value) or changes in DC offset associated with active components such as op amps. In one example embodiment, one input is treated as a reference signal. The op amp circuit is configured in such a way that the reference channel is subtracted from each of the inputs. Changes in value will result in the DC component not being completely eliminated from each of the inputs. Additional aspects of drift correction are described in co-pending U.S. patent application Ser. No. 16 / 026,836, entitled “Measurement Circuit,” and co-pending U.S. patent application Ser. No. 16 / 127,703, entitled “Measurement Circuit,” which are assigned to the same assignee as the present disclosure and are incorporated herein by reference in their entirety.

[0054] refer to Figure 3 Another example measurement circuit 300 according to an embodiment of the present disclosure includes a signal path 310 and a LF offset cancellation circuit 340. In the illustrated embodiment, the signal path 310 includes at least one analog front-end component 320 and an ADC 330.

[0055] In the illustrated embodiment, at least one analog front end component 320 (which may be combined with the above Figure 2 The analog front-end components 212 (which are the same as or similar to the analog front-end components 212 described above) include multiple analog front-end components (here, analog front-end components 322, 324, and 326). In the example embodiment shown, each of the analog front-end components 322, 324, and 326 has a terminal (e.g., a first terminal) coupled to a corresponding input terminal (here, input terminals 301, 302, and 303) of the measurement circuit 300. In some embodiments, at least one of the analog front-end components 322, 324, and 326 includes multiple analog front-end components.

[0056] ADC 330 has at least one input (here, similar multiple inputs serve as multiple analog front-end components 322, 324, 326) and at least one output (here, similar multiple outputs serve as multiple inputs). The ADC input is coupled to corresponding terminals (e.g., second terminals) of analog front-end components 322, 324, 326, and the ADC output is coupled to at least one input of LF offset cancellation circuit 340 (here, similar multiple inputs serve as ADC outputs).

[0057] The LF offset cancellation circuit 340 of the measurement circuit 300 (which can be combined with the above Figure 2 The LF offset cancellation circuit 220 described above (which is the same as or similar to the LF offset cancellation circuit 220) has at least one output terminal (here, similar multiple output terminals serve as multiple input terminals).

[0058] During operation of the measurement circuit 300, the analog front-end components 322, 324, 326 are coupled to input signals 300a, 300b, 300N (e.g., voltage and / or current signals) received at respective input terminals 301, 302, 303 of the measurement circuit 300 and are configured to provide respective analog signals 320a, 320b, 320N (e.g., initial measurement signals) indicative of the input signals 300a, 300b, 300N. The ADC 330 provides corresponding converted digital signals (here, digital data streams 330a, 330b, 330N) in response to the analog signals 320a, 320b, 320N. Similar to the above, the analog front-end components 322, 324, 326 are coupled to input signals 300a, 300b, 300N (e.g., voltage and / or current signals) received at respective input terminals 301, 302, 303 of the measurement circuit 300. Figure 2The digital data stream 210 a , digital data streams 330 a , 330 b , 330 N, for example, have LF offset components present due at least in part to the analog front end components 322 , 324 , 326 and the ADC 330 .

[0059] LF offset cancellation circuit 340 is responsive to digital data streams 330a, 330b, 330N to provide corrected digital data streams 340a, 340b, 340N without LF offset components.Corrected digital data streams 340a, 340b, 340N are each provided to a corresponding measurement circuit output 305, 306, 307.

[0060] Similar to the above combination Figure 2 Similar to the measurement circuit 200 described above, the measurement circuit 300 is capable of dynamically correcting (i.e., in real time or substantially in real time) the digital data streams 330a, 330b, 330N without impeding normal operation of the measurement circuit 300. More specifically, similar to the measurement circuit 200, the measurement circuit 300 is capable of detecting and removing low-frequency offset components from the digital data streams 330a, 330b, 330N to provide corrected digital data streams 340a, 340b, 340N without the low-frequency offset components without impeding normal operation of the measurement circuit 300. For example, the following description is made in conjunction with Figure 4 Example low-frequency offset cancellation circuits and example methods for canceling low-frequency offset components are described.

[0061] Also similar to measurement circuit 200 , the corrected digital data streams 340 a , 340 b , 340N output by measurement circuit 300 may be received by additional circuitry (not shown) of measurement circuit 300 and / or by circuits and devices external to measurement circuit 300 for further processing.

[0062] refer to Figure 4 , shows an example low frequency offset cancellation circuit 400 according to an embodiment of the present disclosure. In the illustrated embodiment, the low frequency offset cancellation circuit 400 includes at least one low pass (LP) finite impulse response (FIR) filter 410 and at least one summing circuit 420.

[0063] In the illustrated embodiment, at least one LP FIR filter 410 includes a plurality of LP FIR filters (here, LPFIR filters 412, 414, 416). In the illustrated example embodiment, each of the LP FIR filters 412, 414, 416 has a terminal (e.g., a first terminal) coupled to a corresponding input terminal (here, input terminals 401, 402, 403) of the low frequency offset cancellation circuit 400. In some embodiments, at least one of the LP FIR filters 412, 414, 416 includes, for example, a plurality of LP FIR filters (e.g., a first terminal) arranged in series. Figure 5 , which will be discussed further below). In some embodiments, the LP FIR filters 412, 414, 416 can take the form of a cascaded integrator comb (CIC) decimation filter. Additionally, in some embodiments, the LP FIR filters 412, 414, 416 can take the form of a recursive moving average filter (which can include at least one CIC decimation filter). According to some embodiments, the CIC filter can only have a low-pass characteristic. By implementing the CIC filter as a multi-rate decimation filter, for example, the filter does not have a multiplication operation and is therefore more efficient. The goal of this example embodiment is to efficiently create a high-pass filter with a passband at very low frequencies. As will be described further below, the act of low-pass filtering a signal and then subtracting it from the original waveform allows a very effective CIC filter (low-pass only) to efficiently become a high-pass filter.

[0064] In the illustrated embodiment, at least one summing circuit 420 of the low-frequency offset cancellation circuit 400 includes a plurality of summing circuits (here, summing circuits 422, 424, 426) configured to subtract the results from the LP FIR filters 412, 414, 416 from the original data stream. Each of the summing circuits 422 has at least two inputs (here, two inputs for each signal received at the low-frequency offset cancellation circuit inputs 401, 402, 403) and at least one output (here, one output for each signal received at the low-frequency offset cancellation circuit inputs 401, 402, 403). In the illustrated embodiment, the summing circuit outputs are coupled to the outputs 405, 406, 407 of the low-frequency offset cancellation circuit 400.

[0065] During operation of the low frequency offset cancellation circuit 400, the LP FIR filters 412, 414, 416 are coupled to input signals 400a, 400b, 400N received at respective input terminals 401, 402, 403 of the low frequency offset cancellation circuit 400 and are configured to process the input signals 400a, 400b, 400N to detect low frequency offset components in the input signals 400a, 400b, 400N. According to an embodiment of the present disclosure, the input signals 400a, 400b, 400N correspond to digital data streams having low frequency offset components present, for example, due to analog front end components, ADC(s), and / or signal sources, similar to Figure 3 The digital data streams 330a, 330b, 330N are shown in FIG.

[0066] The LP FIR filters 412 , 414 , 416 are further configured to generate respective filtered output signals 410 a , 410 b , 410 N containing only the low-frequency offset component.

[0067] According to an embodiment of the present disclosure, the detection of the low-frequency offset component is the result of the selected filter topology. For example, the feature of the low-pass filter topology will be passband and stopband and associated attenuation. By specifying the passband identical with the frequency of the low-frequency (e.g., DC) component that we wish to eliminate from input signal 400a, 400b, 400N, then when the signal is fed into filter 412, 414, 416, the output of the filter (here, output signal 410a, 410b, 410N) will mainly consist of only the passband frequency component. In our case, this is the low-frequency (e.g., DC) component that we wish to eliminate from signal path.

[0068] Each of the summing circuits 422, 424, 426 is responsive to a corresponding one of the filtered output signals 410a, 410b, 410N and a corresponding one of the digital data streams 400a, 400b, 400N to generate a corrected digital data stream 420a, 420b, 420c without a low-frequency offset component. More specifically, each of the summing circuits 422, 424, 426 (e.g., which may take the form of a subtractor or subtraction circuit) is responsive to a corresponding one of the filtered output signals 410a, 410b, 410N and a corresponding one of the digital data streams 400a, 400b, 400N to generate a corrected digital data stream 420a, 420b, 420c that is a combination of the filtered output signals 410a, 410b, 410N and the digital data streams 400a, 400b, 400N. For example, the summing circuits 422, 424, 426 can take the difference between the digital data streams 400a, 400b, 400N and the filtered output signals 410a, 410b, 410N to generate corrected digital data streams 420a, 420b, 420c without the low-frequency offset component. As another example, the results (i.e., outputs) of the decimated LP FIR filters 412, 414, 416 (e.g., FIR low-pass filters) can be used for post-processing of the data. Thus, instead of directly applying the correction, the low-frequency offset correction circuit 400 can determine alternative corrections based on many data sets, or determine (multiple) faults in the system due to large calculated offset components.

[0069] In the illustrated embodiment, corrected digital data streams 420a, 420b, 420c are received at respective outputs 404, 405, 406 of the low frequency offset cancellation circuit 400. In some embodiments, the corrected digital data streams 420a, 420b, 420c may be received by additional circuits and devices (e.g., measurement circuitry) for further processing.

[0070] refer to Figure 5, shows an example arrangement of an LP FIR filter according to an embodiment of the present disclosure. According to some embodiments, for example, the LP FIR filter 500 may be arranged with Figure 4 The LP FIR filter 500 is identical or similar to the one shown. As shown, the LP FIR filter 500 has at least one input (here, input 501) and at least one output (here, output 502). Furthermore, the LP FIR filter 500 includes multiple stages (here, three stages 510, 520, and 530). According to embodiments of the present disclosure, the number of stages is based on multiple factors. For example, a stage with high computational efficiency can be selected to limit bit growth and the number of steps required to complete the calculation. For example, the order can be selected based on the desired attenuation in the passband (for example, in our case, less than 0.5 bits may be required in the first stage). This means the total attenuation of all cascaded filter elements. Less than 0.5 bits means that any measurable low-frequency components (for example, DC components) are below the system resolution. Furthermore, higher-precision results can be created from the FIR filter(s). For example, the input word size can be 12 bits, and the FIR filter result can be 14 bits to increase the resolution. The higher the order, the greater the decimation rate, the larger the result becomes and can no longer be stored efficiently. As is well known, the filter order determines the number of operations required per sample. Another example factor to consider when selecting the number of stages is the overall target cutoff frequency for low frequency (e.g., DC) offset cancellation. For example, in an embodiment targeting frequencies below 1 Hz, a single-stage filter would be too large to implement. Decimation reduces the clock rate without affecting the accuracy of the filtered waveform, so subsequent stages can operate at lower frequencies and have more cycles available for each calculation. Decimation is also multiplicative, so three stages with a decimation rate of 64 effectively implement a decimation rate of 262,144. Attempting to implement this decimation rate in a single stage would be computationally intensive (and therefore inefficient).

[0071] In the illustrated embodiment, filter stages 510, 520, 530 are arranged in series, where stage 1 (labeled 510) has an input coupled to the LP FIR filter input 501 and an output coupled to the input of stage 2 (labeled 520), stage 2 has an output coupled to the input of stage 3 (labeled 530), and stage 3 has an output coupled to the LP FIR filter output 502.

[0072] During operation of the LP FIR filter 500, the filter stage 510 (ie, stage 1) is coupled to receive an unfiltered digital data stream 500a (eg, which may be similar to Figure 44 (i.e., stage 2) is coupled to receive the first filtered digital data stream 510a and is configured to generate a second filtered digital data stream 520a. Furthermore, filter stage 530 (i.e., stage 3) is coupled to receive the second filtered digital data stream 520a and is configured to generate a third filtered digital data stream 530a.

[0073] According to some embodiments of the present disclosure, in the illustrated embodiment, the third filtered digital data stream 530a received at the LP FIR filter output 502 includes only the low-frequency offset components present in the unfiltered digital data stream 500a. In other words, the filter stages 510, 520, 530 eliminate that portion of the unfiltered digital data stream 500a that is not attributable to the low-frequency offset due to, for example, electrical components and / or signal sources (e.g., Figure 3 The measurement circuit 300 shown in FIG.

[0074] Similar to the above combination Figure 4 The corrected digital data streams 420a, 420b, 420c and, in some embodiments, the third filtered digital data stream 530a may be received by additional circuits and devices (eg, measurement circuitry) for further processing.

[0075] refer to Figure 6 , shows a flow chart (or flowchart) of removing low frequency offset components from a digital data stream to illustrate an example method (here, method 600) of the present disclosure. The rectangular elements (referred to herein as "processing blocks") Figure 6 605 in the figure) can represent computer software and / or algorithmic instructions or groups of instructions. Diamond-shaped elements, which may be referred to herein as "decision blocks," represent computer software and / or algorithmic instructions or groups of instructions that affect the execution of the computer software and / or algorithmic instructions represented by the processing blocks. The processing blocks and decision blocks (as well as the other blocks shown) can represent steps performed by functionally equivalent circuits, such as digital signal processor circuits or application-specific integrated circuits (ASICs).

[0076] The flowcharts do not describe the syntax of any particular programming language. Instead, the flowcharts illustrate the functional information required by a person skilled in the art to fabricate a circuit or generate computer software to perform the processing required by a particular device. It should be noted that many routine elements (such as loops and variable initialization and the use of temporary variables) are not shown. A person skilled in the art will understand that, unless otherwise stated herein, the specific sequence of blocks described is illustrative only and can be changed. Therefore, unless otherwise stated, the blocks described below are unordered; this means that, when possible, the blocks can be executed in any convenient or desired order, including that consecutive blocks can be executed simultaneously and vice versa. It will also be understood that, in some embodiments, various features from the flowcharts described below can be combined. Therefore, unless otherwise stated, some features from the flowcharts described below can be combined with other features of the flowcharts described below, for example, to capture the various advantages and characteristics of the systems and methods associated with eliminating low-frequency offset components for which protection is sought in this disclosure. It should also be understood that, in some embodiments, various features from the flowcharts described below can be separated. For example, while a flowchart may be shown as having numerous blocks, in some embodiments the illustrated method illustrated by the flowchart may include fewer blocks or steps.

[0077] refer to Figure 6 , a flow chart shows an example method 600 for removing low frequency offset components (eg, undesirable DC offset components) from a digital data stream. The method 600 may be used in, for example, a metering device (eg, Figure 1 123 shown in the figure) or another device or a processor associated with the metering device or another device. To simplify the discussion herein, method 600 will be discussed with reference to a metering device. However, it should be understood that method 600 can be implemented on other types of devices. These devices are not necessarily devices in or associated with power systems, but can be devices in or associated with many other types of systems. For example, method 600 can be implemented in any metering application where unwanted LF or DC signals present in the sampled data stream will affect the measurement objective. For example, if a bias is used to activate a particular technology of the sensor, the proposed invention will be able to remove the bias from the sampled data stream.

[0078] like Figure 6 As shown in FIG, in one example embodiment of the method 600, the method 600 begins at block 605, where one (or more) signals are measured by a metering device, for example, using a measurement circuit of the metering device (e.g., Figure 2200 as shown). The (multiple) signals may include, for example, energy-related signals. The energy-related signals may include, for example, at least one of a voltage signal, a current signal, and a derived energy-related value. In some embodiments, the derived energy-related value includes at least one of the following: an additional energy-related value calculated, derived, developed, interpolated, extrapolated, evaluated, and otherwise determined from at least one of the voltage signal and the current signal. It should be understood that many other derived (multiple) energy-related values and types of energy-related signals (and other input signals) are possible.

[0079] According to some embodiments of the present disclosure, a signal path of a measurement circuit (e.g., Figure 2 One or more components in 210) shown in FIG. 210) are used to capture (multiple) signals. Figure 2 As described, for example, according to some embodiments of the present disclosure, a measurement circuit signal path (e.g., an analog, digital, and / or mixed signal path) may include one or more components capable of capturing or sampling (multiple) signals. These components may include, for example, one or more analog front-end components (e.g., resistors, capacitors, etc.), and the analog front-end components may generate or provide one or more signals (i.e., analog signals) at their output (or outputs) indicating the captured (multiple) signals. According to some embodiments of the present disclosure, the signals indicating the captured (multiple) signals include or indicate measurement parameters (e.g., voltage, current, etc.) associated with the (multiple) signals. For example, as described above in conjunction with Figure 2 The signal(s) may have an associated low frequency offset (eg, a DC offset). According to some embodiments of the present disclosure, the low frequency offset is at least partially attributable to analog front end components, at least for the reasons described above in conjunction with earlier figures.

[0080] At block 610, for example, at an ADC (e.g., Figure 2 220) and / or other suitable device(s) as shown, and / or generate a digital data stream (or multiple digital data streams) representing the signal(s) captured at block 605. For example, the signal(s) captured at block 605 or a signal (or multiple signals) indicative of the captured signal(s) (e.g., output signal(s) from an analog front end component) may be received at an input of an ADC, and the ADC may generate a digital data stream (or multiple digital data streams) representing the signal(s) at its output (or outputs).

[0081] According to an embodiment of the present disclosure, the digital data stream(s) have an associated low-frequency offset. The offset may be at least partially due to analog components and ADCs and / or other suitable devices.

[0082] At block 615, a low-frequency offset component (e.g., a low-frequency offset from an analog front-end component and an ADC) is detected in the (multiple) digital data streams generated at block 610. For example, the (multiple) digital data streams can be processed, and the low-frequency offset component can be detected based on an analysis of the (multiple) digital data streams. According to some embodiments of the present disclosure, for example, as described in conjunction with the above figures, analysis is performed and the low-frequency offset component is detected by applying one or more low-pass FIR filters to the digital data streams. As previously described, in some embodiments, the low-pass FIR filter may include one or more moving average filters (e.g., a recursive moving average filter). For example, the moving average filter may be implemented as a CIC filter. As is well known, a CIC filter is an effective implementation of a moving average filter.

[0083] At block 620, a filtered output signal (or multiple filtered output signals) is generated in which only the low-frequency offset component is present. According to some embodiments of the present disclosure, at block 615, (multiple) filtered output signals are generated at the output (or multiple outputs) of the low-pass FIR filter responsible for detecting the low-frequency offset component.

[0084] At block 625, a corrected digital data stream (or corrected digital data streams) is generated that is free of the low-frequency offset component. According to some embodiments of the present disclosure, the corrected digital data stream(s) are generated by taking the difference between the digital data stream(s) generated at block 610 and the filtered output signal(s) generated at block 620. For example, the corrected digital data stream(s) can be generated by subtracting the filtered output signal(s) from the digital data stream(s) using a subtractor circuit or functionality implemented by the subtractor (i.e., eliminating the filtered output signal portion). It should be understood that, as described above in conjunction with the accompanying drawings, there are many example ways to generate the corrected digital data stream(s).

[0085] In some embodiments, the method may end after block 625. In other embodiments, the method may return to block 605 and repeat again (e.g., to capture and process additional signal(s). In some embodiments where the method ends after block 625, the method may be started again, for example, in response to user input and / or control signals.

[0086] It should be understood that in some embodiments, method 600 may include one or more additional or alternative blocks. For example, in some embodiments, the method may further include providing the corrected digital data stream(s) generated at block 625 to one or more circuits, systems, and / or devices for further processing. For example, in embodiments where method 600 is implemented on a metering device and the metering device is disposed in / used in a power system, the corrected digital data stream(s) may be received by circuits, systems, and / or devices in or associated with the metering device in the power system. In one embodiment, the corrected digital data stream(s) may be processed (e.g., on one or more processors in or associated with the metering device) to, for example, identify power quality issues (e.g., voltage sags, voltage swells, etc.) in the power system. This processing may be performed locally (e.g., at a location close to the power system) or remotely (e.g., in the cloud).

[0087] In some embodiments, the corrected digital data stream(s) and / or signals representing the corrected digital data stream(s) may also be provided to a control system. The control system may respond to the corrected digital data stream(s) and / or signals representing the corrected digital data stream(s), for example, to control one or more aspects of a circuit, system (e.g., a power system), or device including a metering device. For example, in one embodiment, the corrected digital data stream(s) and / or signals representing the extracted signals may indicate a power quality problem in the power system, and the control system may adjust one or more parameters (e.g., associated with equipment / loads) in the power system in response to the data stream(s) and / or signals to reduce the effects of the power quality problem. The control system may also generate alarms and / or couple or decouple systems and devices (e.g., mitigation devices) to reduce the effects of the power quality problem.

[0088] refer to Figure 7-7A , shows several example signal waveforms. For example, Figure 7 An example sampled signal 700 (ie, a raw sampled signal) is shown, which may be indicative of a signal sampled using the systems and methods disclosed herein (eg, at Figure 6 605 of the method 600 shown). In addition, Figure 7A An example signal 1700 (e.g., a transient signal) is shown after low-frequency offset cancellation (e.g., at block 625 of method 600) using systems and methods according to embodiments of the present disclosure. According to some embodiments of the present disclosure, signal 1700 indicates signal 700 having a low-frequency offset component cancelled from signal 700. The low-frequency offset component may, for example, include a DC offset component, as described above in conjunction with the accompanying figures.

[0089] It should be understood that many other additional and alternative configurations of the above-described systems and methods are contemplated. Figure 8-8C , shows several example measurement circuits according to further embodiments of the present disclosure. First, refer to Figure 8 , shows a measurement circuit 800 according to another embodiment of the present disclosure, wherein Figure 2 Similar elements of the illustrated measurement circuit (i.e., measurement circuit 200) are shown with similar reference labels. As shown, measurement circuit 800 has an input 201 and a plurality of outputs (here, outputs 202, 203). In addition, measurement circuit 800 includes a signal path 210 (e.g., an analog, digital, and / or mixed signal path) and an LF offset cancellation circuit 220. Measurement circuit 800 also includes a node 204 at which the output (or outputs) of signal path 210 (e.g., a digital signal or data stream 210a) is received. Similar to measurement circuit 200, LF offset cancellation circuit 220 in measurement circuit 800 generates a corrected digital data stream / signal 220a provided at output 202 in response to the output(s) of signal path 210. Here, the output(s) of signal path 210 are also provided at output 203. For example, the signals at outputs 202, 203 may be provided to a circuit or system (e.g., an analog, digital, and / or mixed signal path) within or external to measurement circuit 800. Figure 1 123).

[0090] According to some embodiments of the present disclosure, measurement circuit 800 (and alternative configurations described further below) is desirable, for example, when a system user desires to analyze corrected digital data stream / signal 220a (i.e., a signal with low-frequency components removed) and digital data stream / signal 210a in which low-frequency components are present. For example, corrected digital data stream / signal 220a and digital data stream / signal 210a can be analyzed to characterize input signal 200a received at input 201. For example, the presence of LF components in input signal 200a can be reported to provide insight into the current level of the corresponding corrected data stream 220a. For example, if the LF component exceeds a certain threshold, this can be used in downstream applications to flag errors. It should be understood that such insights cannot be obtained by, for example, simply viewing corrected data stream 220a.

[0091] First reference Figure 8A, shows another example measurement circuit 1800 according to an embodiment of the present disclosure. As shown, the measurement circuit 1800 additionally includes a control circuit 240. The control circuit 240 is coupled to the output of the signal path 210, the terminal (e.g., I / O terminal) 205, the input (or multiple inputs) of the LF offset cancellation circuit 220, and the output 203. According to some embodiments of the present disclosure, the control circuit 240 is coupled to receive the output(s) of the signal path 210 and is configured to control the flow of the output(s) of the signal path 210 in response to a control signal 240a received at the terminal 205. The control signal 240a can be received from, for example, a control system / device and / or a processor (e.g., a control system / device coupled to the terminal 205) and / or a processor (e.g., a control system / device coupled to the terminal 205). Figure 1 123). Control signal 240a can indicate, for example, whether the output(s) of signal path 210 should be provided to both LF offset cancellation circuit 220 (as signal(s) 240b) and output 203 (as signal(s) 240c), or only to LF offset cancellation circuit 220 (as signal(s) 240b). In some embodiments, signal(s) 240b and signal(s) 240c are identical or similar to each other. In other embodiments, signal(s) 240b and signal(s) 240c are different from each other.

[0092] like Figure 8B As shown, according to some embodiments of the present disclosure, signal(s) 240c may be received by one or more other circuits 250 before being provided to output 203. More specifically, in measurement circuit 2800, other circuit 250 may be coupled to receive signal(s) 240c at one or more inputs and generate one or more outputs 250a. According to some embodiments of the present disclosure, other circuit 250 may include one or more filtering circuits and / or other circuitry suitable for capturing information (e.g., parameters) associated with input signal(s) 200a received at input 201. For example, other circuit 250 may include a low-pass filter, where the low-pass filter is applied before and / or after LF correction is applied using LF offset cancellation circuit 220. For example, a low-pass filter may be used when the ADC sampling rate (e.g., the sampling rate of ADC 214) is significantly higher than the region of interest in the application, or a shaping filter may be used to compensate for the effects of measurement circuitry (e.g., 2800). It should be understood that other circuit 250 may include other types of filters in addition to low-pass filters and shaping filters. It should also be understood that in some embodiments, other circuitry 250 may include circuitry other than filters.

[0093] like Figure 8CAs shown in the measurement circuit 3800 in FIG. 1 , and as described above, according to some embodiments of the present disclosure, the output(s) 250a of the other circuit 250 can be received at the input(s) of the LF offset cancellation circuit 220. Also as shown in the measurement circuit 3800, the output(s) 220a of the LF offset cancellation circuit 220 can also be received at the input(s) of the other circuit 250. According to some embodiments of the present disclosure, this implementation allows for additional characterization of the input signal(s) 200a. In some embodiments, the characterization and / or flow of the signal(s) (e.g., the output(s) 250a from the other circuit 250 and / or the output(s) 220a from the LF offset cancellation circuit 220) is controlled or determined in response to the control signal 240a received by the control circuit 240.

[0094] It will be appreciated that the above-described further example measurement circuits are but a few of many possible additional and alternative configurations of the systems and methods disclosed herein.

[0095] As shown in the present disclosure, in one aspect, the systems and methods disclosed herein propose using a class of filters known as CIC filters to remove LF and DC from a digital data stream. By routing the input digital data stream from an ADC through one or more CIC decimation filter stages and then subtracting the resulting filtered waveform from the input digital data, a highly economical and effective DC / LF offset removal method can be achieved.

[0096] It should be understood that the concepts, systems, circuits, and techniques sought to be protected herein are not limited to use in the example applications described herein (e.g., metering applications), but may be useful in virtually any application (e.g., protection relays) where it is desired to remove low-frequency offset components from a digital data stream. For example, it is well known that protection of AC power systems (e.g., by protection relays) relies on accurate measurement of power system voltages and currents; typically via transducers, and the signals are converted to the digital domain via an accurate sampling system. Most protection algorithms rely on the extraction of power system frequency signals and higher harmonic components. The presence of a DC component in the collected sampled data can cause errors in the measurements used for protection and compromise the accuracy and selectivity of the protection function. This DC component can be introduced into the relay analog acquisition circuitry for typical numerical protection relays. Using (multiple) CIC filters to subtract the DC component from the collected samples will reduce the source of error in the data used to protect the power system; this will improve the accuracy and performance of the protection function.

[0097] While specific embodiments and applications of the present disclosure have been illustrated and described, it should be understood that the embodiments of the present disclosure are not limited to the precise construction and composition disclosed herein, and that various modifications, changes and variations may be apparent from the foregoing description without departing from the spirit and scope of the disclosure as defined in the appended claims.

[0098] While preferred embodiments have been described to illustrate the various concepts, structures, and techniques that are the subject of this patent, it will now be apparent to those skilled in the art that other embodiments incorporating these concepts, structures, and techniques may be used. Furthermore, elements of the various embodiments described herein may be combined to form other embodiments not specifically described above.

[0099] Accordingly, it is intended that the scope of this patent should not be limited to the described embodiments, but should be limited only by the spirit and scope of the appended claims.

Claims

1. A method for eliminating a low frequency offset component from a digital data stream, the method comprising: receiving an analog input signal from one or more analog front-end components at an input of an analog-to-digital converter (ADC), the analog input signal having an associated low frequency offset due at least in part to the analog front-end components; generating a digital data stream representative of the analog input signal at an output of the ADC, the digital data stream having an associated low frequency offset due at least in part to the analog front end components and the ADC; applying one or more low-pass finite impulse response (FIR) filters to the digital data stream to detect the low-frequency offset component in the digital data stream and generate a filtered output signal containing only the low-frequency offset component; controlling, at an output of the ADC, a first path of the digital data to flow to the one or more low-pass finite impulse response (FIR) filters and a second path of the digital data to flow to one or more other circuits configured to capture information associated with the analog input signal; as well as A difference between the digital data stream and the filtered output signal is taken to generate a corrected digital data stream without the low frequency offset component.

2. The method of claim 1, wherein the low-frequency offset component eliminated from the digital data stream comprises a direct current (DC) offset component. 3 . The method of claim 1 , wherein the one or more low-pass FIR filters comprise at least one cascaded integrator-comb (CIC) filter. The method of claim 1 , wherein the one or more low-pass FIR filters include at least one recursive moving average filter.

5. The method of claim 4, wherein the at least one recursive moving average filter comprises at least one cascaded integrator-comb (CIC) filter. The method of claim 1 , wherein the analog front end component comprises at least one active electrical component. The method of claim 1 , wherein the analog front end component comprises at least one passive electrical component. The method of claim 1 , wherein the analog front end component is coupled to a signal source.

9. The method according to claim 1, further comprising: The corrected digital data stream is provided to one or more systems or devices for further processing.

10. The method of claim 1, wherein the method is implemented in a measurement circuit. The method according to claim 10 , wherein the measuring circuit is a measuring circuit used in a metering device.

12. The method according to claim 11, wherein the metering device is a metering device used in an electric power system.

13. A measurement circuit capable of eliminating a low-frequency offset component from a digital data stream, the measurement circuit comprising: an analog-to-digital converter (ADC) coupled to receive an analog input signal from one or more analog front-end components and configured to generate a digital data stream representative of the analog input signal, the analog input signal having an associated low frequency offset at least in part due to the analog front-end components, and the digital data stream having an associated low frequency offset at least in part due to the analog front-end components and the ADC; a control circuit coupled to an output of the ADC, configured to control a first path of the digital data flow to an input of the one or more low-pass finite impulse response (FIR) filters, and further configured to control a second path of the digital data flow to an input of one or more other circuits configured to capture information associated with the analog input signal; as well as A low-frequency offset cancellation circuit comprising one or more low-pass finite impulse response (FIR) filters and one or more summing circuits, wherein the low-pass FIR filter is coupled to receive the digital data stream in the first path from the ADC and is configured to process the digital data stream to detect a low-frequency offset component in the digital data stream and generate a filtered output signal containing only the low-frequency offset component, and wherein the summing circuit is coupled to receive the filtered output signal and the digital data stream and is configured to obtain a difference between the digital data stream and the filtered output signal to generate a corrected digital data stream without the low-frequency offset component.

14. The measurement circuit of claim 13, wherein the low-frequency offset component eliminated from the digital data stream comprises a direct current (DC) offset component.

15. The measurement circuit of claim 13, wherein the one or more low-pass FIR filters include at least one cascaded integrator-comb (CIC) filter.

16. The measurement circuit of claim 13, wherein the one or more low-pass FIR filters include at least one recursive moving average filter.

17. The measurement circuit of claim 16, wherein the at least one recursive moving average filter comprises at least one cascaded integrator-comb (CIC) filter.

18. The measurement circuit of claim 13, wherein the measurement circuit is configured to provide the corrected digital data stream to one or more systems or devices for further processing.

19. The measurement circuit according to claim 13, wherein the measurement circuit is a measurement circuit used in a metering device.

20. The measurement circuit of claim 19, wherein the metering device is a metering device used in an electric power system.

Images