Encapsulation Structure and Method for Forming the Same

Abstract

The present disclosure relates to a packaging structure and a method of forming the same. The method includes disposing a semiconductor die on a first surface of a redistribution structure. The method further includes forming a first protective layer to surround a portion of the semiconductor die. The method further includes disposing a device element on a second surface of the redistribution structure. The redistribution structure is interposed between the device element and the semiconductor die. In addition, the method includes forming a second protective layer to surround a portion of the device element. The second protective layer is thicker than the first protective layer, and the second protective layer has a different coefficient of thermal expansion from the first protective layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a packaging structure and a method of forming the same, and particularly to a packaging structure having a fan-out component and a method of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Continuous progress in semiconductor manufacturing processes has led to semiconductor devices with finer components and / or higher integration levels. The functional density (i.e., the number of interconnect devices per unit chip area) has generally increased, while the feature size (i.e., the smallest component that can be produced using a manufacturing process) has decreased. This miniaturization process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] Chip packaging not only provides protection for semiconductor devices from environmental pollution, but also provides a connection interface for the semiconductor devices encapsulated therein. Smaller packaging structures using less area or lower height have been developed to package semiconductor devices.

[0004] New packaging technologies have been developed to further increase the density and functionality of semiconductor dies. These relatively novel semiconductor die packaging technologies face some manufacturing challenges. Summary of the Invention

[0005] Embodiments of the present invention provide a method of forming a packaging structure. The method includes disposing a semiconductor die on a first surface of a redistribution structure. The method further includes forming a first protective layer to surround at least a portion of the semiconductor die. The method further includes disposing device elements on a second surface of the redistribution structure. The redistribution structure is interposed between the device elements and the semiconductor die. In addition, the method also includes forming a second protective layer to surround at least a portion of the device elements. The second protective layer is thicker than the first protective layer, and the second protective layer and the first protective layer have different thermal expansion coefficients.

[0006] Embodiments of the present invention provide a method of forming a packaging structure. The method includes disposing device elements on a first surface of a redistribution structure. The method also includes forming a first protective layer to surround at least a portion of the device elements. The method also includes disposing a semiconductor die on a second surface of the redistribution structure. The redistribution structure is interposed between the device elements and the semiconductor die. In addition, the method also includes forming a second protective layer to surround at least a portion of the semiconductor die. The second protective layer is thinner than the first protective layer, and the second protective layer and the first protective layer are formed of different materials.

[0007] Embodiments of the present invention provide a packaging structure, which includes a redistribution structure. The packaging structure also includes a semiconductor die and device elements located on opposite surfaces of the redistribution structure. The packaging structure also includes a first protective layer at least partially surrounding the semiconductor die. In addition, the packaging structure also includes a second protective layer at least partially surrounding the device elements. Description of the Drawings

[0008] The content of the embodiments of the present invention can be better understood through the following detailed description in conjunction with the accompanying drawings of the specification. It should be emphasized that, according to industry standard practices, many components (features) are for illustrative purposes only and are not drawn to scale. In fact, for the sake of clear discussion, the dimensions of various components may be arbitrarily increased or decreased.

[0009] Figures 1A - 1R is a cross-sectional schematic view showing various stages of a process for forming a packaging structure according to some embodiments.

[0010] Figures 2A - 2B is a cross-sectional schematic view showing various stages of a process for forming a packaging structure according to some embodiments.

[0011] Figures 3A - 3B is a cross-sectional schematic view showing various stages of a process for forming a packaging structure according to some embodiments.

[0012] Figure 4 is a cross-sectional schematic view of a packaging structure according to some embodiments.

[0013] Figures 5A - 5E is a cross-sectional schematic view showing various stages of a process for forming a packaging structure according to some embodiments.

[0014] Figure 6 is a cross-sectional schematic view of a packaging structure according to some embodiments.

[0015] Figures 7A - 7L is a cross-sectional schematic view showing various stages of a process for forming a packaging structure according to some embodiments.

[0016] Figures 8A - 8B is a cross-sectional schematic view showing various stages of a process for forming a packaging structure according to some embodiments.

[0017] Figure 9 is a top view layout schematic view of an intermediate stage of a process for forming a packaging structure according to some embodiments.

[0018] Figure 10 is a cross-sectional schematic view of a packaging structure according to some embodiments.

[0019] Description of the Reference Numerals:

[0020] 100: Carrier Substrate

[0021] 101: Tape

[0022] 102: Redistribution Structure

[0023] 104: Insulating Layer

[0024] 105: Conductive Component

[0025] 106a: Conductive Component

[0026] 106b: Conductive Component

[0027] 108: Conductive Component

[0028] 110: Conductive Bump

[0029] 110S: Surface

[0030] 112: Device Element

[0031] 114: Conductive Structure

[0032] 116: Semiconductor Die

[0033] 118: Conductive Component

[0034] 120: Reinforcing Element

[0035] 120’: Reinforcing Element

[0036] 122: Supplier

[0037] 124: Containing Polymer Material

[0038] 126: Protective Layer

[0039] 128: Adhesive Layer

[0040] 130: Carrier Substrate

[0041] 132: Energy Beam

[0042] 134: Solder Element

[0043] 136A: Device Element

[0044] 136B: Device Element

[0045] 136C: Device Element

[0046] 138a: Electrode

[0047] 138b: Electrode

[0048] 140: Protective Layer

[0049] 142: Frame Carrier

[0050] 144: Solder element

[0051] 145: Conductive bump

[0052] 148: Conductive pad

[0053] 146: Board

[0054] 344: Solder element

[0055] 346: Conductive bump

[0056] 520: Reinforcing element

[0057] 520S: Surface

[0058] 700: Carrier substrate

[0059] 701: Tape

[0060] 702: Redistribution structure

[0061] 704: Insulating layer

[0062] 706a: Conductive component

[0063] 706b: Conductive component

[0064] 708: Conductive component

[0065] 710: Solder element

[0066] 712A: Device element

[0067] 712B: Device element

[0068] 712C: Device element

[0069] 714a: Electrode

[0070] 714b: Electrode

[0071] 716: Protective layer

[0072] 718: Adhesive layer

[0073] 720: Carrier substrate

[0074] 722: Conductive bump

[0075] 722S: Surface

[0076] 724: Device element

[0077] 726: Solder element

[0078] 728: Semiconductor die

[0079] 730: Conductive component

[0080] 732: Reinforcing element

[0081] 734: Supplier

[0082] 736 Polymer material

[0083] 738: Protective layer

[0084] 740: Solder element

[0085] 742: Conductive bump

[0086] 744: Frame carrier

[0087] h 1 : Thickness

[0088] h 1 ’: Thickness

[0089] h 2 : Thickness

[0090] h 2 ’: Thickness

[0091] h 3 : Thickness

[0092] h 3 ’: Thickness

[0093] W 1 : Width

[0094] W 2 : Width Detailed implementation manners

[0095] The following provides multiple different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, when it is mentioned in the description that the first component is formed on or above the second component, it may include embodiments where the first and second components are in direct contact, or it may also include embodiments where additional components are provided between the first and second components such that the first and second components are not in direct contact. Additionally, the embodiments of the present invention may repeat element symbols and / or letters in many examples. These repetitions are for the purpose of simplification and clarity, and they do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0096] In addition, spatially relative terms may be used herein, such as "under", "below", "lower", "above", "upper", and other similar terms, to describe the relationship between one element or component and other elements or components as shown in the figures. Such spatially relative terms include not only the orientation shown in the drawings but also different orientations of the device during use or operation. When the device is rotated to other orientations (rotated 90 degrees or other orientations), the spatially relative descriptions used herein can be interpreted accordingly with respect to the rotated orientation.

[0097] In the description, terms such as "substantially", for example, "substantially flat" or "substantially coplanar", will be understood by those of ordinary skill in the art. In some embodiments, the adjective "substantially" is removed. Where applicable, the term "substantially" may also include embodiments with "entirely", "completely", "all", etc. Where applicable, the term "substantially" may also refer to 90% or more, such as 95% or more, especially 99% or more, or including 100%. Furthermore, the terms "substantially parallel" or "substantially perpendicular" are interpreted as not excluding minor deviations from a particular alignment and may include, for example, deviations up to 10°. The term "substantially" does not exclude "completely". For example, a composition that is "substantially free" of Y may be completely free of Y.

[0098] Terms such as "about", when used in connection with a particular distance or dimension, are interpreted as not excluding minor deviations from the particular distance or dimension and may include, for example, deviations up to 10°. The relationship of the term "about" to a numerical value x may represent x ± 5 or 10%.

[0099] Some embodiments are disclosed herein. Additional steps may be provided before, during, or after the stages mentioned in these embodiments. For different embodiments, some of the described stages may be replaced or omitted. Additional components may be added to the encapsulation structure. For different embodiments, some of the components described below may be replaced or omitted. Although some embodiments are discussed in terms of steps in a particular order, these steps may be performed in other logical orders.

[0100] Embodiments of the present disclosure may relate to three-dimensional (3D) packaging or three-dimensional integrated circuit (3D-IC) devices. Other components or processes may also be included. For example, test structures may be included to assist in the verification testing of 3D packaging or 3D-IC devices. Test structures may be included, for example, testing pads formed on a redistribution layer or a substrate, which enable 3D packaging or 3D-IC to be tested, probes or probe cards to be used, and so on. Verification testing may be performed on intermediate structures and final structures. Additionally, the structures and methods disclosed herein may be used in combination with a testing methodology that incorporates intermediate verification of identifying good dies to improve yield and reduce costs.

[0101] Figures 1A - 1R is a cross-sectional schematic diagram showing various stages of a process for forming a packaging structure according to some embodiments. According to some embodiments, as Figure 1A shown, a redistribution structure 102 is formed on a carrier substrate 100. The carrier substrate 100 may be a glass substrate, a semiconductor substrate, or other suitable substrate.

[0102] In some embodiments, an adhesive tape 101 is formed on the carrier substrate 100 before forming the redistribution structure 102. In some embodiments, the adhesive tape 101 is sensitive to energy beam irradiation. In some embodiments, the adhesive tape 101 is a release layer comprising or formed of a light-to-heat conversion (LTHC) material. For example, the adhesive tape 101 is irradiated with a laser. The irradiation can separate the redistribution structure 102 from the carrier substrate 100.

[0103] The redistribution structure 102 is used for routing, which enables the formation of a packaging structure having fan-out components. In some embodiments, the redistribution structure 102 includes a plurality of insulating layers 104 and a plurality of conductive components, such as conductive components 105, 106a, and 106b. The conductive components 105, 106a, and 106b are surrounded by the insulating layers 104. The conductive components 105, 106a, and 106b may include conductive lines, conductive vias, and / or conductive pads.

[0104] The redistribution structure 102 also includes conductive components 108 for holding or receiving other components. In some embodiments, the conductive components 108 are exposed at the topmost surface of the insulating layer 104 or protrude from the topmost surface of the insulating layer 104. The conductive components 108 can be used to hold or receive one or more semiconductor dies and / or one or more passive components. The conductive components 108 can also be used to hold or receive conductive components, such as conductive pillars, and / or conductive bumps.

[0105] The insulating layer 104 can comprise or be formed of one or more polymer materials. The polymer materials can include polybenzoxazole (PBO), polyimide (PI), epoxy-based resin, one or more other suitable polymer materials, or a combination of the foregoing. In some embodiments, the polymer materials are photosensitive. Accordingly, a photolithography process is used to form openings having a desired pattern in the insulating layer 104.

[0106] In some embodiments, some or all of the insulating layer 104 can comprise or be formed of a dielectric material other than a polymer material. The dielectric material can include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more other suitable materials, or a combination of the foregoing.

[0107] The conductive components 105, 106a, 106b, and 108 can include wires providing electrical connections in a horizontal direction and vias providing electrical connections in a vertical direction. In some embodiments, some of the vias are stacked on top of each other. The higher vias are generally aligned with the lower vias. In some embodiments, some of the vias are staggered vias. The higher vias are not aligned with the lower vias.

[0108] The conductive components 105, 106a, 106b, and 108 can comprise or be formed of copper, aluminum, gold, cobalt, titanium, nickel, silver, graphene, one or more other suitable conductive materials, or a combination of the foregoing. In some embodiments, the conductive components 105, 106a, 106b, and 108 include multiple sub-layers. For example, each of the conductive components 105, 106a, 106b, and 108 contains multiple sub-layers, which include titanium / copper (Ti / Cu), titanium / nickel / copper (Ti / Ni / Cu), titanium / copper / titanium (Ti / Cu / Ti), aluminum / titanium / nickel / silver (Al / Ti / Ni / Ag), other suitable sub-layers, or a combination of the foregoing.

[0109] The formation of the redistribution structure 102 can involve multiple deposition or coating processes, multiple patterning processes, and / or multiple planarization processes.

[0110] A deposition or coating process can be used to form an insulating layer and / or a conductive layer. The deposition or coating process can include a spin-on coating process, an electroplating process, an electroless process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, one or more other suitable processes, or a combination of the foregoing.

[0111] A patterning process can be used to pattern the formed insulating layer and / or the formed conductive layer. The patterning process can include a photolithography process, an energy beam drilling process (e.g., a laser beam drilling process, an ion beam drilling process, or an electron beam drilling process), an etching process, a mechanical drilling process, one or more other suitable processes, or a combination of the foregoing.

[0112] A planarization process can be used to provide the formed insulating layer and / or the formed conductive layer with a flat top surface to facilitate subsequent processes. The planarization process can provide a mechanical grinding process, a chemical mechanical polish (CMP) process, a dry grinding process, one or more other suitable processes, or a combination of the foregoing.

[0113] According to some embodiments, as Figure 1B shown, conductive bumps 110 and device elements 112 are formed on some conductive components 108. In some embodiments, the conductive bumps 110 are tin-containing solder bumps. The tin-containing solder bumps can further include copper, silver, gold, aluminum, lead, one or more other suitable materials, or a combination of the foregoing. In some other embodiments, the conductive bumps 110 are lead-free. In some other embodiments, the conductive bumps 110 are solder balls.

[0114] In some embodiments, the device element 112 is bonded to the conductive component 108 through the conductive structure 114. The conductive structure 114 may include solder bumps, conductive pillars, many other suitable bonding structures, or a combination of the foregoing. The device element 112 may include one or more passive components, such as resistors, capacitors, inductors, one or more other suitable components, or a combination of the foregoing. In some other embodiments, the device element 112 includes a memory device. In some embodiments, the device element 112 includes an electrode, and the electrode is bonded to the pad region (i.e., some conductive components 108) of the redistribution structure 102 through the conductive structure 114.

[0115] In some embodiments, before forming or stacking the conductive bumps 110 and the device element 112, a flux material is dispersed onto the conductive component 108. In some embodiments, a thermal reflow step is then performed to fix the conductive bumps 110 and the device element 112 to the redistribution structure 102.

[0116] According to some embodiments, as Figure 1C shown, semiconductor dies 116 are stacked on top of the redistribution structure 102. The semiconductor dies 116 may include an application processor, a power management integrated circuit, a memory device, one or more other suitable circuits, or a combination of the foregoing. In some embodiments, each device element 112 may be thinner than the semiconductor die 116.

[0117] In some embodiments, the semiconductor die 116 is bonded to some of the conductive components 108 through the conductive components 118 of the semiconductor die 116. The conductive components 118 may include conductive pillars, solder elements, one or more other suitable bonding structures, or a combination of the foregoing. For example, each conductive component 118 includes a combination of a metal pillar and a tin-containing solder element. In some embodiments, an underfill material is formed to surround and protect the conductive components 118 and the conductive structure 114. In some other embodiments, no underfill material is formed.

[0118] According to some embodiments, as Figure 1D shown, a stiffener element 120 is formed on top of the redistribution structure 102. The stiffener element 120 can be used to control and / or reduce the warpage of the package structure during subsequent forming processes. In some embodiments, the stiffener element 120 is a stiffener ring surrounding the semiconductor die 116 and the conductive bumps 110.

[0119] Figure 9is a top - view layout schematic showing an intermediate stage of a process for forming a packaging structure. In some embodiments, Figure 9 is a top - view layout schematic showing the reinforcing element 120 and other adjacent elements. In some embodiments, the reinforcing element 120 continuously surrounds the conductive bumps 110, the device element 112, and the semiconductor die 116, as Figure 9 shown.

[0120] The reinforcing element 120 may be formed of or include an insulating material (e.g., a polymer material), a semiconductor material, a metal material, one or more other suitable materials, or a combination of the foregoing. In some embodiments, the reinforcing element 120 is formed of a polymer material similar to a molding compound material or an underfill material, such as an epoxy - based resin. In some cases, a dispensing operation may be used to form the reinforcing element 120.

[0121] According to some embodiments, as Figure 1D shown, a dispenser 122 is used to disperse a polymer material 124 onto the redistribution structure 102. The dispenser 122 can move around the semiconductor die 116 and the conductive bumps 110 while dispersing the polymer material 124. As a result, the dispersed polymer material 124 forms the reinforcing element 120. In some embodiments, the reinforcing element 120 is a reinforcing ring surrounding the semiconductor die 116 and the conductive bumps 110.

[0122] In some other embodiments, the reinforcing element 120 is formed of a semiconductor material (e.g., silicon) or a metal material (e.g., aluminum). In some embodiments, the reinforcing element 120 is a semiconductor frame or a metal frame. A glue material can be used to attach the semiconductor frame or the metal frame to the redistribution structure 102.

[0123] According to some embodiments, as Figure 1E shown, a protective layer 126 is formed over the redistribution structure 102 to surround and protect the semiconductor die 116. The protective layer 126 may further cover and protect the device element 112, the conductive bumps 110, and the reinforcing element 120.

[0124] In some embodiments, the protective layer 126 is formed of or includes an insulating material, such as a molding material. The molding material may include a polymer material, such as an epoxy - based resin with one or more fillers dispersed therein. The fillers may include insulating particles, insulating fibers, one or more other elements, or a combination of the foregoing. For example, the fillers include silica particles, carbon - containing particles, carbon - containing fibers, or a combination of the foregoing.

[0125] In some embodiments, molding material (e.g., liquid molding material) is introduced or injected onto the redistribution structure 102. In some embodiments, a thermal process is then used to cure the liquid molding material and transform it into the protective layer 126.

[0126] According to some embodiments, as Figure 1F shown, the protective layer 126 is planarized to reduce the thickness of the protective layer 126. In some embodiments, the protective layer 126 is planarized to expose the semiconductor die 116. In some embodiments, during the planarization of the protective layer 126, an upper portion of the conductive bump 110 is partially removed. As a result, a surface 110S of the conductive bump 110 is formed, as Figure 1F shown. In some embodiments, the surface 110S is a substantially flat surface. In some embodiments, the surface 110S is substantially flush with the top surface of the protective layer 126. The planarization of the protective layer 126 can be performed using a mechanical grinding process, a chemical mechanical polishing (CMP) process, a dry grinding process, one or more other suitable processes, or a combination of the foregoing.

[0127] As Figure 1F shown, after the planarization process, the protective layer 126 has a thickness h 1 , while the semiconductor die 116 has a thickness h 2 . The thickness h 1 is substantially equal to the thickness h 2 .

[0128] According to some embodiments, as Figure 1G shown, the carrier substrate 130 is attached to the Figure 1F shown structure using the adhesive layer 128. The carrier substrate 130 can be a glass substrate, a semiconductor substrate, or other suitable substrate. The material of the adhesive layer 128 can be a tape of a material different from that of the tape 101.

[0129] According to some embodiments, as Figure 1H shown, the Figure 1G shown structure is flipped upside down and irradiated with an energy beam 132. The energy beam 132 can be a laser, ultraviolet light, or other suitable energy beam. After irradiation with the energy beam 132, the adhesiveness of the tape 101 may be destroyed or reduced. As described above, the tape 101 and the tape 128 are formed of different materials. For example, the adhesive layer 128 is formed of an adhesive material other than a light-to-thermal conversion (LTHC) material. The adhesive layer 128 can maintain its adhesiveness even after irradiation with the energy beam 132.

[0130] According to some embodiments, as Figure 1IAs shown, the tape 101 and the carrier substrate 100 are removed to expose the redistribution structure 102. According to some embodiments, thereafter, a portion of the insulating layer 104 is removed to expose the conductive component 105, such as Figure 1J shown. For example, using a planarization process or an etching process, the topmost layer of the insulating layer 104 is removed.

[0131] According to some embodiments, such as Figure 1K shown, a solder element 134 is formed on the conductive component 105. The solder element 134 may comprise or be formed of a tin-containing solder material. For example, the solder element 134 is a solder paste. The tin-containing solder material may further comprise copper, silver, gold, aluminum, lead, one or more other suitable materials, or a combination of the foregoing. In some other embodiments, the solder element 134 is lead-free. A printing process, a dispensing process, an application process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination of the foregoing may be used to form the solder element 134.

[0132] According to some embodiments, such as Figure 1L shown, the device elements 136A, 136B, and 136C are bonded to the conductive element 105 through the solder element 134. In some embodiments, each of the device elements 136A, 136B, and 136C comprises one or more passive elements, such as resistors, capacitors, inductors, one or more other suitable elements, or a combination of the foregoing. In some other embodiments, one or some of the device elements 136A, 136B, and 136C comprise memory devices. In some embodiments, each of the device elements 136A, 136B, and 136C comprises electrodes 138a and 138b. In some embodiments, the electrodes 138a and 138b of the device elements 136A, 136B, and 136C are bonded to the pad regions (e.g., the conductive component 105) of the redistribution structure 102 through the solder element 134.

[0133] The device elements 136A, 136B, and 136C may have different thicknesses. In some embodiments, the device elements 136A, 136B, and 136C are thicker than the semiconductor die 116. In some embodiments, the semiconductor die 116 is wider than the device elements 136A, 136B, or 136C.

[0134] According to some embodiments, such as Figure 1MAs shown, a protective layer 140 is formed over the redistribution structure 102 to surround and cover the device elements 136A, 136B, and 136C. In some embodiments, the protective layer 140 is formed of a different material than the protective layer 126. In some embodiments, the protective layer 140 comprises or is formed of an insulating material, such as a molding material. The molding material may comprise a polymeric material, such as an epoxy resin with one or more fillers dispersed therein. The fillers may comprise insulating particles, insulating fibers, one or more other elements, or a combination of the foregoing. For example, the fillers comprise silica particles, carbon-containing particles, carbon-containing fibers, or a combination of the foregoing.

[0135] In some embodiments, a molding material (e.g., a liquid molding material) is introduced or injected onto the redistribution structure 102. In some embodiments, a thermal process is then used to cure the liquid molding material and transform it into the protective layer 140. A planarization process may then be performed to provide the protective layer 140 with a substantially flat top surface.

[0136] As Figure 1M shown, the protective layer 140 has a thickness h 3 . In some embodiments, the thickness h 3 is greater than the thickness h 1 of the protective layer 126. Since the semiconductor die 116 is thinner than the device elements 136A, 136B, 136C, the protective layer 126, which is thinner than the protective layer 140, is sufficient to surround and protect the semiconductor die 116. By the thinner protective layer 126, the total thickness of the package structure is further reduced, which meets the requirement of producing a thinner and smaller package structure.

[0137] In some embodiments, the protective layers 126 and 140 have different coefficients of thermal expansion. In some embodiments, the coefficient of thermal expansion of the protective layer 126 is higher than that of the protective layer 140. The thinner protective layer 126 with a higher coefficient of thermal expansion can compensate for the expansion of the thicker protective layer 140 with a lower coefficient of thermal expansion. Thus, warpage that occurs during or after subsequent manufacturing processes of the package structure can be reduced. The quality and reliability of the package structure are improved.

[0138] When below the glass transition temperature (Tg) of the protective layer 126, the protective layer 126 may have a first coefficient of thermal expansion (CET1). When below the glass transition temperature of the protective layer 126, the protective layer 126 may have a second coefficient of thermal expansion (CET2). Similarly, when below or above the glass transition temperature of the protective layer 140, the protective layer 140 may also have a first coefficient of thermal expansion (CET1') and a second coefficient of thermal expansion (CET2'), respectively.

[0139] In some embodiments, the ratio (CTE1’ / CTE1) of the first coefficient of thermal expansion (CET1’) of the protective layer 140 to the first coefficient of thermal expansion (CET1) of the protective layer 126 ranges from about 0.8 to about 0.95. In some embodiments, the ratio (CTE1’ / CTE1) of the second coefficient of thermal expansion (CET2’) of the protective layer 140 to the second coefficient of thermal expansion (CET2) of the protective layer 126 ranges from about 0.1 to about 0.7.

[0140] As previously described, each of the protective layer 126 and the protective layer 140 may include a filler dispersed in a polymer-based material. In some embodiments, the weight percentage of the filler in the protective layer 140 is higher than the weight percentage of the filler in the protective layer 126. In some embodiments, by adjusting the quantity, size, and / or material of the filler within the protective layers 126 and 140, the corresponding coefficients of thermal expansion can be finely tuned. The chain length, functional groups, and / or average molecular weight of the polymer-based material can also be adjusted to finely tune the corresponding coefficients of thermal expansion.

[0141] According to some embodiments, as Figure 1N shown, flip the structure shown Figure 1M upside down and attach it to the frame carrier 142. Thereafter, the carrier substrate 130 is removed to expose the adhesive layer 128.

[0142] According to some embodiments, as Figure 1O shown, the adhesive layer 128 is removed to expose the surface 110S of the conductive bump 110 and the protective layer 126. The adhesive layer 128 can be removed using a back-etching process. The etchant used in the back-etching process can also etch the protective layer 126 to reduce the thickness of the protective layer 126. As a result, a portion of the conductive bump 110 protrudes from the top surface of the protective layer 126. In some embodiments, a portion of the semiconductor die 116 also protrudes from the top surface of the protective layer 126. In some embodiments, the back-etching process is a dry etching process.

[0143] As Figure 1O shown, the protective layer 126 is slightly thinned to a thickness h 1 ’. The thickness h 2 of the semiconductor die 116 is thicker than the thickness h 1 ’. The ratio of the thickness h 1 ’ to the thickness h 2 (h 1 ’ / h 2 ) can range from about 0.8 to about 0.95.

[0144] However, the embodiments of the present invention are not limited thereto. Many variations and / or modifications can be made to the embodiments of the present invention. In some other embodiments, the back-etching process for removing the adhesive layer 128 is a wet etching process. In some embodiments, the protective layer 126 is substantially not back-etched by the wet etching process. In these cases, the semiconductor die 116 can be substantially as thick as the protective layer 126. In some embodiments, the top surfaces of the semiconductor die 116, the protective layer 126, and the conductive bumps 110 are substantially flush with each other.

[0145] According to some embodiments, as Figure 1P shown, a solder element 144 is formed on top of the conductive bump 110, which is exposed after the carrier substrate 130 and the adhesive layer 128 are removed. In some embodiments, the solder element 144 is formed directly above the surface 110S of the conductive bump 110.

[0146] The solder element 144 can be formed of a tin-containing solder material. The tin-containing solder material can further include copper, silver, gold, aluminum, lead, one or more other suitable materials, or a combination of the foregoing. In some other embodiments, the solder element 144 is lead-free. In some embodiments, a thermal reflow process is used to reflow the solder element 144 with the conductive bump 110 below it. As a result, the conductive bump 145 is formed.

[0147] In some embodiments, each conductive bump 145 has a lower portion surrounded by the protective layer 126, as Figure 1P shown. Each conductive bump 145 has an upper portion protruding from the top surface of the protective layer 126. In some embodiments, the sidewall surface of the upper portion of the conductive bump 145 is curved outward. In some embodiments, the upper portion of the conductive bump 145 extends across the edge of the interface between the upper and lower portions of the conductive bump 145. In some embodiments, the conductive bump 145 has a gourd-like profile, as Figure 1P shown.

[0148] After that, using a saw step, the Figure 1P shown structure is cut into a plurality of separate package structures. Figure 1Q A cross-sectional schematic diagram showing one of the resulting package structures removed from the frame carrier 142.

[0149] According to some embodiments, as Figure 1R shown, the package structure is bonded to the board 146. A thermal reflow process can be used to form a bond between the conductive bump 145 and the conductive pad 148 on the board 146. The board 146 can be a printed circuit board, an interposer board, or other suitable substrate.

[0150] Many variations and modifications can be made to the embodiments of the present invention. Figures 2A - 2B It is a cross-sectional schematic diagram showing various stages of a process for forming a packaging structure according to some embodiments. As Figure 2A shown, similar to the embodiment shown in Figure 1F , the protective layer 126 is planarized. The planarization process reduces the thickness of the protective layer 126 to a thickness h 1 . The planarization process also partially removes the conductive bumps 110. However, a portion of the protective layer 126 remains on top of the semiconductor die 116. In these cases, the semiconductor die 116 with a thickness h 2 ' is covered by the protective layer 126 and not exposed.

[0151] According to some embodiments, afterwards, similar steps as those described in Embodiments 1G - 1Q are performed to form a packaging structure, as Figure 2B shown.

[0152] Many variations and modifications can be made to the embodiments of the present invention. Figures 3A - 3B It is a cross-sectional schematic diagram showing various stages of a process for forming a packaging structure according to some embodiments.

[0153] As Figure 3A shown, a structure is received or formed, which is similar to the structure shown in Figure 1O . According to some embodiments, afterwards, the solder elements 344 are dispersed or disposed on the surface 110S of the conductive bumps 110. The material of the solder elements 344 can be the same as or similar to the material of the solder elements 144. Each solder element 344 can have a smaller volume. As Figure 3A shown, the solder element 344 has a width W 2 , while the surface 110S of the conductive bump 110 has a width W 1 . In some embodiments, the width W 1 is wider than the width W 2 . In some embodiments, the solder element 344 is a tin-containing solder paste. By controlling the dispensing amount of the solder paste, the size of the solder element 344 can be fine-tuned accordingly.

[0154] According to some embodiments, afterwards, a thermal reflow process is used to reflow the solder elements 344 and the conductive bumps 110. As a result, the conductive bumps 346 are formed. In these cases, the conductive bumps 346 have a spherical profile. Afterwards, similar to the embodiment described in Figure 1Q , a cutting step is used to form a plurality of packaging structures separated from each other. Figure 3B It is a cross-sectional schematic diagram showing one of these packaging structures taken out from the frame carrier 142.

[0155] In some embodiments, a strengthening element 120 is used to further reduce or control the warping of the package structure during or after the manufacturing process. However, embodiments of the present invention are not limited thereto. Many variations and modifications can be made to the embodiments of the present invention. Figure 4 is a cross-sectional schematic view of a package structure according to some embodiments. In some embodiments, the strengthening element 120 is not formed.

[0156] Many variations and modifications can be made to the embodiments of the present invention. Figures 5A - 5E is a cross-sectional schematic view showing various stages of a process of forming a package structure according to some embodiments.

[0157] As Figure 5A shown, a structure is received or formed, which is similar to the structure Figure 1C shown. According to some embodiments, afterwards, similar to the embodiment Figure 1D shown, a strengthening element 520 is formed, as Figure 5B shown. In some embodiments, unlike the strengthening element 120, the strengthening element 520 is formed to have a greater height. For example, the level of the top end of the strengthening element 520 is higher than the top surface of the device element 112. In some embodiments, the strengthening element 520 surrounds the semiconductor die 116, the conductive bumps 110, and the device element 112.

[0158] According to some embodiments, as Figure 5C shown, similar to the embodiment Figure 1E shown, a protective layer 126 is formed to cover the semiconductor die 116, the conductive bumps 110, and the strengthening element 520.

[0159] According to some embodiments, afterwards, similar to the embodiment Figure 1F shown, the protective layer 126 is planarized, as Figure 5D shown. During the planarization, part of the conductive bumps 110 is removed to form a surface 110S. Also part of the strengthening element 520 is removed to form a surface 520S. In some implementations, the surface 520S is substantially flat. In some embodiments, the surface 520S is flush with the surface 110S of the conductive bumps 110 and / or the top surface of the protective layer 126.

[0160] According to some embodiments, afterwards, a process similar to that shown in 1G-1Q is performed. As a result, a package structure is obtained, as Figure 5E shown.

[0161] Many variations and modifications can be made to the embodiments of the present invention. Figure 6 is a cross-sectional schematic view of a package structure according to some embodiments. In some embodiments, a protective layer 140 is formed to have a thickness h 3 ’. The thickness h 3' greater than the thickness h of the protective layer 126 1 '. In some embodiments, the protective layer 140 is formed to be thinner than one (or more) of the device elements 136A, 136B, and 136C. For example, the device element 136B is taller than the protective layer 140. The device element 136B protrudes from the top surface of the protective layer 140, as Figure 6 shown.

[0162] Many variations and modifications can be made to the embodiments of the present invention. Figures 7A - 7L is a cross-sectional schematic view showing various stages of a process for forming a package structure according to some embodiments.

[0163] According to some embodiments, as Figure 7A shown, a redistribution structure 702 is formed on a tape 701, and the tape 701 is attached to a carrier substrate 700. Similar to the redistribution structure 102 as Figure 1A shown, the redistribution structure 702 includes a plurality of insulating layers 704 and a plurality of conductive components 706a, 706b, and 708. The materials and formation methods of the redistribution structure 702 can be the same as or similar to those of the redistribution structure 102.

[0164] According to some embodiments, as Figure 7B shown, a solder element 710 is formed on the exposed conductive component 708. The materials and formation methods of the solder element 710 can be the same as or similar to those of the solder element 134 as Figure 1K shown.

[0165] According to some embodiments, as Figure 7C shown, similar to the embodiment as Figure 1L shown, device elements 712A, 712B, and 712C are stacked on the redistribution structure 702. The device elements 712A, 712B, and 712C can be similar to the device elements 136A, 136B, and 136C. Each of the device elements 712A, 712B, and 712C has electrodes 714a and 714b. The device elements 712A, 712B, and 712C can be joined to the conductive component 708 through the solder element 710.

[0166] According to some embodiments, as Figure 7D shown, similar to the embodiment as Figure 1M shown, a protective layer 716 is formed. The materials and formation methods of the protective layer 716 can be the same as or similar to those of the protective layer 140 as Figure 1M shown.

[0167] According to some embodiments, as Figure 7E shown, turn upside down Figure 7DThe structure shown is attached to the carrier substrate 720 through the adhesive layer 718. Then, the carrier substrate 700 and the tape 701 are removed to expose the redistribution structure 702. Next, similar to Figure 1J the embodiment shown, a part of the insulating layer 704 is removed to expose the conductive component 706a, as Figure 7E shown.

[0168] According to some embodiments, as Figure 7F shown, similar to Figure 1B the embodiment shown, conductive bumps 722 are formed on some of the conductive components 706a. The material and formation method of the conductive bumps 722 can be the same as or similar to Figure 1B the material and formation method of the conductive bumps 110 shown. The device element 724 is bonded to some of the conductive components 706a through the solder element 726. The device element 724 can be similar to the device element 112.

[0169] According to some embodiments, as Figure 7G shown, similar to Figure 1C the embodiment shown, the semiconductor die 728 is bonded to some of the conductive components 706a through the conductive components 730 of the semiconductor die 728. The semiconductor die 728 can be similar to the semiconductor die 116.

[0170] According to some embodiments, as Figure 7H shown, similar to Figure 1D the embodiment shown, a reinforcing element 732 is formed on the redistribution structure 702. The material and formation method of the reinforcing element 732 can be the same as or similar to Figure 1D the material and formation method of the reinforcing element 120 shown. In some embodiments, a dispenser 734 is used to disperse a polymer material 736 onto the redistribution structure 702 to form the reinforcing element 732. Alternatively, in some other embodiments, the reinforcing element 732 is a pre-formed frame, and a glue material can be used to attach the reinforcing element 732 to the redistribution structure 702.

[0171] According to some embodiments, as Figure 7I shown, a protective layer 738 is formed to surround the semiconductor die 728. The material and formation method of the protective layer 738 can be the same as or similar to Figure 1E the material and formation method of the protective layer 126 shown.

[0172] In some embodiments, a planarization process is then used to provide the protective layer 738 with a substantially flat top surface. In some embodiments, during the planarization process, the conductive bump 722 is partially removed. As a result, a surface 722S of the conductive bump 722 is formed. In some embodiments, the surface 722S is substantially flat. In some embodiments, the surface 722S is substantially flush with the top surface of the protective layer 738.

[0173] According to some embodiments, Figure 7J As shown, similar to Figure 3A In the embodiment shown, the solder element 740 is formed on the surface 722S of the conductive bump 722. Then, a thermal reflow process is used to reflow the solder element 740 and the conductive bump 722. According to some embodiments, as a result, the conductive bump 742 is formed. Figure 7K shown.

[0174] In some embodiments, each solder element 740 is formed to have a larger volume. In these cases, after the thermal reflow process, each resulting conductive bump 742 may have a volume similar to that of the conductive bump 742. Figure 1P The embodiment shown has a gourd-shaped profile.

[0175] According to some embodiments, Figure 7L As shown, flip upside down Figure 7K The structure shown in FIG. 7 is formed by cutting the substrate 718 and attaching the structure to the frame carrier 744. Afterwards, the adhesive layer 718 and the carrier substrate 720 are removed to expose the protective layer 716. Afterwards, a cutting process can be used to form a plurality of package structures separated from each other. These package structures can then be bonded to other components, such as a printed circuit board or an interposer.

[0176] Many variations and modifications may be made to the embodiments of the present invention. Figures 8A - 8B is a cross-sectional schematic diagram showing various stages of a process for forming a package structure according to some embodiments.

[0177] like Figure 8A As shown, receiving or forming a structure, this structure and Figure 7I However, the protective layer 738 is planarized to expose and partially remove the conductive bumps 722, but the semiconductor die 728 is not exposed. In these cases, the protective layer 738 covers the semiconductor die 728.

[0178] According to some embodiments, thereafter, a process similar to Figures 7J - 7L The process steps are shown in FIG. Figure 8B The structure shown in FIG. 1 is then cut into multiple package structures separated from each other using a sawing process. These package structures can then be bonded to other components, such as a printed circuit board or an interposer.

[0179] Many variations and modifications can be made to the embodiments of the present invention. Figure 10 FIG. Figure 10 is a cross-sectional schematic diagram of a packaging structure according to some embodiments. In some embodiments, a reinforcing element 120 is formed on the surface of the semiconductor die 116 where the redistribution structure 102 is located. In some embodiments, another reinforcing element 120' may be formed on the opposite surface of the redistribution structure 102. The material and formation method of the reinforcing element 120' may be the same as or similar to those of the reinforcing element 120'. The reinforcing element 120' can be formed after the device elements 136A, 136B, and 136C are provided and before the protective layer 140 is formed. Many variations and modifications can be made to the embodiments of the present invention. In some other embodiments, the reinforcing element 120' is formed and the reinforcing element 120 is not formed.

[0180] Embodiments of the present invention form a packaging structure having asymmetric protective layers on opposite surfaces of the redistribution structure. One of the protective layers is thinner and is used to protect thinner components, such as semiconductor dies. The other protective layer is thicker and is used to protect thicker components, such as surface-mounted devices with passive components. By using the thinner protective layer, the total thickness of the packaging structure can be reduced. The thinner protective layer is designed to have a higher coefficient of thermal expansion than the thicker protective layer. The thinner protective layer with a higher coefficient of thermal expansion can compensate for the expansion of the thicker protective layer with a lower coefficient of thermal expansion. Therefore, warping that occurs during or after subsequent manufacturing processes of the packaging structure can be reduced. The quality and reliability of the packaging structure are significantly improved.

[0181] According to some embodiments, a method of forming a packaging structure is provided. The method includes disposing a semiconductor die on a first surface of a redistribution structure. The method further includes forming a first protective layer to surround at least a portion of the semiconductor die. The method further includes disposing a device element on a second surface of the redistribution structure. The redistribution structure is between the device element and the semiconductor die. In addition, the method further includes forming a second protective layer to surround at least a portion of the device element. The second protective layer is thicker than the first protective layer, and the second protective layer and the first protective layer have different coefficients of thermal expansion. In some embodiments, the coefficient of thermal expansion of the first protective layer is higher than that of the second protective layer. In some embodiments, the method further includes forming conductive bumps on the first surface before forming the first protective layer. In some embodiments, the first protective layer covers the conductive bumps and the semiconductor die, and the method further includes planarizing the first protective layer to expose the semiconductor die. In some embodiments, during the planarization of the first protective layer, a portion of the conductive bumps is removed. In some embodiments, the method further includes back-etching the first protective layer such that a portion of the conductive bumps protrudes from a top surface of the first protective layer. In some embodiments, the method further includes forming a solder element directly above the conductive bumps after forming the second protective layer. In some embodiments, the method further includes forming a reinforcing ring on the first surface of the redistribution structure before forming the first protective layer. In some embodiments, the reinforcing ring surrounds the semiconductor die and the conductive bumps. In some embodiments, the method further includes disposing a passive element on the first surface of the redistribution structure before forming the first protective layer. The passive element is thinner than the semiconductor die, and the device element is thicker than the semiconductor die.

[0182] According to some embodiments, a method of forming a packaging structure is provided. The method includes disposing a device element on a first surface of a redistribution structure. The method also includes forming a first protective layer to surround at least a portion of the device element. The method also includes disposing a semiconductor die on a second surface of the redistribution structure. The redistribution structure is between the device element and the semiconductor die. In addition, the method also includes forming a second protective layer to surround at least a portion of the semiconductor die. The second protective layer is thinner than the first protective layer, and the second protective layer and the first protective layer are formed of different materials. In some embodiments, the coefficient of thermal expansion of the second protective layer is higher than that of the first protective layer. In some embodiments, the method also includes forming conductive bumps on the second surface of the redistribution structure before disposing the semiconductor die. In some embodiments, the method also includes forming a reinforcing ring on the second surface to surround the semiconductor die and the conductive bumps before forming the second protective layer. In some embodiments, the second protective layer surrounds sidewalls of the conductive bumps and does not cover a top surface of the conductive bumps, and the method also includes forming a solder element on the top surface of the conductive bumps.

[0183] According to some embodiments, a package structure is provided. This package structure includes a redistribution structure. This package structure also includes a semiconductor die and device elements located on opposite surfaces of the redistribution structure. This package structure also includes a first protective layer at least partially surrounding the semiconductor die. In addition, this package structure also includes a second protective layer at least partially surrounding the device elements. The second protective layer is thicker than the first protective layer, and the second protective layer has a different coefficient of thermal expansion from the first protective layer. In some embodiments, the device elements are thicker than the semiconductor die. In some embodiments, this package structure also includes conductive bumps located on the redistribution structure. The first protective layer surrounds the lower portions of the conductive bumps. In some embodiments, the upper portions of the conductive bumps protrude from the top surface of the first protective layer, and the upper portions of the conductive bumps have sidewall surfaces that bend outward. In some embodiments, the coefficient of thermal expansion of the first protective layer is higher than that of the second protective layer.

[0184] The above outlines the components of several embodiments so that those skilled in the art to which the present invention pertains can better understand the viewpoints of the embodiments of the present invention. Those skilled in the art to which the present invention pertains should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the present invention pertains should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the claims.

Claims

1. A method for forming a packaging structure, comprising: forming a first redistribution structure on a first carrier substrate; after forming the redistribution structure, disposing a semiconductor die on a first surface of the redistribution structure; forming a first protective layer to cover the semiconductor die; planarizing the first protective layer such that the semiconductor die originally covered by the first protective layer is exposed, and the topmost surface of the semiconductor die and the topmost surface of the first protective layer are flush with each other; disposing a second carrier substrate on the topmost surface of the semiconductor die and the topmost surface of the first protective layer; after disposing the second carrier substrate, removing the first carrier substrate; disposing a device element on a second surface of the redistribution structure, wherein the redistribution structure is between the device element and the semiconductor die; removing the second carrier substrate; and after disposing the second carrier substrate and before removing the second carrier substrate, forming a second protective layer to surround at least a portion of the device element, wherein the second protective layer is thicker than the first protective layer, and the second protective layer and the first protective layer have different coefficients of thermal expansion.

2. The method for forming a packaging structure according to claim 1, wherein the coefficient of thermal expansion of the first protective layer is higher than that of the second protective layer.

3. The method for forming a packaging structure according to claim 1, further comprising: forming a conductive bump on the first surface before forming the first protective layer.

4. The method for forming a packaging structure according to claim 3, wherein during planarizing the first protective layer, part of the conductive bump is removed.

5. The method for forming a packaging structure according to claim 4, further comprising: etching back the first protective layer such that a portion of the conductive bump protrudes from the topmost surface of the first protective layer.

6. The method for forming a packaging structure according to claim 4, further comprising: after forming the second protective layer, forming a tin-containing solder element directly above the conductive bump, wherein the tin-containing solder covers opposite sidewalls of the portion of the conductive bump protruding from the topmost surface of the first protective layer.

7. The method for forming a packaging structure according to claim 3, further comprising: forming a reinforcing ring on the first surface of the redistribution structure before forming the first protective layer.

8. The method for forming a packaging structure according to claim 7, wherein the reinforcing ring surrounds the semiconductor die and the conductive bump.

9. The method for forming a packaging structure according to claim 1, further comprising: disposing a passive element on the first surface of the redistribution structure before forming the first protective layer, wherein the passive element is thinner than the semiconductor die, and the device element is thicker than the semiconductor die.

10. A method for forming a packaging structure, comprising: forming a first redistribution structure on a first carrier substrate; disposing a device element on a first surface of the redistribution structure; forming a first protective layer to surround at least a portion of the device element; disposing a second carrier substrate on the topmost surface of the first protective layer; after disposing the second carrier substrate, removing the first carrier substrate; Place a semiconductor die on a second surface of the redistribution structure, wherein the redistribution structure is interposed between the device element and the semiconductor die, and the semiconductor die is thinner than the device element; Form a conductive bump on the second surface of the redistribution structure; Remove the second carrier substrate; After placing the second carrier substrate and before removing the second carrier substrate, form a second protective layer to surround at least a portion of the semiconductor die and cover the conductive bump, wherein the second protective layer is thinner than the first protective layer, and the second protective layer and the first protective layer are formed of different materials; and Partially remove the second protective layer and the conductive bump such that a topmost surface of the second protective layer and a topmost surface of the conductive bump are substantially flush with each other.

11. The method of forming a packaged structure as claimed in claim 10, wherein the second protective layer has a higher coefficient of thermal expansion than the first protective layer.

12. The method of forming a packaged structure as claimed in claim 10, further comprising: Before forming the second protective layer, form a reinforcing ring on the second surface to surround the semiconductor die and the conductive bump.

13. The method of forming a packaged structure as claimed in claim 10, wherein the second protective layer surrounds a sidewall of the conductive bump and does not cover a top surface of the conductive bump, and the method further comprising: Form a solder element on the top surface of the conductive bump.

14. A packaged structure, comprising: A redistribution structure; A semiconductor die and a device element located on opposite surfaces of the redistribution structure; A first protective layer that at least partially surrounds the semiconductor die; And A second protective layer that at least partially surrounds the device element, wherein the second protective layer is thicker than the first protective layer, and the first protective layer has a higher coefficient of thermal expansion than the second protective layer.

15. The packaged structure as claimed in claim 14, wherein the device element is thicker than the semiconductor die.

16. The packaged structure as claimed in claim 14, further comprising: A conductive bump located on the redistribution structure, wherein the first protective layer surrounds a lower portion of the conductive bump.

17. The packaged structure as claimed in claim 16, wherein an upper portion of the conductive bump protrudes from a top surface of the first protective layer, and the upper portion of the conductive bump has a sidewall surface that curves outward.

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