Josephson junction with reduced stray inductance

Abstract

Methods, systems, and devices for forming a Josephson junction with reduced stray inductance. In one aspect, a device includes: a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.

Description

Technical Field

[0001] The present disclosure relates to forming tunnel junctions for Josephson junctions. Background Art

[0002] Quantum computing is a relatively new computing method that uses quantum effects such as superposition of ground states and entanglement to perform certain calculations more efficiently than classical digital computers. Compared with digital computers that store and manipulate information in the form of bits (e.g., "1" or "0"), quantum information processing devices can use quantum bits to manipulate information. A quantum bit can refer to a quantum device that can achieve a superposition of multiple states (e.g., data in both a "0" state and a "1" state) and / or to a superposition of the data itself in multiple states. Example physical implementations of quantum bits include quantum bits implemented using Josephson junctions. Summary of the invention

[0003] In general, an innovative aspect of the subject matter described in this specification can be implemented in a method comprising the following actions: providing a substrate comprising a first resist layer, the first resist layer being patterned to expose an opening area, wherein the opening area comprises a central opening portion, a first elongated opening portion, and a second elongated portion, the first elongated opening portion having a length extending from a first side of the central opening portion along a first direction, the second elongated portion having a length extending from a second side of the central opening portion along a second direction different from the first direction, wherein a width of the first elongated portion is smaller than a length of the first side of the central opening, and a width of the second elongated portion is smaller than a length of the second side of the central opening; and forming a first non-normal angle on the patterned resist layer relative to the substrate. The method comprises depositing a first superconductor material at a certain angle to form a first superconductor layer in a central opening portion and a first elongated opening portion of the opening region; forming an insulator layer on a portion of the first superconductor layer; depositing a second superconductor material on the insulator layer and the patterned resist layer at a second non-normal angle relative to the substrate to form a second superconductor layer in the central opening portion and the second elongated portion of the opening region, wherein the first superconductor layer, the insulator layer and the second superconductor layer in the central opening portion provide a superconductor tunnel junction; and forming a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a separated second contact to the superconductor tunnel junction, respectively.

[0004] The foregoing embodiments and other embodiments may each optionally include one or more of the following features, alone or in combination. In some embodiments, the first superconductor layer is formed in a first section of the central opening portion, the second superconductor layer is formed in a second section of the central opening portion, and the first section of the central opening portion and the second section of the central opening portion only partially overlap.

[0005] In some embodiments, a superconductor tunnel junction is formed at a location where the first section of the central opening portion and the second section of the central opening portion partially overlap.

[0006] In some embodiments, the first contact is formed on the surface of the first superconductor layer outside the position where the first segment of the central opening portion and the second segment of the central opening portion partially overlap, and the second contact is formed on the surface of the second superconductor layer outside the position where the first segment of the central opening portion and the second segment of the central opening portion partially overlap.

[0007] In some embodiments, the first contact is formed on a surface of the first superconductor layer within the first elongated opening portion, and wherein the second contact is formed on a surface of the second superconductor layer within the second elongated opening.

[0008] In some embodiments, the width of the first contact is greater than the width of the first superconductor layer within the first elongated portion, and the width of the second contact is greater than the width of the second superconductor layer within the second elongated portion.

[0009] In some embodiments, forming the third superconductor layer includes: forming a second resist layer on the first superconductor layer and the second superconductor layer; and patterning the second resist layer to form a first contact opening and a second contact opening; and depositing a third superconductor on the patterned second resist layer and removing the second resist layer to form a first contact and a second contact.

[0010] In some embodiments, the method further includes, before depositing the third superconductor layer, performing ion milling on a surface of the first superconductor layer exposed in the first contact opening and a surface of the second superconductor layer exposed in the second contact opening.

[0011] In some embodiments, the first resist layer is patterned using photolithography.

[0012] In some embodiments, an aspect ratio between a height of the first resist layer and a width of the first elongated opening portion or a width of the second elongated opening portion is between 1:1 and 10:1.

[0013] In some embodiments, the height of the resist layer is between about 0.1 microns and about 4 microns.

[0014] In some embodiments, a superconductor tunnel junction forms part of an analog circuit element or a single-flux quantum logic circuit element.

[0015] In general, another innovative aspect of the subject matter described in this specification can be implemented in a method comprising the following acts: providing a substrate comprising a first resist layer, the first resist layer being patterned to include an opening region exposing a surface of the substrate, wherein the opening region is laterally surrounded on all sides by the first resist layer; depositing a first superconductor material on the patterned resist layer along a first direction at a first non-normal angle relative to the substrate to form a first superconductor layer in the opening region, wherein the patterned resist layer prevents the first superconductor layer from being formed in at least a first portion of the opening region; forming an insulating layer on a portion of the first superconductor layer The invention relates to a method for manufacturing a second superconductor layer comprising: depositing a second superconductor material on the insulator layer and the patterned resist layer along a second direction at a second non-normal angle relative to the substrate to form a second superconductor layer in the opening area, wherein the patterned resist layer prevents the second superconductor layer from being formed in at least a second portion of the opening area, and wherein the first superconductor layer, the insulator layer and the second superconductor layer in the opening area provide a superconductor tunnel junction; and forming a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a separated second contact to the superconductor tunnel junction, respectively.

[0016] The foregoing embodiments and other embodiments may each optionally include one or more of the following features alone or in combination. In some embodiments, the first superconductor layer is formed in a first section of the opening region, the second superconductor layer is formed in a second section of the opening region, and the first section of the opening region and the second section of the opening region only partially overlap.

[0017] In some embodiments, a superconductor tunnel junction is formed at a location where the first section of the opening region and the second section of the opening region partially overlap.

[0018] In some embodiments, a first contact is formed on a surface of the first superconductor layer outside a position where a first segment of the opening region and a second segment of the opening region partially overlap, and a second contact is formed on a surface of the second superconductor layer outside a position where a first segment of the opening region and a second segment of the opening region partially overlap.

[0019] In some embodiments, the first contact extends away from a first side of the open region and the second contact extends away from a second, different side of the open region.

[0020] In some embodiments, the first contact and the second contact extend in orthogonal directions.

[0021] In some embodiments, forming the third superconductor layer includes: forming a second resist layer on the first superconductor layer and the second superconductor layer; and patterning the second resist layer to form a first contact opening and a second contact opening; and depositing a third superconductor on the patterned second resist layer and removing the second resist layer to form a first contact and a second contact.

[0022] In some embodiments, the method further includes, before depositing the third superconductor layer, performing ion milling on a surface of the first superconductor layer exposed in the first contact opening and a surface of the second superconductor layer exposed in the second contact opening.

[0023] In some embodiments, the first resist layer is patterned using photolithography.

[0024] In some embodiments, the height of the resist layer is between about 0.1 microns and about 4 microns.

[0025] In some embodiments, a superconductor tunnel junction forms part of an analog circuit element or a single-flux quantum logic circuit element.

[0026] In general, another innovative aspect of the subject matter described in this specification can be implemented in a device comprising: a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.

[0027] The foregoing embodiments and other embodiments may each optionally include one or more of the following features alone or in combination. In some embodiments, the first superconductor layer includes a first portion that forms a bottom electrode to a superconductor tunnel junction and includes a second portion directly adjacent to the bottom electrode, wherein the first contact is formed directly on the second portion of the first superconductor layer, and the second superconductor layer includes a first portion that forms a top electrode to a superconductor tunnel junction and includes a second portion directly adjacent to the top electrode, wherein the second contact is formed directly on the second portion of the second superconductor layer.

[0028] In some embodiments, the second portion of the first superconductor layer includes a corresponding wide segment and a corresponding narrow segment, the narrow segment having a length extending outward from the wide segment of the first superconductor layer, and the second portion of the second superconductor layer includes a corresponding wide segment and a corresponding narrow segment, the narrow segment having a length extending outward from the wide segment of the second superconductor layer.

[0029] In some embodiments, a superconductor tunnel junction forms part of an amplifier circuit element.

[0030] In some embodiments, a superconductor tunnel junction forms part of an analog circuit element.

[0031] In some embodiments, a superconductor tunnel junction forms part of a single-flux quantum logic circuit element.

[0032] The subject matter described in this specification can be implemented in a specific manner to achieve one or more of the following advantages.

[0033] For example, in some embodiments, the processes disclosed herein can be used to fabricate Josephson junctions having junction leads with reduced stray series inductance. Alternatively or additionally, the techniques disclosed herein can be used to increase the critical current of a Josephson junction due to the increased size of the overlap region between layers of superconductor material. In some cases, the fabrication processes described herein reduce the number of patterning steps required to form a junction. Fewer patterning steps can result in fewer times to remove a wafer from a deposition chamber, which in turn can reduce the risk of defects and simplify the fabrication process.

[0034] Josephson junctions fabricated using the two-angle deposition technique described in this specification can have arbitrary dimensions (independent of electrode width) without causing accidental short circuits. This is in contrast to Josephson junctions fabricated using other known two-angle deposition techniques, where the side arms of the junction cannot be arbitrarily enlarged due to resist layer sidewalls or due to increased risk of short circuits.

[0035] Because photolithography can be used instead of electron beam etching to perform junction patterning, Josephson junctions made using the techniques described in this specification can be made in parallel. Electron beam etching requires sequential exposure of each individual junction feature on the wafer, whereas with photolithography, all features are exposed simultaneously. Depending on the specific device and wafer size, there can be ~1e6 junctions per wafer.

[0036] In some embodiments, because before completing each deposition step, the junction can be, for example, Figure 1A Regions 104a and 104b are electrically connected to circuitry, so Josephson junctions fabricated using the techniques described in this specification allow the junctions to be probed and characterized for in-line metrology during the fabrication process.

[0037] In some embodiments, because area differences do not dominate resistance changes (as they do in the case of smaller junctions), Josephson junctions fabricated using the techniques described in this specification have improved reproducibility of the junction critical current.

[0038] The details of one or more implementations of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1A is a schematic diagram of an example state of a prior art double-angle Josephson junction.

[0040] Figure 1B is a schematic diagram of example deposition angles relative to the wafer.

[0041] Figure 2 is a flow chart of a first example process for fabricating a low stray inductance Josephson junction.

[0042] Figures 3A-3D is a schematic diagram of top and cross-sectional views of an example substrate during a first example process for forming a Josephson junction with reduced stray inductance.

[0043] Figure 4 is a flow chart of a second example process for fabricating a low stray inductance Josephson junction.

[0044] Figures 5A-5D is a schematic diagram of a top view of an example substrate during a second process of forming a Josephson junction with reduced stray inductance. DETAILED DESCRIPTION

[0045] Quantum computing requires coherently processing quantum information stored in the quantum bits of a quantum computer. Superconducting quantum computing is one implementation of quantum computing technology in which quantum information processing devices are formed in part from superconducting materials. The fabrication of integrated quantum information processing devices with superconducting components typically involves depositing and patterning superconducting materials, dielectrics, and metal layers. Some quantum information processing devices, such as quantum bits, can be constructed using Josephson junctions.

[0046] A Josephson junction can be made by sandwiching a layer of non-superconducting material or a "barrier" of non-superconducting material between two layers of superconducting material. The non-superconducting material layer is thin enough to allow electrons to quantum mechanically tunnel from one superconducting layer to the other through the non-superconducting material. That is, until a critical current is reached, supercurrent can flow through the barrier and electron pairs can tunnel through the barrier without any resistance. For superconducting logic applications in quantum computing, the barrier material is an insulator, such as aluminum oxide.

[0047] One technique for making Josephson junctions is the dual angle deposition lift-off process. During this process, a first superconductor layer is deposited at a first angle relative to patterned resist features on a wafer, the first superconductor layer is next oxidized, and then a second superconductor is next deposited at a second angle relative to the patterned resist. The two angles of deposition result in two offset images of the resist pattern. The technique relies on masking from the resist stack to mask out sections of the pattern to create two electrically distinct metal regions that are connected by a junction oxide in a well-defined overlap region in the pattern.

[0048] Josephson junction with reduced stray inductance

[0049] The present disclosure provides methods and apparatus for fabricating a Josephson junction with reduced stray series inductance of the junction lead using a dual angle deposition process.

[0050] Figure 1A is a schematic diagram of an example dual angle Josephson junction. Regions 102a, 102b represent etched and defined portions of the circuit. Regions 104a, 104b, 104c represent superconductors deposited in two angle steps described below. The area enclosed by dashed line 108 represents the overlapping region where the junction is formed, and region 106 represents the portion of the pattern that is masked by the resist during the two deposition steps. Figure 1B 1 is a schematic diagram of example deposition angles relative to a wafer. Unlike other dual angle deposition techniques, the first deposition is represented by arrow 152 along the negative x-axis (as opposed to deposition along the + axis). The first deposition is 45° to the top surface of the wafer (the surface on which the feature is formed), however, in some cases, the first deposition angle may take other values. The second deposition is represented by arrow 154 along the positive y-axis (as opposed to deposition along the – axis). The second deposition is also 45° to the top surface of the wafer, however, this is merely an example, and in some cases, the second deposition angle may take other values.

[0051] The dual-angle deposition technique used in this specification requires that the leads connecting the junction to the rest of the circuit be long and narrow. The width of these leads must be small enough to be masked by the resist stack, and their length is usually constrained by the minimum spacing design rules of the process. For example, a lead can be 2μm long and 0.3-0.7μm wide, even though the junction itself spans several microns.

[0052] The result of the geometry of the junction leads is that the leads exhibit a large series inductance to the junction, which is unacceptable in applications such as Josephson logic, Josephson amplifiers, and microwave components. In addition, due to the high aspect ratio of the leads, their inductance may be more difficult to control relative to manufacturing process variations.

[0053] Refer to the following Figure 2 and Figures 3A-3D An exemplary process for fabricating a Josephson junction with reduced stray inductance is described.

[0054] Figure 2 is a flow chart of a first example process 200 for forming a Josephson junction with reduced stray inductance. For example, process 200 can be used to form the present application. Figure 3D A Josephson junction is shown.

[0055] A substrate including a first resist layer that has been patterned to expose an opening region is provided (step 202 ). Figure 3A A schematic diagram of the provided substrate is shown.

[0056] The first resist layer may have been patterned using photolithography and may have a height between about 0.1 microns and about 4 microns. In some embodiments, the first resist layer may include a two-layer resist stack, where the bottom of the stack is an undercut layer and the top is an imaging layer.

[0057] The opening area includes: a central opening portion; a first extended opening portion having a length extending from a first side of the central opening portion along a first direction; and a second extended portion having a length extending from a second side of the central opening portion along a second direction, the second direction being different from the first direction, for example, orthogonal to the first direction.

[0058] The width of the first elongated portion is less than the width of the first side of the central opening. In addition, the width of the second elongated portion is less than the length of the second side of the central opening. In some embodiments, the aspect ratio between the height of the first resist layer and the width of the first elongated opening portion or the width of the second elongated opening portion can be between 1:1 and 10:1.

[0059] A first superconductor material is deposited on the patterned resist layer at a first non-normal angle relative to the substrate to form a first superconductor layer within the central opening portion and the first elongated opening portion of the opening region (step 204). Figure 3B A schematic diagram of a substrate after deposition of a first superconductor material on a first resist layer is shown.

[0060] An insulator layer is formed on a portion of the first superconductor layer (step 206). Figure 3C A schematic diagram showing a substrate in which an insulator layer is formed on a portion of a first superconducting layer.

[0061] A second superconductor material is deposited on the insulator layer and the patterned resist layer at a second non-normal angle relative to the substrate to form a second superconductor layer in the central opening portion and the second elongated opening portion of the opening region (step 208). The first superconductor layer, the insulator layer, and the second superconductor layer in the central opening portion provide a superconductor tunnel junction.

[0062] In some embodiments, the first superconductor layer may be formed in a first section of the central opening portion, and the second superconductor layer may be formed in a second section of the central opening portion, wherein the first section of the central opening portion and the second section of the central opening portion only partially overlap. In these embodiments, a superconductor tunnel junction may be formed at a location where the first section of the central opening portion and the second section of the central opening portion partially overlap.

[0063] A third superconductor layer is formed directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a separate second contact to the superconductor tunnel junction, respectively (step 212). Figure 3D A schematic diagram shows a substrate after a third superconductor layer has been formed directly on a portion of the surface of the first superconductor layer and a portion of the surface of the second superconductor layer.

[0064] Forming the third superconductor layer may include forming a second resist layer on the first superconductor layer and on the second superconductor layer (step 210), patterning the second resist layer to form a first contact opening and a second contact opening (step 210), and depositing a third superconductor material on the patterned second resist layer. The third superconductor material may be deposited at a perpendicular angle relative to the substrate. Forming the third superconductor layer may then further include removing the second resist layer to form the first contact and the second contact. Optionally, before depositing the third superconductor layer, ion milling may be performed on the surface of the first superconductor layer exposed in the first contact opening and on the surface of the second superconductor layer exposed in the second contact opening.

[0065] In an embodiment in which a superconductor tunnel junction is formed at a position where the first segment of the central opening portion and the second segment of the central opening portion partially overlap, a first contact may be formed on a surface of the first superconductor layer outside the position where the first segment of the central opening portion and the second segment of the central opening portion partially overlap. Similarly, a second contact may be formed on a surface of the second superconductor layer outside the position where the first segment of the central opening portion and the second segment of the central opening portion partially overlap.

[0066] In some embodiments, the first contact may be formed on a surface of the first superconductor layer within the first elongated opening portion. In some embodiments, the second contact may be formed on a surface of the second superconductor layer within the second elongated opening portion. The width of the first contact may be greater than the width of the first superconductor layer within the first elongated portion. In addition, the width of the second contact may be greater than the width of the second superconductor layer within the second elongated portion.

[0067] For convenience, process 200 has been described with reference to forming a single Josephson junction using a first resist layer that has been patterned to expose a single opening region. However, in some embodiments, the first resist layer can include multiple opening regions so that process 200 can be used to form multiple Josephson junctions in parallel.

[0068] The device formed by the process 200 is, for example, Figure 3D The device shown in the figure can be provided for various applications. For example, the device can be provided for use as an element in a quantum circuit, a Josephson amplifier or as a microwave component. As another example, the device can be provided for use as an element in an analog circuit, for example, a microwave component such as a switch, a mixer, a phase shifter, a resonator, a filter or a detector.

[0069] Figures 3A-3D is a schematic diagram of top and cross-sectional views of an example substrate 302 during a first example process 200 for forming a Josephson junction with reduced stray inductance.

[0070] Figure 3A A schematic diagram of a provided substrate 302 is shown in a top view 300a, a cross-sectional view 300b through the axis A-A' and a cross-sectional view 300c through the axis BB'. The provided substrate 302 corresponds to Figure 2 At step 202 a substrate is provided.

[0071] The substrate 302 includes a first resist layer 304 for defining a Josephson junction. In some embodiments, the height of the first resist layer 304 can be, for example, between about 0.1 microns and about 4 microns. The first resist layer 304 is patterned to expose an opening area 306 defined by a dotted line. The area size of the opening 306 depends on the process and the circuit to which the junction is to be connected. However, the area size of the opening 306 can be limited by factors such as defect rate, stray capacitance of the junction, and manufacturing considerations. As an example, the area size of the opening 306 can be less than 5.0 μm by 5.0 μm. In some embodiments, the first resist layer 304 can be patterned using optical etching.

[0072] The opening region 306 includes a central opening portion 306a, a first elongated opening portion 306b, and a second elongated opening portion 306c.

[0073] The first elongated opening portion 306b has a length extending from the first side 308a of the central opening portion 306a in the first direction. The width 310 of the first elongated opening portion 306b is less than the length 312 of the first side 308a of the central opening 306a (or equivalently, narrower than the width of the central opening portion 306a). In some embodiments, the width 310 can be approximately equal to 0.3 μm. In some embodiments, the length L1 of the first elongated opening portion 306b can be approximately equal to 2 μm. In some embodiments, the aspect ratio between the height of the first resist layer 304 and the width 310 of the first elongated opening portion 306b is between 1:1 and 10:1.

[0074] The second elongated portion 306c has a length extending from the second side 308b of the central opening portion 306a along a second direction different from the first direction. For example, the first direction is orthogonal to the second direction. The width 314 of the second elongated portion 306c is less than the length of the second side 308b of the central opening portion 306a (or equivalently, narrower than the height 316 of the central opening portion 306a). In some embodiments, the width 314 can be approximately equal to 0.3 μm and / or the height 316 of the central opening portion 306a can be approximately equal to 3.5 μm. In some embodiments, the aspect ratio between the height of the first resist layer 304 and the width 314 of the second elongated opening portion 306c can be between 1:1 and 10:1.

[0075] Each of the elongated portions 306b, 306c may be coupled to first and second devices or components 318b, 318c, respectively, formed on the substrate 302. For example, the devices or components 318b, 318c may include a ground connection, a capacitor, an inductor, another Josephson junction, a coplanar waveguide, a qubit, a qubit readout resonator, a qubit control element (e.g., a qubit Z control or a qubit XY control element), and other circuit elements.

[0076] Figure 3B The first superconductor material 320 is deposited on Figure 3A Schematic diagram of the substrate 302 in a top view 300d, a cross-sectional view 300e through the axis CC' and a cross-sectional view 300f through the axis D-D' after the first resist layer 304 is shown. For example, Figure 3B The schematic diagram of the substrate 302 shown corresponds to Figure 2 Step 204. In some embodiments, the first superconductor material 320 may be aluminum.

[0077] The first superconductor material 320 may be deposited on the first resist layer 304 at a first non-normal angle relative to the upper surface of the substrate 302, as described above with reference to Figure 1B In some embodiments, the first non-normal angle may be 45 degrees. The first superconductor material 320 is deposited at the first non-normal angle relative to the substrate surface 302 to form a first superconductor layer 322 (defined by dashed lines) within the central opening portion 306a and the first elongated opening portion 306b of the opening region 306.

[0078] Figure 3C The insulator layer 360 (eg, an oxide layer) is formed on Figure 3B and a second superconductor material 326 is deposited on a portion of the first superconducting layer 322 and the insulator layer 360 and Figure 3A Schematic diagram of the substrate 302 in a top view 300g, a cross-sectional view 300h through the axis EE' and a cross-sectional view 300i through the axis FF' after the first resist layer 304 is shown. For example, Figure 3C The schematic diagram of the substrate 302 shown may correspond to Figure 2 Step 206. In some embodiments, second superconductor material 326 may be aluminum.

[0079] The second superconductor material 326 may be deposited on the insulator layer 360 and the first resist layer 304 at a second non-linear angle relative to the substrate 302, as described above with reference to Figure 1B In some embodiments, the second non-normal angle may be 45 degrees. A second superconductor material 326 is deposited at a second non-normal angle relative to the substrate surface 302 to form a second superconductor layer 328 (defined by dashed lines) within the central opening portion 306a and the second elongated opening portion 306c of the opening region 306.

[0080] The portions of the first superconductor layer 322, the insulator layer 360, and the second superconductor layer 328 that are located within the central opening portion 306a and overlap provide a superconductor tunnel junction. In some embodiments, a first section of the central opening portion 306a in which the first superconductor layer 322 is formed and a second section of the central opening portion 306a in which the second superconductor layer 328 is formed may overlap only partially in the region 330. Figure 3C In the example shown, the superconductor tunnel junction is defined within the region enclosed by dashed line 324 .

[0081] Figure 3D shows that the third superconductor layer has been formed directly on Figure 3C A portion of the surface of the first superconductor layer 322 and Figure 3C A schematic diagram of the substrate 302 after a portion of the surface of the second superconductor layer 328 is formed. For example, Figure 3DThe schematic diagram of the substrate 302 shown may correspond to Figure 2 Step 212.

[0082] The third superconductor layer provides first contact 332a and separate second contact 332b to superconducting tunnel junction 330, respectively. Deposition of the third superconductor layer provides electrical contact to superconductor tunnel junction 330 and to the remainder of the circuit (e.g., etchedly defined portions 318a and 318b) to provide a current path.

[0083] In some embodiments, first contact 332a may be formed on the surface of first superconductor layer 322 outside the location where the first segment of central opening portion 306a and the second segment of central opening portion 306a partially overlap (e.g., outside region 330). In these embodiments, first contact 332a may be formed on the surface of first superconductor layer 322 within first elongated opening portion 306b.

[0084] Similarly, in some embodiments, second contact 332b may be formed on the surface of second superconductor layer 328 outside the location where the first segment of central opening portion 306a and the second segment of central opening portion 306a partially overlap (e.g., outside region 330). In these embodiments, second contact 332b may be formed on the surface of second superconductor layer 328 within second elongated opening portion 306c.

[0085] The width 334a of the first contact 332a is greater than the width of the first superconductor layer 322 within the first elongated portion 306b (eg, Figure 3A Similarly, the width 334b ​​of the second contact 332b is greater than the width of the second superconductor layer 328 within the second elongated portion 306b (e.g. Figure 3A In some embodiments, the width 334a of the first contact 332a and / or the width 334b ​​of the second contact 332b can be approximately equal to 2 μm, or a value between 2 μm and 5 μm. Such widths can reduce the lead stray inductance of the Josephson junction to approximately 2 pH per lead. In the event that wider contacts are required, additional widths can be achieved by extending other elements such as the etched defined portions 318a and 318b.

[0086] Refer to the following Figure 4 and Figures 5A-5C Another exemplary process for fabricating a Josephson junction with reduced stray inductance is described.

[0087] Figure 4is a flow chart of a second example process 400 for forming a Josephson junction with reduced stray inductance. For example, process 400 can be used to form the present application. Figure 5D A Josephson junction is shown.

[0088] A substrate is provided that includes a first resist layer that is patterned to include an open area that exposes a surface of the substrate (step 402). In some embodiments, the first resist layer can be a bilayer, i.e., a layer suitable for angled deposition techniques. In some embodiments, the first resist layer can have been patterned using photolithography and can have a height between about 0.1 microns and about 4 microns.

[0089] The opening region may, for example, be in the shape of a rectangle, such as a square, which is laterally surrounded on all sides by the first resist layer. For example, the opening region is a central opening region without any elongated opening portions extending outwardly from the central opening region. The size of the area of ​​the central opening region depends on the deposition angle and the resist thickness. For example, for a 1 μm thick resist and a deposition angle of 45 degrees, the area of ​​the central opening region may be at least 1 μm by 1 μm. Figure 5A A schematic diagram of a substrate provided in step 402 is shown in FIG.

[0090] A first superconductor material is deposited on the patterned resist layer along a first direction at a first non-normal angle relative to the substrate to form a first superconductor layer in the opening region (step 404). The patterned resist layer prevents the first superconductor layer from being formed in at least a first portion of the opening region. Figure 5B A schematic diagram of a substrate after deposition of a first superconductor material on a first resist layer is shown.

[0091] An insulator layer is formed on a portion of the first superconductor layer (step 406).

[0092] A second superconductor material is deposited on the insulator layer and the patterned resist layer along a second direction at a second non-normal angle relative to the substrate to form a second superconductor layer in the opening region (step 408). The patterned resist layer prevents the second superconductor layer from being formed in at least a second portion of the opening region, and the first superconductor layer, the insulator layer, and the second superconductor layer in the opening region provide a superconductor tunnel junction. Figure 5C A schematic diagram of the substrate is shown after an insulator layer is formed on a portion of the first superconducting layer and a second superconductor material is deposited on the insulator layer and the first resist layer.

[0093] In some embodiments, the first superconductor layer may be formed in a first section of the opening region, and the second superconductor layer may be formed in a second section of the opening region. The first section of the opening region and the second section of the opening region may only partially overlap. In these embodiments, a superconductor tunnel junction may be formed at a location where the first section of the opening region and the second section of the opening region partially overlap.

[0094] A third superconductor layer is formed directly on the surface of the first superconductor layer and directly on the surface of the second superconductor layer (after a second patterning step as described below) to provide a first contact to the superconducting tunnel junction and a separate second contact to the superconductor tunnel junction, respectively (step 410). The first contact may be formed on the surface of the first superconductor layer outside the location where the first segment of the opening region and the second segment of the opening region partially overlap. Similarly, the second contact may be formed on the surface of the second superconductor layer outside the location where the first segment of the opening region and the second segment of the opening region partially overlap. Figure 5D A schematic diagram of the substrate is shown after a third superconductor layer has been formed directly on a portion of the surface of the first superconductor layer and a portion of the surface of the second superconductor layer.

[0095] In some embodiments, the first contact extends away from a first side of the opening region and the second contact extends away from a second, different side of the opening region. In these embodiments, the first contact and the second contact may extend in orthogonal directions.

[0096] Forming the third superconductor layer may include: forming a second resist layer on the first superconductor layer and the second superconductor layer; patterning the second resist layer to form a first contact opening and a second contact opening; and depositing the third superconductor layer on the patterned second resist layer and removing the second resist layer to form the first contact and the second contact. Optionally, before depositing the third superconductor layer, ion milling may be performed on a surface of the first superconductor layer exposed in the first contact opening and on a surface of the second superconductor layer exposed in the second contact opening.

[0097] For convenience, process 400 has been described with reference to forming a single Josephson junction using a first resist layer that has been patterned to expose a single opening region. However, in some embodiments, the first resist layer can include multiple opening regions so that process 400 can be used to form multiple Josephson junctions in parallel.

[0098] The device formed by the process 400 is, for example, Figure 5DThe device shown can be provided for various applications. For example, the device can be provided for use as an element in a quantum circuit, a Josephson amplifier, or as a microwave component. As another example, the device can be provided for use as an element in an analog circuit, for example a microwave component, such as a switch, a mixer, a phase shifter, a resonator, a filter, or a detector.

[0099] Figures 5A-5D is a schematic diagram of a top view of an example substrate 502 during a second example process 400 for forming a Josephson junction with reduced stray inductance.

[0100] Figure 5A A schematic diagram of a provided substrate 502 is shown. The substrate 502 includes a first resist layer 504 for defining a Josephson junction. In some embodiments, the height of the first resist layer 504 can be between about 0.1 microns and about 4 microns. The first resist layer 504 is patterned to include an opening area 506 that exposes the surface of the substrate 502. For example, the first resist layer 504 can be patterned using optical etching. The opening area 506 includes, for example, a rectangular opening area (such as a square opening area) that is laterally surrounded by the first resist layer 504 on all sides. For example, the opening area 506 is a central opening area that does not have any elongated opening portions (such as a square opening area) extending outward from the central opening area 506. Figure 3A The extension portions 306c, 306b are shown). Figure 5A The schematic diagram of the substrate 502 shown corresponds to Figure 4 Step 402.

[0101] Figure 5B shows that the first superconductor material 508 is deposited on Figure 5A A schematic diagram of a substrate 502 after a first resist layer 504 is shown. Figure 5B The schematic diagram of the substrate 502 shown corresponds to Figure 4 Step 404. In some embodiments, the first superconductor material 508 can be aluminum.

[0102] The first superconductor material 508 may be deposited on the first resist layer 504 along a first direction at a first non-normal angle relative to the upper surface of the substrate 502, as described above with reference to Figure 1B In some embodiments, the first non-normal angle may be 45 degrees. A first superconductor material 508 is deposited at a first non-normal angle relative to the substrate 502 along a first direction to form a first superconductor layer 510 (defined by a dotted line) within the opening region 506. Figure 5BAs shown, the patterning of the resist layer 504 prevents the first superconductor layer 510 from being formed in at least a first portion of the opening region 506, for example, in a top section of the opening region 506. An insulator layer, such as an oxide layer, may be formed on a portion of the first superconductor layer 510, which may serve as a barrier layer for a superconductor tunnel junction or a Josephson junction.

[0103] Figure 5C It is shown that an insulator layer such as an oxide layer is formed on Figure 5B and a second superconductor material 512 is deposited on a portion of the first superconducting layer 510 and the second superconductor material 512 is deposited on the insulator layer and Figure 5A A schematic diagram of a substrate 502 after a first resist layer 504 is shown. Figure 5C The schematic diagram of the substrate 502 shown corresponds to Figure 4 Step 406. In some embodiments, the second superconductor material 512 can be aluminum.

[0104] The second superconductor material 512 may be deposited on the insulator layer and the first resist layer 504 along a second direction at a second non-normal angle relative to the upper surface of the substrate 502, as described above with reference to Figure 1B In some embodiments, the second non-normal angle may be 45 degrees. A second superconductor material 512 is deposited at a second non-normal angle relative to the substrate 502 along a second direction to form a second superconductor layer 514 (defined by the shaded area) within the opening region 506. Figure 5C As shown, patterning of the resist layer 504 prevents the second superconductor layer 514 from being formed in at least a second portion of the opening region 506, for example, in the rightmost segment of the opening region 506, thereby leaving the uppermost right corner without a superconductor layer formed on the exposed portion of the substrate.

[0105] The first superconductor layer 510, the insulator layer, and the second superconductor layer 514 within the opening region 506 provide a superconductor tunnel junction. In some embodiments, a first section of the opening portion 506 in which the first superconductor layer 510 is formed and a second section of the opening portion 506 in which the second superconductor layer 514 is formed may only partially overlap, for example, in the region 516. In these embodiments, a superconductor tunnel junction may be formed at a location where the first section of the opening portion 506 and the second section of the opening portion 506 partially overlap. Figure 5C In the example shown, the superconductor tunnel junction is defined within the region enclosed by dashed line 518 .

[0106] Figure 5D shows that the third superconductor layer has been formed directly on Figure 5B A portion of the surface of the first superconductor layer 510 and Figure 5CSchematic diagram of substrate 502 after a portion of the surface of second superconductor layer 514 is formed. The third superconductor layer provides first contact 520a to superconducting tunnel junction 518 and separate second contact 520b to superconductor tunnel junction 518, respectively. Figure 5D The schematic diagram of the substrate 502 shown corresponds to Figure 4 Step 410.

[0107] In some embodiments, the first contact 520a may be formed outside the location where the first section of the opening portion 506 and the second section of the opening portion 506 partially overlap (eg, at Figure 5C Similarly, in some embodiments, the second contact 520b can be formed outside the location where the first section of the opening portion 506 and the second section of the opening portion 506 partially overlap (for example, at Figure 5C On the surface of the second superconductor layer 514 (outside the region 516).

[0108] like Figure 5D As shown, the first contact 520a can extend away from the first side 522a of the opening region 506, and the second contact 520b can extend away from a different second side 522b of the opening region. In some embodiments, the first contact 520a and the second contact 520b can extend in orthogonal directions, that is, the first side 522a and the second side 522b can be orthogonal.

[0109] Depositing the third superconductor layer in this manner provides electrical contact to superconductor tunnel junction 518 and to the rest of the circuit (e.g., circuit elements 524a and 524b) to provide a low inductance current path. Circuit elements 524a and 524b may include, for example, other components formed on the substrate, including, for example, ground connections, inductors, capacitors, other Josephson junctions, qubits, coplanar waveguides, qubit readout resonators, qubit control elements (e.g., qubit Z control elements or qubit XY control elements), and other circuit elements. Although not described in detail herein, the present invention provides a method for depositing a third superconductor layer in this manner. Figure 5D , but in some embodiments, circuit elements 520a, 520b, 524a, and 524b may be wider than junction leads 514 and 510 (if desired, for example, to reduce inductance).

[0110] An example of a superconducting material that can be used to form a quantum circuit element is aluminum. Aluminum can be used in combination with a dielectric to establish a Josephson junction, which is a common component of a quantum circuit element. Examples of quantum circuit elements that can be formed with aluminum include circuit elements such as superconducting coplanar waveguides, quantum LC oscillators, qubits (e.g., flux qubits or charge qubits), superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUIDs or DC-SQUIDs), inductors, capacitors, transmission lines, ground planes, etc. Other superconductor materials can include, for example, niobium or titanium nitrides.

[0111] Aluminum can also be used to form superconducting classical circuit elements, which can interoperate with superconducting quantum circuit elements and other classical circuit elements based on complementary metal oxide semiconductor (CMOS) circuits. Examples of classical circuit elements that can be formed with aluminum include fast single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices, and ERSFQ devices (which are energy-efficient versions of RSFQ that do not use bias resistors). Other classical circuit elements can also be formed with aluminum. Classical circuit elements can be configured to collectively execute instructions of a computer program by performing basic arithmetic, logic, and / or input / output operations on data, where the data is represented in analog or digital form.

[0112] Another example of a superconducting material that can be used to form a quantum circuit element is niobium. Niobium can be used to form wiring, waveguides, inductors, or capacitors. In some embodiments, different types of superconducting materials can be used in the same circuit element. For example, a first type of superconducting material (e.g., niobium) can be used for wiring, waveguides, inductors, capacitors, etc., and a second type of superconductor (e.g., aluminum) can be used to form a Josephson junction.

[0113] The processes described herein may require the deposition of one or more materials, such as superconductors, dielectrics, and / or metals. Depending on the materials selected, these materials may be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques and other deposition processes. The processes described herein may also require the removal of one or more materials from the device during manufacturing. Depending on the material to be removed, the removal process may include, for example, wet etching techniques, dry etching techniques, stripping processes, or chemical mechanical polishing.

[0114] Implementations of the subject matter and operations described in this specification may be implemented in digital electronic circuitry, analog electronic circuitry, suitable quantum circuits (or more generally, quantum computing systems), in tangibly embodied software or firmware, in computer hardware including the structures disclosed in this specification and their structural equivalents, or in a combination of one or more of them. The term "quantum computing system" may include, but is not limited to, a quantum computer, a quantum information processing system, a quantum cryptographic system, or a quantum simulator.

[0115] The terms quantum information and quantum data refer to information or data carried, held, or stored in a quantum system, wherein the smallest non-trivial system is a quantum bit, i.e., a system that defines the unit of quantum information. It is to be understood that the term "quantum bit" encompasses all quantum systems that can be appropriately approximated as a two-level system in the corresponding context. Such quantum systems may include, for example, multi-level systems having two or more energy levels. For example, such systems may include atoms, electrons, photons, ions, or superconducting quantum bits. In many embodiments, the computational basis states are identified as the ground state and the first excited state, however it is to be understood that other arrangements are possible in which higher energy level excited states are used to identify the computational state.

[0116] Quantum circuit elements (also referred to as quantum computing circuit elements) include circuit elements for performing quantum processing operations. That is, quantum circuit elements are configured to exploit quantum mechanical phenomena such as superposition and entanglement to perform operations on data in a non-deterministic manner. Certain quantum circuit elements (such as qubits) can be configured to represent information and operate on information in more than one state at the same time. Examples of superconducting quantum circuit elements include circuit elements such as quantum LC oscillators, qubits (e.g., flux qubits, phase qubits, or charge qubits), and superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUIDs or DC-SQUIDs).

[0117] In contrast, classical circuit elements generally process data in a deterministic manner. Classical circuit elements can be configured to collectively execute the instructions of a computer program by performing basic arithmetic, logic, and / or input / output operations on data, wherein the data is represented in analog or digital form. In some embodiments, classical circuit elements can be used to send data to and / or receive data from quantum circuit elements via electrical or electromagnetic connections. Examples of classical circuit elements include circuit elements based on CMOS circuits, fast single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices, and ERSFQ devices (which are energy-efficient versions of RSFQ that do not use bias resistors).

[0118] In some cases, some or all of quantum and / or classical circuit elements can be implemented using, for example, superconducting quantum and / or classical circuit elements. The manufacture of superconducting circuit elements may require the deposition of one or more materials, such as superconductors, dielectrics and / or metals. Depending on the selected material, these materials can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (such as evaporation or sputtering) or epitaxial techniques and other deposition processes. The process described herein for making circuit elements may need to be removed from the device during manufacture. Depending on the material to be removed, the removal process may include, for example, wet etching techniques, dry etching techniques, stripping processes or chemical mechanical polishing. The material of the circuit element described herein can be patterned using known etching techniques (such as photolithography or electron beam etching) to form a pattern.

[0119] During operation of a quantum computing system using superconducting quantum circuit elements and / or superconducting classical circuit elements (such as the circuit elements described herein), the superconducting circuit elements are cooled in a cryostat to a temperature that allows the superconductor material to exhibit superconducting properties. Superconductor (alternatively, superconducting) materials can be understood as materials that exhibit superconducting properties at or below the superconducting critical temperature. Examples of superconducting materials include aluminum (superconducting critical temperature of 1.2 Kelvin) and niobium (superconducting critical temperature of 9.3 Kelvin). Therefore, superconducting structures such as superconducting traces and superconducting ground planes are formed of materials that exhibit superconducting properties at or below the superconducting critical temperature.

[0120] In certain embodiments, control signals for quantum circuit elements (e.g., qubits and qubit couplers) may be provided using classical circuit elements that are electrically and / or electromagnetically coupled to the quantum circuit elements. The control signals may be provided in digital and / or analog form.

[0121] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of the claimed protection, but should be interpreted as descriptions of features peculiar to a particular embodiment. Certain features described in the context of separate embodiments in this specification may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments, respectively, or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed, one or more features in the claimed combination may be removed from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variant of a sub-combination.

[0122] Similarly, although operations are depicted in a specific order in the accompanying drawings, this should not be understood as requiring to perform such operations in the specific order shown or in a continuous order, or requiring to perform all operations shown to achieve the desired result. In some cases, multitasking and parallel processing can be advantageous. In addition, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems generally can be integrated together in a single software product or packaged into multiple software products.

[0123] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In some cases, multitasking and parallel processing can be advantageous.

Claims

1. A method comprising: providing a substrate including a first resist layer, the first resist layer being patterned to expose an opening region, wherein the opening region includes a central opening portion, a first elongated opening portion, and a second elongated opening portion, the first elongated opening portion having a length extending from a first side of the central opening portion along a first direction, the second elongated opening portion having a length extending from a second side of the central opening portion along a second direction different from the first direction, wherein a width of the first elongated opening portion is smaller than a length of the first side of the central opening portion, and a width of the second elongated opening portion is smaller than a length of the second side of the central opening portion; depositing a first superconductor material on the patterned first resist layer at a first non-normal angle relative to the substrate to form a first superconductor layer within the central opening portion and the first elongated opening portion of the opening region; forming an insulator layer on a portion of the first superconductor layer; depositing a second superconductor material on the insulator layer and the patterned first resist layer at a second non-normal angle relative to the substrate to form a second superconductor layer within the central opening portion and the second elongated opening portion of the opening region, wherein the first superconductor layer, the insulator layer, and the second superconductor layer within the central opening portion provide a superconductor tunnel junction; as well as A third superconductor layer is formed directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconductor tunnel junction and a separate second contact to the superconductor tunnel junction, respectively.

2. The method according to claim 1, wherein the first superconductor layer is formed in a first section of the central opening portion, and wherein the second superconductor layer is formed in a second section of the central opening portion, and wherein the first section of the central opening portion and the second section of the central opening portion only partially overlap. 3 . The method according to claim 2 , wherein the superconductor tunnel junction is formed at a position where the first section of the central opening portion and the second section of the central opening portion partially overlap.

4. The method according to claim 3, wherein the first contact is formed on the surface of the first superconductor layer outside a position where the first section of the central opening portion and the second section of the central opening portion partially overlap, and wherein the second contact is formed on the surface of the second superconductor layer outside a position where the first section of the central opening portion and the second section of the central opening portion partially overlap.

5. The method of claim 4, wherein the first contact is formed on the surface of the first superconductor layer located within the first elongated opening portion, and wherein the second contact is formed on the surface of the second superconductor layer located within the second elongated opening portion.

6. The method of claim 5, wherein the width of the first contact is greater than the width of the first superconductor layer within the first elongated opening portion, and wherein a width of the second contact is greater than the width of the second superconductor layer within the second elongated opening portion.

7. The method of claim 1, wherein forming the third superconductor layer comprises: forming a second resist layer on the first superconductor layer and the second superconductor layer; as well as patterning the second resist layer to form a first contact opening and a second contact opening; as well as The third superconductor layer is deposited on the patterned second resist layer and the second resist layer is removed to form the first contact and the second contact.

8. The method according to claim 7, further comprising: Before depositing the third superconductor layer, ion milling is performed on a surface of the first superconductor layer exposed in the first contact opening and a surface of the second superconductor layer exposed in the second contact opening.

9. The method of claim 1, wherein the first resist layer is patterned using photolithography. 10 . The method of claim 1 , wherein an aspect ratio between a height of the first resist layer and a width of the first elongated opening portion or a width of the second elongated opening portion is between 1:1 and 10:

1.

11. The method according to claim 1, wherein a height of the first resist layer is between 0.1 micrometers and 4 micrometers.

12. A method according to any one of claims 1 to 11, wherein the superconductor tunnel junction forms part of an analog circuit element.

13. A method according to any one of claims 1 to 11, wherein the superconductor tunnel junction forms part of a single flux quantum logic circuit element.

14. A method comprising: providing a substrate including a first resist layer, the first resist layer being patterned to include an open area exposing a surface of the substrate, wherein the open area is laterally surrounded on all sides by the first resist layer; depositing a first superconductor material on the patterned first resist layer along a first direction at a first non-normal angle relative to the substrate to form a first superconductor layer in the opening region, wherein the patterned first resist layer prevents the first superconductor layer from being formed in at least a first portion of the opening region; forming an insulator layer on a portion of the first superconductor layer; depositing a second superconductor material on the insulator layer and the patterned first resist layer in a second direction at a second non-normal angle relative to the substrate to form a second superconductor layer in the opening region, wherein the patterned first resist layer prevents the second superconductor layer from being formed in at least a second portion of the opening region, and wherein the first superconductor layer, the insulator layer, and the second superconductor layer in the opening region provide a superconductor tunnel junction; as well as A third superconductor layer is formed directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconductor tunnel junction and a separate second contact to the superconductor tunnel junction, respectively.

15. The method of claim 14, wherein the first superconductor layer is formed in a first section of the opening region, and wherein the second superconductor layer is formed in a second section of the opening region, and the first section of the opening region and the second section of the opening region only partially overlap. 16 . The method according to claim 15 , wherein the superconductor tunnel junction is formed at a position where the first section of the opening region and the second section of the opening region partially overlap.

17. The method according to claim 16, wherein the first contact is formed on the surface of the first superconductor layer outside a position where the first section of the opening region and the second section of the opening region partially overlap, and The second contact is formed on the surface of the second superconductor layer outside a position where the first section of the opening region and the second section of the opening region partially overlap.

18. The method of claim 14, wherein the first contact extends away from a first side of the opening region, and the second contact extends away from a second, different side of the opening region. The method of claim 18 , wherein the first contact and the second contact extend in orthogonal directions.

20. The method of claim 14, wherein forming the third superconductor layer comprises: forming a second resist layer on the first superconductor layer and the second superconductor layer; as well as patterning the second resist layer to form a first contact opening and a second contact opening; as well as The third superconductor layer is deposited on the patterned second resist layer and the second resist layer is removed to form the first contact and the second contact.

21. The method according to claim 20, further comprising: Before depositing the third superconductor layer, ion milling is performed on a surface of the first superconductor layer exposed in the first contact opening and a surface of the second superconductor layer exposed in the second contact opening.

22. The method of claim 14, wherein the first resist layer is patterned using photolithography.

23. The method of claim 14, wherein the height of the first resist layer is between 0.1 micrometers and 4 micrometers.

24. A method according to any one of claims 14 to 23, wherein the superconductor tunnel junction forms part of an analog circuit element.

25. A method according to any one of claims 14 to 23, wherein the superconductor tunnel junction forms part of a single flux quantum logic circuit element.

26. A device comprising: substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer and the second superconductor layer form a superconductor tunnel junction; as well as A third superconductor layer is directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconductor tunnel junction and a second contact to the superconductor tunnel junction, respectively.

27. The device of claim 26, wherein the first superconductor layer includes a first portion forming a bottom electrode to the superconductor tunnel junction and includes a second portion directly adjacent to the bottom electrode, wherein the first contact is formed directly on the second portion of the first superconductor layer, and wherein the second superconductor layer includes a first portion forming a top electrode to the superconductor tunnel junction and includes a second portion directly adjacent to the top electrode, wherein the second contact is formed directly on the second portion of the second superconductor layer.

28. The device of claim 27, wherein the second portion of the first superconductor layer comprises a corresponding wide segment and a corresponding narrow segment, the narrow segment having a length extending outwardly from the wide segment of the first superconductor layer, and The second portion of the second superconductor layer includes a corresponding wide section and a corresponding narrow section, the narrow section having a length extending outward from the wide section of the second superconductor layer.

29. A device as claimed in claim 28, wherein the superconductor tunnel junction forms part of an amplifier circuit element.

30. The device of claim 28, wherein the superconductor tunnel junction forms part of an analog circuit element.

31. The device of claim 28, wherein the superconductor tunnel junction forms part of a single-flux quantum logic circuit element.

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