Phase change memory system, phase change memory device and refresh method thereof

Abstract

A phase change memory system includes a phase change memory device including a plurality of memory cells including a plurality of memory elements in units of at least one or more codewords, and a phase change memory controller performing a chip refresh operation for refreshing the entire phase change memory device, wherein the phase change memory device includes a setting circuit determining one of the plurality of memory cells in a desired manner, a refresh controller refreshing the determined memory cell, a sensing circuit sensing data of the at least one or more codewords included in the refreshed memory cell, and a request circuit requesting the chip refresh operation to a host based on a result of the sensing operation.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0129762, filed on October 18, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] Various example embodiments of inventive concepts relate to a phase change memory system, a phase change memory device, and / or a method for refreshing a phase change memory device. BACKGROUND

[0003] Based on and / or depending on a resistance value and / or a voltage value, in a phase change memory device using a variable resistance element (GST) and an access element (a voice threshold switch: OTS), a memory element can have a set state value and / or a reset state value. A voltage difference applied to the memory element moves in an increasing direction due to element characteristics, which is defined as a drift phenomenon. Due to the drift phenomenon of the memory element, an error can occur in a data sensing operation of a memory cell.

[0004] In order to reduce and / or prevent such an error, a refresh operation that increases a voltage difference to an original state can be performed. However, since a voltage value as a sensing criterion and a drift degree are different for each memory element, a timing of a refresh operation that reduces and / or prevents a sensing error is expected and / or required to be different for each memory element. Accordingly, a refresh operation that reflects a state of a memory cell is expected and / or required. SUMMARY

[0005] Aspects of at least one example embodiment of inventive concepts provide a phase change memory system in which a possibility of a sensing error is low by reflecting a state of a memory element in a phase change memory device and performing a refresh operation at an appropriate time.

[0006] Aspects of at least one example embodiment of inventive concepts also provide a phase change memory system that detects a memory cell in a memory device that exhibits a sensing error due to a factor other than a drift in a phase change memory device.

[0007] However, aspects of at least one example embodiment of inventive concepts are not limited to the aspects set forth herein. The above and other aspects of at least one example embodiment of inventive concepts will become more apparent to those skilled in the art from the following detailed description of example embodiments of inventive concepts, given by way of example, taken in conjunction with the accompanying drawings.

[0008] According to some aspects of at least one of the example embodiments of the present inventive concepts, there is provided a phase change memory system including a phase change memory controller configured to perform a chip refresh operation for refreshing a phase change memory device including a plurality of memory elements of at least one or more codewords, the phase change memory device including a control logic circuit configured to determine memory cells of the plurality of memory elements including at least one codeword, perform a refresh operation on the determined memory cells, perform a sensing operation on data of the memory cells, and request the chip refresh operation to a host based on a result of the sensing operation.

[0009] According to some aspects of at least one of the example embodiments of the present inventive concepts, there is provided a method of refreshing a phase change memory device, the method including determining, using a control logic circuit, memory cells of a plurality of memory elements of the phase change memory device including a plurality of codewords, performing, using the control logic circuit, a refresh operation on the memory cells based on a sensing voltage for reading data stored in a first codeword of the plurality of codewords and a desired reference voltage, performing, using the control logic circuit, a sensing operation on data of the plurality of codewords included in the memory cells, and performing, using the control logic circuit, a refresh operation on the entire phase change memory device based on a result of the sensing operation.

[0010] According to some aspects of at least one of the example embodiments of the present inventive concepts, there is provided a phase change memory system including an array of phase change memory elements including at least one codeword, a host including a phase change memory controller configured to perform a chip refresh operation for refreshing the entire array of phase change memory elements, and a control logic circuit configured to sense data of the at least one codeword of the array of phase change memory elements and transmit a request for the chip refresh operation to the host based on a result of the sensing.

[0011] DETAILED DESCRIPTION AND SPECIFIC DETAILS OF OTHER ASPECTS OF THE EXAMPLE EMBODIMENTS INCLUDING IN THE DRAWINGS. BRIEF DESCRIPTION OF DRAWINGS

[0012] The above and other aspects and features of the example embodiments of the present inventive concepts will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0013] Figure 1 is a graph for explaining a differential change of a phase change memory element due to a drift phenomenon according to at least one of the example embodiments;

[0014] Figure 2 and Figure 3 is a graph for explaining a refresh operation according to a differential change of a phase change memory element according to at least one of the example embodiments;

[0015] Figure 4 is a block diagram schematically illustrating a system of a phase change memory device according to some example embodiments;

[0016] Figure 5 is a block diagram schematically illustrating a phase change memory device according to some example embodiments;

[0017] Figure 6 is a diagram schematically illustrating an array of memory elements in a phase change memory device according to some example embodiments;

[0018] Figure 7 is a flowchart for illustrating a refresh operation of a phase change memory device according to some example embodiments;

[0019] Figure 8 is a diagram for illustrating a condition for performing a partial refresh operation according to some example embodiments;

[0020] Figure 9 is a flowchart illustrating a memory element read operation according to some example embodiments;

[0021] Figure 10 is a diagram for illustrating a memory element read operation according to some example embodiments;

[0022] Figure 11 is a diagram for illustrating a correction of a sense voltage according to some example embodiments;

[0023] Figure 12 is a flowchart illustrating a partial refresh operation according to some example embodiments;

[0024] Figure 13 is a diagram for illustrating an example of a memory cell determination according to some example embodiments;

[0025] Figure 14 is a diagram for illustrating an example of a memory cell determination according to some example embodiments;

[0026] Figure 15 is a diagram illustrating a memory cell replacement operation according to some example embodiments;

[0027] Figure 16 is a diagram for illustrating a chip refresh request operation according to some example embodiments; and

[0028] Figure 17 is a diagram for illustrating an effect of a memory system according to some example embodiments. DETAILED DESCRIPTION

[0029] In the following, various example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0030] Figure 1 is a graph for explaining a difference in a change of a phase change memory element due to a drift phenomenon according to at least one example embodiment. The phase change memory element can store different data according to a resistance value of a phase change material. A voltage value applied to the phase change memory element also changes with a change in the resistance value.

[0031] For example, the phase change material becomes a crystalline state when slowly cooled after being heated, and becomes an amorphous state when rapidly cooled. The phase change material in the crystalline state has a low resistance, and the phase change material in the amorphous state has a high resistance.

[0032] Accordingly, when a current and / or a voltage is applied to a resistive material (e.g., a phase change material), a voltage applied to the phase change material in the crystalline state can be low, and a voltage applied to the phase change material in the amorphous state can be high. Accordingly, the crystalline state can be defined as a set data or "0" data, and the amorphous state can be defined as a reset data or "1" data, etc.

[0033] The voltage applied to the memory cell can be shown as a voltage difference value at time t1. If a lower voltage value is applied to the memory cell near the common middle point V cmp around the initial time t1, it can be determined that set data or 0 data has been input to the memory element. If a higher voltage value is applied, it can be determined that reset data or 1 data has been input to the memory element. In other words, the memory cell can be read based on the voltage value applied to the memory element, in which a lower voltage value is used to read a set data (e.g., 0 data) value, and a higher voltage value is used to read a reset data (e.g., 1 data) value, etc. Further, the common middle point V cmp of the initial voltage difference can be used as a sensing voltage.

[0034] The temperature, structure, etc. of the phase change material can change over time. The resistance value of the phase change material of the phase change memory element can change over time, or in other words, the resistance value of the phase change memory element can change over time. Accordingly, as described above, the voltage difference of the memory element can change due to a change in the resistance value. Factors thereof can include a temperature change of the phase change material, a structural relaxation process, etc.

[0035] For example, while structural defects of the phase change material can be eliminated according to a time change and / or a continuous operation of the phase change memory device, the resistance of the phase change material can also change over time, and thus, the voltage distribution applied to the memory cell and the common middle point V cmp may change. This change in the voltage difference can be referred to as a drift.

[0036] As an example, with a phase change memory device as Figure 1The voltage difference of the memory element changes in an increasing direction from tl to t3, or in other words, the voltage can increase over time. However, the manner in which the voltage difference of the memory element changes is not limited thereto, and can also include a decreasing direction, etc. While an increase in the voltage difference of the memory element will be described below, the technical idea of the example embodiments of the inventive concept is not limited thereto, and can also be applied to a case in which the voltage difference of the memory element also decreases.

[0037] While the voltage difference increases at t3, if the criterion for data sensing is the same as the sensing voltage V cmp at time tl, an error can occur in data sensing (e.g., a read operation, etc.) of the memory element. Accordingly, it is desirable and / or necessary to reduce the likelihood of such an error occurring.

[0038] Figure 2 and Figure 3 is a graph for illustrating a refresh operation according to a change in the difference of a phase change memory element according to some example embodiments.

[0039] A method of reducing the likelihood of an error occurring due to drift includes a refresh operation. The voltage difference of the memory element can be initialized by the refresh operation.

[0040] Since the chip refresh operation is performed by the host at a period T, the chip refresh operation is performed on the entire memory device, and the operation of the memory device is stopped while the chip refresh operation is performed. If the chip refresh operation is performed again at time t" (t" « t) after any chip refresh operation is performed, the operation of the memory device can be stopped for more than a desirable and / or necessary time. Accordingly, the operation efficiency of the memory device can be reduced, slowed, and / or inefficient, etc.

[0041] In addition, the memory element drifts at t' which is earlier than time A than the period T, and an error can occur in the data of many memory elements. In this case, the memory device cannot normally operate in the [t', t] section, etc. Accordingly, considering the state of the memory element, it can be desirable and / or necessary to perform a chip refresh operation, etc.

[0042] Figure 4 is a block diagram schematically illustrating a phase change memory system according to some example embodiments. Reference is made to Figure 4A phase change memory system according to some example embodiments can include a host 100 and / or a memory device 200, but is not limited thereto, and can include other constituent components. The host 100 can include a memory controller 110 having access and / or read authority to the memory device 200, etc. A bus 300 for signal and data exchange can be provided between the host 100 and the memory device 200, etc.

[0043] The host 100 can execute various applications according to a user's request. The host 100 can load and execute an application in the memory device 200 to execute the application.

[0044] The host 100 can execute an operating system (OS), and can execute various software applications on the operating system (OS). For such operations, the host 100 can write data on the memory device 200, read data and / or erase data stored in the memory device 200, etc.

[0045] In addition, the host 100 transmits a command CMD for a refresh operation of the memory device 200 through the memory controller 110, and can perform the refresh operation on the entire memory elements of the memory device 200. Further, a state of the memory device 200 and a refresh operation request can be read through the memory controller 110.

[0046] The memory device 200 can be a main memory of an electronic device, an auxiliary memory of an electronic device, etc. When the electronic device is booted, an operating system (OS), a basic application program, etc. are loaded into the memory device 200.

[0047] For example, when the host 100 is booted, an OS image stored in a non-volatile memory (not shown) can be loaded into the memory device 200 based on a booting sequence. The operating system can support all input and / or output operations of the host 100.

[0048] Similarly, an application program can be loaded into the memory device 200 for a selected user and / or for providing a basic service (e.g., a background service, etc.). The memory device 200 can also be used as a buffer memory for storing video data to be provided from an image sensor such as a camera, etc.

[0049] The memory device 200 can be a phase change memory device (PRAM) capable of performing byte access. The memory device 200 can also be provided as a non-volatile memory device capable of performing rewriting.

[0050] For example, the memory device 200 can be a non-volatile RAM such as a PRAM, a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM or RRAM), a ferroelectric RAM (FRAM), and / or a NOR flash memory, etc., but example embodiments are not limited thereto. The memory device 200 stores an operating system (OS), at least one running application, data, updated data, etc., when the electronic device is executed and / or when the electronic device is powered off.

[0051] The memory device 200 can be provided in the form of a multi-chip package and / or a module in which memory multi-chips are stacked. However, the configuration method of the memory device 200 is not limited thereto, and although a case in which the memory device 200 is a PRAM will be described below, the technical idea of example embodiments of the inventive concept is not limited thereto.

[0052] The bus 300 can provide a transmission path for data and / or signals on the host 100 and / or the memory device 200. Although Figure 4 Although a single bus is illustrated in FIG. 3, example embodiments are not limited thereto, and can also include a case in which a plurality of buses are included. When a plurality of buses 300 are present, the memory device 200 can be controlled according to a channel interleaving method, etc., a plurality of hosts and / or memory devices can communicate with each other, and / or the memory device 200 and the host 100 can independently transmit data through a plurality of buses, etc.

[0053] Figure 5 FIG. 4 is a block diagram schematically illustrating a phase change memory device according to some example embodiments. Figure 6 FIG. 5 is a diagram schematically illustrating an array of memory elements in a phase change memory device according to some example embodiments.

[0054] Referring to Figure 5 and Figure 6 The memory device according to at least one example embodiment of the inventive concept can include an array of memory elements 210, a column decoder 212, a row decoder and driver 213, a write driver 214, a sensing circuit 215, an address register 216, and / or a control logic circuit 220, but example embodiments are not limited thereto, and can include a greater or lesser number of constituent elements.

[0055] The memory device 200 can be implemented as only a single layer of an array of memory elements, and can also be implemented by stacking a plurality of arrays of memory elements in a three-dimensional manner, but example embodiments are not limited thereto. The array of memory elements 210 can include a single memory element 211 connected to a single word line WL selected based on a row address XADD, and a single bit line BL selected based on a column address YADD, etc.

[0056] Each memory element 211 can include a variable resistance element GST including a phase change material, an access element OTS for controlling current flowing through the variable resistance element GST, and / or the like.

[0057] For the phase change material of the memory element, for example, various materials obtained by combining two elements, such as GaSb, InSb, InSe, Sb2Te3, and / or GeTe, and / or the like, GeSbTe, GaSeTe, InSbTe, SnSb2Te4, and / or InSbGe obtained by combining three elements, and / or AgInSbTe, (GeSn)SbTe, GeSb(SeTe), Te81Ge15Sb2S2, and / or the like obtained by combining four elements can be used, although example embodiments are not limited thereto.

[0058] In some example embodiments, GeSbTe including germanium (Ge), antimony (Sb), and tellurium (Te) can be used as the phase change material, although example embodiments are not limited thereto. The access element OTS can be a diode and / or a transistor (not shown) connected in series with the variable resistance element GST and / or the like.

[0059] In the case of RRAM, the variable resistance element GST can include a complex metal oxide and / or the like. If the resistance memory element RMC is RRAM, the resistance memory element RMC can include, for example, NiO, a perovskite, and / or the like. A filament can be formed in the variable resistance element GST, and the filament can be a current path of a unit element current flowing through the memory element. In some example embodiments, if the memory element RMC is RRAM, the access element for controlling current flowing through the variable resistance element GST can be omitted.

[0060] In the case of MRAM, the variable resistance element GST can include a magnetic upper electrode, a magnetic lower electrode, a dielectric, and / or the like therebetween.

[0061] The memory element array 210 can be divided into a plurality of memory blocks BLK, and each memory block can be divided into a plurality of memory banks and a plurality of memory pages, and / or the like.

[0062] Further, the memory element array 210 includes a plurality of memory units (e.g., a memory set, such as a group of memory blocks, memory banks, memory pages, word lines, codewords, and / or the like) to be partially refreshed, which will be described below in at least one example embodiment of the inventive concept. That is, in at least one example embodiment of the inventive concept, a refresh operation can be performed on a memory unit (e.g., a memory set, a memory unit set, and / or the like) by determining in units of memory units. The memory unit can be divided in units of memory blocks, memory banks, memory pages, word lines, and / or codewords, and / or the like, and / or can be set by grouping them into a plurality.

[0063] The column decoder 212 can decode a column address YADD output from the address register 216 and select at least one bit line (or column) from among a plurality of bit lines BL.

[0064] The row decoder and driver 213 can decode a row address output from the address register 216 and select at least one word line (or row) from among a plurality of word lines WL. The write driver 214 can write data onto the memory elements selected by the column decoder 212, the row decoder and driver 213.

[0065] The sensing circuit 215 can perform a read operation for sensing (e.g., reading) data stored in the memory elements 211 and a verify read operation for detecting errors in data when sensed (e.g., detecting errors in data written into the memory elements 211, etc.). In sensing operations according to some example embodiments, data stored in the memory elements 211 can be sensed in units of codewords, but is not limited thereto. According to at least one example embodiment, the sensing circuit 215 can be processing circuitry, which can include hardware including logic circuitry; a hardware / software combination, such as at least one processor executing software; or a combination thereof. In addition, the sensing circuit 215 can be separate from or included in the control logic circuit 220.

[0066] A codeword can include data bits and error correction code (ECC) bits, but is not limited thereto. In sensing a codeword, a function of correcting errors in some memory elements corresponding to the codeword using the ECC bits can be performed. The ECC bits can include RS (Reed-Solomon) code bits, Hamming code bits, BCH (Bose-Chaudhuri-Hocquenghem) code bits, CRC (Cyclic Redundancy Code) bits, etc. However, the ECC code according to example embodiments is not limited thereto.

[0067] However, the number of error bits that can be corrected using the ECC bits is limited. For example, up to 10 bits of errors in one codeword can be corrected by detection using a specific ECC bit. When 10 or more errors occur, errors of the codeword can not be corrected, and sensing of the codeword by the sensing circuit 215 can fail and / or can not correctly read data of the codeword.

[0068] As described above, when drift occurs and the voltage difference of the memory elements 211 included in the codeword increases, data errors occur in multiple memory cells, and the sensing of the codeword may fail and / or the data in the memory elements 211 may not be read correctly. Furthermore, depending on the type and / or number of ECC bits included in the memory elements 211, not only the number of error bits but also the position of the error bits in the codeword may affect whether the codeword detection passes or fails (e.g., correct reading or reading failure).

[0069] The control logic circuit 220 may include a refresh controller 221, a setting circuit 222, a correction circuit 223, a request circuit 224, and a detection circuit 225. The control logic circuit 220 may be a processing circuit and may include hardware with logic circuitry; a hardware / software combination, such as at least one processor executing software; or a combination thereof. For example, the control logic circuit 220 may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. Furthermore, the refresh controller 221, setting circuit 222, correction circuit 223, request circuit 224, and detection circuit 225 may also include hardware with logic circuitry; a hardware / software combination, such as at least one processor executing software; or a combination thereof, or may be integrated into the control logic circuit and / or may be dedicated programming executed by the control logic circuit 220.

[0070] The refresh controller 221 can perform a refresh operation on a specific memory cell in the memory element array 210. The setting circuit 222 can designate a portion of the memory element array 210 as a memory cell by a user-desired and / or predetermined method. Taking into account the voltage difference of the memory cells, the correction circuit 223 can correct the sensing voltage used to sense the memory element 211.

[0071] Request circuit 224 can pass Figure 4 The bus 300 sends a chip refresh operation request to the host 100, and / or sends the status of memory elements or memory cells to the host via the bus 300. The detection circuit 225 can determine whether the sensed voltage is equal to and / or higher than the reference voltage, which will be described below.

[0072] Figure 7 This is a flowchart illustrating the refresh operation of a phase-change memory device according to some example embodiments. (Reference) Figure 4 , Figure 5 and Figure 7, the sensing circuit 215 reads data of the codeword of the memory element of the address sent to the address register 216 (S110). The memory element read operation of the sensing circuit 215 will be described in detail below with reference to Figures 9 to 11 The memory element read operation of the sensing circuit 215 will be described in detail below.

[0073] The detection circuit 225 determines the common midpoint V cmp of the voltage difference of the memory elements is higher than a user desired and / or predetermined reference voltage V cmd_ref (S120).

[0074] Figure 8 is a diagram for illustrating a condition for performing (S140) a partial refresh operation according to some example embodiments.

[0075] Additionally referring to Figure 8 , when the detection circuit 225 determines that the common midpoint V cmp of the voltage difference of the memory elements is less than (e.g., lower than) a user desired and / or predetermined reference voltage Vcmd_ref, the request circuit 224 transmits the state of the memory elements to the host 100 (S130).

[0076] After transmitting the data to the host, the detection circuit 225 can perform an operation of reading data of the codeword of the memory element of the address transmitted to the address register 216 (S110), and can repeat the operation until it is determined that the common midpoint V cmp of the voltage difference of the memory elements is greater than a user desired and / or predetermined reference voltage V cmd_ref .

[0077] If the detection circuit 225 determines that the common midpoint V cmp of the voltage difference of the memory elements is higher than a user desired and / or predetermined reference voltage V cmd_ref , the memory device 200 performs a partial refresh operation (S140). The partial refresh operation will be described in detail below in the detailed description of Figures 12 to 17 .

[0078] Figure 9 is a flowchart for illustrating a memory element read operation according to some example embodiments.

[0079] Figure 10 is a diagram for illustrating a memory element read operation according to some example embodiments.

[0080] Figure 11 is a diagram for illustrating correction of a sensing voltage according to some example embodiments.

[0081] Referring to Figure 5 and Figures 9 to 11The sensing circuit 215 reads the data of the codeword on the memory element (S111).

[0082] After the reading operation of the sensed data, the sensed circuit 215 determines whether there is an error in the sensed data on the codeword (S112).

[0083] As an example of determining data, when the voltage applied to the memory element is less than the sensing voltage during the period when the memory element in the sensing codeword indicates the state of the set data (e.g., Figure 10 When the voltage applied to the memory element is greater than the sensing voltage during the period when the memory element is sensed to indicate the state of reset data, the sensing circuit 215 can consider the codeword to have passed sensing (e.g., sensing passed, data read correctly, etc.).

[0084] When multiple memory elements exceeding the maximum number of error correction bits in the codeword are sensed to indicate the state of set data, there exists a voltage greater than the sensed voltage in a portion of the memory elements. Figure 10 V cmp When the difference A value is less than the sensing voltage (default value), or during a state where a memory element is sensed to indicate reset data (e.g., sensing failed, etc.), the voltage applied to the memory element is less than the sensing voltage (default value). Figure 9 V cmp When the difference (default value) is less than or equal to the value of the codeword corresponding to the memory element, the sensing circuit 215 may not need to sense the codeword (e.g., failed read).

[0085] If the sensing circuit 215 determines that an error exists in the codeword reading operation, the sensing circuit 215 performs an operation on the sensed voltage V. s Correction (S113).

[0086] when Figure 11 When considered as an example of some example embodiments, if the common intermediate point V before the voltage difference changes cmp If ΔV changes as the voltage difference in the memory element changes, the sensing circuit 215 may fail to sense the codeword (e.g., fail to sense, etc.).

[0087] If sensing fails, then, according to at least one example embodiment, an action can be taken to make the sensing voltage of the memory element in the codeword (e.g., increase the sensing voltage, etc.) equal to the upward common intermediate point V. cmp 'Upward correction'.

[0088] The correction circuit 223 can be corrected as follows, so that the common intermediate point V changes according to Formula 1. cmp 'Equivalent to the sensed voltage Vs.

[0089] V cmp ’ = V cmp + ΔV [Equation 1]

[0090] When the voltage difference of the memory elements moves to the right (e.g., the voltage increases), the common intermediate point moves from V cmp to V cmp ’, and the sensing voltage V s may also be corrected upward accordingly (e.g., can increase).

[0091] Figure 12 is a flowchart for illustrating a partial refresh operation according to some example embodiments.

[0092] Referring to Figure 2 and Figure 12 , the setting circuit 222 can determine (e.g., set, designate, etc.) the memory cells present in the memory element array 210 (S141). The setting circuit 222 can set, designate, and / or determine the memory elements in the memory element array 210 by sampling a plurality of memory cells in the memory element array 210, while including the memory elements that satisfy the condition in operation S120. Figure 8

[0093] The determination method of the memory cells to be partially refreshed is performed in a manner pre-designated by a user, and the setting circuit 222 can determine one of a plurality of memory cells included in the memory element array 210.

[0094] Figure 13 is a diagram illustrating an example of memory cell determination according to some example embodiments. Referring to Figure 13 , the setting circuit 222 can determine a single memory cell by sampling the memory elements connected to the word line WL1, including the memory element 211 that has performed operation S120. Figure 7 The memory elements can be configured in a codeword unit, but example embodiments are not limited thereto, and other memory cells can be used.

[0095] Figure 14 is a diagram illustrating an example of memory cell determination according to some example embodiments. Referring to Figure 14 , the setting circuit 222 can sample the memory elements connected to the blocks WL1, WL2, BL1, and BL2, etc., including the memory element 211 that has performed operation S120, and determine (e.g., set, designate, etc.) them as a single memory cell, but example embodiments are not limited thereto. Figure 7

[0096] ​​In addition to the example embodiments described above, the memory cells can be determined by sampling in units of one or more memory pages, and / or the memory cells can be determined by sampling in units of one or more memory banks, etc., but the example embodiments are not limited thereto.

[0097] The memory cells can be determined by sampling in units of one or more error correction units of codewords in which the data bits are 256 or less, but the example embodiments are not limited thereto. Thus, since the sampling and the refresh can be performed in units that can be corrected by the error correction code, it is possible to further reduce the likelihood that sensing errors occur. In other words, the size of the memory cells for the sampling operation and / or the refresh operation can be set based on the expectation of successful error correction operations of the memory device and / or the maximum storage size.

[0098] In addition, the memory cells can be determined (e.g., set, determined, assigned, etc.) by including a desired and / or predefined partial memory area in the memory device 200 without performing the sampling operation.

[0099] The refresh controller 221 can perform a refresh operation (S142) for initializing the voltage difference value of the determined (S141) memory cells. After performing the refresh operation (S142), the sensing circuit 215 detects whether an error has occurred in the sensing operation based on the common midpoint Vcmp (default value) of the initial voltage difference value of the memory elements cmp (S143).

[0100] Figure 15 is a diagram for explaining a memory cell replacement operation according to some example embodiments. Further reference is made to Figure 15 The sensing circuit 215 can determine the sensing error based on the common midpoint Vcmp (default value).

[0101] If a plurality of codewords having a desired and / or predetermined ratio or greater in the memory cells fail the sensing (e.g., fail the sensing operation and / or are unsuccessful, etc.), since it can not be determined that a change in the voltage difference value of the memory elements has occurred due to drift, the request circuit 224 transmits the data of the memory cells to the host 100 (S144). Even if one codeword in the memory cells fails the sensing, the request circuit according to some other example embodiments can transmit the data of the memory cells to the host. In other words, the sensing circuit 215 can determine the ratio of the memory cells (and / or sub-cells of the memory cells) that pass the sensing operation. Based on a comparison of the determined ratio with a desired sensing operation ratio threshold, the request circuit transmits the read data to the host or requests a partial or full refresh operation.

[0102] In addition to drift, a factor of a change in a voltage difference of a memory element can also be determined as a factor such as a physical crack and / or disconnection of a phase change material in a memory element and / or a thin film in a memory element.

[0103] Accordingly, the host 100 can transmit a command (e.g., a memory cell replacement CMD, etc.) to the memory device 200 that replaces the function and / or operation of the memory cell with another memory cell in the memory device 200 (S145).

[0104] Figure 16 is a diagram for illustrating a chip refresh request operation according to some example embodiments. Further reference is made to Figure 16 , the sensing circuit 215 can determine a sensing error based on a common intermediate point V -cmp (default value).

[0105] If a desired and / or predetermined ratio or greater ratio of codewords in a memory cell pass the sensing operation (e.g., if a desired number of codewords in a total number of codewords in a memory cell pass the sensing operation, etc.), the memory device 200 can determine that a change in a voltage difference of a memory element has occurred due to drift. As an example, if all codewords in a memory cell pass the sensing operation, the memory device 200 can similarly determine that a change in a voltage difference of the memory cell has occurred due to drift. Accordingly, the request circuit 224 requests a chip refresh operation from the host 100 for refreshing the entire memory element array 210 (S146). In accordance with the host chip refresh request, a refresh command CMD is transmitted to the memory device 200.

[0106] Figure 17 is a diagram for illustrating an effect of a phase change memory system according to some example embodiments.

[0107] Reference is made to Figure 4 , Figure 5 and Figure 17 , the memory device 200 according to some example embodiments can perform a chip refresh operation on the entire memory element array 210 with a period T.

[0108] In a phase change memory system according to some example embodiments, the sensing circuit 215 and the control logic circuit 220 operate at a time t' which is a time A shorter than the period T after performing the arbitrary chip refresh operation 1 and the chip refresh operation 2. Thus, in the part [t', t], it is possible to reduce and / or prevent an error in data sensing of a codeword of a memory element due to drift in the memory element in the memory device 200. It is possible to reduce the possibility of an operation of the memory device 200 occurring an error. The chip refresh operation 2 is performed at t', and it is possible to perform the chip refresh operation at a cycle period T from the start of the chip refresh. Thereafter, it is possible to perform the chip refresh operation at t'" after T time from t'.

[0109] In a phase change memory system according to some other example embodiments, since the time A is less than half of the period T, after the chip refresh operation 1 is initially performed after the memory device 200 is powered on, the sensing circuit 215 and the control logic circuit 220 operate at t' which is a fixed time A shorter than the period T, and it is possible to perform the chip refresh operation 2.

[0110] In a phase change memory system according to some other example embodiments, the time A is less than half of the period T, after half of the period T elapses, the sensing circuit 215, the refresh controller 221, the setting circuit 222, the correction circuit 223, and the request circuit 224 operate, and it is possible to perform the chip refresh operation 2 at t'.

[0111] At the end of the detailed description, it will be understood by those of ordinary skill in the art that many variations and modifications can be made to the example embodiments without substantially departing from the principles of the inventive concepts. Therefore, the disclosed example embodiments of the inventive concepts are used only in a generic and descriptive sense, and not for purposes of limitation.

Claims

1. A phase change memory system, comprising: a phase change memory controller configured to perform a chip refresh operation for refreshing an entire phase change memory device; and the phase change memory device comprising a plurality of memory elements of at least one codeword, the phase change memory device comprising a control logic circuit configured to: determine memory cells of the plurality of memory elements comprising at least one codeword; perform a refresh operation on the determined memory cells, perform a sense operation on data of the memory cells, determine whether the sense operation is successful based on a sense voltage of the sense operation, a desired reference voltage, and a result of the sense operation; and request the chip refresh operation to a host based on a result of determining that the sense operation is successful.

2. The phase change memory system of claim 1, wherein the control logic circuit is further configured to: determine a ratio of codewords of the memory cells that successfully pass the sense operation; request the chip refresh operation based on the determined ratio of the memory cells and a desired threshold; and in response to the determined ratio being less than the desired threshold, send information corresponding to the memory cells to the host.

3. The phase change memory system of claim 2, wherein the control logic circuit is further configured to: increase a sense voltage for a sense operation of the at least one codeword of the memory cells; and determine whether the sense voltage is equal to or higher than a desired reference voltage.

4. The phase change memory system of claim 3, wherein the phase change memory controller is further configured to: perform the chip refresh operation based on a desired period; and after performing the chip refresh operation and before a next period of the desired period arrives, the phase change memory controller is configured to control the control logic circuit to determine the memory cells, perform the refresh operation, perform the sense operation, and request the chip refresh operation again.

5. The phase change memory system of claim 4, wherein a size of the memory cells is based on any one of a plurality of pages, word lines, memory banks, or memory blocks.

6. The phase change memory system of claim 4, wherein the memory cells comprise codewords having 256 bits or less of data bits.

7. The phase change memory system of claim 3, wherein after the phase change memory device is powered on and initially performs the chip refresh operation, the control logic circuit is further configured to operate after a desired amount of time elapses, the desired amount of time being less than a desired period for performing the chip refresh operation.

8. The phase change memory system of claim 1, wherein the phase change memory controller is further configured to perform the chip refresh operation based on a desired period, and after the chip refresh operation is performed, the control logic circuit is further configured to operate after half of the period elapses and before a next period arrives.

9. The phase change memory system of claim 1, wherein the control logic circuit is further configured to: increasing a sense voltage for sensing the codeword; and determining whether the sense voltage is equal to or higher than a desired reference voltage.

10. The phase change memory system of claim 1, wherein the control logic circuit is further configured to: in response to none of the at least one codeword of the memory cell passing the sense operation, send information of the memory cell to a host; and in response to all of the at least one codeword of the memory cell successfully passing the sense operation, request the chip refresh operation to a host.

11. The phase change memory system of claim 1, wherein the control logic circuit is further configured to set a portion of memory region of the memory cell without performing a sampling operation.

12. A method of refreshing a phase change memory device, the method comprising: determining, using a control logic circuit, a memory cell of a plurality of memory elements of a phase change memory device that includes a plurality of codewords; performing, using the control logic circuit, a refresh operation on the memory cell based on a sense voltage for reading data stored in a first codeword of the plurality of codewords and a desired reference voltage; performing, using the control logic circuit, a sense operation on data of the plurality of codewords included in the memory cell; determining, based on a sense voltage of the sense operation, a desired reference voltage, and a result of the sense operation, whether the sense operation is successful; and performing, using the control logic circuit, a refresh operation on the entire phase change memory device based on a result of determining that the sense operation is successful.

13. The method of refreshing a phase change memory device of claim 12, wherein based on the result of the sense operation: in response to a ratio of a number of codewords of the memory cell that successfully pass the sense operation being greater than or equal to a desired threshold, performing, using the control logic circuit, the refresh operation on the entire phase change memory device; and in response to the ratio of the plurality of codewords of the memory cell being less than the desired threshold, sending, using the control logic circuit, information of the memory cell to a host.

14. The method of refreshing a phase change memory device of claim 13, further comprising: in response to the first codeword not passing the sense operation, increasing a sense voltage corresponding to the first codeword according to a changed voltage discrete value.

15. The method of refreshing a phase change memory device of claim 14, wherein a size of the plurality of codewords of the memory cell is 256 bits or less.

16. The method of refreshing a phase change memory device of claim 12, wherein based on the result of the sense operation: in response to at least one codeword of the plurality of codewords of the memory cell not passing the sense operation, sending, using the control logic circuit, information of the memory cell; and in response to all of the codewords of the memory cell passing the sense operation, performing, using the control logic circuit, a refresh operation.

17. A phase change memory system, comprising: an array of phase change memory elements including at least one codeword; ​ a host including a phase change memory controller configured to perform a chip refresh operation for refreshing an entire array of phase change memory elements; and control logic circuitry configured to: sense data of the at least one codeword of the array of phase change memory elements, determine whether the sensing was successful based on a sensing voltage used in the sensing, a desired reference voltage, and a result of the sensing; and send a request for the chip refresh operation to the host based on a result of determining that the sensing was successful.

18. The phase change memory system of claim 17, wherein the control logic circuitry is further configured to: send a request for the chip refresh operation in response to a ratio of at least one codeword in a memory cell that successfully passed the sensing being greater than a desired threshold; and send information of the memory cell to the host in response to the ratio of the at least one codeword being less than or equal to the desired threshold.

19. The phase change memory system of claim 18, wherein the phase change memory controller is configured to perform the chip refresh operation based on a desired period; and the control logic circuitry is further configured to operate after the chip refresh operation is performed and before a next period of the desired period arrives.

20. The phase change memory system of claim 18, wherein a size of the at least one codeword is 256 bits or less.

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