Fin field effect transistor device and method for forming the same

Abstract

The present disclosure relates to a fin field effect transistor device and a method for forming the same. A method for forming a semiconductor device includes: surrounding a dummy gate disposed above a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing an upper portion of a first gate spacer disposed along a sidewall of the dummy gate, the gate trench including a lower trench located between remaining lower portions of the first gate spacer and including an upper trench located above the lower trench; sequentially forming a gate dielectric layer, a work function layer, and a glue layer in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removal; and removing the gate electrode material from the upper trench, the remaining portion of the gate electrode material forming a gate electrode.

Description

Technical Field

[0001] The present disclosure generally relates to FinFieldEffectTransistor devices and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this increase in integration density comes from the ever-decreasing minimum feature size, which allows more components to be integrated into a given area.

[0003] Fin field effect transistor (FinFET) devices are becoming common for integrated circuits. FinFET devices have a three-dimensional structure that includes a semiconductor fin protruding from a substrate. A gate structure configured to control the flow of charge carriers within a conductive channel of the FinFET device surrounds the semiconductor fin. For example, in a tri-gate FinFET device, the gate structure surrounds three sides of the semiconductor fin, thereby forming a conductive channel on the three sides of the semiconductor fin. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, the method comprising: surrounding a dummy gate disposed above a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing an upper portion of a first gate spacer disposed along a sidewall of the dummy gate, the gate trench comprising a lower trench located between remaining lower portions of the first gate spacer and comprising an upper trench located above the lower trench; sequentially forming a gate dielectric layer, a work function layer, and a glue layer in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removal; and removing the gate electrode material from the upper trench, the remaining portion of the gate electrode material forming a gate electrode.

[0005] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a gate trench in a dielectric material by removing a dummy gate and by removing an upper portion of a first gate spacer surrounding the dummy gate, wherein the gate trench comprises a lower trench located between remaining lower portions of the first gate spacer and comprises an upper trench located above the lower trench; lining the sidewalls and bottom of the gate trench by sequentially forming a gate dielectric layer, a work function layer, a cap layer and a first glue layer in the gate trench; removing the first glue layer, the cap layer and the work function layer from the upper trench; forming a second glue layer in the gate trench after removing the first glue layer, the cap layer and the work function layer; filling the gate trench with a gate metal after forming the second glue layer; removing the gate metal from the upper trench, the remaining portion of the gate metal located in the lower trench forming a gate electrode; and removing the second glue layer and the gate dielectric layer from the upper trench after removing the gate metal.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a fin protruding above a substrate; a first metal gate located above the fin; a first gate spacer extending along a side wall of the first metal gate; a second gate spacer extending along a side wall of the first gate spacer, a second upper surface of the second gate spacer away from the substrate extending farther from the substrate than a first upper surface of the first gate spacer away from the substrate; a dielectric material surrounded by the second gate spacer and extending from the first upper surface of the first gate spacer to the second upper surface of the second gate spacer; and a first gate contact extending through the dielectric material and electrically coupled to the first metal gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A perspective view of a fin field effect transistor (FinFET) device is shown in accordance with some embodiments.

[0009] Figure 2-Figure 6 , Fig. 7A , Figure 7B , Figure 7C and Figure 8-Figure 21 Cross-sectional views of a FinFET device at various fabrication stages according to an embodiment are shown.

[0010] Fig. 22 A cross-sectional view of a FinFET device according to an embodiment is shown.

[0011] Fig.23 A cross-sectional view of a FinFET device according to an embodiment is shown.

[0012] Fig.24 A flow chart of a method of manufacturing a semiconductor device according to some embodiments is shown. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact.

[0014] In addition, spatially relative terms (e.g., "below," "below," "below," "above," "upper," etc.) may be used herein to facilitate description of the relationship of one element or feature shown in the figures relative to another (one or more) elements or (one or more) features. These spatially relative terms are intended to cover different orientations of the device in use or operation other than the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly. Throughout the discussion herein, unless otherwise stated, the same or similar figure numbers in different figures refer to the same or similar elements formed by the same or similar methods using the same or similar (one or more) materials.

[0015] Embodiments of the present disclosure are discussed in the context of forming a FinFET device, and in particular in the context of forming a replacement gate for a FinFET device. In some embodiments, a dummy gate structure is formed above a fin. A first gate spacer is formed around the dummy gate structure, and a second gate spacer is formed around the first gate spacer. After forming an interlayer dielectric (ILD) layer around the second gate spacer, the dummy gate structure is removed. Next, the upper portion of the first gate spacer is removed, while the lower portion of the first gate spacer remains. After removing the upper portion of the first gate spacer, a gate trench is formed in the ILD layer, the gate trench having a lower trench between the lower portion of the first gate spacer, and having an upper trench above the lower trench, the upper trench being wider than the lower trench. Next, a gate dielectric layer, a work function layer, an optional cap layer, and a glue layer are sequentially formed in the gate trench. Next, the glue layer is selectively removed from the upper trench by a first wet etching process, the optional cap layer (if formed) is removed from the upper trench by a second wet etching process, and the work function layer is selectively removed from the upper trench by a third wet etching process. After the third wet etching process, the remaining portion of the gate dielectric layer, the remaining portion of the work function layer, the remaining portion of the cap layer, and the remaining portion of the glue layer are disposed in the lower trench and have a concave upper surface below the interface between the upper trench and the lower trench. Next, the glue layer is formed again (e.g., a second time) in the gate trench, and the gate metal fills the gate trench. Next, a fourth wet etching process is performed to selectively remove the gate metal from the upper trench, and the remaining portion of the gate metal in the lower trench forms a gate electrode. After the gate electrode is formed, a fifth wet etching process is performed to selectively remove the glue layer from the upper trench. Next, an etching process such as dry etching is performed to remove the gate dielectric layer from the upper trench.

[0016] The metal gates above the fins formed by the above method have a large distance (e.g., pitch) between them, thereby reducing metal gate leakage in advanced process nodes. The various selective etching processes used in the above method can accurately control the end point of the etching process, avoid damage to the gate dielectric layer, and avoid loading effects during the etching back of the various layers of the metal gate. As a result, the gate height of the metal gate is accurately controlled. In addition, the critical dimension (CD) of the metal gate and the sidewall profile of the ILD layer and the overlying mask layer are retained.

[0017] Figure 1An example of a FinFET 30 is shown in a perspective view. The FinFET 30 includes a substrate 50 and a fin 64 that protrudes above the substrate 50. An isolation region 62 is formed on opposite sides of the fin 64, and the fin 64 protrudes above the isolation region 62. A gate dielectric 66 is along the sidewalls of the fin 64 and over the top surface of the fin 64, and a gate 68 is over the gate dielectric 66. Source / drain regions 80 are in the fin 64 and on opposite sides of the gate dielectric 66 and the gate 68. Figure 1 Reference cross-sectional views used in subsequent figures are further illustrated. Cross-section BB extends along the longitudinal axis of gate 68 of FinFET 30. Cross-section AA is perpendicular to cross-section BB and along the longitudinal axis of fin 64 and in the direction of current flow, for example, between source / drain regions 80. Cross-section CC is parallel to cross-section BB and crosses source / drain regions 80. For clarity, subsequent figures refer to these reference cross-sections.

[0018] Figure 2-Figure 6 , Fig. 7A , Figure 7B , Figure 7C and Figure 8-Figure 21 is a cross-sectional view of a FinFET device 100 at various stages of manufacture according to an embodiment. The FinFET device 100 is similar to Figure 1 The FinFET 30 in FIG. 1 is similar to the FinFET 30 in FIG. 1 , but has multiple fins and multiple gate structures. Figure 2-Figure 5 A cross-sectional view of the FinFET device 100 along cross section BB is shown. Figure 6 , Fig. 7A and Figure 8-Figure 21 A cross-sectional view of the FinFET device 100 along the cross-section AA is shown, and Figure 7B and Figure 7C A cross-sectional view of the FinFET device 100 along cross section CC is shown.

[0019] Figure 2A cross-sectional view of a substrate 50 is shown. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate includes a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0020] refer to Figure 3 , using techniques such as photolithography and etching to Figure 2 The substrate 50 shown is patterned. For example, a mask layer is formed over the substrate 50, such as a substrate oxide layer 52 and an overlying substrate nitride layer 56. The pad oxide layer 52 may be a thin film including silicon oxide formed, for example, using a thermal oxidation process. The substrate oxide layer 52 may serve as an adhesion layer between the substrate 50 and the overlying pad nitride layer 56. In some embodiments, the pad nitride layer 56 is formed of silicon nitride, silicon oxynitride, silicon carbonitride, etc., or a combination thereof, and may be formed using, for example, low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0021] The mask layer may be patterned using photolithography techniques. Typically, photolithography techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material (e.g., the mask layer in this example) from subsequent process steps, such as etching. In this example, the photoresist material is used to pattern the pad oxide layer 52 and the pad nitride layer 56 to form a patterned mask 58, as shown in FIG. Figure 3 shown.

[0022] The exposed portions of the substrate 50 are then patterned using a patterned mask 58 to form trenches 61, thereby defining semiconductor fins 64 between adjacent trenches 61, as shown in FIG. Figure 3As shown. In some embodiments, the semiconductor fin 64 is formed by etching a groove in the substrate 50 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. In some embodiments, the grooves 61 may be strips that are parallel to each other and closely spaced relative to each other (viewed from the top). In some embodiments, the grooves 61 may be continuous and surround the semiconductor fin 64. Hereinafter, the semiconductor fin 64 may also be referred to as the fin 64.

[0023] The fins 64 may be patterned by any suitable method. For example, the fins 64 may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines photolithography and self-alignment processes, allowing for the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0024] Figure 4 An insulating material is shown formed between adjacent semiconductor fins 64 to form isolation regions 62. The insulating material may be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it to another material, e.g., an oxide), etc., or a combination thereof. Other insulating materials and / or other formation processes may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. A planarization process such as chemical mechanical polishing (CMP) may remove any excess insulating material and form coplanar top surfaces of the isolation regions 62 and the top surfaces of the semiconductor fins 64 (not shown). The patterned mask 58 (see Figure 3 ) can also be removed by planarization process.

[0025] In some embodiments, the isolation region 62 includes a liner, such as a liner oxide (not shown), at the interface between the isolation region 62 and the substrate 50 / semiconductor fin 64. In some embodiments, the liner oxide is formed to reduce crystal defects at the interface between the substrate 50 and the isolation region 62. Similarly, the liner oxide can also be used to reduce crystal defects at the interface between the semiconductor fin 64 and the isolation region 62. The liner oxide (e.g., silicon oxide) can be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 50, but other suitable methods can also be used to form the liner oxide.

[0026] Next, the isolation region 62 is recessed to form a shallow trench isolation (STI) region 62. The isolation region 62 is recessed so that the upper portion of the semiconductor fin 64 protrudes from between adjacent STI regions 62. The top surface of the STI region 62 may have a flat surface (as shown), a convex surface, a concave surface (e.g., a butterfly shape), or a combination thereof. The top surface of the STI region 62 may be formed to be flat, convex, and / or concave by appropriate etching. An acceptable etching process may be used to recess the isolation region 62, for example, an etching process that is selective to the material of the isolation region 62. For example, a dry etch or wet etch using dilute hydrofluoric acid (dHF) may be performed to recess the isolation region 62.

[0027] Figures 2 to 4 An embodiment of forming fins 64 is shown, but the fins may be formed in a variety of different processes. For example, the top of substrate 50 may be replaced by an appropriate material, such as an epitaxial material suitable for the intended type (e.g., N-type or P-type) semiconductor device to be formed. Thereafter, substrate 50 having the epitaxial material on the top is patterned to form semiconductor fins 64 including the epitaxial material.

[0028] As another example, a dielectric layer may be formed over a top surface of the substrate; a trench may be etched through the dielectric layer; a homoepitaxial structure may be epitaxially grown in the trench; and the dielectric layer may be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form a fin.

[0029] In yet another example, a dielectric layer may be formed over a top surface of a substrate; a trench may be etched through the dielectric layer; a heteroepitaxial structure may be epitaxially grown in the trench using a different material than the substrate; and the dielectric layer may be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form a fin.

[0030] In embodiments where epitaxial material(s) or epitaxial structures (e.g., heteroepitaxial structures or homoepitaxial structures) are grown, the grown material(s) or structures may be doped in situ during growth, which may avoid prior and subsequent implants, although in situ and implant doping may be used together. In addition, it may be advantageous to epitaxially grow a different material in the NMOS region than in the PMOS region. In various embodiments, the fins 64 may include silicon germanium (Si x Ge 1-x , where x can be between 0 and 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc.

[0031] Figure 5 The formation of a dummy gate structure 75 is shown. In some embodiments, the dummy gate structure 75 includes a gate dielectric 66 and a gate 68. A mask 70 may be formed over the dummy gate structure 75. To form the dummy gate structure 75, a dielectric layer is formed on the semiconductor fin 64. The dielectric layer may be, for example, silicon oxide, silicon nitride, multiple layers thereof, etc., and may be deposited or thermally grown.

[0032] A gate layer is formed over the dielectric layer, and a mask layer is formed over the gate layer. The gate layer may be deposited over the dielectric layer and then planarized, for example, by CMP. The mask layer may be deposited over the gate layer. The gate layer may be formed, for example, of polysilicon, but other materials may also be used. The mask layer may be formed, for example, of silicon nitride.

[0033] After forming the layers (e.g., dielectric layer, gate layer, and mask layer), the mask layer may be patterned using acceptable photolithography and etching techniques to form a mask 70. The pattern of mask 70 may then be transferred to the gate layer and the dielectric layer by acceptable etching techniques to form a gate 68 and a gate dielectric 66, respectively. The gate 68 and the gate dielectric 66 cover the respective channel regions of the semiconductor fins 64. The gate 68 may also have a length direction substantially perpendicular to the length direction of the respective semiconductor fins 64.

[0034] exist Figure 5In the example of FIG. 5 , gate dielectric 66 is shown as being formed over fin 64 (e.g., over the top surface and sidewalls of fin 64) and over STI region 62. In other embodiments, gate dielectric 66 may be formed by, for example, thermal oxidation of the material of fin 64, and thus, gate dielectric 66 may be formed over fin 64 but not over STI region 62. These and other variations are fully intended to be included within the scope of the present disclosure.

[0035] Figure 6 , Fig. 7A and Figure 8-21 A cross-sectional view along cross section AA (along the longitudinal axis of the fin 64 ) of the FinFET device 100 is shown in further processing. Figure 7B and Figure 7C The FinFET device 100 is shown in Fig. 7A Two embodiment cross-sectional views at the process step but along the cross section CC. Figure 6-8 , three dummy gate structures 75A, 75B, and 75C are shown above the fin 64. For simplicity, the dummy gate structures 75A, 75B, and 75C may be collectively referred to as dummy gate structures 75. Those skilled in the art will appreciate that more or less than three gate structures may be formed above the fin 64, and these and other variations are fully intended to be included within the scope of the present disclosure.

[0036] like Figure 6 As shown, a lightly doped drain (LDD) region 65 is formed in the fin 64. The LDD region 65 may be formed by a plasma doping process. The plasma doping process may include forming and patterning a mask (e.g., a photoresist) to cover the FinFET region to be protected from the plasma doping process. The plasma doping process may implant N-type or P-type impurities in the fin 64 to form the LDD region 65. For example, a P-type impurity such as boron may be implanted in the fin 64 to form an LDD region 65 for a P-type device. As another example, an N-type impurity such as phosphorus may be implanted in the fin 64 to form an LDD region 65 for an N-type device. In some embodiments, the LDD region 65 is adjacent to the channel region of the FinFET device 100. Portions of the LDD region 65 may extend under the gate 68 and into the channel region of the FinFET device 100. Figure 6 A non-limiting example of an LDD region 65 is shown. Other configurations, shapes, and methods of forming the LDD region 65 are also possible and are fully intended to be included within the scope of the present disclosure. For example, the LDD region 65 may be formed after forming the gate spacers 87 / 85. In some embodiments, the LDD region 65 is omitted.

[0037] Still refer to Figure 6, after forming the LDD region 65, a first gate spacer 85 is formed around the dummy gate structure 75 (e.g., along the sidewalls thereof and in contact therewith), and a second gate spacer 87 is formed around the first gate spacer 85 (e.g., along the sidewalls thereof and in contact therewith). For example, the first gate spacer 85 may be formed on the opposite sidewalls of the dummy gate structure 75. The second gate spacer 87 is formed on the first gate spacer 85. The first gate spacer 85 may be a low-k spacer and may be formed of a suitable dielectric material, such as silicon oxide, silicon oxynitride, and the like. The second gate spacer 87 may be formed of a nitride, such as silicon nitride, silicon oxynitride, silicon carbonitride, and the like, or a combination thereof. The first gate spacer 85 and the second gate spacer 87 may be formed using any suitable deposition method such as thermal oxidation, chemical vapor deposition (CVD), and the like. In the illustrated embodiment, the first gate spacer 85 and the second gate spacer 87 are formed of different materials to provide etching selectivity in subsequent processing. The first gate spacer 85 and the second gate spacer 87 may be collectively referred to as gate spacers 85 / 87 .

[0038] like Figure 6 The shapes and formation methods of the gate spacers (eg, 85 and 87) shown in are non-limiting examples only, and other shapes and formation methods are possible. These and other variations are fully intended to be included within the scope of the present disclosure.

[0039] Next, in Fig. 7A In the embodiment of the present invention, recesses are formed in the fins 64 adjacent to the dummy gate structures 75, for example, between adjacent dummy gate structures 75 and / or adjacent to the dummy gate structures 75, and source / drain regions 80 are formed in the recesses. In some embodiments, the recesses are formed by, for example, an anisotropic etching process using the dummy gate structures 75 as an etching mask, but any other suitable etching process may also be used.

[0040] The source / drain regions 80 are formed by epitaxially growing a semiconductor material in the recesses using an appropriate method (e.g., metal organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), etc., or a combination thereof).

[0041] like Fig. 7A As shown, the epitaxial source / drain regions 80 may have surfaces that are raised from the corresponding surfaces of the fins 64 (e.g., raised above the non-recessed portions of the fins 64) and may have facets. The source / drain regions 80 of adjacent fins 64 may merge to form a continuous epitaxial source / drain region 80 (see Figure 7BIn some embodiments, the source / drain regions 80 of adjacent fins 64 are not merged together, but remain separate source / drain regions 80 (see Figure 7C ). In some embodiments, the resulting FinFET is an n-type FinFET, and the source / drain region 80 includes silicon carbide (SiC), silicon phosphorus (SiP), phosphorus-doped silicon carbon (SiCP), etc. In some embodiments, the resulting FinFET is a p-type FinFET, and the source / drain region 80 includes SiGe and p-type impurities, such as boron or indium.

[0042] The epitaxial source / drain regions 80 may be implanted with dopants to form the source / drain regions 80 and then subjected to an annealing process. The implantation process may include forming and patterning a mask (e.g., a photoresist) to cover the areas of the FinFET to be protected from the implantation process. The source / drain regions 80 may have a thickness from about 1E19 cm -3 to about 1E21 cm -3 The impurity (e.g., dopant) concentration may be within a range of . P-type impurities such as boron or indium may be implanted in the source / drain regions 80 of a P-type transistor. N-type impurities such as phosphorus or arsenide may be implanted in the source / drain regions 80 of an N-type transistor. In some embodiments, the epitaxial source / drain regions may be doped in situ during growth.

[0043] Next, if Figure 8 As shown, in Fig. 7A A contact etch stop layer (CESL) 83 is formed over the structure shown. The CESL 83 is used as an etch stop layer in a subsequent etching process and may include a suitable material, such as silicon oxide, silicon nitride, silicon oxynitride, a combination thereof, etc., and may be formed by a suitable formation method, such as CVD, PVD, a combination thereof, etc.

[0044] Next, an interlayer dielectric (ILD) 90 is formed over the CESL 83 and over the dummy gate structures 75 (e.g., 75A, 75B, and 75C). In some embodiments, the ILD 90 is formed of a dielectric material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., and may be deposited by any suitable method, such as CVD, PECVD, or FCVD. After forming the ILD 90, a dielectric layer 91 is formed over the ILD 90. The dielectric layer 91 serves as a protective layer to prevent or reduce the loss of the ILD 90 in a subsequent etching process. The dielectric layer 91 may be formed of a suitable material such as silicon nitride, silicon carbonitride, etc. using a suitable method such as CVD, PECVD, or FCVD. After forming the dielectric layer 91, a planarization process such as a CMP process may be performed to achieve a level upper surface of the dielectric layer 91. The CMP may also remove mask 70 and a portion of CESL 83 disposed over gate 68. In some embodiments, after the planarization process, the upper surface of dielectric layer 91 is flush with the upper surface of gate 68.

[0045] An embodiment gate-last process (sometimes referred to as a replacement gate process) is then performed to replace the gate 68 and gate dielectric 66 of the dummy gate structure 75 with an active gate (also referred to as a replacement gate or metal gate).

[0046] Next, in Fig. 9 , removing the dummy gate structures 75A, 75B and 75C (see Fig. 7A ) to form gate trenches 89A, 89B or 89C, respectively. Next, the upper portions of the gate trenches 89A, 89B and 89C are expanded by removing the upper portions of the first gate spacers 85, so that each of the gate trenches 89A, 89B and 89C has an upper trench 89U and a lower trench 89L, wherein the upper trench 89U is wider than the lower trench 89L. The details of forming the gate trenches 89A, 89B and 89C are discussed below. For simplicity, the gate trenches 89A, 89B and 89C may be collectively referred to as gate trenches 89.

[0047] In some embodiments, to remove the dummy gate structure 75, one or more etching steps are performed to remove the gate 68 and the gate dielectric 66 directly below the gate 68, so that gate trenches 89 (which may also be referred to as grooves) are formed between the corresponding first gate spacers 85. Each gate trench 89 exposes a channel region of a corresponding fin 64. During the removal of the dummy gate, the gate dielectric 66 may be used as an etch stop layer when etching the gate 68. The gate dielectric 66 may then be removed after the gate 68 is removed.

[0048] Next, an anisotropic etching process (e.g., a dry etching process) is performed to remove the upper portion of the first gate spacer 85. In some embodiments, the anisotropic etching process is performed using an etchant that is selective to the material of the first gate spacer 85 (e.g., has a higher etching rate), so that the first gate spacer 85 is recessed (e.g., the upper portion is removed) without substantially corroding the second gate spacer 87 and the dielectric layer 91. After removing the upper portion of the first gate spacer 85, the upper sidewall 87SU of the second gate spacer 87 is exposed.

[0049] like Fig. 9 As shown, after removing the upper portion of the first gate spacer 85, each of the gate trenches 89 has an upper trench 89U and a lower trench 89L. The lower trench 89L is between the remaining lower portions of the first gate spacer 85. The upper trench 89U is above the lower trench and is defined by (e.g., adjacent to) the upper sidewall 87SU of the second gate spacer 87. Fig. 9 An interface 86 between the upper trench 89U and the lower trench 89L is shown, which is flush with the upper surface 85U of the remaining lower portion of the first gate spacer 85. Each of the gate trenches 89 has a wider upper trench 89U and a narrower lower trench 89L, similar to the letter "Y", and therefore, the gate trenches 89 can be referred to as Y-shaped gate trenches.

[0050] In some embodiments, the upper trench 89U has a width W1 between about 20 nm and about 30 nm (e.g., the distance between the corresponding opposing upper sidewalls 87SU), and has a depth H1 between about 40 nm and about 80 nm (e.g., the distance between the upper surface of the second gate spacer 87 and the interface 86). The lower trench 89L has a width W2 between about 10 nm and about 20 nm (e.g., the distance between the corresponding opposing sidewalls of the remaining lower portion of the first gate spacer 85), and has a depth H2 between about 20 nm and about 40 nm (e.g., the distance between the bottom of the gate trench 89 and the interface 86). As will be described in subsequent processes, a metal gate 97 is formed in the lower trench 89L (see, e.g., Fig.21 ). For example, a gate electrode material such as tungsten is used (see, e.g. Fig.21 101 in the figure is used to fill the lower trench 89L to form the gate electrode of the metal gate. Therefore, the size of the lower trench 89L determines the size of the metal gate and the size of the gate electrode.

[0051] Next, in Fig.10In the embodiment, a gate dielectric layer 92, a work function layer 94, an optional capping layer 96 and a glue layer 98 are sequentially formed in the gate trench 89. The gate dielectric layer 92 is conformally deposited in the gate trench 89, for example, on the top surface and sidewalls of the fin 64, on the top surface and sidewalls of the gate spacer 85 / 87, and on the top surface of the dielectric layer 91. According to some embodiments, the gate dielectric layer 92 includes silicon oxide, silicon nitride, or multiple layers thereof. In example embodiments, the gate dielectric layer 92 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 92 may have a k value greater than about 7.0 and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation method of the gate dielectric layer 92 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc. For example, the thickness of the gate dielectric layer 92 may be between about 8 angstroms and about 20 angstroms. In some embodiments, an interfacial layer (IL) is formed in the gate trench 89 before forming the gate dielectric layer 92 .

[0052] Next, a work function layer 94 is formed over (eg, conformally) the gate dielectric layer 92. In some embodiments, the work function layer 94 may be a P-type work function layer, an N-type work function layer, multiple layers thereof, or a combination thereof. Fig.10 In the example shown, the work function layer 94 is an N-type work function layer. In the discussion herein, the work function layer may also be referred to as a work function metal. Exemplary P-type work function metals that may be included in the gate structure of a P-type device include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable P-type work function materials, or combinations thereof. Exemplary N-type work function metals that may be included in the gate structure of an N-type device include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof. The work function value is associated with the material composition of the work function layer, and therefore, the material of the work function layer is selected to adjust its work function value so that a target threshold voltage V is achieved in the device to be formed. t The work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), ALD, and / or other suitable processes. For example, the thickness of the P-type work function layer may be between about 8 angstroms and about 15 angstroms, and the thickness of the N-type work function layer may be between about 15 angstroms and about 30 angstroms.

[0053] Next, an optional capping layer 96 is formed over (e.g., conformally) the work function layer 94. The capping layer 96, if formed, protects the underlying work function layer 94 from oxidation. In some embodiments, the capping layer 96 is a silicon-containing layer, such as a silicon layer, a silicon oxide layer, or a silicon nitride layer, formed by a suitable method such as ALD, MBD, CVD, etc. The thickness of the capping layer 96 can be between about 8 angstroms and about 15 angstroms. In some embodiments, the capping layer 96 is omitted.

[0054] Next, a glue layer 98 is formed (e.g., conformally) over the cap layer 96 or (if the cap layer 96 is omitted) over the work function layer 94. The glue layer 98 serves as an adhesion layer between the underlying layer (e.g., 96) and the gate electrode material subsequently formed over the glue layer 98. The glue layer 98 can be formed of a suitable material, such as titanium nitride, using a suitable deposition method (e.g., CVD, PVD, ALD, etc.). Depending on the width W2 of the lower trench 89L and the thickness of the layers previously formed in the gate trench (e.g., 92, 94, 96), the glue layer 98 can fill the remaining portion of the lower trench 89L, as shown in the example of 10.

[0055] Figure 11-Figure 20 Additional process steps for forming the metal gate of the FinFET device 100 are shown. Figure 11-Figure 20 Each shows only a portion of the FinFET device 100. Specifically, Figure 11-Figure 20 Each shows Fig.10 An enlarged view of region 88 in FIG. Fig.11 The following diagram shows the structure of the adhesive layer 98 after forming the adhesive layer 98. Fig.10 of area 88.

[0056] Next reference Fig.12 , the glue layer 98 is removed from the upper trench 89U of the gate trench 89 by a glue layer pull-back process. In some embodiments, a wet etching process is performed as a glue layer pull-back process to selectively remove the glue layer 98 from the upper trench 89U without corroding (e.g., damaging, removing) the underlying layer (e.g., the cap layer 96). In some embodiments, the wet etching process is performed using a chemical substance including an acid and an oxidant. For example, the chemical substance used can be a mixture of hydrochloric acid (HCl) and hydrogen peroxide (H2O2), wherein HCl is used as an acid and H2O2 is used as an oxidant. In some embodiments, for the wet etching process, the mixing ratio (e.g., volume ratio) between HCl and H2O2 is between about 1:1 and 1:20. The wet etching process can be performed at a temperature of about 40°C to about 70°C for a duration of about 1 minute to about 5 minutes. As Fig.12As shown, after the glue layer pull-back process, the capping layer 96 is exposed in the upper trench 89U, and the remaining portion of the glue layer 98 still fills the lower trench 89L.

[0057] Next, in Fig.13 In some embodiments, the cap layer 96 is removed from the upper trench 89U by a cap layer break-through process. In some embodiments, a wet etching process is performed as the cap layer break-through process to remove the cap layer 96 from the upper trench 89U. In some embodiments, a fluoride-containing chemical is used to perform the wet etching process for removing the cap layer 96 from the upper trench 89U. For example, the fluoride-containing chemical may be a mixture of hydrofluoric acid (HF) and water (e.g., H2O or deionized water (DIW)). In some embodiments, for the wet etching process, the mixing ratio (e.g., volume ratio) between HF and H2O is between about 1:100 and 1:2000. The wet etching process may be performed at a temperature of about 20°C to about 40°C for a duration of about 3 minutes to about 6 minutes. Fig.13 As shown, after the cap layer penetration process, the work function layer 94 is exposed in the upper trench 89U. In some embodiments, the etching selectivity of the fluorine-containing chemical may not be high, and therefore, the wet etching process (cap layer penetration process) is performed in a timed mode. In other words, the wet etching process is timed (e.g., performed for a predetermined time period) so as to completely remove the cap layer 96 in the upper trench without substantially attacking the work function layer 94 and / or the gate dielectric layer 92. Fig.13 As shown, the cap layer breakthrough process also recesses the portion of layer 94 / 96 / 98 in the lower trench so that layer 94 / 96 / 98 in the lower trench has a curved (eg, concave) upper surface that extends below the interface 86 between the upper trench 89U and the lower trench 89L.

[0058] Next, in Fig.14 , the work function layer 94 is removed from the upper trench 89U. In some embodiments, a wet etching process is performed to selectively remove the work function layer 94 from the upper trench 89U without corroding the underlying gate dielectric layer 92. In some embodiments, the wet etching process is performed using a chemical substance including an alkali and an oxidant. For example, the chemical substance used can be a mixture of ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2), wherein NH4OH is used as a base and H2O2 is used as an oxidant. In some embodiments, for the wet etching process, the mixing ratio (e.g., volume ratio) between NH4OH and H2O2 is between about 1:1 and 1:2001. The wet etching process can be performed at a temperature of about 40°C to about 70°C for a duration of about 1 minute to about 5 minutes. Fig.14 As shown, after the wet etching process, the gate dielectric layer 92 is exposed in the upper trench 89U. Fig.14 Also shown is a height H3 measured between the lowest location of the curved upper surface of layer 94 / 96 / 98 in the lower trench (e.g., closest to substrate 50) and the interface 86 between upper trench 89U and lower trench 89L, where in some embodiments, H3 is between about 3 nm and about 12 nm.

[0059] Next, in Fig.15 In the embodiment, a glue layer 98 is again formed in the gate trench 89 (eg, conformally), and a filling metal 101 (also referred to as a gate metal or a gate electrode material) is formed to fill the remaining portion of the gate trench 89. Fig.15 As shown, a glue layer 98 (e.g., TiN) is conformally formed along the gate dielectric layer 92 and along the curved upper surface of the layer 94 / 96 / 98 in the lower trench 89L. The newly formed glue layer 98 may merge with the remaining portion of the glue layer 98 in the lower trench 89L. After the glue layer 98 is formed, a fill metal 101 is formed to fill the gate trench 89. The fill metal 101 may be a suitable metal such as tungsten (W) formed by a suitable method such as PVD, CVD, electroplating, electroless plating, etc. In addition to tungsten, other suitable materials such as copper, gold, cobalt, combinations thereof, multiple layers thereof, alloys thereof, etc. may also be used as the fill metal 101.

[0060] Next, in Fig.16 In some embodiments, the fill metal 101 is etched back (e.g., recessed) by a wet etching process that selectively removes the fill metal 101 without substantially attacking the underlying glue layer 98. In some embodiments, the wet etching process of etching back the fill metal 101 is performed using a chemical including an acid and an oxidant. For example, the chemical used may be a mixture of hydrochloric acid (HCl) and hydrogen peroxide (H2O2), wherein HCl is used as an acid and H2O2 is used as an oxidant. In some embodiments, for the wet etching process, the mixing ratio (e.g., volume ratio) between HCl and H2O2 is between about 1:1 and 1:20. The wet etching process may be performed at a temperature of about 30°C to about 70°C for a duration of about 5 minutes to about 10 minutes. In some embodiments, the mixing ratio between HCl and H2O2 is adjusted to achieve a target etching selectivity between the fill metal 101 and the glue layer 98. For example, by adjusting the mixing ratio, the etching selectivity (e.g., the ratio of etching rates) between the fill metal 101 (e.g., W) and the glue layer 98 (e.g., TiN) is between about 20 and about 60. As Fig.16 As shown, after the wet etching process, the remaining portion of the filling metal 101 fills the lower trench 89L, and the upper surface of the remaining portion of the filling metal 101 is slightly higher than the upper surface of the first gate spacer 85 .

[0061] Next, in Fig.17In some embodiments, a second glue layer pull-back process is performed to remove the glue layer 98 from the upper groove 89U. In some embodiments, a wet etching process is performed as a second glue layer pull-back process to selectively remove the glue layer 98 from the upper groove 89U without substantially attacking the fill metal 101. In some embodiments, a chemical (e.g., an etcher) including a fluorine-containing chemical, an inhibitor, and an oxidant is used to perform the wet etching process. For example, the fluoride-containing chemical may be ammonium fluoride (NH4F), tetra-n-butylammonium fluoride (TBAF), or tetramethylammonium fluoride (TMAF). The inhibitor may be benzimidazole (C7H6N2), tolyltriazole (TTA), or 5-chloro-1H-benzotriazole. The inhibitor may protect the fill metal 101 from being etched by the wet etching process. The oxidant may be hydrogen peroxide (H2O2), nitric acid (HNO3), or a mixture of the two. In some embodiments, the mixing ratio (e.g., volume ratio) between the fluorine-containing chemical, the inhibitor, and the oxidant is adjusted to achieve a target etching selectivity between the glue layer 98 and the fill metal 101. For example, a selectivity between about 20 and about 60 can be achieved to remove the glue layer 98 without substantially attacking the fill metal 101. In some embodiments, the wet etching process is performed at a temperature of about 30° C. to about 60° C. for a duration of about 1 minute to about 5 minutes. Fig.17 As shown, after the wet etching process, the gate dielectric layer 92 is exposed in the upper trench 89U, and the upper surface of the remaining portion of the filling metal 101 is flush with the upper surface of the first gate spacer 85 or flush with the interface 86 between the upper trench 89U and the lower trench 89L.

[0062] Next, in Fig.18 In the embodiment, a portion of the gate dielectric layer 92 disposed in the upper trench 89U, for example, along the inner sidewall of the second gate spacer 87 is removed. In some embodiments, a dry etching process is performed to remove the portion of the gate dielectric layer 92. The remaining portion of the fill metal 101 forms the gate electrode 101. Fig.18 As shown, the remaining portions of the various layers in the lower trench 89L, for example, the gate dielectric layer 92 , the work function layer 94 , the cap layer 96 , the glue layer 98 , and the filling metal 101 , form a metal gate 97 .

[0063] exist Fig.18 In the embodiment, the upper surface of the metal gate 97 is substantially flush with the upper surface of the first gate spacer 85. The gate dielectric layer 92, the work function layer 94 and the cap layer 96 are Fig.18 The glue layer 98 is vertically disposed between the gate electrode 101 and the cap layer 96, and the glue layer 98 has a lower portion extending into and filling the central area surrounded by the U-shaped cap layer 96. In addition, the glue layer 98 is horizontally disposed between two opposite inner side walls of the U-shaped work function layer 94.

[0064] Next, in Fig.19 In the embodiment, a semiconductor material 111 such as silicon is formed in the gate trench 89 using a suitable formation method such as PVD, CVD, etc. Next, a gate contact 102 is formed in the semiconductor material 111 to be electrically coupled to the gate electrode 101. In order to form the gate contact 102 (also referred to as a contact plug), a contact opening is formed in the semiconductor material 111 using, for example, photolithography and etching to expose the gate electrode 101. Once the contact opening is formed, a barrier layer 104, a seed layer 109, and a filling material 110 are sequentially formed in the contact opening to form the gate contact 102.

[0065] In some embodiments, barrier layer 104 includes a conductive material such as titanium nitride, but other materials such as tantalum nitride, titanium, tantalum, etc. may be used instead. A CVD process such as PECVD may be used to form barrier layer 104. However, other alternative processes such as sputtering, metal organic chemical vapor deposition (MOCVD), or ALD may be used instead.

[0066] Next, a seed layer 109 is formed over the barrier layer 104. The seed layer 109 may include copper, titanium, tantalum, titanium nitride, tantalum nitride, etc., or a combination thereof, and may be deposited by ALD, sputtering, PVD, etc. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sublayers formed of different materials. For example, the seed layer 109 may include a titanium layer and a copper layer over the titanium layer.

[0067] Next, a fill metal 110 is deposited over the seed layer 109 and fills the rest of the contact opening. The fill metal 110 may be a metal-containing material such as Cu, Al, W, or the like, a combination thereof, or multiple layers thereof, and may be formed by, for example, electroplating, electroless plating, or other suitable methods. After forming the fill metal 110, a planarization process such as CMP may be performed to remove excess portions of the barrier layer 104, the seed layer 109, and the fill metal 110 that are formed on the dielectric layer 91 (see FIG. Fig.21 ) and the upper surface of the second gate spacer 87. The resulting barrier layer 104, seed layer 109 and the remaining portion of the fill metal 110 thus form the gate contact 102.

[0068] Next, in Fig. 20In the embodiment of the present invention, the semiconductor material 111 is replaced by the dielectric material 113. The semiconductor material 111 may be removed by an etching process using an etchant that is selective to the semiconductor material 111. After the semiconductor material 111 is removed, a dielectric material 113 (e.g., silicon oxide, silicon nitride, a low-K dielectric material, etc.) is formed to fill the space previously occupied by the semiconductor material 111.

[0069] Fig.21 FIG. 4 shows a cross-sectional view of the FinFET device 100 after the semiconductor material 111 is replaced by the dielectric material 113. Fig.21 As shown, gates 97A, 97B, and 97C are formed over the fin 64, which replace the dummy gate structures 75A, 75B, and 75C, respectively. Those skilled in the art will appreciate that additional processes may be performed to complete the fabrication of the FinFET device 100, such as forming source / drain contacts and forming metallization layers over the dielectric layer 91. For the sake of brevity, the details are not discussed herein.

[0070] As semiconductor manufacturing processes continue to develop, the distance (e.g., spacing) between adjacent metal gates 97 is getting closer. For advanced process nodes such as 5nm or higher, the small spacing between the metal gates 97 may cause metal gate leakage, which reduces the reliability of the formed device. Compared with the reference design in which the metal gate 97 is formed between the second gate spacers 87 (e.g., the first gate spacer 85 is completely removed, and the metal gate 97 fills the space between the second gate spacers 87), the present disclosure increases the spacing between the metal gates 97 by forming the metal gates 97 between the recessed first gate spacers 85, thereby reducing metal gate leakage and increasing device reliability. The increased spacing between adjacent metal gates 97 can also increase the spacing between adjacent gate contacts 102, which, combined with the fact that the gate contacts 102 are surrounded by the second gate spacers 87, prevents or reduces the possibility of electrical short circuits between adjacent gate contacts 102.

[0071] exist Fig.21 In the example of FIG. 1 , all metal gates 97 have the same structure (e.g., the same film scheme in the metal gate). In other embodiments, the metal gates 97 may have different structures. For example, each of the metal gates 97 may have (one or more) different work function layers to achieve different threshold voltages, and / or form metal gates in different regions of the FinFET device 100 (e.g., N-type device regions or P-type device regions). Fig. 22 An example is shown.

[0072] Fig. 22 FIG. 1 is a cross-sectional view of various parts of a FinFET device 100A in an embodiment. The FinFET device 100A is similar to Fig.21 The FinFET device 100 of FIG. 1 is a device of the type shown in FIG. 1 , but with different work function layers (one or more) for each metal gate. For simplicity, Fig. 22 Only a portion of the FinFET device 100A adjacent to the metal gates 97A, 97B, and 97C is shown, for example, a region 88 of the FinFET device 100A (see FIG. Fig.10 ) in the portion. The metal gates 97A, 97B, and 97C are separated by spacers 121, wherein the spacers 121 indicate additional features between the metal gates 97A, 97B, and 97C (see, e.g. Fig.21 ) are omitted for simplicity.

[0073] exist Fig. 22 In the embodiment, the metal gate 97A and Fig.21 97A in FIG. 1 and has an N-type work function layer 94. The metal gate 97B has two work function layers. Specifically, the metal gate 97B has a P-type work function layer 94A that contacts (e.g., physically contacts) the gate dielectric layer 92 and extends along the gate dielectric layer 92, and has an N-type work function layer 94 that contacts (e.g., physically contacts) the P-type work function layer 94A and extends along the P-type work function layer 94A. Note that although the cap layer 96 of the metal gate 97A has a U-shaped cross-section, the cap layer 96 of the metal gate 97B has a rectangular cross-section, which may be due to the dual work function layer structure of the metal gate 97B having less space available for the cap layer 96. Therefore, although the lower portion of the glue layer 98 of the metal gate 97A protrudes into the central area surrounded by the U-shaped cap layer 96, the glue layer 98 of the metal gate 97B is disposed above the rectangular cap layer 96 and does not have such a lower portion. Metal gate 97C is similar to metal gate 97B, but has a different P-type work function layer 94B.

[0074] The present disclosure provides many advantages for forming FinFET devices with metal gates 97A, 97B, and 97C using different film schemes (e.g., different work function layers). In this article, the term film scheme refers to the materials and structures of the layer stack (e.g., 92, 94 / 94A / 94B, 96, and 98) of the metal gate 97. To understand these advantages, consider a process in which the removal of the glue layer 98, the cap layer 96, and the work function layer 94 / 94A / 94B from the upper trench 89U is performed by a dry etching process (e.g., an anisotropic plasma etching process) (see FIG. 1 ). Figure 12-14Due to the different film schemes (e.g., different work function layers) of the metal gates in the gate trenches 89A, 89B, and 89C, the etching rates of the different layer combinations in the gate trenches 89A, 89B, and 89C are different, which produces a loading effect (e.g., non-uniformity) when removing the layers in the gate trenches. In other words, the number of layers removed in the gate trenches 89A, 89B, and 89C is different. This may cause the gate heights of the subsequently formed metal gates 97A, 97B, and 97C to be non-uniform. In addition, the dry etching process may damage the gate dielectric layer 92, the dielectric layer 91, and / or the ILD 90, and may change the critical dimension (CD) of the formed features (e.g., the CD of the metal gate).

[0075] In contrast, the currently disclosed method uses a wet etching process to remove the glue layer 98, the cap layer 96, and the work function layer 94 / 94A / 94B from the upper trench 89U. The endpoint of the wet etching process can be precisely controlled by, for example, using an etchant that is selective to the layer being removed. The wet etching process reduces or avoids the loading effect. As a result, the subsequently formed metal gates 97A, 97B, and 97C have a well-controlled uniform gate height. In addition, damage to the gate dielectric layer 92 is avoided, the loss of the ILD 90 and / or the dielectric layer 91 is reduced, and the critical dimensions of the metal gate are retained.

[0076] Fig.23 FIG. 1 is a cross-sectional view of various parts of a FinFET device 100B in an embodiment. The FinFET device 100B is similar to Fig. 22 The FinFET device 100A does not have the cap layer 96. Fig.23 , the gate dielectric layer 92 and the work function layer (e.g., 94, 94A, 94B) all have a U-shaped cross-section. As a result, the glue layer 98 of the metal gate 97A is disposed in the central region of the U-shaped work function layer 94 (e.g., N-type work function layer). The glue layer 98 of the metal gate 97B has an upper portion disposed above the U-shaped work function layer 94 (e.g., N-type work function layer), and has a lower portion protruding into the central region surrounded by the U-shaped work function layer 94. In addition, the upper portion of the glue layer 98 of the metal gate 97B is disposed in the central region surrounded by the P-type work function layer 94A, and the gate electrode 101 is surrounded by the glue layer 98. The structure of the metal gate 97C is similar to that of the metal gate 97B, and therefore will not be described in detail.

[0077] Variations or modifications to the disclosed embodiments are possible and are fully intended to be included within the scope of the present disclosure. For example, in addition to forming a metal gate for a FinFET device, the disclosed embodiments may also be used in other metal gate exposure processes where precise control of gate height is required. In addition, the conditions and / or parameters (e.g., temperature, duration, and / or chemical composition of the etchant) of the wet etching process used to remove various layers from the upper trench may be modified to fine-tune the etching rate to achieve a target gate height. As another example, the disclosed embodiments may be used to control the height of a metal island or metal gate.

[0078] Embodiments can achieve advantages. For example, the disclosed embodiments increase the spacing between adjacent metal gates, thereby reducing metal gate leakage and improving the reliability of the formed device. The increased gate spacing also reduces the possibility of electrical shorts between adjacent gate contacts. Using a wet etching process to remove various layers (e.g., 94, 96, 98) from the upper trench 89U reduces the loading effect and helps to accurately control the gate height of the formed metal gate. In addition, damage to the gate dielectric layer 92 and loss of the ILD layer 90 / dielectric layer 91 are prevented or reduced. In addition, the critical dimension (CD) of the formed feature (e.g., the CD of the metal gate) is retained.

[0079] Fig.24 1 shows a flow chart of a method for manufacturing a semiconductor device according to some embodiments. It should be understood that Fig.24 The illustrated embodiment methods are merely examples of many possible embodiment methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the following may be added, removed, replaced, rearranged, and repeated. Fig.24 The steps shown.

[0080] refer to Fig.24 , at step 1010, a dummy gate located above the fin is surrounded by a dielectric material. At step 1020, a gate trench is formed in the dielectric material by removing the dummy gate and by removing the upper portion of the first gate spacer disposed along the sidewall of the dummy gate, the gate trench including a lower trench between the remaining lower portions of the first gate spacer and including an upper trench located above the lower trench. At step 1030, a gate dielectric layer, a work function layer, and a glue layer are sequentially formed in the gate trench. At step 1040, the glue layer and the work function layer are removed from the upper trench. At step 1050, the gate trench is filled with a gate electrode material after the removal. At step 1060, the gate electrode material is removed from the upper trench, and the remaining portion of the gate electrode material forms a gate electrode.

[0081] In an embodiment, a method of forming a semiconductor device includes: surrounding a dummy gate disposed above a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing an upper portion of a first gate spacer disposed along a sidewall of the dummy gate, the gate trench including a lower trench located between remaining lower portions of the first gate spacer and including an upper trench located above the lower trench; sequentially forming a gate dielectric layer, a work function layer, and a glue layer in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removal; and removing the gate electrode material from the upper trench, the remaining portion of the gate electrode material forming a gate electrode. In an embodiment, after removing the glue layer and the work function layer, the remaining portion of the glue layer and the remaining portion of the work function layer have a curved upper surface extending below an interface between the upper trench and the lower trench. In an embodiment, forming the gate trench includes: performing one or more etching processes to remove the dummy gate; and after removing the dummy gate, performing another etching process to remove the upper portion of the first gate spacer. In an embodiment, the second gate spacer surrounds the first gate spacer, wherein, after removing the upper portion of the first gate spacer, the sidewall of the second gate spacer located above the remaining lower portion of the first gate spacer defines an upper trench. In an embodiment, the upper trench is wider than the lower trench. In an embodiment, removing the glue layer and the work function layer from the upper trench includes: performing a first etching process to selectively remove the glue layer from the upper trench; and after the first etching process, performing a second etching process to selectively remove the work function layer from the upper trench. In an embodiment, the method also includes: forming a silicon-containing capping layer between the work function layer and the glue layer; and before filling the gate trench with the gate electrode material, removing the silicon-containing capping layer from the upper trench. In an embodiment, removing the silicon-containing capping layer includes: performing a third etching process after the first etching process and before the second etching process, the third etching process removing a portion of the silicon-containing capping layer, a portion of the glue layer, and a portion of the work function layer. In an embodiment, removing the glue layer and the work function layer from the upper trench exposes an upper portion of the gate dielectric layer disposed in the upper trench, wherein the method further comprises: after removing the glue layer and the work function layer from the upper trench and before filling the gate trench, forming the glue layer again in the gate trench and on the exposed upper portion of the gate dielectric layer. In an embodiment, removing the gate electrode material from the upper trench comprises: performing a first wet etching process to selectively remove the gate electrode material, wherein removing the gate electrode material from the upper trench exposes an upper portion of the glue layer disposed in the upper trench. In an embodiment, the method further comprises: after removing the gate electrode material from the upper trench, performing a second wet etching process to selectively remove the upper portion of the glue layer disposed in the upper trench; and after the second wet etching process, performing a dry etching process to remove the upper portion of the gate dielectric layer disposed in the upper trench.

[0082] In an embodiment, a method of forming a semiconductor device includes: forming a gate trench in a dielectric material by removing a dummy gate and by removing an upper portion of a first gate spacer surrounding the dummy gate, wherein the gate trench includes a lower trench located between remaining lower portions of the first gate spacer and includes an upper trench located above the lower trench; lining the sidewalls and bottom of the gate trench by sequentially forming a gate dielectric layer, a work function layer, a cap layer, and a first glue layer in the gate trench; removing the first glue layer, the cap layer, and the work function layer from the upper trench; forming a second glue layer in the gate trench after removing the first glue layer, the cap layer, and the work function layer; filling the gate trench with a gate metal after forming the second glue layer; removing the gate metal from the upper trench, the remaining portion of the gate metal located in the lower trench forming a gate electrode; and removing the second glue layer and the gate dielectric layer from the upper trench after removing the gate metal. In an embodiment, the first width of the upper trench is greater than the second width of the lower trench. In an embodiment, removing the first glue layer, the capping layer, and the work function layer from the upper trench comprises: performing a first wet etching process using a first mixture of an acid and a first oxidant to selectively remove the first glue layer; after the first wet etching process, performing a second wet etching process using a fluoride-containing chemical to remove the capping layer; and after the second wet etching process, performing a third wet etching process using a second mixture of an alkali and a second oxidant to selectively remove the work function layer. In an embodiment, removing the second glue layer and the gate dielectric layer from the upper trench comprises: performing a wet etching process using a mixture of a fluoride-containing chemical, a metal inhibitor, and an oxidant to selectively remove the second glue layer; and after the wet etching process, performing a dry etching process to remove the gate dielectric layer.

[0083] In an embodiment, a semiconductor device includes: a fin protruding above a substrate; a first metal gate located above the fin; a first gate spacer extending along a sidewall of the first metal gate; a second gate spacer extending along a sidewall of the first gate spacer, a second upper surface of the second gate spacer away from the substrate extending further from the substrate than a first upper surface of the first gate spacer away from the substrate; a dielectric material surrounded by the second gate spacer and extending from a first upper surface of the first gate spacer to a second upper surface of the second gate spacer; and a first gate contact extending through the dielectric material and electrically coupled to the first metal gate. In an embodiment, the first upper surface of the first gate spacer is substantially flush with an upper surface of the first metal gate. In an embodiment, the first metal gate includes a gate dielectric layer, wherein a sidewall of the first gate spacer contacts the gate dielectric layer of the first metal gate, and a sidewall of the second gate spacer contacts a sidewall of the first gate spacer. In an embodiment, the first metal gate further comprises: a work function layer located above the gate dielectric layer, a silicon-containing cap layer located above the work function layer, a glue layer located above the silicon-containing cap layer, and a gate electrode located above the glue layer. In an embodiment, the silicon-containing cap layer has a U-shaped cross section.

[0084] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0085] Example 1 is a method for forming a semiconductor device, the method comprising: surrounding a dummy gate disposed above a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing an upper portion of a first gate spacer disposed along a side wall of the dummy gate, the gate trench comprising a lower trench located between remaining lower portions of the first gate spacer and comprising an upper trench located above the lower trench; sequentially forming a gate dielectric layer, a work function layer, and a glue layer in the gate trench; removing the glue layer and the work function layer from the upper trench; after the removal, filling the gate trench with a gate electrode material; and removing the gate electrode material from the upper trench, the remaining portion of the gate electrode material forming a gate electrode.

[0086] Example 2 is the method described in Example 1, wherein, after removing the glue layer and the work function layer, the remaining portion of the glue layer and the remaining portion of the work function layer have a curved upper surface, and the curved upper surface extends below the interface between the upper groove and the lower groove.

[0087] Example 3 is the method described in Example 1, wherein forming the gate trench includes: performing one or more etching processes to remove the dummy gate; and after removing the dummy gate, performing another etching process to remove an upper portion of the first gate spacer.

[0088] Example 4 is the method described in Example 3, wherein a second gate spacer surrounds the first gate spacer, wherein after removing an upper portion of the first gate spacer, a sidewall of the second gate spacer located above a remaining lower portion of the first gate spacer defines the upper trench.

[0089] Example 5 is the method of Example 1, wherein the upper groove is wider than the lower groove.

[0090] Example 6 is the method described in Example 1, wherein removing the glue layer and the work function layer from the upper groove includes: performing a first etching process to selectively remove the glue layer from the upper groove; and after the first etching process, performing a second etching process to selectively remove the work function layer from the upper groove.

[0091] Example 7 is the method described in Example 6, further comprising: forming a silicon-containing cap layer between the work function layer and the glue layer; and removing the silicon-containing cap layer from the upper trench before filling the gate trench with the gate electrode material.

[0092] Example 8 is the method described in Example 7, wherein removing the silicon-containing cap layer includes: performing a third etching process after the first etching process and before the second etching process, the third etching process removing a portion of the silicon-containing cap layer, a portion of the glue layer, and a portion of the work function layer.

[0093] Example 9 is the method described in Example 1, wherein the glue layer and the work function layer are removed from the upper trench to expose the upper portion of the gate dielectric layer disposed in the upper trench, wherein the method further includes: after removing the glue layer and the work function layer from the upper trench and before filling the gate trench, forming the glue layer again in the gate trench and on the exposed upper portion of the gate dielectric layer.

[0094] Example 10 is the method described in Example 9, wherein removing the gate electrode material from the upper trench includes: performing a first wet etching process to selectively remove the gate electrode material, wherein removing the gate electrode material from the upper trench exposes an upper portion of the glue layer disposed in the upper trench.

[0095] Example 11 is the method described in Example 10, further comprising: after removing the gate electrode material from the upper trench, performing a second wet etching process to selectively remove the upper portion of the glue layer disposed in the upper trench; and after the second wet etching process, performing a dry etching process to remove the upper portion of the gate dielectric layer disposed in the upper trench.

[0096] Example 12 is a method for forming a semiconductor device, the method comprising: forming a gate trench in a dielectric material by removing a dummy gate and by removing an upper portion of a first gate spacer surrounding the dummy gate, wherein the gate trench includes a lower trench located between the remaining lower portions of the first gate spacer and includes an upper trench located above the lower trench; lining the sidewalls and bottom of the gate trench by sequentially forming a gate dielectric layer, a work function layer, a cap layer and a first glue layer in the gate trench; removing the first glue layer, the cap layer and the work function layer from the upper trench; forming a second glue layer in the gate trench after removing the first glue layer, the cap layer and the work function layer; filling the gate trench with a gate metal after forming the second glue layer; removing the gate metal from the upper trench, the remaining portion of the gate metal located in the lower trench forming a gate electrode; and removing the second glue layer and the gate dielectric layer from the upper trench after removing the gate metal.

[0097] Example 13 is the method of Example 12, wherein a first width of the upper groove is greater than a second width of the lower groove.

[0098] Example 14 is the method described in Example 12, wherein removing the first glue layer, the cap layer and the work function layer from the upper groove includes: performing a first wet etching process using a first mixture of an acid and a first oxidant to selectively remove the first glue layer; after the first wet etching process, performing a second wet etching process using a fluoride-containing chemical to remove the cap layer; and after the second wet etching process, performing a third wet etching process using a second mixture of an alkali and a second oxidant to selectively remove the work function layer.

[0099] Example 15 is the method described in Example 12, wherein removing the second glue layer and the gate dielectric layer from the upper groove includes: performing a wet etching process using a mixture of fluoride-containing chemicals, metal inhibitors, and oxidants to selectively remove the second glue layer; and after the wet etching process, performing a dry etching process to remove the gate dielectric layer.

[0100] Example 16 is a semiconductor device comprising: a fin protruding above a substrate; a first metal gate located above the fin; a first gate spacer extending along a sidewall of the first metal gate; a second gate spacer extending along a sidewall of the first gate spacer, a second upper surface of the second gate spacer away from the substrate extending farther from the substrate than a first upper surface of the first gate spacer away from the substrate; a dielectric material surrounded by the second gate spacer and extending from the first upper surface of the first gate spacer to the second upper surface of the second gate spacer; and a first gate contact extending through the dielectric material and electrically coupled to the first metal gate.

[0101] Example 17 is the semiconductor device of Example 16, wherein the first upper surface of the first gate spacer is substantially flush with an upper surface of the first metal gate.

[0102] Example 18 is a semiconductor device as described in Example 16, wherein the first metal gate includes a gate dielectric layer, wherein the sidewalls of the first gate spacer contact the gate dielectric layer of the first metal gate, and the sidewalls of the second gate spacer contact the sidewalls of the first gate spacer.

[0103] Example 19 is a semiconductor device described in Example 18, wherein the first metal gate further includes: a work function layer located above the gate dielectric layer, a silicon-containing cap layer located above the work function layer, a glue layer located above the silicon-containing cap layer, and a gate electrode located above the glue layer.

[0104] Example 20 is the semiconductor device of Example 19, wherein the silicon-containing capping layer has a U-shaped cross-section.

Claims

1. A method for forming a semiconductor device, the method comprising: surrounding a dummy gate disposed above the fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing an upper portion of a first gate spacer disposed along a sidewall of the dummy gate, the gate trench including a lower trench located between remaining lower portions of the first gate spacers and including an upper trench located above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer in sequence in the gate trench; removing the glue layer and the work function layer from the upper trench, wherein removing the glue layer and the work function layer from the upper trench exposes an upper portion of the gate dielectric layer disposed in the upper trench; After removing the glue layer and the work function layer from the upper trench, forming the glue layer again in the gate trench and on the exposed upper portion of the gate dielectric layer; After forming the glue layer again, filling the gate trench with a gate electrode material; as well as The gate electrode material is removed from the upper trench, and the remaining portion of the gate electrode material forms a gate electrode.

2. The method according to claim 1, wherein: After removing the glue layer and the work function layer, a remaining portion of the glue layer and a remaining portion of the work function layer have a curved upper surface extending below an interface between the upper trench and the lower trench.

3. The method according to claim 1, wherein: Forming the gate trench comprises: performing one or more etching processes to remove the dummy gate; and After removing the dummy gate, another etching process is performed to remove an upper portion of the first gate spacer.

4. The method according to claim 3, wherein: A second gate spacer surrounds the first gate spacer, wherein after removing the upper portion of the first gate spacer, sidewalls of the second gate spacer over a remaining lower portion of the first gate spacer define the upper trench.

5. The method according to claim 1, wherein: The upper trench is wider than the lower trench.

6. The method according to claim 1, wherein: Removing the glue layer and the work function layer from the upper groove comprises: performing a first etching process to selectively remove the glue layer from the upper trench; and After the first etching process, a second etching process is performed to selectively remove the work function layer from the upper trench.

7. The method according to claim 6, further comprising: forming a silicon-containing capping layer between the work function layer and the glue layer; as well as The silicon-containing capping layer is removed from the upper trench before filling the gate trench with the gate electrode material.

8. The method according to claim 7, wherein: Removing the silicon-containing capping layer includes performing a third etching process after the first etching process and before the second etching process, the third etching process removing a portion of the silicon-containing capping layer, a portion of the glue layer, and a portion of the work function layer.

9. The method according to claim 1, wherein: Removing the gate electrode material from the upper trench includes performing a first wet etching process to selectively remove the gate electrode material, wherein removing the gate electrode material from the upper trench exposes an upper portion of the glue layer disposed in the upper trench.

10. The method according to claim 9, further comprising: After removing the gate electrode material from the upper trench, performing a second wet etching process to selectively remove an upper portion of the glue layer disposed in the upper trench; as well as After the second wet etching process, a dry etching process is performed to remove an upper portion of the gate dielectric layer disposed in the upper trench.

11. A method for forming a semiconductor device, the method comprising: forming a gate trench in the dielectric material by removing a dummy gate and by removing an upper portion of a first gate spacer surrounding the dummy gate, wherein the gate trench includes a lower trench located between remaining lower portions of the first gate spacers and includes an upper trench located above the lower trench; Forming a lining on the sidewall and bottom of the gate trench by sequentially forming a gate dielectric layer, a work function layer, a cap layer and a first glue layer in the gate trench; removing the first glue layer, the cap layer and the work function layer from the upper groove; After removing the first glue layer, the cap layer and the work function layer, forming a second glue layer in the gate trench; After forming the second glue layer, filling the gate trench with a gate metal; removing the gate metal from the upper trench, the remaining portion of the gate metal in the lower trench forming a gate electrode; and After removing the gate metal, removing the second glue layer and the gate dielectric layer from the upper trench.

12. The method according to claim 11, wherein: The first width of the upper trench is greater than the second width of the lower trench.

13. The method according to claim 11, wherein: Removing the first glue layer, the cap layer, and the work function layer from the upper groove includes: performing a first wet etching process using a first mixture of an acid and a first oxidizing agent to selectively remove the first glue layer; After the first wet etching process, performing a second wet etching process using a fluoride-containing chemical to remove the capping layer; and After the second wet etching process, a third wet etching process is performed using a second mixture of an alkali and a second oxidizing agent to selectively remove the work function layer.

14. The method according to claim 11, wherein: Removing the second glue layer and the gate dielectric layer from the upper trench comprises: performing a wet etching process using a mixture of a fluoride-containing chemical, a metal inhibitor, and an oxidant to selectively remove the second glue layer; and After the wet etching process, a dry etching process is performed to remove the gate dielectric layer.

15. A semiconductor device comprising: fins, which protrude above the substrate; A first metal gate located above the fin; a first gate spacer extending along a sidewall of the first metal gate; a second gate spacer extending along a sidewall of the first gate spacer, wherein a second upper surface of the second gate spacer, which is away from the substrate, extends further from the substrate than a first upper surface of the first gate spacer, which is away from the substrate; a dielectric material surrounded by the second gate spacer and extending from the first upper surface of the first gate spacer to the second upper surface of the second gate spacer; as well as a first gate contact extending through the dielectric material and electrically coupled to the first metal gate, The first metal gate further includes: a gate dielectric layer, a work function layer located above the gate dielectric layer, a silicon-containing cap layer located above the work function layer, a glue layer located above the silicon-containing cap layer, and a gate electrode located above the glue layer.

16. The semiconductor device according to claim 15, wherein: The first upper surface of the first gate spacer is substantially flush with an upper surface of the first metal gate.

17. The semiconductor device according to claim 15, wherein: A sidewall of the first gate spacer contacts the gate dielectric layer of the first metal gate, and a sidewall of the second gate spacer contacts the sidewall of the first gate spacer.

18. The semiconductor device according to claim 15, wherein: The silicon-containing capping layer has a U-shaped cross section.

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