Chip packaging structure with shielding function and its packaging method

Abstract

The present invention discloses a chip packaging method with a shielding function, including: providing a second substrate made of glass and a dielectric layer attached to one side thereof, forming a first redistribution layer embedded in the dielectric layer on one side of the dielectric layer, forming a plurality of grooves on the surface of the first redistribution layer flush with the dielectric layer to obtain a first sub-substrate; providing a third substrate made of glass, manufacturing a metal shielding layer and a plurality of conductive posts embedded in the third substrate and the metal shielding layer on the third substrate, so that the conductive posts have protrusions protruding from the metal shielding layer to obtain a second sub-substrate; aligning and embedding the protrusions into the grooves to make the first sub-substrate and the second sub-substrate fit and connect to obtain a substrate for chip packaging; providing a plurality of chip sets, flip-chip mounting them on the side where the circuits are exposed, encapsulating the chip sets and electrically leading out the chip sets on the other side of the circuits. The present invention can effectively reduce the warpage generated by chip packaging, enhance the electromagnetic shielding function of the chip, and improve the yield of the chip packaging structure.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and particularly relates to a chip packaging structure with a shielding function and a packaging method thereof. Background Art

[0002] With the trend of miniaturization and integration of electronic products, the high density of microelectronic packaging technology has gradually become the mainstream in new-generation electronic products. In order to conform to the development of new-generation electronic products, especially the development of products such as mobile phones, laptops, and smart wearable devices, chips are developing in the directions of higher density, faster speed, smaller size, and lower cost.

[0003] During the packaging process, due to the differences in the thermal expansion coefficients of materials such as plastic, silicon, and metal, the volume changes of these materials are out of sync, resulting in stress and warping. Among them, the difference in the thermal expansion coefficients of the chip and the injection molding material causes the stress generated during the cooling process of the injection molding material, which is the main reason for warping in packaging technology.

[0004] In addition, during the chip fan-out packaging process, it is usually necessary to drill holes in the plastic encapsulation layer of the encapsulated flip-chip for electroplating to make conductive posts, so as to electrically lead out the inverted chip. During the hole-opening process, it is difficult to control the depth of the hole, and it is easy to damage the chip or break through other conductive lines, affecting the yield of the chip packaging structure. Summary of the Invention

[0005] The purpose of the present invention is to provide a chip packaging method with a shielding function and a chip packaging structure with a shielding function prepared by using this method, which can effectively reduce the warping generated during chip packaging, enable the chip to have an electromagnetic shielding function, and improve the yield of the chip packaging structure.

[0006] To achieve this purpose, the present invention adopts the following technical solutions:

[0007] On the one hand, a chip packaging method with a shielding function is provided, including:

[0008] Providing a second substrate made of glass and a dielectric layer attached to one side of the second substrate, forming a first redistribution layer embedded in the dielectric layer and flush with one surface of the dielectric layer on the side of the dielectric layer away from the second substrate, and forming a plurality of grooves on the surface of the first redistribution layer flush with the dielectric layer to obtain a first sub-substrate;

[0009] Providing a third substrate made of glass, fabricating a metal shielding layer on the third substrate and fabricating a plurality of conductive posts embedded in the third substrate and the metal shielding layer, and making the conductive posts have a boss protruding from the metal shielding layer and making the position of the boss correspond to the position of the groove one by one to obtain a second sub-substrate;

[0010] Align and embed the boss into the groove, and bond the first sub-substrate and the second sub-substrate together to obtain a substrate for chip packaging. At least the conductive posts and the first redistribution layer form the circuit of the substrate for chip packaging;

[0011] Provide a number of chip sets, flip-chip the chip sets on the exposed side of the circuit and electrically connect them to the circuit, encapsulate the chip sets, and electrically lead out the chip sets on the other side of the circuit.

[0012] In the present invention, a first redistribution layer with a groove structure is directly formed on a second glass substrate, and conductive posts with bosses are fabricated on a third glass substrate. The conductive posts are inserted into the grooves to be connected to the first redistribution layer to obtain a substrate for chip packaging for encapsulating chips, avoiding the adverse effects caused by making conductive posts after chip mounting, and at the same time reducing the warping phenomenon generated during the chip packaging process. The metal shielding layer is located inside the chip packaging structure and on one side of the chip sets, which can effectively enhance the electromagnetic shielding effect of the chip packaging structure.

[0013] As a preferred embodiment of the chip packaging method with shielding function, the first sub-substrate is specifically obtained by the following steps:

[0014] S10a. Provide a first substrate made of glass with a number of bumps on one surface, and fabricate a first seed layer made of copper on the first substrate;

[0015] S10b. Fabricate a first photosensitive dry film on the first seed layer, and open a patterned window at least exposing each bump;

[0016] S10c. Fabricate a first redistribution layer in the patterned window;

[0017] S10d. Remove the remaining first photosensitive dry film;

[0018] S10e. Etch away the first seed layer exposed outside the first redistribution layer;

[0019] S10f. Press a dielectric material on the first redistribution layer to form a dielectric layer;

[0020] S10g. Provide a second substrate made of glass, and attach the dielectric layer to the second substrate;

[0021] S10h. Remove the first substrate, and form a groove on the first redistribution layer.

[0022] Among them, the first seed layer made of copper can improve the connection stability between the subsequent conductive posts and the first redistribution layer.

[0023] As a preferred embodiment of the chip packaging method with a shielding function, the bump is a hemispherical structure or a conical structure, and the groove is a hemispherical structure or a conical structure that matches the boss.

[0024] Specifically, when the bump is a conical structure, the area of one end of the bump away from the first substrate is slightly smaller than the area of the end connected to the first substrate, so as to facilitate the subsequent close fit between the groove formed on the first redistribution layer and the boss of the conductive pillar.

[0025] As a preferred embodiment of the chip packaging method with a shielding function, the second sub-substrate is specifically prepared by the following steps:

[0026] S20a. Provide a third substrate made of glass, and fabricate a metal shielding layer on one side of the third substrate;

[0027] S20b. Open TGV vias on the third substrate and the metal shielding layer;

[0028] S20c. Fabricate conductive pillars in the TGV vias, and make one end of the conductive pillar flush with the side of the third substrate away from the metal shielding layer, and the other end protrude from the metal shielding layer to form the boss.

[0029] Optionally, a metal shielding layer made of copper or silver can be fabricated on the third substrate by electroplating, or a metal shielding layer made of silver or titanium tungsten can be fabricated on the third substrate by vacuum sputtering, or a metal shielding layer made of various metal materials such as copper or silver can be fabricated on the third substrate by electroless plating.

[0030] As a preferred embodiment of the chip packaging method with a shielding function, the substrate for chip packaging is specifically prepared by the following steps:

[0031] S30a. Coat the first sub-substrate and / or the second sub-substrate with nano metal powder, align the boss on the second sub-substrate with the groove on the first sub-substrate and insert it, and melt and fill the nano metal powder between the boss and the groove by hot pressing to form a metal connection layer, so as to bond and connect the first sub-substrate and the second sub-substrate; wherein, the nano metal powder can be nano copper powder, or other metal materials that can be melted by heating, preferably nano copper powder, which is consistent with the materials of the first redistribution layer and the conductive pillar, and can improve the electrical connection stability;

[0032] Alternatively, after the first sub-substrate and the second sub-substrate are subjected to plasma cleaning to remove surface impurities, the boss is aligned and inserted into the groove, and then the first sub-substrate and the second sub-substrate are bonded and connected by electrostatic adsorption;

[0033] S30b. Fabricate a second seed layer electrically connected to the conductive pillars on the third substrate and a second redistribution layer on the second seed layer to obtain a substrate for chip packaging. At least the conductive pillars, the first redistribution layer, the second seed layer, and the second redistribution layer form the circuit.

[0034] Among them, step S30b specifically includes:

[0035] Fabricate a second seed layer electrically connected to the conductive pillars on the third substrate by vacuum sputtering;

[0036] Attach a second photosensitive dry film on the second seed layer, and form a patterned window through exposure and development processing;

[0037] Fabricate a second redistribution layer within the patterned window by electroplating;

[0038] Remove the remaining second photosensitive dry film and the second seed layer exposed outside the second redistribution layer.

[0039] As a preferred embodiment of a chip packaging method with a shielding function, the chip packaging includes the following specific steps:

[0040] S40a. Provide a plurality of chip sets, and flip-chip the chip sets onto the second redistribution layer;

[0041] S40b. Encapsulate the chip sets to form an encapsulation layer;

[0042] S40c. Remove the second substrate, and perform an opening process on the dielectric layer to expose the pad area of the first redistribution layer;

[0043] S40d. Provide a plurality of metal bumps, and implant the metal bumps into the pad area to be electrically connected to the first redistribution layer.

[0044] On the other hand, provide a chip packaging structure obtained by the above-mentioned chip packaging method with a shielding function, including:

[0045] A substrate for chip packaging, comprising a third substrate, a metal shielding layer on one side of the third substrate, and a plurality of conductive posts embedded in the third substrate and the metal shielding layer. One end of the conductive post is flush with the surface of the third substrate away from the metal shielding layer, and the other end protrudes from the metal shielding layer to form a boss; it further includes a dielectric layer on the side of the metal shielding layer away from the third substrate, a first redistribution layer with a plurality of grooves embedded in the dielectric layer, and a first seed layer made of copper on the side of the first redistribution layer away from the dielectric layer. The openings of the grooves are located on the side of the first redistribution layer close to the metal shielding layer, and the bosses are connected to the grooves one by one. The dielectric layer is provided with holes for exposing the pad areas of the first redistribution layer;

[0046] A plurality of chip sets, flip-chip mounted on the side of the third substrate away from the metal shielding layer and electrically connected to the conductive posts;

[0047] A plastic encapsulation layer, located on the third substrate and covering the chip sets:

[0048] A plurality of metal bumps, implanted in the pad areas and electrically connected to the first redistribution layer.

[0049] The metal shielding layer of the present invention is located inside the chip packaging structure and on one side of the third substrate, which can effectively reduce the warping phenomenon generated during the chip packaging process, enhance the electromagnetic shielding effect of the chip packaging structure, and improve the yield of the substrate structure for chip packaging.

[0050] As a preferred solution of the chip packaging structure with shielding function, it further includes a second seed layer on the third substrate and a second redistribution layer on the second seed layer. The second redistribution layer is electrically connected to the conductive posts, and a plurality of the chip sets are flip-chip mounted on the second redistribution layer and electrically connected to the second redistribution layer. The plastic encapsulation layer is located on the side of the third substrate away from the metal shielding layer and covers the chip sets.

[0051] As a preferred solution of the chip packaging structure with shielding function, the substrate for chip packaging further includes a metal connection layer, and the metal connection layer is filled between the conductive post and the groove to connect the conductive post and the groove.

[0052] Furthermore, the metal connection layer, the conductive post, and the first redistribution layer are made of the same material to improve the connection stability.

[0053] Even further, the metal connection layer, the conductive post, and the first redistribution layer are all made of copper material, which can further improve the connection stability and make the electrical signal transmission more stable.

[0054] As a preferred embodiment of the chip packaging structure with shielding function, the boss is a hemispherical structure or a conical structure, and the groove is a hemispherical structure or a conical structure that matches the boss.

[0055] As a preferred embodiment of the chip packaging structure with shielding function, the metal shielding layer is made of any one of copper, silver, and titanium tungsten to improve the electromagnetic shielding effect of the chip packaging structure.

[0056] As a preferred embodiment of the chip packaging structure with shielding function, the third substrate is made of glass.

[0057] Advantages of the present invention: The present invention directly forms the first rewiring layer with a groove structure on the second substrate made of glass, and manufactures the conductive posts with bosses on the third substrate made of glass. The conductive posts are inserted into the grooves to be connected with the first rewiring layer to obtain the substrate for chip packaging used to package chips, avoiding the adverse effects caused by making conductive posts after chip mounting, and at the same time reducing the warping phenomenon generated during the chip packaging process. The metal shielding layer is located inside the chip packaging structure and on one side of the chip group, which can effectively enhance the electromagnetic shielding effect of the chip packaging structure and improve the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly introduced below. Obviously, the following described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0059] Figure 1 It is a cross-sectional schematic view of the first photosensitive dry film in Embodiment 1 of the present invention attached to the first substrate.

[0060] Figure 2 It is a cross-sectional schematic view of the first photosensitive dry film after exposure and development in Embodiment 1 of the present invention.

[0061] Figure 3 It is a cross-sectional schematic view of the first rewiring layer fabricated on the first substrate in Embodiment 1 of the present invention.

[0062] Figure 4 It is a cross-sectional schematic view of the residual first photosensitive dry film removed in Embodiment 1 of the present invention.

[0063] Figure 5 It is a cross-sectional schematic view of the dielectric layer attached to the first substrate and covering the first rewiring layer in Embodiment 1 of the present invention.

[0064] Figure 6It is a cross-sectional schematic diagram after removing the first substrate and attaching the dielectric layer to the second substrate according to the first embodiment of the present invention.

[0065] Figure 7 It is a cross-sectional schematic diagram after fabricating a metal shielding layer on the third substrate according to the first embodiment of the present invention.

[0066] Figure 8 It is a cross-sectional schematic diagram after opening TGV vias in the third substrate and the metal shielding layer according to the first embodiment of the present invention.

[0067] Figure 9 It is a cross-sectional schematic diagram after electroplating conductive pillars in the TGV vias according to the first embodiment of the present invention.

[0068] Figure 10 It is a cross-sectional schematic diagram after bonding the first sub-substrate and the second sub-substrate according to the first embodiment of the present invention.

[0069] Figure 11 It is a cross-sectional schematic diagram after flip-chip mounting the chip group on the substrate for chip packaging and electrically connecting it to one end face of the conductive pillar according to the first embodiment of the present invention.

[0070] Figure 12 It is a cross-sectional schematic diagram after encapsulating the chip group according to the first embodiment of the present invention.

[0071] Figure 13 It is a cross-sectional schematic diagram after implanting metal bumps according to the first embodiment of the present invention.

[0072] Figure 14 It is a cross-sectional schematic diagram after fabricating a second redistribution layer on the third substrate according to the second embodiment of the present invention.

[0073] Figure 15 It is a cross-sectional schematic diagram after flip-chip mounting the chip group on the second redistribution layer according to the second embodiment of the present invention.

[0074] Figure 16 It is a cross-sectional schematic diagram after encapsulating the chip group according to the second embodiment of the present invention.

[0075] Figure 17 It is a cross-sectional schematic diagram after implanting metal bumps according to the second embodiment of the present invention.

[0076] In the figure:

[0077] 11. First substrate; 12. Bump; 13. First photosensitive dry film; 14. First redistribution layer; 15. Dielectric layer; 16. Second substrate; 17. Groove; 21. Third substrate; 22. Metal shielding layer; 23. TGV via; 24. Conductive pillar; 25. Second redistribution layer; 31. Chip group; 32. Encapsulation layer; 33. Metal bump. Detailed implementation manners

[0078] The technical solution of the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0079] Among them, the accompanying drawings are only for illustrative purposes, showing only schematic diagrams, not physical diagrams, and should not be construed as a limitation of this patent; in order to better illustrate the embodiments of the present invention, some components in the accompanying drawings will be omitted, enlarged or reduced, which do not represent the dimensions of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the accompanying drawings may be omitted.

[0080] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if terms such as "upper", "lower", "left", "right", "inner", "outer", etc. are used to indicate the orientation or positional relationship, it is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the accompanying drawings are only for illustrative purposes and should not be construed as a limitation of this patent. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0081] In the description of the present invention, unless otherwise clearly defined and limited, if terms such as "connection" are used to indicate the connection relationship between components, this term should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0082] Embodiment 1

[0083] The chip packaging method with a shielding function in this embodiment includes the following steps:

[0084] Step S10: Prepare the first sub-substrate:

[0085] S10a: Provide a first substrate 11 made of glass and having a plurality of hemispherical bumps 12 on one surface, and deposit a first seed layer made of copper on the first substrate 11;

[0086] S10b: Refer to Figure 1 , make a first photosensitive dry film 13 on the first seed layer, and open a patterned window through exposure and development at least to expose each bump 12, refer to Figure 2 ;

[0087] S10c. Fabricate the first rewiring layer 14 within the patterned window by electroplating, with the upper surface of the first rewiring layer 14 flush with the upper surface of the first photosensitive dry film 13. Refer to Figure 3 ;

[0088] S10d. Remove the remaining first photosensitive dry film 13. Refer to Figure 4 ;

[0089] S10e. Etch away the first seed layer exposed outside the first rewiring layer 14;

[0090] S10f. Press a dielectric material onto the first rewiring layer 14 to form a dielectric layer 15. Refer to Figure 5 ;

[0091] S10g. Provide a second substrate 16 made of glass, and attach the dielectric layer 15 to the second substrate 16 through a temporary bonding adhesive;

[0092] S10h. Remove the first substrate 11, and form a hemispherical groove 17 on the first rewiring layer 14. Refer to Figure 6 。

[0093] Step S20. Prepare a second sub-substrate:

[0094] S20a. Provide a third substrate 21 made of glass, and fabricate a metal shielding layer 22 made of copper on one side of the third substrate 21 by electroplating. Refer to Figure 7 ;

[0095] S20b. Open TGV vias 23 on the third substrate 21 and the metal shielding layer 22. Refer to Figure 8 ;

[0096] S20c. Fabricate conductive posts 24 within the TGV vias 23 by electroplating, and make one end of the conductive posts 24 flush with the side of the third substrate 21 away from the metal shielding layer 22, and the other end protrude from the metal shielding layer 22 to form a hemispherical boss. Refer to Figure 9 。

[0097] Step S30. Prepare a substrate for chip packaging:

[0098] Dip the first sub-substrate and the second sub-substrate with nano copper powder respectively, align the boss on the second sub-substrate with the groove 17 on the first sub-substrate and insert it, and melt and fill the nano copper powder between the boss and the groove 17 through hot pressing to form a metal connection layer, so that the first sub-substrate and the second sub-substrate are bonded and connected. Refer to Figure 10 。

[0099] Step S40. Chip packaging:

[0100] S40a. Provide a plurality of chip sets 31, flip-chip the chip sets 31 on the exposed side of the conductive posts 24, refer to Figure 11 ;

[0101] S40b. Encapsulate the chip sets 31 to form an encapsulation layer 32, refer to Figure 12 ;

[0102] S40c. Remove the second substrate 16, perform an opening process on the dielectric layer 15 to expose the pad area of the first redistribution layer 14;

[0103] S40d. Provide a plurality of metal bumps 33, implant the metal bumps 33 into the pad area to be electrically connected to the first redistribution layer 14, refer to Figure 13 。

[0104] Wherein, the metal bumps 33 are solder, silver solder or gold-tin alloy solder, and in this embodiment, it is preferably a tin ball made of solder.

[0105] This embodiment includes two groups of chip sets 31, and each group of chip sets includes three chips. In other embodiments, the number of chip sets and the number of chips in each chip set are determined according to specific design requirements, and are not specifically limited.

[0106] The chip package structure with shielding function obtained by using the chip packaging method with shielding function of this embodiment is as Figure 13 shown, including:

[0107] A substrate for chip packaging, including a third substrate 21, a metal shielding layer 22 made of copper on one side of the third substrate 21, and a plurality of conductive posts 24 embedded in the third substrate 21 and the metal shielding layer 22. The conductive posts 24 are made of copper. One end of the conductive post 24 is flush with the side of the third substrate 21 away from the metal shielding layer 22, and the other end protrudes from the metal shielding layer 22 to form a boss; it also includes a dielectric layer 15 on the side of the metal shielding layer 22 away from the third substrate 21, a first redistribution layer 14 with a plurality of grooves 17 embedded in the dielectric layer 15, and a first seed layer made of copper on the side of the first redistribution layer 14 away from the dielectric layer 15. The opening of the groove 17 is located on the side of the first redistribution layer 14 close to the metal shielding layer 22. The boss is connected to the groove 17 in a one-to-one correspondence. The dielectric layer 15 is provided with a hole for the pad area of the first redistribution layer 14 to be exposed;

[0108] A plurality of chip sets 31, flip-chip on the side of the third substrate 21 away from the metal shielding layer 22 and electrically connected to the conductive posts 24;

[0109] The plastic encapsulation layer 32 is located on the third substrate 21 and covers the chipset 31:

[0110] A plurality of solder balls (metal bumps 33) are implanted and electrically connected to the pad area and the first rewiring layer 14.

[0111] In this embodiment, the metal shielding layer 22 is made of copper, is located inside the chip packaging structure, and is located on one side of the third substrate 21, which can effectively reduce the warping phenomenon generated during the chip packaging process, enhance the electromagnetic shielding effect of the chip packaging structure, and improve the yield of the substrate structure for chip packaging.

[0112] Furthermore, the substrate for chip packaging further includes a metal connection layer, and the metal connection layer is filled between the conductive posts 24 and the grooves 17 to enhance the stability of chip signal transmission.

[0113] The boss is a hemispherical structure, and the groove 17 is a hemispherical structure that matches the boss.

[0114] Embodiment 2

[0115] This embodiment is basically the same as the above Embodiment 1 (refer to some of the drawings in the above Embodiment 1, and the same components use the same reference numerals as in the above Embodiment 1), and the difference lies in steps S30 and S40.

[0116] Specifically, the preparation of the substrate for chip packaging in step S30 includes the following steps:

[0117] S30a. Coat the first sub-substrate and the second sub-substrate with nano copper powder respectively, align the boss on the second sub-substrate with the groove 17 on the first sub-substrate and insert it, and melt the nano copper powder by hot pressing to fill the space between the boss and the groove 17 to form a metal connection layer, so as to bond and connect the first sub-substrate and the second sub-substrate;

[0118] S30b. Fabricate a second seed layer electrically connected to the conductive posts 24 on the third substrate 21 by vacuum sputtering;

[0119] Attach a second photosensitive dry film on the second seed layer, and form a patterned window through exposure and development processing;

[0120] Fabricate a second rewiring layer 25 in the patterned window by electroplating;

[0121] Remove the remaining second photosensitive dry film and the second seed layer exposed outside the second rewiring layer 25 to obtain the structure as Figure 14 described.

[0122] Specifically, the chip packaging in step S40 includes the following steps:

[0123] S40a. Provide a plurality of chip sets 31, flip-chip the chip sets 31 on the second redistribution layer 25, refer to Figure 15 ;

[0124] S40b. Encapsulate the chip sets 31 to form an encapsulation layer 32, refer to Figure 16 ;

[0125] S40c. Remove the second substrate 16, perform an opening process on the dielectric layer 15 to expose the pad area of the first redistribution layer 14;

[0126] S40d. Provide a plurality of solder balls (metal bumps 33), implant the solder balls into the pad area to be electrically connected to the first redistribution layer 14, refer to Figure 17 .

[0127] Among them, the metal shielding layer 22 is a silver metal shielding layer obtained by electroless plating.

[0128] In this embodiment, a second seed layer and a second redistribution layer 25 are fabricated on the basis of the above-mentioned Embodiment 1, increasing the mounting range of the chip sets 31, avoiding the situation that the exposed end face area of the conductive pillars 24 is too small and affecting the smooth assembly of the chip sets 31, and further improving the yield of the chip packaging structure.

[0129] The chip packaging structure with shielding function obtained by using the chip packaging method with shielding function of this embodiment is basically the same as the chip packaging structure obtained by the above-mentioned Embodiment 1, the difference being that it further includes a second seed layer and a second redistribution layer 25.

[0130] As Figure 17 shown, the chip packaging structure with shielding function of this embodiment further includes a second seed layer on the third substrate 21 and a second redistribution layer 25 on the second seed layer. The second redistribution layer 25 is electrically connected to the conductive pillars 24 through the second seed layer. A plurality of the chip sets 31 are flip-chip on the second redistribution layer 25 and electrically connected to the second redistribution layer 25. The encapsulation layer 32 is located on the side of the third substrate 21 away from the metal shielding layer 22 and covers the chip sets 31.

[0131] By fabricating a second seed layer and a second redistribution layer 25 electrically connected to the conductive pillars 24 on the third substrate 21, the restricted range during the flip-chip of the chip sets 31 is reduced, facilitating the flip-chip of the chip sets 31 and improving the yield of the chip packaging structure.

[0132] Embodiment 3

[0133] This embodiment is basically the same as the above-mentioned Embodiment 2 (refer to the drawings in the above-mentioned Embodiment 1, and the same components use the reference numerals in the above-mentioned Embodiment 1), the difference being S30a in step S30.

[0134] Specifically, the preparation of the substrate for chip packaging in step S30a includes the following steps:

[0135] Perform plasma cleaning on the first sub-substrate and the second sub-substrate. After removing surface impurities, align and embed the boss into the groove 17, and then make the first sub-substrate and the second sub-substrate fit and connect through electrostatic adsorption.

[0136] The chip packaging structure with a shielding function in this embodiment is basically the same as the second embodiment above, except that it does not include a metal connection layer, and details are not described again.

[0137] It should be stated that the above specific implementation manners are only the preferred embodiments of the present invention and the technical principles applied. Those skilled in the art should understand that various modifications, equivalent replacements, changes, etc. can be made to the present invention. However, as long as these transformations do not deviate from the spirit of the present invention, they should be within the protection scope of the present invention. In addition, some terms used in the specification and claims of this application are not restrictive, but are only for the convenience of description.

Claims

1. A chip packaging method with a shielding function, characterized in that, it includes: providing a second substrate made of glass and a dielectric layer attached to one side of the second substrate, forming a first redistribution layer embedded in the dielectric layer and flush with one surface of the dielectric layer on the side of the dielectric layer away from the second substrate, and forming a plurality of grooves on the surface of the first redistribution layer flush with the dielectric layer to obtain a first sub-substrate; providing a third substrate made of glass, fabricating a metal shielding layer on the third substrate and fabricating a plurality of conductive posts embedded in the third substrate and the metal shielding layer, and making the conductive posts have bosses protruding from the metal shielding layer and making the positions of the bosses correspond to those of the grooves one by one to obtain a second sub-substrate; aligning and embedding the bosses into the grooves, and attaching and connecting the first sub-substrate and the second sub-substrate to obtain a substrate for chip packaging, and at least the conductive posts and the first redistribution layer form the circuit of the substrate for chip packaging; providing a plurality of chip groups, flip-chip mounting the chip groups on the exposed side of the circuit and electrically connecting them to the circuit, encapsulating the chip groups and electrically leading out the chip groups on the other side of the circuit.

2. The chip packaging method with a shielding function according to claim 1, characterized in that, the first sub-substrate is specifically obtained by the following steps: S10a. Providing a first substrate made of glass and having a plurality of bumps on one surface, and fabricating a first seed layer made of copper on the first substrate; S10b. Fabricating a first photosensitive dry film on the first seed layer and opening a patterned window at least exposing each bump; S10c. Fabricating a first redistribution layer in the patterned window; S10d. Removing the remaining first photosensitive dry film; S10e. Etching away the first seed layer exposed outside the first redistribution layer; S10f. Pressing a dielectric material on the first redistribution layer to form a dielectric layer; S10g. Providing a second substrate made of glass and attaching the dielectric layer to the second substrate; S10h. Removing the first substrate and forming grooves on the first redistribution layer.

3. The chip packaging method with a shielding function according to claim 2, characterized in that, the bumps are hemispherical structures or conical structures, and the grooves are hemispherical structures or conical structures matching the bosses.

4. The chip packaging method with a shielding function according to claim 1, characterized in that, the second sub-substrate is specifically obtained by the following steps: S20a. Providing a third substrate made of glass and fabricating a metal shielding layer on one side of the third substrate; S20b. Opening TGV vias on the third substrate and the metal shielding layer; S20c. Fabricating conductive posts in the TGV vias and making one end of the conductive posts flush with the side of the third substrate away from the metal shielding layer and the other end protruding from the metal shielding layer to form the bosses.

5. The chip packaging method with a shielding function according to claim 1, characterized in that, The substrate for chip packaging is specifically prepared by the following steps: S30a. Coat the first sub-substrate and / or the second sub-substrate with nano metal powder, align the bosses on the second sub-substrate with the grooves on the first sub-substrate and insert them. Through hot pressing, the nano metal powder is melted and filled between the bosses and the grooves to form a metal connection layer, so that the first sub-substrate and the second sub-substrate are bonded and connected; Alternatively, perform plasma cleaning on the first sub-substrate and the second sub-substrate, align the bosses and embed them into the grooves, and then bond and connect the first sub-substrate and the second sub-substrate through electrostatic adsorption; S30b. Fabricate a second seed layer electrically connected to the conductive pillars and a second redistribution layer located on the second seed layer on the third substrate to obtain the substrate for chip packaging. At least the conductive pillars, the first redistribution layer, the second seed layer, and the second redistribution layer form the circuit.

6. The chip packaging method with a shielding function according to claim 5, wherein, the chip packaging includes the following specific steps: S40a. Provide a plurality of chip groups and flip-chip the chip groups onto the second redistribution layer; S40b. Encapsulate the chip groups to form an encapsulation layer; S40c. Remove the second substrate, perform an opening process on the dielectric layer to expose the pad area of the first redistribution layer; S40d. Provide a plurality of metal bumps and implant the metal bumps into the pad area to be electrically connected to the first redistribution layer.

7. A chip packaging structure with a shielding function prepared by the chip packaging method with a shielding function according to any one of claims 1 or 4 to 6, wherein, it includes: A substrate for chip packaging, including a third substrate, a metal shielding layer on one side of the third substrate, and a plurality of conductive pillars embedded in the third substrate and the metal shielding layer. One end of the conductive pillar is flush with the surface of the third substrate away from the metal shielding layer, and the other end protrudes from the metal shielding layer to form a boss; it also includes a dielectric layer on the side of the metal shielding layer away from the third substrate and a first redistribution layer with a plurality of grooves embedded in the dielectric layer. The openings of the grooves are located on the side of the first redistribution layer close to the metal shielding layer. The bosses are connected to the grooves in one-to-one correspondence, and the dielectric layer is provided with holes for exposing the pad area of the first redistribution layer; A plurality of chip groups, flip-chip mounted on the side of the third substrate away from the metal shielding layer and electrically connected to the conductive pillars; An encapsulation layer, located on the third substrate and covering the chip groups; A plurality of metal bumps, implanted into the pad area to be electrically connected to the first redistribution layer.

8. The chip packaging structure with a shielding function according to claim 7, wherein, It further includes a second seed layer located on the third substrate and a second rewiring layer located on the second seed layer. The second rewiring layer is electrically connected to the conductive posts. A plurality of the chip sets are flip-chip mounted on the second rewiring layer and electrically connected to the second rewiring layer. The encapsulation layer is located on a side of the third substrate away from the metal shielding layer and covers the chip sets.

9. The chip packaging structure with a shielding function according to claim 7, wherein, the substrate for chip packaging further includes a metal connection layer, and the metal connection layer is filled between the conductive posts and the grooves.

10. The chip packaging structure with a shielding function according to claim 7, wherein, the boss is a hemispherical structure or a conical structure, and the groove is a hemispherical structure or a conical structure that mates with the boss.

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