Semiconductor device and method for forming the same

Abstract

A semiconductor device and a method for forming the same, the semiconductor device comprising: a first chip-on-wafer (CoW) device having a first interposer and a first die attached to a first side of the first interposer; a second chip-on-wafer device having a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced from the first interposer; and a redistribution structure extending along a second side of the first interposer opposite to the first side of the first interposer and extending along a second side of the second interposer opposite to the first side of the second interposer, the redistribution structure extending continuously from the first chip-on-wafer device to the second chip-on-wafer device.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to continued improvements in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In large part, such improvements in integration density come from repeated reductions in minimum feature size, which enables more components to be integrated into a given area.

[0003] As the demand for shrinking electronic devices grows, smaller and more creative semiconductor die packaging technologies are needed. An example of such a packaging system is the Package-on-Package (PoP) technology. In a PoP device, the top semiconductor package is stacked on top of the bottom semiconductor package to provide a high level of integration and component density. Another example is the Chip-On-Wafer-On-Substrate (CoWoS) structure. In some embodiments, to form a CoWoS device, a plurality of semiconductor chips are bonded to a wafer, and then a dicing process is performed to separate the wafer into a plurality of interposers, each of which is bonded with one or more semiconductor chips. The interposer bonded with semiconductor chips is called a Chip-On-Wafer (CoW) device. The CoW device is then bonded to a substrate (e.g., a printed circuit board (PCB)) to form a CoWoS structure. These and other advanced packaging technologies enable the production of semiconductor devices with enhanced functionality and a small footprint. Summary of the invention

[0004] According to one embodiment, the present invention provides a semiconductor device, comprising: a first chip-on-wafer device, comprising a first interposer and a first die attached to a first side of the first interposer; a second chip-on-wafer device, comprising a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced apart from the first interposer; and a redistribution structure, extending along a second side of the first interposer opposite to the first side of the first interposer, and extending along a second side of the second interposer opposite to the first side of the second interposer, the redistribution structure extending continuously from the first chip-on-wafer device to the second chip-on-wafer device.

[0005] According to another embodiment, the present invention provides a semiconductor device, comprising: a substrate, comprising conductive features; and a chip-on-composite wafer device, adhered to a first surface of the substrate, the chip-on-composite wafer device comprising: a first interposer; a first die, coupled to a first side of the first interposer facing away from the substrate; a second interposer, laterally spaced apart from the first interposer; a second die, coupled to a first side of the second interposer facing away from the substrate; a first molding material, located around the first die, the second die, the first interposer and the second interposer; and a redistribution structure, extending continuously along a second side of the first interposer facing the substrate, along a second side of the second interposer facing the substrate and along a first surface of the first molding material facing the substrate.

[0006] According to another embodiment, the present invention provides a method for forming a semiconductor device, the method comprising: bonding a first chip-on-wafer device on a first side of a carrier, the first chip-on-wafer device comprising a first interposer and a first die bonded to the first interposer; bonding a second chip-on-wafer device on the first side of the carrier, adjacent to the first chip-on-wafer device, the second chip-on-wafer device comprising a second interposer and a second die bonded to the second interposer; forming a molding material on the first side of the carrier and around the first chip-on-wafer device and around the second chip-on-wafer device, wherein a first conductive pad of the first interposer and a second conductive pad of the second interposer are exposed at an upper surface of the molding material away from the carrier; and forming a rewiring structure on the first chip-on-wafer device and on top of the second chip-on-wafer device and the molding material, wherein the rewiring structure extends continuously from the first chip-on-wafer device to the second chip-on-wafer device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A cross-sectional view of a chip-on-wafer (CoW) device is shown in accordance with some embodiments.

[0009] Figures 2 to 5 , Fig. 6A and Figure 6B Various views are shown of a semiconductor device at various stages of fabrication in accordance with an embodiment.

[0010] Figure 7 and Figure 8Various embodiment cross-sectional views of a portion of a semiconductor device are shown.

[0011] Fig. 9 and Fig.10 Various top views of a wafer used to form a CoW device in some embodiments are shown.

[0012] Fig.11 A flow chart illustrating a method of forming a semiconductor device in some embodiments.

[0013] [Explanation of Symbols]

[0014] 100, 100A: Semiconductor devices

[0015] 101: Die

[0016] 102: Carrier

[0017] 103: Conductive pillar / die connector

[0018] 105, 131, 139: Solder area

[0019] 107, 168: Bottom filling material

[0020] 109, 118: Molding materials

[0021] 110: Semiconductor devices / CoW devices

[0022] 110A, 110B: CoW devices

[0023] 111. S: Substrate

[0024] 112: Intermediary layer

[0025] 113, 117, 132: Conductive pads

[0026] 114: Gap

[0027] 115: Perforation

[0028] 119: Passivation layer

[0029] 121, 121A, 135: Conductive wire

[0030] 122: Rewiring Structure

[0031] 123, 137, 153: Through hole

[0032] 125, 133, 145: Dielectric layer

[0033] 127: Under Bump Metal (UBM) Structure

[0034] 128: Integrated Passive Devices

[0035] 141A: Top dielectric layer

[0036] 141B: Bottom dielectric layer

[0037] 143: Core

[0038] 147: Copper wire

[0039] 149: Copper through hole

[0040] 150: Composite CoW device

[0041] 151: Copper pad / conductive pad

[0042] 152: Dielectric Materials

[0043] 161: External connector

[0044] 163: Ring

[0045] 165: Adhesive material

[0046] 170: Partial

[0047] 1010, 1020, 1030, 1040: Steps

[0048] AA: Cross section

[0049] C1, C2: Critical dimensions

[0050] D1: Distance

[0051] H1, H2: Height

[0052] H3: Thickness

[0053] P1, P2: Pitch

[0054] S1: Substrate / lower substrate

[0055] S2: Upper substrate

[0056] X: First size

[0057] Y: Second dimension DETAILED DESCRIPTION

[0058] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed "on" a second feature or "on" a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, thereby making the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. Unless otherwise stated, throughout the specification, the same reference numbers in different figures refer to the same or similar components formed by the same or similar methods and using the same or similar materials.

[0059] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0060] Figure 1 1 shows a cross-sectional view of a semiconductor device 110 (also referred to as a CoW device) having a chip-on-wafer (CoW) structure according to some embodiments. Figure 1 Only the left side portion of the semiconductor device 110 is shown, and as those skilled in the art will readily appreciate, the right side portion of the semiconductor device 110 may be Figure 1 The left side parts shown in are the same (eg, symmetrical) or similar.

[0061] To form semiconductor device 110, one or more dies 101 (also referred to as semiconductor dies, chips, or integrated circuit (IC) dies) are attached to interposer 112. In some embodiments, dies 101 are dies of the same type (e.g., memory dies or logic dies). In other embodiments, dies 101 are of different types, for example, some dies 101 are logic dies and other dies 101 are memory dies. Figure 1 Two dies 101 are shown in FIG. 1 , however, as will be readily appreciated by one skilled in the art, the number of dies 101 attached to the interposer 112 may be any suitable number.

[0062] Each of the dies 101 includes a substrate, electrical components (e.g., transistors, resistors, capacitors, diodes, etc.) formed in / on the substrate, and an interconnect structure over the substrate that connects the electrical components to form functional circuitry of the die 101. The die 101 also includes conductive pillars 103 (also referred to as die connectors) that provide electrical connections to the circuitry of the die 101.

[0063] The substrate of the die 101 may be a doped or undoped semiconductor substrate, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer formed of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. Other substrates that may be used include a multi-layered substrate, a gradient substrate, or a hybrid orientation substrate.

[0064] The electrical components of the die 101 include a variety of active devices (e.g., transistors) and passive devices (e.g., capacitors, resistors, inductors), etc. The electrical components of the die 101 can be formed in or on the substrate of the die 101 using any suitable method. The internal wiring structure of the die 101 includes one or more metallization layers (e.g., copper layers) formed in one or more dielectric layers, and is used to connect various electrical components to form a functional circuit system. In an embodiment, the internal wiring structure is formed by alternating dielectric layers and conductive material (e.g., copper) layers, and can be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.).

[0065] One or more passivation layers (not shown) may be formed over the interconnect structures of die 101 to provide a degree of protection for the underlying structures of die 101. The passivation layers may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics (e.g., carbon-doped oxides), ultra-low-k dielectrics (e.g., porous carbon-doped silicon dioxide), combinations thereof, or the like. The passivation layers may be formed by processes such as chemical vapor deposition (CVD), although any suitable process may be used.

[0066] Conductive pads (not shown) may be formed over the passivation layer and may extend through the passivation layer to make electrical contact with interconnect structures of die 101. The conductive pads may comprise aluminum, although other materials such as copper may alternatively be used.

[0067] Conductive pillars 103 of die 101 are formed on conductive pads to provide conductive areas for electrical connection to circuitry of die 101. Conductive pillars 103 may be copper pillars, contact bumps such as microbumps, or the like, and may include materials such as copper, tin, silver, or other suitable materials.

[0068] Looking at the interposer 112 , the interposer 112 includes a substrate 111 , a through-substrate via 115 (also referred to as a through-substrate via (TSV)), and conductive pads 113 / 117 located on the upper and lower surfaces of the substrate 111 . Figure 1 Also shown is a passivation layer 119 (eg, a polymer layer) of the interposer 112 disposed on the lower surface of the substrate 111, the passivation layer 119 surrounding and contacting (eg, physically contacting) the conductive pad 117. In other embodiments, the passivation layer 119 is omitted.

[0069] The substrate 111 may be, for example, a doped or undoped silicon substrate, or an active layer of a silicon-on-insulator (SOI) substrate. However, as another alternative, the substrate 111 may be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that can provide suitable protection and / or internal connection functions.

[0070] In some embodiments, the substrate 111 may include electrical components such as resistors, capacitors, signal distribution circuitry, combinations of these, or the like. These electrical components may be active, passive, or a combination thereof. In other embodiments, there are no active or passive electrical components in the substrate 111. All such combinations are fully intended to be included within the scope of the present disclosure.

[0071] The through-hole 115 extends from the upper surface of the substrate 111 to the lower surface of the substrate 111 and provides an electrical connection between the conductive pad 113 and the conductive pad 117. The through-hole 115 may be formed of a suitable conductive material such as copper, tungsten, aluminum, alloys, doped polysilicon, combinations thereof, and the like. A barrier layer may be formed between the through-hole 115 and the substrate 111. The barrier layer may include a suitable material such as titanium nitride, although other materials such as tantalum nitride, titanium, or the like may alternatively be used.

[0072] In some embodiments, a pitch P1 between adjacent conductive pads 117 is between about 20 μm (micrometers) and about 200 μm, a critical dimension (CD) (e.g., width) C1 of the conductive pad 117 is between about 10 μm and about 100 μm, and a height H1 of the conductive pad 117 is between about 3 μm and about 30 μm.

[0073] like Figure 1As shown in FIG. 1 , the conductive pillar 103 of the die 101 is bonded to the conductive pad 113 of the interposer 112 through, for example, the solder region 105. A reflow process may be performed to bond the die 101 to the interposer 112.

[0074] After the die 101 is bonded to the interposer 112, an underfill material 107 is formed between the die 101 and the interposer 112. The underfill material 107 may include, for example, a liquid epoxy that is dispensed in the gap between the die 101 and the interposer 112 using, for example, a dispensing needle or other suitable dispensing tool, and then cured to harden. Figure 1 As shown in FIG. 1 , the underfill material 107 fills the gap between the die 101 and the substrate 111 of the interposer 112, and may also fill the gap between the sidewalls of the die 101. In other embodiments, the underfill material 107 is omitted, in which case a subsequently formed molding material (e.g., 109) may fill the gap between the die 101 and the substrate 111 and between the dies 101.

[0075] Next, a molding material 109 is formed over the interposer 112 and around the die 101. In embodiments where the bottom fill material 107 is formed, the molding material 109 also surrounds the bottom fill material 107. As an example, the molding material 109 may include an epoxy resin, an organic polymer, a polymer with or without a silicon-based filler or a glass filler, or other materials. In some embodiments, the molding material 109 includes a liquid molding compound (LMC) that is a gel-type liquid when applied. When applied, the molding material 109 may also include a liquid or a solid. Alternatively, the molding material 109 may include other insulating and / or encapsulating materials. In some embodiments, the molding material 109 is applied using a wafer-level molding process. The molding material 109 may be molded using, for example, compression molding, transfer molding, molded underfill (MUF), or other methods.

[0076] Next, in some embodiments, a curing process is used to cure the molding material 109. The curing process may include heating the molding material 109 to a predetermined temperature for a predetermined time period using an annealing process or other heating process. The curing process may also include an ultraviolet (UV) exposure process, an infrared (IR) energy exposure process, a combination thereof, or a combination thereof plus a heating process. Alternatively, the molding material 109 may be cured using other methods. In some embodiments, a curing process is not included.

[0077] After the molding material 109 is formed, a planarization process, such as chemical and mechanical planarization (CMP), may be performed to remove excess portions of the molding material 109 from above the die 101 so that the molding material 109 and the die 101 have coplanar upper surfaces. Figure 1 As shown in , the molding material 109 interfaces with the substrate 111 such that the sidewalls of the molding material 109 are aligned with the corresponding sidewalls of the substrate 111 .

[0078] exist Figure 1 In the example shown, the CoW device 110 includes an interposer 112, a die 101, an underfill material 107, and a molding material 109. In some embodiments, the underfill material 107 is not formed, but is replaced by a molding material 109. Although not shown, a person skilled in the art will readily understand that a plurality of CoW devices 110 may be formed on the same wafer in the same process step, and a dicing process may then be performed to separate the plurality of CoW devices 110 into separate (e.g., individual) CoW devices 110.

[0079] The CoW device 110 may be bonded to a substrate (e.g., a printed circuit board (PCB)) to form a semiconductor device having a chip-on-wafer-on-substrate (CoWoS) structure. To form high-performance semiconductor devices (e.g., devices designed for artificial intelligence (AI) or network server applications), more and more dies 101 are integrated into the CoW device 110 to provide enhanced functionality and / or more storage capacity (e.g., memory capacity). As the number of dies in a CoW device increases, the size of the interposer may have to increase to accommodate the dies. For example, a high-performance semiconductor device having a CoW structure may have a size (e.g., a surface area in a top view) greater than 3 reticles, where the reticles correspond to an area of ​​approximately 26 mm (millimeters) × 32 mm. When a high-performance device having a CoW structure is bonded to a substrate (e.g., a PCB), the size of the substrate may be greater than 70 mm × 70 mm, for example, 100 mm × 100 mm.

[0080] However, as the size of the interposer (e.g., 112) and the size of the substrate (e.g., PCB) increase, new challenges arise. For example, due to the difference in coefficient of thermal expansion (CTE) of different materials in the CoW device 110, the interposer 112 may warp, and the warping of the interposer may become worse as the size of the interposer increases. The warping of the interposer may cause stress in the conductive connections between the die 101 and the interposer 112, wherein the conductive connections include the solder region 105, the die connector 103, and the conductive pad 113. The stress is particularly high near the corner regions (e.g., the corner regions in the top view) of the interposer 112, and when the size of the CoW device is large (e.g., greater than 2 masks), the high stress increases the risk of bump fatigue.

[0081] Another challenge brought about by the increase in the size of CoW devices is the low bump joint yield, which may occur when a larger CoW device is bonded to a large substrate (e.g., a PCB) to form a CoWoS semiconductor device. This is because it is increasingly difficult to keep a large substrate (e.g., a PCB) flat (e.g., having a flat upper surface and / or a flat lower surface). The warping of the large substrate makes it difficult to align the conductive pads 117 of the CoW device 110 with the corresponding conductive features (e.g., conductive pads) on the surface of the large substrate for bonding. In addition, due to the warping of the large substrate, the conductive features (e.g., conductive pads) on the surface of the large substrate are not arranged in the same plane, making it difficult to bond the CoW device 110 to the large substrate. Therefore, problems such as cold joints or high stress in the conductive connectors between the CoW device 110 and the large substrate may occur. The various reliability issues discussed above can be collectively referred to as chip package integration (CPI) issues or CPI risks. The present disclosure discloses various embodiments of a composite CoW structure to mitigate or avoid CIP risk. The details of the composite CoW structure are discussed below.

[0082] Figures 2 to 5 , Fig. 6A and Figure 6B Various diagrams of a semiconductor device 100 at various stages of manufacture are shown in accordance with an embodiment. Figure 2 , attaching two CoW devices 110 to the upper surface of the carrier 102, and the two CoW devices 110 can be Figure 1 The CoW devices 110 shown are the same or similar. Note that although Figure 1Two CoW devices 110 are shown in FIG. 1 , however more than two CoW devices 110 may be used to form the semiconductor device 100 , and these and other variations are fully intended to be included within the scope of the present disclosure.

[0083] The carrier 102 may be made of materials such as silicon, polymer, polymer composite, metal foil, ceramic, glass, glass epoxy, beryllium oxide, tape, or other suitable materials for structural support. In some embodiments, before attaching the CoW device 110 to the carrier 102, a release film, such as a light-to-heat-conversion (LTHC) coating, is formed on the carrier 102. The release film may be photosensitive and can be easily detached from the carrier 120 by irradiating, for example, ultraviolet (UV) light on the carrier 102 in a subsequent carrier de-bonding process.

[0084] The CoW device 110 is attached to the carrier 102 (or to a release film if one is formed) using, for example, a die attaching film (DAF). Figure 2 In the embodiment, the back side of the die 101 is attached to the carrier 102, and the conductive pads 117 of the interposer 112 of the CoW devices 110 face upwardly away from the carrier 102. The CoW devices 110 are laterally spaced apart from each other with gaps 114 therebetween.

[0085] Next, in Figure 3 , a molding material 118 is formed on the carrier 102 and around the CoW device 110. The molding material 118 also fills the gaps 114 between the CoW devices 110. The material and the forming method of the molding material 118 may be the same or similar to the material and the forming method of the molding material 109 of the CoW device 110, and thus will not be described in detail. In some embodiments, the molding material 118 and the molding material 109 are different materials (e.g., have different compositions), and the molding material 118 surrounds and physically contacts the molding material 109. In other embodiments, the molding material 118 and the molding material 109 are the same material (e.g., have the same composition), and thus there may or may not be an interface between the molding material 118 and the molding material 109.

[0086] After forming the molding material 118, a planarization process (e.g., CMP) may be performed to remove excess portions of the molding material 118 disposed over the CoW device 110. After the planarization process, the molding material 118, the conductive pad 117, and the passivation layer 119 of the CoW device 110 have coplanar (e.g., flush) upper surfaces. Figure 3In the embodiment, the molding material 118 physically contacts the sidewalls of the substrate 111 and the sidewalls of the passivation layer 119 .

[0087] Next, in Figure 4 In the embodiment of the present invention, a rewiring structure 122 is formed over the molding material 118 and the CoW device 110. The rewiring structure 122 includes one or more dielectric layers 125 and conductive features (e.g., conductive lines 121 and vias 123) formed in the one or more dielectric layers 125. The rewiring structure 122 is electrically coupled to the conductive pad 117 and to the die 101 through the interposer of the CoW device 110. An under bump metallurgy (UBM) structure 127 is formed over the rewiring structure 122 and electrically coupled to the rewiring structure 122. Figure 4 Further shown are conductive lines 121A (e.g., copper lines) extending over the gaps between the CoW devices 110. The conductive lines 121A electrically couple at least one of the dies 101 in the CoW device 110A (CoW device 110 on the left) with at least one of the dies 101 in the CoW device 110B (CoW device 110 on the right). Figure 4 The device shown in FIG. 1 including multiple CoW devices 110 that are physically separated and electrically coupled together by a single rewiring structure 122 (without the carrier 102 ) is also referred to as a composite CoW device 150 or as a semiconductor device having a composite CoW structure.

[0088] In some embodiments, the one or more dielectric layers 125 are formed of a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 125 is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like. The one or more dielectric layers 125 may be formed by any acceptable deposition process such as spin coating, chemical vapor deposition (CVD), laminating, the like, or a combination thereof.

[0089] In some embodiments, the conductive features of the redistribution structure 122 include conductive lines 121 / 121A and vias 123 formed of suitable conductive materials such as copper, titanium, tungsten, aluminum, or the like. The conductive features may be formed, for example, by forming openings in the dielectric layer 125 to expose underlying conductive features; forming a seed layer on the dielectric layer 125 and in the openings; forming a patterned photoresist having a designed pattern on the seed layer; plating (e.g., electroplating or electroless plating) a conductive material in the designed pattern and on the seed layer; and removing the photoresist and portions of the seed layer on which the conductive material is not formed.

[0090] In some embodiments, the redistribution structure has 1 to 10 metal layers, wherein each metal layer includes a conductive line 121 and a via 123 formed on / through the same dielectric layer 125. In some embodiments, the thickness of each dielectric layer 125 measured along a first direction perpendicular to the main surface of the interposer of the CoW device 110 is between about 2 μm and about 10 μm. The thickness of the conductive features (e.g., 121) of the redistribution structure 122 measured along the first direction is between about 0.5 μm and about 5 μm.

[0091] The disclosed composite CoW device 150 provides excellent signal integrity. For example, since the redistribution structure 122 is formed using a silicon fab processing technique, the conductors (e.g., 121, 123) in the redistribution structure 122 have a low roughness (e.g., having a profile roughness parameter Ra≤0.1 μm), which helps reduce insertion loss and skin effect. The dielectric layer 125 (e.g., polyimide) of the redistribution structure 122 is made thin (e.g., having a thickness between 2 μm and about 10 μm), which helps reduce the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the dielectric layer 125, thereby reducing the dissipation factor Df (e.g., Df≤0.01) of the dielectric layer 125. The lower ESL and ESR of the dielectric layer 125 improve the power integrity of the composite CoW device 150. Optionally, one or more integrated passive devices (IPDs) (composed of Figure 4The composite CoW device 150 (shown by the dashed box 128 in FIG. 1 ) can be integrated with the composite CoW device 150 (e.g., bonded to the UBM structure 127), which reduces the number of power plan layers in the composite CoW device 150 and further improves power integrity. Due to the excellent signal integrity, the composite CoW device 150 is very suitable for high-speed devices such as serializer / deserializer (SerDes) devices.

[0092] After the redistribution structure 122 is formed, a UBM structure 127 is formed over the redistribution structure 122 that is electrically coupled to the conductive features of the redistribution structure 122. In an embodiment, the UBM structure 127 includes three layers of conductive materials, such as a titanium layer, a copper layer, and a nickel layer. However, there are many suitable arrangements of materials and layers for forming the UBM structure 127, such as a chromium / chromium-copper alloy / copper / gold arrangement, a titanium / titanium tungsten / copper arrangement, or a copper / nickel / gold arrangement. Any suitable material or material layer that can be used for the UBM structure 127 is fully intended to be included within the scope of the present disclosure.

[0093] The UBM structure 127 may be formed by forming an opening in the topmost dielectric layer 125 to expose the conductive features in the redistribution structure 122; forming a seed layer over the topmost dielectric layer 125 and along the interior of the opening in the topmost dielectric layer; forming a patterned mask layer (e.g., photoresist) over the seed layer; forming (e.g., by plating) a conductive material in the opening of the patterned mask layer and over the seed layer; and removing the mask layer and removing portions of the seed layer on which the conductive material is not formed. Other methods for forming the UBM structure 127 may exist and are fully intended to be included within the scope of the present disclosure.

[0094] In some embodiments, a critical dimension (CD) (eg, width) C2 of the UBM structure 127 is between about 10 μm and about 100 μm, a pitch P2 between adjacent UBM structures 127 is between about 20 μm and about 200 μm, and a height H2 of the UBM structure 127 is between about 3 μm and about 30 μm.

[0095] like Figure 4 As shown in FIG. 1 , the rewiring structure 122 extends continuously from the CoW device 110A to the CoW device 110B. Specifically, the rewiring structure 122 extends along and physically contacts the upper surfaces of the passivation layer 119 and the molding material 118 of the CoW devices 110A / 110B.

[0096] although Figure 4One composite CoW device 150 is shown formed over the carrier 102 , however as readily understood by those skilled in the art, more than one composite CoW device 150 may be formed over the carrier 102 in the same process step, and a subsequent sawing process may be performed to separate the composite CoW device 150 into individual composite CoW devices.

[0097] Temporary reference Fig. 9 and 10 , which shows various top views of a carrier 102 (eg, a wafer) used in forming a composite CoW device 150. Fig. 9 In the example shown, a plurality of composite CoW devices 150 are formed on a carrier 102, which has a circular shape in a top view. Fig. 9 In FIG. 1 , the dashed area corresponds to one composite CoW device 150 , and four composite CoW devices 150 are shown as a non-limiting example. The number of composite CoW devices 150 formed on the carrier 102 may be any suitable number. Fig.10 In the embodiment, the carrier 102 has a rectangular shape or a square shape. Fig.10 , nine composite CoW devices 150 are shown to be formed over the carrier 102 , and the number of composite CoW devices 150 formed on the carrier 102 may be any suitable number.

[0098] Next, in Figure 5 In the embodiment, a carrier stripping process is performed to separate the carrier 102 from the composite CoW device 150. The stripping process may use any suitable process such as etching, grinding, and mechanical stripping to remove the carrier 102. In some embodiments in which an LTHC release film is formed between the carrier 102 and the composite CoW device 150, the carrier 102 is stripped by irradiating a laser or UV light on the surface of the carrier 102. Although not shown, a cutting process may be performed after the carrier stripping process to separate the plurality of composite CoW devices 150 (see FIG. 1 ) formed on the carrier 102. Fig. 9 and Fig.10 ) are singulated into individual composite CoW devices 150. In some embodiments, due to the sawing process, the redistribution structure 122 and the molding material 118 of the composite CoW device 150 have the same width, so that the sidewalls of the redistribution structure 122 are aligned with the corresponding sidewalls of the molding material 118.

[0099] Still refer to Figure 5 After the carrier stripping process and the cutting process, the composite CoW device 150 is flipped over, and the UBM structure 127 of the composite CoW device 150 is aligned with the corresponding conductive pad 132 at the upper surface of the substrate S to prepare for bonding with the substrate S. Figure 5In the example shown, a solder region 131 is formed over the conductive pad 132. The solder region 131 may be a solder paste deposited over the conductive pad 132, or may be a conductive bump including solder formed over the conductive pad 132. The solder region 131 bonds the composite CoW device 150 to the substrate S in a subsequent reflow process.

[0100] Figure 5 The illustrated substrate S includes an upper substrate S2 and a lower substrate S1. The upper substrate S2 is bonded to the lower substrate S1 via a solder region 139. In the illustrated embodiment, the upper substrate S2 and the lower substrate S1 are preformed (e.g., formed separately before being bonded together) and bonded together via the solder region 139, for example, using a reflow process.

[0101] In some embodiments, the lower substrate S1, which may be a printed circuit board (PCB), includes a core 143 formed of a dielectric material such as a prepreg, epoxy resin, silica filler, Ajinomoto build-up film (ABF), polyimide, molding compound, or the like. In some embodiments, the core 143 includes bismaleimide triazine (BT) resin, Frankel's functional regulator-4 (FR-4) (a composite material composed of woven glass fiber cloth and a flame retardant epoxy resin adhesive), ceramic, glass, plastic, tape, film, or other supporting material. A through hole 153 extending through the core 143 is formed. In some embodiments, the through hole 153 is formed by drilling a through hole in the core 143 and forming (e.g., plating) a conductive material (e.g., copper) along the sidewalls of the through hole. After the conductive material is formed along the sidewalls of the through hole, such as Figure 5 As shown in the illustrated example, the remainder of the through-hole may be filled with a dielectric material 152 .

[0102] Still refer to Figure 5 Conductive features such as copper wires 147, copper vias 149, and / or copper pads 151 are formed on opposite sides of the core 143 and act as redistribution layers to reroute electrical signals from a first location on the substrate S1 to a second location on the substrate S1. The conductive features are formed in a plurality of dielectric layers 145, which may be formed of a suitable dielectric material such as ABF or prepreg. Figure 5The topmost dielectric layer 141A and the bottommost dielectric layer 141B of the lower substrate S1 are further shown. The topmost dielectric layer 141A and the bottommost dielectric layer 141B may be formed of, for example, solder resist, ABF or polyimide. The conductive pad 151 of the lower substrate S1 is exposed through the opening in the topmost dielectric layer 141A and the opening in the bottommost dielectric layer 141B.

[0103] The upper substrate S2 includes a plurality of dielectric layers 133 and conductive features (e.g., conductive lines 135, vias 137, and conductive pads 132) formed in the plurality of dielectric layers 133. The dielectric layers 133 are formed of suitable dielectric materials, such as prepreg, resin coated copper (RCC), molding compound, polyimide, photo image dielectric (PID), etc.

[0104] In some embodiments, the dielectric layer 133 and the conductive features of the upper substrate S2 are formed on a carrier (not shown) using the same or similar process steps (e.g., silicon fab process technology) as the redistribution structure 122. For example, the upper substrate S2 can be formed by: forming a first dielectric layer (e.g., 133) on the carrier; forming a first conductive feature (e.g., 132) on the first dielectric layer (e.g., by plating); forming a second dielectric layer on the first conductive feature; forming an opening in the second dielectric layer to expose the first conductive feature; forming a seed layer on the second dielectric layer and in the opening; forming a patterned photoresist having a designed pattern on the seed layer; plating (e.g., electroplating or electroless plating) a conductive material (e.g., copper) in the designed pattern and on the seed layer, and removing the photoresist and the portion of the seed layer on which the conductive material is not formed. The above process can be repeated to form additional layers of dielectric layers and additional layers of conductive features. After the upper substrate S2 is formed, the carrier is removed. A solder region 139, which may be a solder paste or a conductive bump containing solder, is formed on the conductive pad 132 of the upper substrate S2. Next, the conductive pad 132 at the lower surface of the upper substrate S2 is aligned with the corresponding conductive pad 151 at the upper surface of the lower substrate S1, and a reflow process is performed so that the solder region 139 bonds the upper substrate S2 to the lower substrate S1. Figure 5 As shown in FIG. 1 , the solder region 139 at least partially extends through (eg, extends to) the topmost dielectric layer 141A of the lower substrate S1 to be bonded with the conductive pad 151 .

[0105] In some embodiments, the conductive pads 132 at the upper surface of the upper substrate S2 facing the composite CoW device 150 may be formed to have a micron-scale size (e.g., width, pitch) that matches the size (e.g., width, pitch) of the UBM structure 127 of the composite CoW device 150, so as to be properly aligned and electrically coupled with the composite CoW device 150. Remember that the upper substrate S2 is formed using silicon fab process technology, which enables the formation of micron-scale feature sizes. The conductive pads 132 at the lower surface of the upper substrate S2 facing the lower substrate S1 may have a larger size (e.g., width and pitch) to match the size of the conductive pads 151 at the upper surface of the lower substrate S1 (e.g., PCB) to be properly aligned and electrically coupled with the lower substrate S1. Note that the conductive pads 151 may be formed using PCB manufacturing technology, and therefore, it may not be possible to form the conductive pads 151 with a size that matches the size of the UBM structure 127 of the composite CoW device 150. Thus, the disclosed structure of substrate S (with upper substrate S2 acting as an interface between conductive pads of different sizes) enables proper alignment and coupling between the UBM structure 127 of the composite CoW device 150 and the conductive pads 151 of the lower substrate S1 (eg, PCB).

[0106] Next, in Fig. 6A In the embodiment, a reflow process is performed to bond the UBM structure 127 of the composite CoW device 150 to the conductive pad 132 of the upper substrate S2 through the solder region 131. Next, an underfill material 168 is formed between the redistribution structure 122 of the composite CoW device 150 and the upper substrate S2. In some embodiments, the underfill material 168 is omitted. Fig. 6A The semiconductor device 100 in FIG. 1 is a semiconductor package including a composite CoW device 150 bonded to a substrate S, and thus has a chip-on-wafer-on-substrate (CoWoS) structure. Fig. 6A The CoWoS structure shown is different from the traditional CoWoS structure. Fig. 6A The semiconductor device 100 may be referred to as a composite CoWoS device, or may be referred to as a semiconductor device having a composite CoWoS structure.

[0107] Next, the ring 163 is attached to the upper surface of the upper substrate S2 by the adhesive material 165. The ring 163 can be used to improve the flatness (e.g., planarity) of the substrate S. In some embodiments, the ring 163 is formed of a rigid material such as steel, copper, glass, or the like. In an embodiment, the ring 163 is formed of a block material (e.g., block steel, block copper, block glass) to provide structural support, and there are no electrical components or circuits inside the ring 163. In the illustrated embodiment, the ring 163 is a rectangular ring (e.g., having a hollow rectangular shape in a top view, see Figure 6B), and attached to the substrate S, such that the ring 163 surrounds the composite CoW device 150 (eg, surrounds the die 101 and the interposer 112). Fig. 6A In the example shown, the upper surface of the ring 163 is higher than the interposer 112 of the CoW device 110 (see Figure 1 The upper surface of the substrate (marked in ) extends further from the substrate S.

[0108] Fig. 6A Further shown is an external connector 161 formed on the conductive pad 151 at the lower surface of the lower substrate S1. The external connector 161 may be a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel-electrolesspalladium-immersion gold (ENEPIG) technology, a combination thereof (e.g., a metal column attached with a solder ball), or the like. The external connector 161 may be formed using any suitable formation method.

[0109] Figure 6B Show Fig. 6A A top view of the semiconductor device 100 is shown, and Fig. 6A is along Figure 6B The cross-sectional view of the cross section AA is shown. Figure 6B As shown in the non-limiting example, each of the CoW devices 110 in the composite CoW device 150 has five dies 101. The middle die 101 (larger die) may be, for example, a processor (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)), and the corner die 101 (smaller die) may be, for example, a high bandwidth memory (HBM) die. Note that in Figure 6B In the top view shown, the boundary (eg, perimeter) of CoW device 110 overlaps the boundary of molding material 109 , the boundary of composite CoW device 150 overlaps the boundary of molding material 118 , and the boundary of substrate S overlaps the boundary of topmost dielectric layer 133 of upper substrate S2 .

[0110] In some embodiments, Figure 6BThe first dimension X and the second dimension Y of the semiconductor device 100 in FIG. 1 are between about 10 mm and about 75 mm. The distance D1 between the CoW devices 110 is between about 25 μm and about 500 μm. The thickness H3 of the composite CoW device 150 measured between the back side of the die 101 and the lower surface of the redistribution structure 122 facing the substrate S (see FIG. 1 ) is about 10 mm and about 75 mm. Figure 7 ) is between about 100 μm and about 1500 μm. Although the size of the semiconductor device 100 is quite large (eg, may be 75 mm×75 mm), the CPI risk is avoided or reduced due to the unique architecture of the composite CoWoS device.

[0111] Figure 6B Further, the conductive line 121A of the rewiring structure 122 disposed between the CoW devices 110 is shown in phantom. Figure 6B It is not visible in the top view shown. Note that the conductive line 121A is formed during the formation of the redistribution structure 122 using a silicon fab manufacturing process. Therefore, it is possible to form very thin conductive lines 121A (e.g., with a line thickness of 2 μm), which enables multiple conductive lines 121A to be formed in a small gap area between CoW devices 110, and the size (e.g., width, pitch) of the conductive lines 121A matches the size of the conductive pads 117 of the CoW devices 110 to achieve proper alignment and electrical connection.

[0112] Figure 7 Show Fig. 6A An enlarged view of a portion 170 of semiconductor device 100 is shown in FIG. Figure 7 In the example shown, each of the CoW devices 110 in the composite CoW device 150 has a passivation layer 119 (e.g., a polymer layer) on the lower surface of the substrate 111. The passivation layer 119 surrounds and physically contacts the conductive pads 117 of the interposer located on the lower surface of the substrate 111. Therefore, the passivation layer 119, the conductive pads 117, and the molding material 118 of the composite CoW device 150 have coplanar (e.g., flush) lower surfaces that physically contact the redistribution structure 122. The redistribution structure 122 has the same width as the molding material 118, so that the sidewalls of the redistribution structure 122 are aligned with the corresponding sidewalls of the molding material 118.

[0113] Figure 8 FIG. 1 is an enlarged view of a portion of a semiconductor device 100A in the embodiment. Figure 7 The semiconductor device 100 is similar to that shown, but in Figure 8In the illustrated embodiment, the passivation layer 119 on the lower surface of the substrate 111 is omitted. Therefore, the molding material 118 surrounds and physically contacts the conductive pads 117 on the lower surface of the substrate 111. Therefore, the molding material 118 and the conductive pads 117 have coplanar (e.g., flush) surfaces that physically contact the redistribution structure 122. The redistribution structure 122 has the same width as the molding material 118, so that the sidewalls of the redistribution structure 122 are aligned with the corresponding sidewalls of the molding material 118.

[0114] Variations of the disclosed embodiments may exist and are fully intended to be included within the scope of the present disclosure. For example, the number of dies 101 within each CoW device 110 and the location of each die 101 within the CoW device 110 may be modified without departing from the spirit of the present disclosure. Additionally, the number of CoW devices 110 and the location of CoW devices 110 within the composite CoW device 150 may be modified without departing from the spirit of the present disclosure. Additionally, although Fig. 6A The substrate S in the embodiment includes an upper substrate S2 bonded to a lower substrate S1, however the substrate S may have other configurations, such as a simpler configuration. For example, the substrate S may have only the upper substrate S2. In addition, other devices such as integrated passive devices (IPDs) may be bonded to the redistribution structure 122 and encapsulated by the bottom fill material 168. These and other variations are fully intended to be included within the scope of the present disclosure.

[0115] Embodiments can achieve advantages such as reduced chip package integration (CPI) risk. The disclosed composite CoW device includes two or more CoW devices integrated together by a rewiring structure. This enables the size (e.g., surface area in a top view) of the composite CoW device 150 to be quite large (e.g., ≥ 3 masks) and still avoid or reduce the risk of bump fatigue due to high stress at, for example, the conductive connections between the die 101 and the interposer 112, especially at the corners of the interposer. The smaller interposer inside each of the CoW devices 110 reduces the cost of the interposer, and the smaller interposer also reduces the warping of the interposer at the edges, and thus reduces the stress of the conductive connections at the corners of the interposer.

[0116] In addition, the disclosed embodiments enable large substrates with an area greater than 100 mm x 100 mm (e.g., Fig. 6AThe composite CoW device 150 can be combined with the substrate S in the rewiring structure 122 to form a large semiconductor package while avoiding or reducing various CPI issues such as cold joints and bump fatigue risks, thereby increasing bump bonding yield and on-substrate assembly yield. In some embodiments, the average CTE of the material used in the rewiring structure 122 is adjusted to have a target value (e.g., between 20 ppm / °C and 60 ppm / °C) to modify the warpage profile of the composite CoW device 150 so that the composite CoW device 150 has less warpage, or the composite CoW device 150 has the same or similar warpage profile as the substrate S (e.g., both are bent upward or downward) to facilitate the bonding between the composite CoW device 150 and the substrate S. Otherwise, if the composite CoW device 150 and the substrate S have opposite profiles (e.g., one is bent upward and the other is bent downward), it will be difficult to bond the composite CoW device 150 to the substrate S, and problems such as bump fatigue risk or cold joint may occur. Other advantages include, for example, reduced interposer cost; high component yield for composite CoW device 150 due to use of silicon fab processes; and improved signal integrity due to low dissipation factor Df (eg, Df≤0.01) of dielectric layer 125 in, for example, a redistribution structure.

[0117] Fig.11 Flowchart 1000 shows a method of forming a semiconductor device in some embodiments. It should be understood that Fig.11 The embodiments shown in the present invention are merely examples of many possible embodiments. Those skilled in the art will recognize that there are many variations, changes, and modifications. For example, the present invention may be added, removed, substituted, rearranged, and repeated. Fig.11 The various steps shown in .

[0118] Reference Fig.11 At step 1010, a first chip-on-wafer (CoW) device is bonded to a first side of a carrier, the first CoW device comprising a first interposer and a first die bonded to the first interposer. At step 1020, a second CoW device is bonded to a first side of the carrier adjacent to the first CoW device, the second CoW device comprising a second interposer and a second die bonded to the second interposer. At step 1030, a molding material is formed on the first side of the carrier, around the first CoW device, and around the second CoW device, wherein a first conductive pad of the first interposer and a second conductive pad of the second interposer are exposed at an upper surface of the molding material away from the carrier. At step 1040, a rewiring structure is formed over the first CoW device, the second CoW device, and the molding material, wherein the rewiring structure extends continuously from the first CoW device to the second CoW device.

[0119] According to an embodiment, a semiconductor device includes: a first chip-on-wafer (CoW) device including a first interposer and a first die attached to a first side of the first interposer; a second CoW device including a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced apart from the first interposer; and a rewiring structure extending along a second side of the first interposer opposite to the first side of the first interposer and extending along a second side of the second interposer opposite to the first side of the second interposer, the rewiring structure extending continuously from the first CoW device to the second CoW device. In an embodiment, the semiconductor device further includes a first molding material located around the first CoW device, around the second CoW device, and between the first CoW device and the second CoW device, wherein the rewiring structure contacts a first side of the first molding material facing the rewiring structure and extends along the first side of the first molding material. In an embodiment, the rewiring structure has the same width as the first molding material, so that the sidewalls of the rewiring structure are aligned with the corresponding sidewalls of the first molding material. In an embodiment, the first interposer has a first conductive pad at the second side of the first interposer, and a first passivation layer at the second side of the first interposer around the first conductive pad, wherein the second interposer has a second conductive pad at the second side of the second interposer, and a second passivation layer at the second side of the second interposer around the second conductive pad, wherein the first conductive pad, the second conductive pad, the first passivation layer, the second passivation layer, and the first molding material have a coplanar surface facing the rewiring structure. In an embodiment, the first interposer has a first conductive pad at the second side of the first interposer, and the second interposer has a second conductive pad at the second side of the second interposer, wherein the first molding material surrounds and contacts the first conductive pad and the second conductive pad, wherein the first conductive pad, the second conductive pad, and the first molding material have a coplanar surface facing the rewiring structure. In an embodiment, the semiconductor device further includes a substrate having a conductive feature, wherein the rewiring structure is physically coupled to and electrically coupled to a first surface of the substrate. In an embodiment, the rewiring structure is physically coupled to and electrically coupled to the first surface of the substrate through a solder region. In an embodiment, the semiconductor device further comprises a ring attached to the first surface of the substrate, wherein the ring surrounds the first CoW device and the second CoW device. In an embodiment, the semiconductor device further comprises an underfill material between the redistribution structure and the first surface of the substrate.In an embodiment, the substrate comprises a lower substrate and an upper substrate, the upper substrate being disposed between the lower substrate and the redistribution structure, wherein the upper substrate is bonded to the lower substrate via a first solder region, wherein the redistribution structure is physically and electrically coupled to an upper surface of the upper substrate facing away from the lower substrate via a second solder region. In an embodiment, the lower substrate comprises: a dielectric core; a through hole extending through the dielectric core; a dielectric layer located on opposite sides of the dielectric core; a conductive feature located in the dielectric layer; and a first solder resist layer and a second solder resist layer, the first solder resist layer being located on an uppermost dielectric layer of the dielectric layers, the second solder resist layer being located on a lowermost dielectric layer of the dielectric layers, wherein the first solder region extends into the first solder resist layer.

[0120] According to an embodiment, a semiconductor device includes: a substrate including conductive features; and a composite chip-on-wafer (CoW) device attached to a first surface of the substrate. The composite CoW device includes: a first interposer; a first die coupled to a first side of the first interposer facing away from the substrate; a second interposer laterally spaced apart from the first interposer; a second die coupled to a first side of the second interposer facing away from the substrate; a first molding material located around the first die, the second die, the first interposer, and the second interposer; and a redistribution structure extending continuously along a second side of the first interposer facing the substrate, along a second side of the second interposer facing the substrate, and along a first surface of the first molding material facing the substrate. In an embodiment, the redistribution structure includes a conductive line located between the first interposer and the second interposer, the conductive line electrically coupling at least one of the first dies to at least one of the second dies. In an embodiment, the semiconductor device further includes a first solder region located between the first surface of the substrate and the redistribution structure. In an embodiment, the semiconductor device further comprises an underfill material between the redistribution structure and the first surface of the substrate, wherein the underfill material surrounds the first solder area. In an embodiment, the semiconductor device further comprises a ring attached to the first surface of the substrate, an upper surface of the ring away from the substrate extends further from the substrate than the first side of the first interposer.

[0121] According to an embodiment, a method of forming a semiconductor device includes: attaching a first chip-on-wafer (CoW) device on a first side of a carrier, the first CoW device including a first interposer and a first die attached to the first interposer; attaching a second CoW device on the first side of the carrier, adjacent to the first CoW device, the second CoW device including a second interposer and a second die attached to the second interposer; forming a molding material on the first side of the carrier, around the first CoW device and around the second CoW device, wherein a first conductive pad of the first interposer and a second conductive pad of the second interposer are exposed at an upper surface of the molding material away from the carrier; and forming a rewiring structure over the first CoW device, the second CoW device and the molding material, wherein the rewiring structure extends continuously from the first CoW device to the second CoW device. In an embodiment, the rewiring structure electrically couples at least one of the first dies to at least one of the second dies. In an embodiment, the method further includes: removing the carrier; and after removing the carrier, bonding the rewiring structure to a first surface of a substrate using solder. In an embodiment, the method further includes attaching a ring to the first surface of the substrate, wherein the ring surrounds the first CoW device and the second CoW device.

[0122] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that include: A first chip-on-wafer device includes a first interposer and a first die attached to a first side of the first interposer; a second chip-on-wafer device including a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced apart from the first interposer; as well as a redistribution structure extending along a second side of the first interposer opposite to the first side of the first interposer and extending along a second side of the second interposer opposite to the first side of the second interposer, the redistribution structure extending continuously from the first chip-on-wafer device to the second chip-on-wafer device, The rewiring structure comprises a first plurality of dielectric layers and a first plurality of conductive features, wherein the first plurality of conductive features are arranged between a first surface of the first plurality of dielectric layers closest to the first interposer and a second surface of the first plurality of dielectric layers farthest from the first interposer, wherein the first plurality of dielectric layers are stacked together with no gaps therebetween, and wherein one of the first plurality of conductive features of the rewiring structure extends continuously from the chip device on the first wafer to the chip device on the second wafer.

2. The semiconductor device according to claim 1 further includes a first molding material located around the first chip-on-wafer device, around the second chip-on-wafer device, and between the first chip-on-wafer device and the second chip-on-wafer device, wherein the rewiring structure contacts a first side of the first molding material facing the rewiring structure and extends along the first side of the first molding material. 3 . The semiconductor device according to claim 2 , wherein the redistribution structure and the first molding material have the same width, such that sidewalls of the redistribution structure are aligned with corresponding sidewalls of the first molding material.

4. The semiconductor device according to claim 2, wherein the first interposer has a first conductive pad at the second side of the first interposer, and a first passivation layer at the second side of the first interposer and around the first conductive pad, wherein the second interposer has a second conductive pad at the second side of the second interposer, and a second passivation layer at the second side of the second interposer and around the second conductive pad, wherein the first conductive pad, the second conductive pad, the first passivation layer, the second passivation layer and the first molding material have a coplanar surface facing the rewiring structure.

5. The semiconductor device of claim 2 , wherein the first interposer has a first conductive pad at the second side of the first interposer, and the second interposer has a second conductive pad at the second side of the second interposer, wherein the first molding material surrounds and contacts the first conductive pad and the second conductive pad, wherein the first conductive pad, the second conductive pad, and the first molding material have a coplanar surface facing the redistribution structure. 6 . The semiconductor device of claim 1 , further comprising a substrate having a conductive feature, wherein the redistribution structure is physically and electrically coupled to the first surface of the substrate. 7 . The semiconductor device according to claim 6 , wherein the redistribution structure is physically and electrically coupled to the first surface of the substrate through a solder region. 8 . The semiconductor device of claim 6 , further comprising a ring attached to the first surface of the substrate, wherein the ring surrounds the first chip-on-wafer device and the second chip-on-wafer device. 9 . The semiconductor device of claim 6 , further comprising an underfill material between the redistribution structure and the first surface of the substrate.

10. A semiconductor device according to claim 6, wherein the substrate comprises a lower substrate and an upper substrate, the upper substrate is arranged between the lower substrate and the redistribution structure, wherein the upper substrate is bonded to the lower substrate through a first solder region, and wherein the redistribution structure is physically and electrically coupled to an upper surface of the upper substrate facing away from the lower substrate through a second solder region.

11. The semiconductor device according to claim 10, wherein the lower substrate comprises: Dielectric core; a through hole extending through the dielectric core; a second plurality of dielectric layers disposed on opposite sides of the dielectric core; a second conductive feature disposed in the second plurality of dielectric layers; as well as A first solder resist layer and a second solder resist layer, the first solder resist layer is located on an uppermost dielectric layer of the second plurality of dielectric layers, the second solder resist layer is located on a lowermost dielectric layer of the second plurality of dielectric layers, wherein the first solder region extends into the first solder resist layer.

12. A semiconductor device, characterized in that include: a substrate including conductive features; as well as A chip-on-composite wafer device is attached to the first surface of the substrate, and the chip-on-composite wafer device includes: First intermediary layer; a first die coupled to a first side of the first interposer facing away from the substrate; a second interposer laterally spaced apart from the first interposer; a second die coupled to a first side of the second interposer facing away from the substrate; a first molding material disposed around the first die, the second die, the first interposer, and the second interposer; and a redistribution structure extending continuously along a second side of the first interposer facing the substrate, along a second side of the second interposer facing the substrate, and along a first surface of the first molding material facing the substrate, The rewiring structure comprises a plurality of dielectric layers and a first plurality of conductive features, wherein the conductive lines of the first plurality of conductive features are arranged between a first surface of the plurality of dielectric layers closest to the first interposer and a second surface of the plurality of dielectric layers farthest from the first interposer, wherein the plurality of dielectric layers of the rewiring structure are stacked together with no gaps therebetween, and wherein the conductive lines of the rewiring structure extend continuously from the first interposer to the second interposer. 13 . The semiconductor device of claim 12 , wherein the conductive line electrically couples at least one of the first dies to at least one of the second dies. 14 . The semiconductor device of claim 12 , further comprising a first solder region between the first surface of the substrate and the redistribution structure. 15 . The semiconductor device of claim 14 , further comprising an underfill material between the redistribution structure and the first surface of the substrate, wherein the underfill material surrounds the first solder region. 16 . The semiconductor device of claim 14 , further comprising a ring attached to the first surface of the substrate, an upper surface of the ring remote from the substrate extending further from the substrate than the first side of the first interposer.

17. A method for forming a semiconductor device, characterized in that The method comprises: attaching a first chip-on-wafer device to a first side of a carrier, the first chip-on-wafer device comprising a first interposer and a first die attached to the first interposer; attaching a second chip-on-wafer device to the first side of the carrier adjacent to the first chip-on-wafer device, the second chip-on-wafer device comprising a second interposer and a second die attached to the second interposer; forming a molding material on the first side of the carrier and around the first chip-on-wafer device and the second chip-on-wafer device, wherein the first conductive pad of the first interposer and the second conductive pad of the second interposer are exposed at an upper surface of the molding material away from the carrier; and forming a redistribution structure on the first chip-on-wafer device and over the second chip-on-wafer device and the molding material, wherein the redistribution structure extends continuously from the first chip-on-wafer device to the second chip-on-wafer device, The rewiring structure comprises a plurality of dielectric layers and a plurality of conductive features, wherein the plurality of conductive features are arranged between a first surface of the plurality of dielectric layers closest to the first interposer and a second surface of the plurality of dielectric layers farthest from the first interposer, wherein the plurality of dielectric layers are stacked together with no gaps therebetween, wherein one of the plurality of conductive features of the rewiring structure extends continuously from the chip device on the first wafer to the chip device on the second wafer. 18 . The method of forming a semiconductor device of claim 17 , wherein the one of the plurality of conductive features of the redistribution structure electrically couples at least one of the first dies to at least one of the second dies.

19. The method for forming a semiconductor device according to claim 17, further comprising: removing the carrier; as well as After removing the carrier, the redistribution structure is bonded to the first surface of the substrate using solder.

20. The method of forming a semiconductor device of claim 19, further comprising attaching a ring to the first surface of the substrate, wherein the ring surrounds the first chip-on-wafer device and the second chip-on-wafer device.

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