Display device

Abstract

A display device is provided. The display device includes a substrate, a first conductive layer, a second conductive layer, a planarization layer, and a display element, wherein the substrate has a display area and a peripheral area located outside the display area, the first conductive layer is located on the substrate in the peripheral area and includes a first hole, the second conductive layer is located on and overlaps the first conductive layer, the second conductive layer includes a second hole, the planarization layer extends from the display area to the peripheral area and includes at least two organic insulating layers located between the first conductive layer and the second conductive layer, and the display element is located on the planarization layer in the display area, wherein a portion of the second conductive layer excluding the second hole contacts a portion of the first conductive layer excluding the first hole.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0129329, filed on October 17, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of one or more embodiments relate to a display device. Background Art

[0004] Recently, the various uses of display devices have become more diverse. Moreover, as display devices become thinner and lighter, they can be used more widely. Research has been conducted to provide flexible display devices other than flat panel display devices, such as foldable display devices or rollable display devices.

[0005] The above information disclosed in this Background section is only for enhancement of background understanding and therefore, the information discussed in this Background section does not necessarily constitute prior art. Summary of the Invention

[0006] Aspects of one or more embodiments relate to a display device, and for example, to a foldable display device that can be folded or bent.

[0007] One or more embodiments include a display device having a structure capable of preventing or reducing degradation in display quality of an image. However, these characteristics are merely examples, and the scope of the present disclosure is not limited thereto.

[0008] Additional aspects will be set forth in part in the detailed description which follows and, in part, will be apparent from the description, or may be learned by practice of the embodiments presented herein.

[0009] According to one or more embodiments, a display device includes a substrate, a first conductive layer, a second conductive layer, a planarization layer, and a display element, wherein the substrate has a display area and a peripheral area located outside the display area, the first conductive layer is arranged on the substrate in the peripheral area and includes a first hole, the second conductive layer is arranged on the first conductive layer while overlapping with the first conductive layer and includes a second hole, the planarization layer extends from the display area to the peripheral area and includes at least two organic insulating layers arranged between the first conductive layer and the second conductive layer, and the display element is arranged on the planarization layer in the display area, wherein a portion of the second conductive layer other than the second hole contacts a portion of the first conductive layer other than the first hole.

[0010] According to some embodiments, the planarization layer may include a first organic insulating layer and a second organic insulating layer, wherein the first organic insulating layer includes a third hole, and the second organic insulating layer is arranged on the first organic insulating layer and includes a fourth hole, the second hole of the second conductive layer may be staggered with the first hole of the first conductive layer, each of the third hole of the first organic insulating layer and the fourth hole of the second organic insulating layer may be staggered with each of the first hole of the first conductive layer and the second hole of the second conductive layer, and the second conductive layer may contact the first conductive layer at a position where the third hole of the first organic insulating layer overlaps with the fourth hole of the second organic insulating layer.

[0011] According to some embodiments, a size of the third hole of the first organic insulating layer may be different from a size of the fourth hole of the second organic insulating layer.

[0012] According to some embodiments, the planarization layer may include a first organic insulating layer and a second organic insulating layer, wherein the first organic insulating layer includes an insulating pattern overlapping the first hole of the first conductive layer, and the second organic insulating layer is arranged on the first organic insulating layer, the second organic insulating layer may be staggered with each of the first hole of the first conductive layer and the second hole of the second conductive layer and may include a fourth hole arranged around the insulating pattern of the first organic insulating layer, the second hole of the second conductive layer may be staggered with the first hole of the first conductive layer, and the second conductive layer may contact the first conductive layer at the position of the fourth hole of the second organic insulating layer.

[0013] According to some embodiments, the planarization layer may include a first organic insulating layer and a second organic insulating layer, wherein the first organic insulating layer includes an insulating pattern overlapping with the first hole of the first conductive layer, and the second organic insulating layer is arranged on the first organic insulating layer, the second organic insulating layer may include a fourth hole staggered with each of the first hole of the first conductive layer and the second hole of the second conductive layer, and the fourth hole may be arranged around the insulating pattern of the first organic insulating layer, the second hole of the second conductive layer may overlap with the first hole of the first conductive layer, and the second conductive layer may contact the first conductive layer at the position of the fourth hole of the second organic insulating layer.

[0014] According to some embodiments, the display element may include a first electrode arranged on the same layer as the second conductive layer, a second electrode facing the first electrode, and an emission layer between the first and second electrodes, and the second electrode may extend to a peripheral area.

[0015] According to some embodiments, the display device may further include an insulating layer, wherein the insulating layer covers an edge of the first electrode of the display element in the display area and includes an insulating pattern overlapping with the second hole of the second conductive layer in the peripheral area, wherein the second electrode of the display element may contact the second conductive layer.

[0016] According to some embodiments, the display device may further include a thin film transistor and a power line, wherein the thin film transistor is electrically connected to the first electrode of the display element in the display area, and the power line is located in the area between the end of the second electrode of the display element and the edge of the substrate in the peripheral area, wherein the end of the first conductive layer can contact the power line, and the end of the second conductive layer can contact the end of the first conductive layer.

[0017] According to some embodiments, the substrate and the window over the display element may be flexible, allowing the display area to be folded or bent.

[0018] According to some embodiments, the planarization layer may include a first organic insulating layer and a second organic insulating layer, wherein the first organic insulating layer includes a first organic material and the second organic insulating layer includes a second organic material different from the first organic material.

[0019] According to one or more embodiments, a display device includes a substrate, a first conductive layer, a second conductive layer, a first organic insulating layer, a second organic insulating layer, and a display element, wherein the substrate includes a display area and a peripheral area located outside the display area, the first conductive layer is arranged on the substrate in the peripheral area and includes a first hole, the second conductive layer is arranged on the first conductive layer while overlapping with the first conductive layer and includes a second hole, the first organic insulating layer extends from the display area to the peripheral area and is arranged between the first conductive layer and the second conductive layer in the peripheral area, the second organic insulating layer is arranged on the first organic insulating layer, a portion of the second organic insulating layer arranged in the peripheral area is removed, and the display element is arranged on the second organic insulating layer in the display area, wherein a portion of the second conductive layer other than the second hole is in contact with a portion of the first conductive layer other than the first hole.

[0020] According to some embodiments, the second hole of the second conductive layer may overlap with the first hole of the first conductive layer, the first organic insulating layer may include an insulating pattern overlapping with the first hole of the first conductive layer, and the second conductive layer may contact a portion of the first conductive layer not covered by the insulating pattern of the first organic insulating layer.

[0021] According to some embodiments, the second hole of the second conductive layer may be staggered with the first hole of the first conductive layer, the first organic insulating layer may include a third hole staggered with each of the first hole of the first conductive layer and the second hole of the second conductive layer, and the second conductive layer may contact the first conductive layer at the position of the third hole of the first organic insulating layer.

[0022] According to some embodiments, the second hole of the second conductive layer may overlap with the first hole of the first conductive layer, the first organic insulating layer may include a third hole staggered with each of the first hole of the first conductive layer and the second hole of the second conductive layer, and the second conductive layer may contact the first conductive layer at the position of the third hole of the first organic insulating layer.

[0023] According to some embodiments, the display element may include a first electrode on the second organic insulating layer and a second electrode facing the first electrode and extending to a peripheral region.

[0024] According to some embodiments, the display device may further include an insulating layer, wherein the insulating layer covers an edge of the first electrode of the display element in the display area and includes an insulating pattern overlapping with the second hole of the second conductive layer in the peripheral area, wherein the second electrode of the display element may contact the second conductive layer.

[0025] According to some embodiments, the display device may further include a power supply line arranged between an end of the second electrode and an edge of the substrate, wherein an end of the first conductive layer may contact the power supply line and an end of the second conductive layer may contact an end of the first conductive layer.

[0026] According to some embodiments, the substrate and the window over the display element may be flexible, allowing the display area to be folded or bent.

[0027] According to some embodiments, the first organic insulating layer may include a first organic material, and the second organic insulating layer may include a second organic material different from the first organic material.

[0028] According to one or more embodiments, a display device includes a substrate, a first organic insulating layer, a first conductive layer, a second organic insulating layer, a third organic insulating layer, a second conductive layer, and a display element, wherein the substrate includes a display area and a peripheral area outside the display area, the first organic insulating layer is arranged on the substrate in the display area and the peripheral area, the first conductive layer is arranged on the first organic insulating layer in the peripheral area and includes a plurality of first holes, the second organic insulating layer covers the first conductive layer and is arranged on the first organic insulating layer, the third organic insulating layer is arranged on the second organic insulating layer, the second conductive layer is arranged on the third organic insulating layer in the peripheral area and includes a plurality of second holes, the centers of the second holes of the second conductive layer are staggered from the centers of the first holes of the first conductive layer, and the display element is arranged on the third organic insulating layer in the display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects, features and characteristics of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1A and Figure 1B is a perspective view schematically illustrating a display device before folding according to some embodiments;

[0031] Figure 2A and Figure 2B is a cross-sectional view schematically illustrating a display device in a folded state according to some embodiments;

[0032] Figure 3A and Figure 3B is a cross-sectional view of a display device according to some embodiments;

[0033] Figure 4A and Figure 4B is a plan view schematically illustrating a peripheral area of ​​a display panel according to some embodiments;

[0034] Figure 5 is an equivalent circuit diagram schematically illustrating pixels arranged in a display panel according to some embodiments;

[0035] Figure 6 yes Figure 4A A plan view of Area I, and Figure 7 It is along Figure 6 A sectional view taken along line II-II';

[0036] Figures 8A to 8C It shows Figure 6 a plan view of a stacking relationship between the first conductive layer and the second conductive layer;

[0037] Figure 9A and Figure 10A Along Figure 8C A cross-sectional view taken along line III-III', and Figure 9B and Figure 10B are shown separately Figure 9A and Figure 10A a plan view of a first contact area;

[0038] Figure 11 According to some embodiments Figure 4A A plan view of Area I, and Figure 12 It is along Figure 11 a sectional view taken along line IV-IV';

[0039] Figure 13A and Figure 13B It shows Figure 11 a plan view of the stacking relationship between the first conductive layer and the second conductive layer, and Figure 14 It is along Figure 13B A sectional view taken along line V-V';

[0040] Figure 15According to some embodiments, the image is taken along the second direction. Figure 4A A cross-sectional view of area I;

[0041] Figure 16A and Figure 16B It shows Figure 15 a plan view of the stacking relationship between the first conductive layer and the second conductive layer, and Figure 17 It is along Figure 16B A cross-sectional view taken along line VI-VI';

[0042] Figure 18 According to some embodiments, the image is taken along the second direction. Figure 4A A cross-sectional view of area I;

[0043] Figure 19A and Figure 19B It shows Figure 18 a plan view of the stacking relationship between the first conductive layer and the second conductive layer, and Figure 20 It is along Figure 19B A sectional view taken along line VII-VII';

[0044] Figure 21 According to some embodiments, the image is taken along the second direction. Figure 4A A cross-sectional view of area I;

[0045] Figure 22A and Figure 22B It shows Figure 21 a plan view of the stacking relationship between the first conductive layer and the second conductive layer, and Figure 23 It is along Figure 22B a sectional view taken along line VIII-VIII';

[0046] Figure 24 According to some embodiments, the image is taken along the second direction. Figure 4A A cross-sectional view of area I;

[0047] Figure 25A and Figure 25B It shows Figure 24 a plan view of the stacking relationship between the first conductive layer and the second conductive layer, and Figure 26 It is along Figure 25B A cross-sectional view taken along line IX-IX'; and

[0048] Figure 27 is a cross-sectional view schematically showing a display device according to some embodiments, Figure 28 It shows Figure 27 A diagram showing the relationship between the black matrix and the emission area, and Figure 29 It shows Figure 27Diagram of the relationship between the color filter and the emission area. DETAILED DESCRIPTION

[0049] Reference will now be made in more detail to various aspects of some embodiments shown in the accompanying drawings, wherein similar reference numerals always indicate similar elements. In this respect, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Accordingly, some embodiments are described below only by reference to the accompanying drawings to explain various aspects of this specification. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout this disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0050] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0051] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0052] It will be further understood that the term “comprising” as used herein refers to the presence of stated features or elements, but does not preclude the presence or addition of one or more other features or elements.

[0053] It will be understood that when a layer, region or element is referred to as being “formed on” another layer, region or element, it can be directly or indirectly formed on the other layer, region or element. That is, for example, intervening layers, regions or elements may be present.

[0054] For the convenience of explanation, the sizes of the elements in the drawings may be exaggerated. In other words, since the sizes and thicknesses of the elements in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0055] In the present specification, the expression “A and / or B” indicates only A, only B, or both A and B. Throughout the present disclosure, the expression “at least one of A and B” indicates only A, only B, or both A and B.

[0056] In the following embodiments, the expression "the line extends in the "first direction" or the "second direction"" as used herein may include not only the case where the line extends in a linear shape, but also the case where the line extends in a zigzag shape or a curved shape along the first direction or the second direction.

[0057] In the following embodiments, the expression "when viewed in a plan view" as used herein may indicate a state where an object is viewed from above, and the expression "when viewed in a cross-sectional view" as used herein may indicate a state where a cross section obtained by vertically cutting an object is viewed from the side. In the following embodiments, the expression "a first element overlaps with a second element" may mean that the first element is arranged above or below the second element.

[0058] Figure 1A and Figure 1B is a perspective view schematically illustrating a display device before being folded, according to some embodiments. Figure 2A and Figure 2B is a cross-sectional view schematically illustrating a display device in a folded state according to some embodiments. Figure 3A and Figure 3B is a cross-sectional view of a display device according to some embodiments.

[0059] The display device according to some embodiments may be a display device that can be folded or bent. The display device can be set in various shapes. For example, the display device can be set in a rectangular plate shape with two pairs of sides or edges parallel to each other. When the display device is set in a rectangular plate shape, one pair of opposite sides among the two pairs of sides can be set to be longer than the other pair of sides. According to some embodiments, for the convenience of description, the display device has a rectangular shape including a pair of long sides and a pair of short sides. Figure 1A For example, the extending direction of the long sides is indicated by a first direction D1, the extending direction of the short sides is indicated by a second direction D2, and a direction perpendicular to the extending directions of the long sides and the short sides is indicated by a third direction D3.

[0060] The shape of the display device according to some embodiments is not limited to the above-mentioned shapes. However, the display device according to some embodiments may have various shapes. For example, the display device may be arranged in various shapes, such as a closed polygon including straight edges, a circle including curved edges, an ellipse or similar shapes, and a semicircle, a semi-ellipse or similar shapes including straight lines and curved lines. According to some embodiments, when the display device has straight edges, at least a portion of the corners of each shape may be curved. For example, when the display device has a rectangular shape, the portion where adjacent straight edges intersect may be replaced by a curve with a certain curvature. That is, the vertex portion of the rectangle may have a curved edge, and the curved edge has two adjacent ends connected to two adjacent straight edges and has a certain curvature. The curvature may be set differently according to the position. For example, the curvature may change according to the starting position of the curve, the length of the curve, and similar parameters.

[0061] Reference Figure 1A 、 Figure 1B 、 Figure 2A and Figure 2BThe display device may include a display panel 10. The display panel 10 may have a display area DA and a peripheral area PA located outside the display area DA. The display area DA is an area where a plurality of pixels P are arranged to display an image. The peripheral area PA surrounds the display area DA and is a non-display area where no pixels P are arranged. For example, the peripheral area PA may be a frame area.

[0062] At least a portion of the display panel 10 may be flexible, and the display panel 10 may be foldable at the flexible portion. That is, the display panel 10 may include a foldable area FA and a plurality of non-folding areas NFA1 and NFA2, the foldable area FA being flexible and foldable, for example, along an axis (e.g., a set or predetermined axis), and the plurality of non-folding areas NFA1 and NFA2 being arranged on at least one side of the foldable area FA and being non-foldable. According to some embodiments, the non-foldable area is referred to as a non-folding area, but this is merely for convenience of description. The expression "non-folding" includes a case where the area is not flexible and is rigid, a case where the area is flexible but less flexible than the foldable area FA, and a case where the area is flexible but non-foldable. The display panel 10 may be configured to display an image in a display area DA of the foldable area FA and the non-folding area NFA.

[0063] exist Figure 1A In the figure, for the convenience of description, the first non-folding area NFA1 and the second non-folding area NFA2 are shown as having similar areas, and a foldable area FA is shown as being located between the first non-folding area NFA1 and the second non-folding area NFA2, but the embodiment is not limited thereto. For example, according to some embodiments, the first non-folding area NFA1 and the second non-folding area NFA2 may have different areas. In addition, as Figure 1B As shown in , a plurality of foldable areas (e.g., a plurality of foldable areas FA1 and FA2) may be provided. In this case, a plurality of non-foldable areas NFA1, NFA2, and NFA3 may be positioned to be separated from each other with corresponding foldable areas in the plurality of foldable areas FA1 and FA2 located therebetween. The plurality of foldable areas FA, FA1, and FA2 may be folded based on a plurality of folding lines FL, FL1, and FL2, respectively, and a plurality of folding lines FL, FL1, and FL2 may be provided in each of the foldable areas FA, FA1, and FA2. The plurality of folding lines FL, FL1, and FL2 are respectively arranged in the plurality of foldable areas FA, FA1, and FA2 in a second direction D2, which is an extending direction of the plurality of foldable areas FA, FA1, and FA2. Therefore, the display panel 10 may be folded in the plurality of foldable areas FA, FA1, and FA2.

[0064] exist Figure 1A and Figure 1BIn the figure, the plurality of folding lines FL, FL1, and FL2 are shown as passing through the centers of the plurality of foldable areas FA, FA1, and FA2, and the plurality of foldable areas FA, FA1, and FA2 are shown as being linearly symmetrical with respect to the plurality of folding lines FL, FL1, and FL2, but embodiments are not limited thereto. That is, the plurality of folding lines FL, FL1, and FL2 may be asymmetrically arranged in the plurality of foldable areas FA, FA1, and FA2. The plurality of foldable areas FA, FA1, and FA2 and the plurality of folding lines FL, FL1, and FL2 of the plurality of foldable areas FA, FA1, and FA2 may overlap with an area of ​​the display panel 10 displaying an image. When the display panel 10 is folded, the portion of the display panel 10 displaying an image may be folded.

[0065] According to some embodiments, the display panel 10 may completely correspond to the foldable area. For example, in the case where the display device is rollable like a roll of paper, the display panel 10 may completely correspond to the foldable area.

[0066] like Figure 1A and Figure 1B As shown in FIG, the display panel 10 can be unfolded to be flat as a whole. According to some embodiments, as shown in FIG. Figure 2A As shown in , the display panel 10 may be folded based on the folding line FL so that different portions of the display area DA face each other. Figure 2B As shown in , the display panel 10 can be folded along the folding line FL (or along the foldable area FA) so that the display area DA faces outward. The term "folding" does not mean that the form is fixed, but may mean that the form is modified from the original form to another form. The term "folding" includes a form that is bent, folded, or curled like a roll of paper along one or more specific lines (i.e., the folding line FL). Therefore, according to some embodiments, the surfaces of the two non-folding areas NFA1 and NFA2 are shown as being arranged parallel to each other and folded to face each other, but the embodiment is not limited thereto. The surfaces of the two non-folding areas NFA1 and NFA2 can be folded at a certain angle (e.g., an acute angle, a right angle, or an obtuse angle) with the foldable area FA located therebetween.

[0067] Reference Figure 3A , the display device 1 may include an optical functional layer 50 located on the display panel 10, and the display panel 10 and the optical functional layer 50 may be covered by a window 60. The window 60 may be bonded to an underlying element, for example, the optical functional layer 50, by an adhesive layer such as an optically clear adhesive (OCA). The display device 1 may be used in various electronic devices such as mobile phones, tablet personal computers (PCs), notebook computers, and smart watches. Figure 3BAs shown in , the display device 1 may further include an input sensing layer 40 located between the display panel 10 and the optical functional layer 50 .

[0068] The input sensing layer 40 acquires coordinate information based on external input such as a touch event (e.g., from a user's body or finger, a stylus, or the like). The input sensing layer 40 may include sensing electrodes (or touch electrodes) and signal lines (or traces) connected to the sensing electrodes. According to some embodiments, the input sensing layer 40 may be arranged directly on the display panel 10. The expression "the input sensing layer 40 is arranged directly on the display panel 10" may indicate a state in which no separate adhesive material layer is arranged between the input sensing layer 40 and the display panel 10, and may mean that elements of the input sensing layer 40 are patterned directly on the display panel 10. According to some embodiments, the input sensing layer 40 may be formed in a process separate from the display panel 10 and then bonded to the display panel 10 by using a transparent adhesive material layer or the like.

[0069] The optical function layer 50 may include a structure of a black matrix and a color filter. The color filter may be arranged according to the color of light emitted from each pixel of the display panel 10. The optical function layer 50 may function as an anti-reflection layer that reduces the reflectivity of light (external light) incident from the outside to the display panel 10 through the window 60.

[0070] The window 60 may cover and protect the optical functional layer 50, the input sensing layer 40, and / or the display panel 10. The window 60 may be provided on the display panel 10 without a polarizing layer to reduce the reflectivity of external light between the display panel 10 and the window 60. Aspects of some embodiments may include a foldable display device, which may be capable of preventing or reducing external light reflection by including an optical functional layer 50 including a color filter instead of a rigid polarizing layer (e.g., a retarder and a polarizer) and / or a planarization layer including a plurality of organic insulating layers in the display panel 10.

[0071] According to some embodiments, the window 60 may be formed to be larger than the input sensing layer 40, the optical function layer 50, and the display panel 10 so that the sides of the window 60 protrude more than the sides of each of the input sensing layer 40, the optical function layer 50, and the display panel 10. The window 60 may include a transparent material. The window 60 may be flexible. For example, the window 60 may include a polymer resin such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), or cellulose acetate propionate (CAP). The window 60 may be bonded on the input sensing layer 40 and the optical function layer 50 by using a transparent adhesive material layer or the like. The window 60 may include a light transmitting area 61 corresponding to the display area DA and a light blocking area 62 corresponding to the peripheral area PA.

[0072] Figure 4A and Figure 4B is a plan view schematically illustrating a peripheral area PA of the display panel 10 according to some embodiments.

[0073] Reference Figure 4A According to some embodiments, the display panel 10 includes a substrate 100 having a display area DA and a peripheral area PA outside the display area DA. A plurality of pixels P and signal lines configured to apply electrical signals to the pixels P may be arranged in the display area DA.

[0074] Each of the plurality of pixels P may include a display element and a pixel circuit for driving the display element. For example, the display element may include an organic light emitting diode, and the pixel circuit may include a plurality of transistors and a capacitor. The plurality of pixels P may include a first pixel that emits light of a first color, a second pixel that emits light of a second color, and a third pixel that emits light of a third color. For example, the first pixel may be a red pixel (R), the second pixel may be a green pixel (G), and the third pixel may be a blue pixel (B).

[0075] The signal lines configured to apply electrical signals to the pixels P may include a plurality of scan lines SL, a plurality of data lines DL, and the like. Each of the plurality of data lines DL may extend in a first direction D1, and each of the plurality of scan lines SL may extend in a second direction D2. For example, the plurality of scan lines SL may be arranged in a plurality of rows to transmit a plurality of scan signals to the plurality of pixels P, and the plurality of data lines DL may be arranged in a plurality of columns to transmit a plurality of data signals to the plurality of pixels P. Each of the plurality of pixels P may be connected to at least one corresponding scan line SL among the plurality of scan lines SL and a corresponding data line DL among the plurality of data lines DL.

[0076] The peripheral area PA may surround the display area DA. The peripheral area PA is an area where pixels P are not arranged. Various electronic devices, printed circuit boards and the like may be electrically attached to the peripheral area PA, and voltage lines configured to supply power for driving the display elements may be arranged in the peripheral area PA. For example, a scan driver 1100 that provides a scan signal to each pixel P, a data driver 1200 that provides a data signal to each pixel P, signal supply lines (clock signal lines, carry signal lines, drive voltage lines and the like) configured to supply signals to the scan driver 1100 and the data driver 1200, and a main voltage line configured to provide a first power supply voltage ELVDD and a second power supply voltage ELVSS may be arranged in the peripheral area PA. Figure 4A In FIG, the data driver 1200 is shown as being arranged directly on the substrate 100 so as to be adjacent to one side of the substrate 100. However, according to some embodiments, the data driver 1200 may be arranged on a flexible printed circuit board (FPCB), and the FPCB is electrically connected to pads arranged on one side of the display panel 10. Figure 4A , the scan driver 1100 is arranged on the left side, but according to some embodiments, the scan driver 1100 may also be arranged on the right side.

[0077] A first conductive layer 150 and a second conductive layer 160 may be arranged in the peripheral area PA. The first conductive layer 150 and the second conductive layer 160 may overlap with the scan driver 1100.

[0078] The first conductive layer 150 may extend to partially surround the display area DA along an edge of the display area DA. The second conductive layer 160 may overlap the first conductive layer 150 and extend to partially surround the display area DA along an edge of the display area DA. The area where the first and second conductive layers 150 and 160 overlap may include a contact area where the first and second conductive layers 150 and 160 are electrically connected. As described below, the first and second conductive layers 150 and 160 may each include a plurality of holes.

[0079] The first conductive layer 150 and the second conductive layer 160 may overlap with the power supply line 170. The power supply line 170 may have a loop extending to partially surround the display area DA and having one open side. The power supply line 170 may be connected to the pad PAD of the peripheral area PA and may be configured to receive the second power supply voltage ELVSS from the power supply of the FPCB electrically connected to the pad PAD. The first conductive layer 150 and the second conductive layer 160 may be electrically connected to the power supply line 170 and may be configured to receive the second power supply voltage ELVSS through the power supply line 170.

[0080] Some of the insulating layers in the peripheral area PA may include openings VH penetrating the insulating layers. The openings VH may surround the display area DA. The openings VH may form a closed loop completely surrounding the display area DA. According to some embodiments, the openings VH may overlap with the scan driver 1100.

[0081] According to some embodiments, Figure 4A As shown in , the first conductive layer 150 and the second conductive layer 160 may extend along the edge of the substrate 100 in a ring shape with one side of the display area DA adjacent to the data driver 1200 being opened. For example, the first conductive layer 150 and the second conductive layer 160 may extend along three of the four sides of the substrate 100 and not exist in one of the four sides of the substrate 100. According to some embodiments, as Figure 4B As shown in FIG, the first conductive layer 150 and the second conductive layer 160 may extend along the edge of the substrate 100 in a closed loop shape that completely surrounds the display area DA.

[0082] exist Figure 4A and Figure 4B , the width of the first conductive layer 150 is shown to be smaller than the width of the second conductive layer 160, but embodiments are not limited thereto. According to some embodiments, the width of the first conductive layer 150 may be substantially equal to or greater than the width of the second conductive layer 160.

[0083] Figure 5 is an equivalent circuit diagram schematically illustrating pixels P arranged in the display panel 10 according to some embodiments.

[0084] Reference Figure 5 , a plurality of signal lines SL1, SL2, SL3, EL, and DL, an initialization voltage line VIL, and a power supply voltage line PL are provided for each pixel P. According to some embodiments, at least one of the plurality of signal lines SL1, SL2, SL3, EL, and DL, the initialization voltage line VIL, and / or the power supply voltage line PL may be shared by adjacent pixels.

[0085] The plurality of signal lines SL1, SL2, SL3, EL, and DL include a first scan line SL1 configured to transmit a first scan signal GW, a second scan line SL2 configured to transmit a second scan signal GI, a third scan line SL3 configured to transmit a third scan signal GB, an emission control line EL configured to transmit an emission control signal EM, and a data line DL configured to transmit a data signal DATA. The third scan line SL3 may be the second scan line SL2 of the next row, and the third scan signal GB may be the second scan signal GI of the next row.

[0086] The power voltage line PL is configured to transmit a first power voltage ELVDD to the first transistor T1 , and the initialization voltage line VIL is configured to transmit an initialization voltage VINT for initializing the first transistor T1 and the organic light emitting diode OLED to the pixel P.

[0087] The first scan line SL1, the second scan line SL2, the third scan line SL3, the emission control line EL, and the initialization voltage line VIL may extend in the second direction D2 and may be spaced apart from each other in each row. The data line DL and the power supply voltage line PL may extend in the first direction D1 and may be spaced apart from each other in each column.

[0088] The pixel circuit PC of the pixel P may include a plurality of first to seventh transistors T1 to T7 and a capacitor Cst. The first to seventh transistors T1 to T7 may be implemented as thin film transistors.

[0089] The first transistor T1 is electrically connected to the power supply voltage line PL through the fifth transistor T5 and is electrically connected to the organic light emitting diode OLED through the sixth transistor T6. The first transistor T1 functions as a driving transistor and is configured to receive the data signal DATA according to the switching operation of the second transistor T2 and supply the driving current Ioled to the organic light emitting diode OLED.

[0090] The second transistor T2 is connected to the first scan line SL1 and the data line DL, and is turned on according to the first scan signal GW received through the first scan line SL1 to perform a switching operation to transmit the data signal DATA transmitted to the data line DL to the node N.

[0091] The third transistor T3 is connected to the organic light emitting diode OLED through the sixth transistor T6. The third transistor T3 is turned on according to the first scan signal GW received through the first scan line SL1, and is diode-connected to the first transistor T1.

[0092] The fourth transistor T4 is turned on according to the second scan signal GI received through the second scan line SL2 to transfer the initialization voltage VINT from the initialization voltage line VIL to the gate electrode of the first transistor T1 to initialize the gate voltage of the first transistor T1.

[0093] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the emission control signal EM received through the emission control line EL to form a current path so that the driving current Ioled flows from the power voltage line PL toward the organic light emitting diode OLED.

[0094] The seventh transistor T7 is turned on according to the third scan signal GB received through the third scan line SL3 to transmit the initialization voltage VINT from the initialization voltage line VIL to the organic light emitting diode OLED to initialize the organic light emitting diode OLED. The seventh transistor T7 may be omitted.

[0095] Figure 5 A case is shown where the fourth transistor T4 is connected to the second scan line SL2 and the seventh transistor T7 is connected to a separate third scan line SL3. According to some embodiments, the seventh transistor T7 may be connected to the second scan line SL2 together with the fourth transistor T4.

[0096] The capacitor Cst may be connected to the power voltage line PL and the gate electrode of the first transistor T1 to store and maintain a voltage corresponding to a difference between voltages across it so that a voltage applied to the gate electrode of the first transistor T1 is maintained.

[0097] The organic light emitting diode OLED may include a pixel electrode and an opposite electrode, and the opposite electrode may be configured to receive the second power voltage ELVSS. The organic light emitting diode OLED is configured to receive the driving current Ioled from the first transistor T1 and emit light to display an image.

[0098] Figure 6 yes Figure 4A Plan view of Area I. Figure 7 It is along Figure 6 A sectional view taken along line II-II'. Figures 8A to 8C It shows Figure 6 FIG. 1 is a plan view of a stacking relationship between the first conductive layer 150 and the second conductive layer 160 . Figure 9A and Figure 10A Along Figure 8C A cross-sectional view taken along line III-III', and Figure 9B and Figure 10B are shown separately Figure 9A and Figure 10A Hereinafter, reference will be made to the plan view of the first contact region CNT1. Figures 6 to 10B Provide the following description. Figure 6 For the convenience of explanation, Figure 4A The power line 170 is omitted.

[0099] Reference Figure 7 In the display area DA of the substrate 100 , a first thin film transistor TFT1 , a capacitor Cst, and an organic light emitting diode OLED electrically connected to the first thin film transistor TFT1 may be arranged.

[0100] The substrate 100 may include various materials, such as metal materials or plastic materials. According to some embodiments, the substrate 100 may be a flexible substrate. The substrate 100 may include a first base layer, a first barrier layer, a second base layer, and a second barrier layer stacked sequentially. The first base layer and the second base layer may each include a polymer resin. For example, the first base layer and the second base layer may each include a polymer resin, such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), or cellulose acetate propionate (CAP). The polymer resin may be transparent. The first barrier layer and the second barrier layer are layers each configured to prevent external foreign matter from penetrating. The first barrier layer and the second barrier layer may each be a single layer or multiple layers including an inorganic material such as amorphous silicon, silicon nitride, and / or silicon oxide.

[0101] A buffer layer 110 may be arranged on the substrate 100. The buffer layer 110 may prevent foreign matter or moisture from penetrating the substrate 100. The buffer layer 110 may include an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may be a single layer or a multilayer.

[0102] The first thin film transistor TFT1 may be Figure 5 One of the plurality of transistors described, for example, is used as a first transistor T1 serving as a driving transistor. The first thin film transistor TFT1 may include a semiconductor layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0103] The semiconductor layer ACT may include amorphous silicon, polycrystalline silicon, an oxide semiconductor material, or an organic semiconductor material. The semiconductor layer ACT may include a channel region CH overlapping the gate electrode GE, and a source region SE and a drain region DE arranged on either side of the channel region CH and including impurities. The impurities may include N-type impurities or P-type impurities. The source region SE and the drain region DE may respectively serve as the source electrode and drain electrode of the first thin film transistor TFT1.

[0104] The gate electrode GE may include a single layer or multiple layers containing at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and copper (Cu), taking into account adhesion to adjacent layers, surface flatness of stacked layers, processability or similar properties.

[0105] The gate insulating layer 111 between the semiconductor layer ACT and the gate electrode GE may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide. The gate insulating layer 111 may be a single layer or multiple layers including the above materials.

[0106] The capacitor Cst includes a lower electrode CE1 and an upper electrode CE2 that overlap each other with the first interlayer insulating layer 112 therebetween. The capacitor Cst may overlap the first thin film transistor TFT1. Figure 7 , the gate electrode GE of the first thin film transistor TFT1 is shown as the lower electrode CE1 of the capacitor Cst. According to some embodiments, the capacitor Cst may not overlap with the first thin film transistor TFT1. The capacitor Cst may be covered by the second interlayer insulating layer 113.

[0107] The first and second interlayer insulating layers 112 and 113 may each include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide.

[0108] A power supply voltage line PL and a first connection electrode CM1 may be arranged on the second interlayer insulating layer 113. The power supply voltage line PL and the first connection electrode CM1 may each be a single layer or multiple layers including at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). According to some embodiments, the power supply voltage line PL and the first connection electrode CM1 may each be a multilayer of Ti / Al / Ti.

[0109] A protective layer 114 may be arranged on the power voltage line PL and the first connection electrode CM1. The protective layer 114 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide, and may be a single layer or multiple layers.

[0110] A first insulating layer 115 may be arranged on the protective layer 114. A data line DL and a second connection electrode CM2 may be arranged on the first insulating layer 115. The data line DL and the second connection electrode CM2 may each include the same material as that of the power supply voltage line PL. For example, the data line DL and the second connection electrode CM2 may each be a single layer or a multilayer including at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and copper (Cu). According to some embodiments, the data line DL and the second connection electrode CM2 may each be a multilayer of Ti / Al / Ti. The data line DL and the second connection electrode CM2 may be covered by the second insulating layer 116 and the third insulating layer 117. Figure 7 As shown in , at least a portion of the data line DL may overlap with the power voltage line PL. According to some embodiments, the data line DL may not overlap with the power voltage line PL.

[0111] like Figure 7 As shown in , according to some embodiments, the data line DL may be arranged above the power voltage line PL, but according to some embodiments, the data line DL may be arranged on the second interlayer insulating layer 113, or the power voltage line PL may be arranged on the first insulating layer 115, so that the data line DL and the power voltage line PL may be arranged on the same layer. According to some embodiments, the power voltage line PL may have a double-layer structure, and the double-layer structure includes a lower power voltage line arranged on the second interlayer insulating layer 113, and an upper power voltage line arranged on the first insulating layer 115 and electrically connected to the lower power voltage line.

[0112] The first insulating layer 115, the second insulating layer 116, and the third insulating layer 117 may each be an organic insulating layer used as a planarizing insulating layer. For example, the first insulating layer 115, the second insulating layer 116, and the third insulating layer 117 may each include an organic insulating material, for example, a general polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, a siloxane polymer, an aromatic ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and any blend thereof. According to some embodiments, the first insulating layer 115 and the third insulating layer 117 may each be an organic insulating layer including polyimide, and the second insulating layer 116 may be an organic insulating layer including siloxane.

[0113] When the organic light-emitting diode (OLED) has wrinkles due to a step difference in the conductive layer arranged below the organic light-emitting diode (OLED), a reflective color band caused by the reflection of light emitted by the organic light-emitting diode (OLED) may be observed. According to some embodiments, a multi-layered organic insulating layer including at least two layers positioned between the organic light-emitting diode (OLED) and the thin film transistor may be provided to planarize the layer arranged below the organic light-emitting diode (OLED), thereby alleviating the above-mentioned problem.

[0114] Because a portion of the organic insulating layer is removed in the peripheral area PA through a process such as ashing or etching, the thickness of the organic insulating layer can be reduced, and the distance between the conductive layer located above the organic insulating layer and the conductive layer located below the organic insulating layer can be reduced. This can cause quality degradation due to coupling between the conductive layers or process / drive progressive burn-in. The multi-layered organic insulating layer according to some embodiments reduces or mitigates degradation caused by coupling between the conductive layers or process / drive progressive burn-in in the peripheral area PA.

[0115] like Figure 3A and Figure 3B As shown in FIG, the foldable display device according to some embodiments includes a window 60 of thin plastic and does not include a polarizing layer between the display panel 10 and the window 60. Therefore, in the foldable display device according to some embodiments, since the planarization of the layer arranged below the organic light emitting diode OLED is improved by the multi-layered organic insulating layer, external light reflection can be minimized without a separate polarizing layer.

[0116] exist Figure 7 , two organic insulating layers (i.e., the second insulating layer 116 and the third insulating layer 117) are arranged between the first conductive layer 150 and the second conductive layer 160, but according to some embodiments, three or more organic insulating layers may be arranged between the first conductive layer 150 and the second conductive layer 160.

[0117] A display element (eg, an organic light emitting diode OLED) may be arranged in the display area DA above the third insulating layer 117. The organic light emitting diode OLED may include a first electrode 221 serving as a pixel electrode, an intermediate layer 222, and a second electrode 223 serving as an opposite electrode.

[0118] The first electrode 221 of the organic light emitting diode OLED may be arranged on the third insulating layer 117 and may be connected to the first thin film transistor TFT1 through a first connection electrode CM1 on the second interlayer insulating layer 113 and a second connection electrode CM2 on the first insulating layer 115 .

[0119] The first electrode 221 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In some embodiments, the first electrode 221 may include a reflective film containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any compound thereof. In some embodiments, the first electrode 221 may further include a film containing ITO, IZO, ZnO, or In2O3 located above and / or below the reflective film.

[0120] A fourth insulating layer 118 may be arranged on the third insulating layer 117. The fourth insulating layer 118 may include an opening corresponding to each pixel P in the display area DA, that is, an opening OP exposing a portion of the first electrode 221. The opening OP of the fourth insulating layer 118 may define an emission area EA of the pixel P (see FIG. Figure 6 ). That is, the fourth insulating layer 118 may be arranged to correspond to the remaining area except the emission area EA, that is, the non-emission area NEA. The size of the emission area EA may be changed according to the color of the light emitted from the pixel P.

[0121] In addition, since the fourth insulating layer 118 increases the distance between the edge of the first electrode 221 and the second electrode 223 located above the first electrode 221, the fourth insulating layer 118 can prevent or reduce the occurrence of arcing or the like at the edge of the first electrode 221. The fourth insulating layer 118 may include, for example, an organic material such as polyimide (PI) or hexamethyldisiloxane (HMDSO).

[0122] The intermediate layer 222 includes an emissive layer. The emissive layer may include a high molecular weight or low molecular weight organic material that emits light of a certain color. In some embodiments, the intermediate layer 222 may include a first functional layer arranged below the emissive layer and / or a second functional layer arranged above the emissive layer. The first functional layer and / or the second functional layer may include a single layer located above the first electrode 221, or may include multiple patterned layers corresponding to the multiple first electrodes 221.

[0123] The first functional layer may be a single layer or multiple layers. For example, when the first functional layer comprises a high molecular weight material, the first functional layer is a hole transport layer (HTL) having a single layer structure and may comprise poly(3,4)-ethylene-dioxythiophene (PEDOT) or polyaniline (PANI). When the first functional layer comprises a low molecular weight material, the first functional layer may comprise a hole injection layer (HIL) and the HTL.

[0124] The second functional layer may be omitted. For example, when the first functional layer and the emissive layer each include a high molecular weight material, the second functional layer may be formed to improve the characteristics of the organic light-emitting diode. The second functional layer may be a single layer or multiple layers. The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0125] The second electrode 223 is arranged to face the first electrode 221 with the intermediate layer 222 located therebetween. The second electrode 223 may include a conductive material having a relatively low work function. For example, the second electrode 223 may include a (semi-) transparent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or any alloy thereof. Alternatively, the second electrode 223 may also include a layer such as ITO, IZO, ZnO, or In2O3 located on the (semi-) transparent layer including the above materials.

[0126] The second electrode 223 may be integrally formed in the plurality of organic light emitting diodes OLED in the display area DA to face the plurality of first electrodes 221 , and may be arranged over the intermediate layer 222 and the fourth insulating layer 118 .

[0127] Next, refer to Figure 7A scan driver 1100 may be arranged in the peripheral area PA of the substrate 100. The scan driver 1100 may include a second thin film transistor TFT2, and may include wiring (not shown) connected to the second thin film transistor TFT2. The second thin film transistor TFT2 may be formed by the same process as the first thin film transistor TFT1 of the pixel circuit PC. Therefore, a detailed description of the second thin film transistor TFT2 will be omitted. Although not shown, a control signal line configured to apply a control signal to the scan driver 1100 including the second thin film transistor TFT2 may also be arranged in the peripheral area PA. The control signal line may include a signal line configured to apply a clock signal, an inverted clock signal, a carry signal, and the like. The control signal line may be arranged on the same layer as the semiconductor layer ACT, the gate electrode GE, the upper electrode CE2 of the capacitor Cst, or the power supply voltage line PL. As shown Figure 7 As shown in FIG, the scan driver 1100 may be covered by a protective layer 114. According to some embodiments, the protective layer 114 may not be arranged in the peripheral area PA.

[0128] The buffer layer 110 , the gate insulating layer 111 , the first interlayer insulating layer 112 , and the second interlayer insulating layer 113 arranged in the display area DA may extend to the peripheral area PA.

[0129] The power line 170 may be arranged on the second interlayer insulating layer 113 outside the scan driver 1100. The power line 170 may be a line arranged in the peripheral area PA to provide the second power voltage ELVSS to each pixel P. The power line 170 may include the same material as that of the data line DL and / or the power voltage line PL and may be arranged on the same layer as that of the data line DL and / or the power voltage line PL.

[0130] The first insulating layer 115, the second insulating layer 116, and the third insulating layer 117 arranged in the display area DA may extend to the peripheral area PA and have an opening VH in the peripheral area PA. The opening VH may include an opening 115VH of the first insulating layer 115, an opening 116VH of the second insulating layer 116, and an opening 117VH of the third insulating layer 117. The plurality of openings 115VH, 116VH, and 117VH may overlap with each other. The inner surfaces of the plurality of openings 115VH, 116VH, and 117VH may not overlap with each other, and the sizes of the plurality of openings 115VH, 116VH, and 117VH may be different from each other. According to some embodiments, the inner surfaces of the plurality of openings 115VH, 116VH, and 117VH may overlap with each other.

[0131] The first insulating layer 115, the second insulating layer 116, and the third insulating layer 117 may be physically divided into at least two parts relative to the opening VH in the peripheral area PA. Therefore, for example, impurities or contaminants infiltrated from the outside, gas or moisture generated in the first insulating layer 115, the second insulating layer 116, and the third insulating layer 117 arranged outside the opening VH, and the like may be prevented from reaching the inside of the display area DA through the inside of the first insulating layer 115, the second insulating layer 116, and the third insulating layer 117.

[0132] The first conductive layer 150 and the second conductive layer 160 may overlap the scan driver 1100. Each of the first width W1 of the first conductive layer 150 and the second width W2 of the second conductive layer 160 may be greater than or equal to the width of the scan driver 1100. Figure 6 and Figure 7 , the second width W2 is shown to be greater than the first width W1, but the second width W2 may be less than or equal to the first width W1.

[0133] The first conductive layer 150 may be arranged on a layer between the first insulating layer 115 and the second insulating layer 116. The first conductive layer 150 may be arranged on the same layer as the data line DL and the second connection electrode CM2. The first conductive layer 150 may include the same material as the data line DL and may completely cover the opening 115VH of the first insulating layer 115. The second conductive layer 160 may be arranged on the third insulating layer 117. The second conductive layer 160 may be arranged on the same layer as the first electrode 221 of the organic light emitting diode OLED. The second conductive layer 160 may include the same material as the first electrode 221 and may completely cover the opening 116VH of the second insulating layer 116 and the opening 117VH of the third insulating layer 117.

[0134] At least one of the first conductive layer 150 and the second conductive layer 160 may include a hole. The first conductive layer 150 may include a plurality of first holes 150H arranged around the opening VH. Figure 6 and Figure 8A As shown in , when viewed in a plan view, the plurality of first holes 150H may be separated from each other. The second conductive layer 160 may include a plurality of second holes 160H arranged around the opening VH. Figure 6 and Figure 8B As shown in FIG, the plurality of second holes 160H may be separated from each other when viewed in a plan view.

[0135] The first holes 150H of the first conductive layer 150 and the second holes 160H of the second conductive layer 160 may be used as exhaust passages configured to discharge gas generated from the first insulating layer 115, the second insulating layer 116, and the third insulating layer 117 to the outside. Therefore, it is possible to prevent or reduce the problem that the gas generated from the first insulating layer 115, the second insulating layer 116, and the third insulating layer 117 penetrates into the display area DA and deteriorates the image quality achieved on the display device.

[0136] The first holes 150H and the second holes 160H may be staggered from each other. That is, the first holes 150H of the first conductive layer 150 and the second holes 160H of the second conductive layer 160 do not overlap with each other in the third direction D3 and may be staggered in the first direction D1 and the second direction D2 so as to be alternately arranged. Figure 7 and Figure 8C As shown in , the center of the first hole 150H and the center of the second hole 160H may be offset from each other and may not overlap. The first hole 150H of the first conductive layer 150 overlaps with the portion 160S of the second conductive layer 160, and the second hole 160H of the second conductive layer 160 overlaps with the portion 150S of the first conductive layer 150. The portion of the conductive layer represents an area where no hole of the conductive layer is formed. Therefore, the portion 150S of the first conductive layer 150 may be the remaining area of ​​the first conductive layer 150 excluding the first hole 150H, and the portion 160S of the second conductive layer 160 may be the remaining area of ​​the second conductive layer 160 excluding the second hole 160H.

[0137] like Figure 7 and Figure 8C As shown in FIG, the second hole 160H of the second conductive layer 160 may be covered by the fourth insulating layer 118 extending from the display area DA to the peripheral area PA. The fourth insulating layer 118 may include island-shaped insulating patterns 118a arranged corresponding to the second hole 160H of the second conductive layer 160. The insulating pattern 118a may be formed by patterning the fourth insulating layer 118 in the peripheral area PA.

[0138] exist Figure 7 and Figure 8C , the first hole 150H and the second hole 160H are shown as square, but according to some embodiments, the first hole 150H and the second hole 160H may have various shapes, such as polygonal (such as rectangular or triangular), circular or elliptical. The size of the first hole 150H may be the same as or different from the size of the second hole 160H.

[0139] The first conductive layer 150 and the second conductive layer 160 may contact each other in at least one first contact region CNT1 and may be electrically connected to each other. The first contact region CNT1 may be arranged between the first hole 150H of the first conductive layer 150 and the second hole 160H of the second conductive layer 160. The first contact region CNT1 may be a region where a portion 150S of the first conductive layer 150 and a portion 160S of the second conductive layer 160 overlap with each other. In the first contact region CNT1, the second insulating layer 116 may include a hole 116H penetrating the second insulating layer 116, and the third insulating layer 117 may include a hole 117H penetrating the third insulating layer 117. The hole 116H of the second insulating layer 116 and the hole 117H of the third insulating layer 117 may overlap with each other. According to some embodiments, as Figure 9A and Figure 9B As shown in FIG, the width (size) W4 of the hole 117H of the third insulating layer 117 may be greater than the width W3 of the hole 116H of the second insulating layer 116. According to some embodiments, as Figure 10A and Figure 10B As shown in FIG, the width W4 of the hole 117H of the third insulating layer 117 may be smaller than the width W3 of the hole 116H of the second insulating layer 116. In this case, the third insulating layer 117 may cover the inner surface of the hole 116H of the second insulating layer 116. The hole 116H of the second insulating layer 116 and the hole 117H of the third insulating layer 117 may not overlap with the first hole 150H of the first conductive layer 150 and the second hole 160H of the second conductive layer 160, and may be staggered. The second conductive layer 160 may contact the first conductive layer 150 through the hole 116H of the second insulating layer 116 and the hole 117H of the third insulating layer 117.

[0140] like Figure 6 and Figure 7 , an end portion of the first conductive layer 150 and an end portion of the second conductive layer 160 may overlap with and contact the power line 170 in the second contact region CNT2 around the edge of the substrate 100. In the second contact region CNT2, the power line 170 may be exposed through the opening 115OP of the first insulating layer 115, and the first conductive layer 150 may contact the power line 170 at the opening 115OP of the first insulating layer 115. In the second contact region CNT2, an end portion of the first conductive layer 150 may directly contact the power line 170, and an end portion of the second conductive layer 160 may directly contact an end portion of the first conductive layer 150.

[0141] The exposed portion of the second conductive layer 160 (i.e., the portion of the second conductive layer 160 not covered by the fourth insulating layer 118) may be in direct contact with the second electrode 223 extending from the display area DA to the peripheral area PA. The second conductive layer 160 may be in direct contact with the second electrode 223 at the opening VH. Since the second conductive layer 160 may be in contact with the second electrode 223, the second power supply voltage ELVSS supplied from the power line 170 may be supplied to the second electrode 223. Therefore, a drop in the second power supply voltage ELVSS may be reduced. Figure 7 A case is shown in which the end portion of the second electrode 223 extends toward the outer edge of the substrate 100 so as to cover at least a portion of the scan driver 1100 .

[0142] The encapsulation layer 300 may be arranged on the second electrode 223 to protect the display panel 10 from foreign matter, moisture, or the like. The encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. Figure 7 The case where the encapsulation layer 300 includes a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 therebetween is shown. According to some embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and a stacking order may be changed.

[0143] When necessary, a plurality of layers including the capping layer 230 may be arranged between the first inorganic encapsulating layer 310 and the opposite electrode 223. Figure 7 The cover layer 230 is shown in FIG. 3 , but according to some embodiments, the cover layer 230 may be omitted.

[0144] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may each include one or more inorganic insulating materials such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and silicon oxynitride. The organic encapsulation layer 320 may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid or the like) or any combination thereof. Since the first inorganic encapsulation layer 310 is formed along the structure of its lower layer, the upper surface of the first inorganic encapsulation layer 310 may be uneven. The organic encapsulation layer 320 may cover the first inorganic encapsulation layer 310 and have a sufficient thickness. The upper surface of the organic encapsulation layer 320 may be substantially flat. The second inorganic encapsulating layer 330 may extend outward on the organic encapsulating layer 320 to contact the first inorganic encapsulating layer 310 in order to prevent or reduce exposure of the organic encapsulating layer 320 to the outside.

[0145] At the same time, when forming the organic encapsulation layer 320, it is necessary to restrict the material used to form the organic encapsulation layer 320 so that it is located in a predetermined area. Figure 7 As shown in FIG, at least one dam 180 may be formed in the peripheral area PA. The dam 180 may have a multi-layer structure. The dam 180 may include at least one layer, and the at least one layer is formed simultaneously when the first insulating layer 115, the second insulating layer 116, the third insulating layer 117, or the fourth insulating layer 118 is formed, and the at least one layer is formed of the same material as the first insulating layer 115, the second insulating layer 116, the third insulating layer 117, or the fourth insulating layer 118. According to some embodiments, the dam 180 may include at least one of an organic layer and an inorganic layer formed by a separate process.

[0146] At least a portion of the dam 180 may be arranged on the end of the first conductive layer 150 on the power line 170. The first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 may be formed to the outside of the dam 180. The position of the organic encapsulating layer 320 may be limited by the dam 180, thereby preventing or reducing the material used to form the organic encapsulating layer 320 from overflowing outside the dam 180.

[0147] Figure 11 According to some embodiments Figure 4A Plan view of Area I. Figure 12 It is along Figure 11 A sectional view taken along line IV-IV'. Figure 13A and Figure 13B It shows Figure 11 FIG. 1 is a plan view of a stacking relationship between the first conductive layer 150 and the second conductive layer 160 . Figure 14 It is along Figure 13B In the following, reference will be made to the cross-sectional view of the line V-V'. Figures 11 to 14 The following description is given, but the Figures 6 to 10B The same construction as described in the construction of . Figure 11 For the convenience of explanation, Figure 4A The power line 170 is omitted.

[0148] The first insulating layer 115 arranged in the display area DA may extend to the peripheral area PA and have an opening 115VH in the peripheral area PA. A first conductive layer 150 may be arranged on the first insulating layer 115. The first conductive layer 150 may completely cover the opening 115VH of the first insulating layer 115. The first conductive layer 150 may include a plurality of first holes 150H. Figure 11 and Figure 13A As shown in FIG, the plurality of first holes 150H may be separated from each other when viewed in a plan view. The first holes 150H of the first conductive layer 150 may be covered by the second insulating layer 116 extending from the display area DA to the peripheral area PA.

[0149] The second insulating layer 116 may extend from the display area DA to the peripheral area PA and may have an opening 116VH in the peripheral area PA that overlaps with the opening 115VH of the first insulating layer 115. The second insulating layer 116 may include an island-shaped insulating pattern 116a corresponding to the first hole 150H of the first conductive layer 150. The insulating pattern 116a may be formed by patterning the second insulating layer 116 in the peripheral area PA. A portion 150S of the first conductive layer 150 not covered by the insulating pattern 116a may be exposed.

[0150] A second conductive layer 160 may be arranged on the exposed portion of the first conductive layer 150 and the second insulating layer 116 including the insulating pattern 116a. The second conductive layer 160 may completely cover the opening 116VH of the second insulating layer 116. The second conductive layer 160 may include a plurality of second holes 160H. Figure 11 and Figure 13B As shown in , when viewed in a plan view, the plurality of second holes 160H may be separated from each other. When viewed in a cross-sectional view and a plan view, the second holes 160H may be arranged to overlap with the first holes 150H. That is, the center of the first hole 150H and the center of the second hole 160H may coincide with each other. The second holes 160H may be arranged above the insulating pattern 116a to expose the upper surface of the insulating pattern 116a. Figure 13B , the size of the first hole 150H is shown to be larger than the size of the second hole 160H, but this is only an example. According to some embodiments, the size of the first hole 150H may be equal to or smaller than the size of the second hole 160H.

[0151] The second conductive layer 160 may be in direct contact with an exposed portion of the portion 150S of the first conductive layer 150 not having the insulating pattern 116a arranged thereon. That is, the first contact region CNT1 of the first conductive layer 150 and the second conductive layer 160 may be a region where the exposed portion of the first conductive layer 150 overlaps with the portion 160S of the second conductive layer 160. The direct contact between the first conductive layer 150 and the second conductive layer 160 may increase the contact area between the first conductive layer 150 and the second conductive layer 160, and further reduce a drop in the second power supply voltage ELVSS.

[0152] The second hole 160H of the second conductive layer 160 may be covered by the fourth insulating layer 118 extending from the display area DA to the peripheral area PA. The fourth insulating layer 118 may include an insulating pattern 118a corresponding to the second hole 160H of the second conductive layer 160. The fourth insulating layer 118 may not be arranged in the opening VH. The insulating pattern 118a of the fourth insulating layer 118 may overlap with the insulating pattern 116a of the second insulating layer 116.

[0153] The third insulating layer 117 arranged in the display area DA may not extend to the peripheral area PA. For example, the third insulating layer 117 may be formed on the second insulating layer 116, but the third insulating layer 117 may be removed in the peripheral area PA. In this case, a portion of the third insulating layer 117 may remain in the peripheral area PA to form the dam 180.

[0154] Because the peripheral area PA requires a relatively low level of planarization compared to the display area DA, the third insulating layer 117 is omitted in the peripheral area PA, and the second hole 160H of the second conductive layer 160 and the first hole 150H of the first conductive layer 150 overlap each other. It is possible to reduce the thickness of the peripheral area PA to reduce the thickness of the gas generating layer and shorten the path of the exhaust channel.

[0155] An exposed portion of the second conductive layer 160 (ie, a portion of the second conductive layer 160 not covered by the fourth insulating layer 118 ) may directly contact the second electrode 223 extending from the display area DA to the peripheral area PA.

[0156] Figure 15 According to some embodiments, the image is taken along the second direction D2. Figure 4A Cross-sectional view of zone I. Figure 16A and Figure 16B It shows Figure 15 FIG. 1 is a plan view of a stacking relationship between the first conductive layer 150 and the second conductive layer 160 . Figure 17 It is along Figure 16B A cross-sectional view taken along line VI-VI'.

[0157] Figure 15 Can be along Figure 6 Hereinafter, reference will be made to the cross-sectional view taken along the line II-II'. Figures 15 to 17 The following description is given, but the Figures 6 to 10B The constructor is the same as the description of the constructor.

[0158] The first insulating layer 115 arranged in the display area DA may extend to the peripheral area PA and have an opening 115VH in the peripheral area PA. A first conductive layer 150 may be arranged on the first insulating layer 115. The first conductive layer 150 may completely cover the opening 115VH of the first insulating layer 115. The first conductive layer 150 may include a plurality of first holes 150H arranged around the opening 115VH of the first insulating layer 115. Figure 16A As shown in FIG, the plurality of first holes 150H may be separated from each other when viewed in a plan view. The first holes 150H of the first conductive layer 150 may be covered by the second insulating layer 116 extending from the display area DA to the peripheral area PA.

[0159] The second insulating layer 116 may extend from the display area DA to the peripheral area PA and have an opening 116VH in the peripheral area PA that overlaps with the opening 115VH of the first insulating layer 115. The second insulating layer 116 may include an insulating pattern 116a corresponding to the first hole 150H of the first conductive layer 150. A portion of a portion 150S of the first conductive layer 150 not covered by the insulating pattern 116a may be exposed.

[0160] The third insulating layer 117 extending from the display area DA to the peripheral area PA may be arranged on the exposed portion of the first conductive layer 150 and the insulating pattern 116a. The third insulating layer 117 may cover the exposed portion of the first conductive layer 150 and the second insulating layer 116 including the insulating pattern 116a in the peripheral area PA, and may have an opening 117VH overlapping the opening 115VH of the first insulating layer 115 and the opening 116VH of the second insulating layer 116.

[0161] The second conductive layer 160 may be arranged on the third insulating layer 117. The second conductive layer 160 may completely cover the opening 116VH of the second insulating layer 116 and the opening 117VH of the third insulating layer 117. The second conductive layer 160 may include a plurality of second holes 160H. Figure 16B As shown in FIG, when viewed in a plan view, the plurality of second holes 160H may be separated from each other. The first hole 150H and the second hole 160H may be staggered. That is, the first hole 150H of the first conductive layer 150 and the second hole 160H of the second conductive layer 160 do not overlap with each other in the third direction D3, and may be staggered in the first direction D1 and the second direction D2 so as to be alternately arranged. The center of the first hole 150H and the center of the second hole 160H may be staggered and not overlap with each other.

[0162] The second conductive layer 160 may be in contact with the first conductive layer 150 in the first contact region CNT1 and electrically connected to the first conductive layer 150. Figure 17 As shown in FIG, the third insulating layer 117 may include a hole 117H penetrating the third insulating layer 117 in the first contact region CNT1. The hole 117H of the third insulating layer 117 may be staggered so as not to overlap with the first hole 150H of the first conductive layer 150 and the second hole 160H of the second conductive layer 160. The second conductive layer 160 may contact the first conductive layer 150 in the first contact region CNT1 through the hole 117H of the third insulating layer 117.

[0163] The second hole 160H of the second conductive layer 160 may be covered by the fourth insulating layer 118 extending from the display area DA to the peripheral area PA. The fourth insulating layer 118 may include an insulating pattern 118a corresponding to the second hole 160H of the second conductive layer 160. The insulating patterns 118a of the fourth insulating layer 118 and the insulating patterns 116a of the second insulating layer 116 may be staggered and not overlapped.

[0164] An exposed portion of the second conductive layer 160 (ie, a portion of the second conductive layer 160 not covered by the fourth insulating layer 118 ) may directly contact the second electrode 223 extending from the display area DA to the peripheral area PA.

[0165] Figure 18 According to some embodiments, the image is taken along the second direction D2. Figure 4A Cross-sectional view of zone I. Figure 19A and Figure 19B It shows Figure 18 FIG. 1 is a plan view of a stacking relationship between the first conductive layer 150 and the second conductive layer 160 . Figure 20 It is along Figure 19B A cross-sectional view taken along line VII-VII'. Figure 18 Can be along Figure 6 Hereinafter, reference will be made to the cross-sectional view taken along line IV-IV'. Figures 18 to 20 The following description is given, but the Figures 11 to 14 The constructor is the same as the description of the constructor.

[0166] The first insulating layer 115 arranged in the display area DA may extend to the peripheral area PA and have an opening 115VH in the peripheral area PA. A first conductive layer 150 may be arranged on the first insulating layer 115. The first conductive layer 150 may completely cover the opening 115VH of the first insulating layer 115. The first conductive layer 150 may include a plurality of first holes 150H arranged around the opening 115VH of the first insulating layer 115. Figure 19A As shown in FIG, the plurality of first holes 150H may be separated from each other when viewed in a plan view. The first holes 150H of the first conductive layer 150 may be covered by the second insulating layer 116 extending from the display area DA to the peripheral area PA.

[0167] The second insulating layer 116 may extend from the display area DA to the peripheral area PA and have an opening 116VH in the peripheral area PA that overlaps with the opening 115VH of the first insulating layer 115. The second insulating layer 116 may include an insulating pattern 116a corresponding to the first hole 150H of the first conductive layer 150. A portion of a portion 150S of the first conductive layer 150 not covered by the insulating pattern 116a may be exposed.

[0168] The third insulating layer 117 extending from the display area DA to the peripheral area PA may be arranged on the second insulating layer 116 including the exposed portion of the first conductive layer 150 and the insulating pattern 116a. The third insulating layer 117 may cover the exposed portion of the first conductive layer 150 and the second insulating layer 116 in the peripheral area PA and may have an opening 117VH overlapping with the opening 115VH of the first insulating layer 115 and the opening 116VH of the second insulating layer 116.

[0169] The second conductive layer 160 may be arranged on the third insulating layer 117. The second conductive layer 160 may completely cover the opening 116VH of the second insulating layer 116 and the opening 117VH of the third insulating layer 117. The second conductive layer 160 may include a plurality of second holes 160H. Figure 19B As shown in FIG, when viewed in a plan view, the plurality of second holes 160H may be separated from each other. When viewed in a cross-sectional view and a plan view, the second holes 160H may overlap with the first holes 150H. That is, the center of the first hole 150H and the center of the second hole 160H may coincide with each other. The second holes 160H may overlap with the insulating pattern 116a.

[0170] The second conductive layer 160 may be in contact with the first conductive layer 150 in the first contact region CNT1 and electrically connected to the first conductive layer 150. Figure 20 As shown in FIG, the third insulating layer 117 may include a hole 117H that penetrates the third insulating layer 117 and exposes a portion 150S of the first conductive layer 150 in the first contact region CNT1. The hole 117H of the third insulating layer 117 may be staggered so as not to overlap with the first hole 150H of the first conductive layer 150 and the second hole 160H of the second conductive layer 160. The second conductive layer 160 may contact the first conductive layer 150 in the first contact region CNT1 through the hole 117H of the third insulating layer 117.

[0171] The second hole 160H of the second conductive layer 160 may be covered by the fourth insulating layer 118 extending from the display area DA to the peripheral area PA. The fourth insulating layer 118 may include an island-shaped insulating pattern 118a corresponding to the second hole 160H of the second conductive layer 160. The insulating pattern 118a of the fourth insulating layer 118 may overlap with the insulating pattern 116a of the second insulating layer 116.

[0172] An exposed portion of the second conductive layer 160 (ie, a portion of the second conductive layer 160 not covered by the fourth insulating layer 118 ) may directly contact the second electrode 223 extending from the display area DA to the peripheral area PA.

[0173] Figure 21 According to some embodiments, the image is taken along the second direction D2. Figure 4A Cross-sectional view of zone I. Figure 22A and Figure 22B It shows Figure 21 FIG. 1 is a plan view of a stacking relationship between the first conductive layer 150 and the second conductive layer 160 . Figure 23 It is along Figure 22B A sectional view taken along line VIII-VIII'. Figure 21 Can be along Figure 6 Hereinafter, reference will be made to the cross-sectional view taken along the line II-II'. Figures 21 to 23 The following description is given, but the Figures 6 to 10B The constructor is the same as the description of the constructor.

[0174] The first insulating layer 115 arranged in the display area DA may extend to the peripheral area PA and have an opening 115VH in the peripheral area PA. A first conductive layer 150 may be arranged on the first insulating layer 115. The first conductive layer 150 may include a plurality of first holes 150H arranged around the opening 115VH. Figure 22A As shown in FIG, the plurality of first holes 150H may be separated from each other when viewed in a plan view.

[0175] A second insulating layer 116 covering the first conductive layer 150 and extending from the display area DA to the peripheral area PA may be arranged above the first conductive layer 150. The second insulating layer 116 may include an opening 116VH overlapping the opening 115VH of the first insulating layer 115.

[0176] The second conductive layer 160 may be arranged on the second insulating layer 116. The second conductive layer 160 may completely cover the opening 116VH of the second insulating layer 116. The second conductive layer 160 may include a plurality of second holes 160H. Figure 22B As shown in , when viewed in a plan view, the plurality of second holes 160H may be separated from each other. The first hole 150H and the second hole 160H may be staggered from each other. That is, the first hole 150H of the first conductive layer 150 and the second hole 160H of the second conductive layer 160 do not overlap with each other in the third direction D3, and may be staggered in the first direction D1 and the second direction D2 so as to be alternately arranged. The center of the first hole 150H and the center of the second hole 160H may be staggered from each other and not coincide with each other.

[0177] The second conductive layer 160 may be in contact with the first conductive layer 150 in the first contact region CNT1 and electrically connected to the first conductive layer 150. Figure 23 As shown in FIG, the second insulating layer 116 may include a hole 116H penetrating the second insulating layer 116 and exposing the first conductive layer 150 in the first contact region CNT1. The second conductive layer 160 may contact the first conductive layer 150 through the hole 116H in the second insulating layer 116 in the first contact region CNT1.

[0178] The second hole 160H of the second conductive layer 160 may be covered by the fourth insulating layer 118 extending from the display area DA to the peripheral area PA. The fourth insulating layer 118 may include an insulating pattern 118a corresponding to the second hole 160H of the second conductive layer 160. An exposed portion of the second conductive layer 160 (i.e., a portion of the second conductive layer 160 not covered by the fourth insulating layer 118) may directly contact the second electrode 223 extending from the display area DA to the peripheral area PA.

[0179] Figure 24 According to some embodiments, the image is taken along the second direction D2. Figure 4A Cross-sectional view of zone I. Figure 25A and Figure 25B It shows Figure 24 FIG. 1 is a plan view of a stacking relationship between the first conductive layer 150 and the second conductive layer 160 . Figure 26 It is along Figure 25B A cross-sectional view taken along line IX-IX'.

[0180] Figure 24 Can be along Figure 11 Hereinafter, reference will be made to the cross-sectional view taken along line IV-IV'. Figures 24 to 26 The following description is given, but the Figures 11 to 14 The constructor is the same as the description of the constructor.

[0181] The first insulating layer 115 arranged in the display area DA may extend to the peripheral area PA and have an opening 115VH in the peripheral area PA. A first conductive layer 150 may be arranged on the first insulating layer 115. The first conductive layer 150 may include a plurality of first holes 150H. Figure 25A As shown in FIG, the plurality of first holes 150H may be separated from each other when viewed in a plan view.

[0182] A second insulating layer 116 may be arranged above the first conductive layer 150, covering the first hole 150H of the first conductive layer 150 and extending from the display area DA to the peripheral area PA. The second conductive layer 160 may be arranged on the second insulating layer 116. The second conductive layer 160 may include a plurality of second holes 160H. Figure 25B As shown in FIG, when viewed in a plan view, the plurality of second holes 160H may be separated from each other. When viewed in a cross-sectional view and a plan view, the second holes 160H may overlap with the first holes 150H. That is, the centers of the first holes 150H and the second holes 160H may coincide with each other.

[0183] The second conductive layer 160 may be in contact with the first conductive layer 150 in the first contact region CNT1 and electrically connected to the first conductive layer 150. Figure 26As shown in FIG, the second insulating layer 116 may include a hole 116H penetrating the second insulating layer 116 and exposing the first conductive layer 150 in the first contact region CNT1. The second conductive layer 160 may contact the first conductive layer 150 through the hole 116H in the second insulating layer 116 in the first contact region CNT1.

[0184] The second hole 160H of the second conductive layer 160 may be covered by the fourth insulating layer 118 extending from the display area DA to the peripheral area PA. The fourth insulating layer 118 may include an insulating pattern 118a corresponding to the second hole 160H of the second conductive layer 160. An exposed portion of the second conductive layer 160 (i.e., a portion of the second conductive layer 160 not covered by the fourth insulating layer 118) may directly contact the second electrode 223 extending from the display area DA to the peripheral area PA.

[0185] Figure 27 is a cross-sectional view schematically showing a display device according to some embodiments, Figure 28 It shows Figure 27 A diagram showing the relationship between the black matrix BM and the emission area EA, and Figure 29 It shows Figure 27 FIG. 4 is a diagram showing the relationship between the color filter CF and the emission area EA.

[0186] Reference Figure 27 , a black matrix BM and a color filter CF serving as an optical functional layer may be arranged on the encapsulation layer 300. Figure 28 As shown in FIG, the black matrix BM may surround the emission area EA and may be arranged to correspond to an area other than the opening OP of the fourth insulating layer 118. Figure 29 As shown in , the color filter CF may be arranged to correspond to at least the emission area EA. The color filter CF may include a first color filter CF1 that selectively transmits only light of a first color, a second color filter CF2 that selectively transmits only light of a second color, and a third color filter CF3 that selectively transmits only light of a third color. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be adjacent to each other and arranged in a specific pattern. The black matrix BM may be arranged to correspond to the boundaries of the first color filter CF1, the second color filter CF2, and the third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may each partially overlap with the black matrix BM.

[0187] Although not shown, an input sensing layer may be further provided between the black matrix BM and the encapsulation layer 300 and between the color filter CF and the encapsulation layer 300 .

[0188] When impurities such as gas or moisture generated from an organic material included in a display device are introduced from the outside or penetrate into the display device, image quality may deteriorate during the manufacturing process or during use. According to one or more embodiments, it is possible to provide a display device that can solve or reduce various problems including the above-mentioned problems by preventing or reducing degradation in image quality of an image.

[0189] According to one or more embodiments, it is possible to realize a display device capable of preventing or reducing degradation of image quality during a manufacturing process or during use. The scope of the present disclosure is not limited by these effects.

[0190] It should be understood that the embodiments described herein should be considered in a descriptive manner only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope and spirit as defined by the following claims and their equivalents.

Claims

1. A display device comprising: a substrate comprising a display area and a peripheral area located outside the display area; a first conductive layer located on the substrate in the peripheral region and comprising a first hole; a second conductive layer located on and overlapping the first conductive layer in the peripheral region, the second conductive layer comprising a second hole; a planarization layer extending from the display area to the peripheral area and comprising at least two organic insulating layers between the first conductive layer and the second conductive layer; as well as a display element, the display element being located on the planarization layer in the display region, Part of the second conductive layer excluding the second hole contacts part of the first conductive layer excluding the first hole.

2. The display device according to claim 1, wherein The planarization layer comprises: a first organic insulating layer, the first organic insulating layer comprising a third hole; and a second organic insulating layer, the second organic insulating layer being located on the first organic insulating layer and comprising a fourth hole; The second hole in the second conductive layer is staggered with the first hole in the first conductive layer. Each of the third hole of the first organic insulating layer and the fourth hole of the second organic insulating layer is staggered with each of the first hole of the first conductive layer and the second hole of the second conductive layer, and The second conductive layer contacts the first conductive layer at a location where the third hole of the first organic insulating layer overlaps with the fourth hole of the second organic insulating layer.

3. The display device according to claim 2, wherein: A size of the third hole of the first organic insulating layer is different from a size of the fourth hole of the second organic insulating layer.

4. The display device according to claim 1, wherein The planarization layer comprises: a first organic insulating layer including an insulating pattern overlapping the first hole of the first conductive layer; and a second organic insulating layer, the second organic insulating layer being located on the first organic insulating layer; The second organic insulating layer includes fourth holes that are staggered from each of the first holes of the first conductive layer and the second holes of the second conductive layer, the fourth holes being arranged around the insulating pattern of the first organic insulating layer, The second hole of the second conductive layer is staggered with the first hole of the first conductive layer, and The second conductive layer contacts the first conductive layer at a position of the fourth hole of the second organic insulating layer.

5. The display device according to claim 1, wherein The planarization layer comprises: a first organic insulating layer including an insulating pattern overlapping the first hole of the first conductive layer; and a second organic insulating layer, the second organic insulating layer being located on the first organic insulating layer; The second organic insulating layer includes fourth holes that are staggered from each of the first holes of the first conductive layer and the second holes of the second conductive layer, the fourth holes being arranged around the insulating pattern of the first organic insulating layer, The second hole of the second conductive layer overlaps with the first hole of the first conductive layer, and The second conductive layer contacts the first conductive layer at the fourth hole of the second organic insulating layer. The display device according to claim 1 , wherein: The display element includes: a first electrode, the first electrode being located on the same layer as the second conductive layer; a second electrode facing the first electrode; and an emitting layer located between the first electrode and the second electrode, and The second electrode extends to the peripheral region.

7. The display device according to claim 6, further comprising: an insulating layer covering an edge of the first electrode of the display element in the display area and including an insulating pattern overlapping the second hole of the second conductive layer in the peripheral area, The second electrode of the display element is in contact with the second conductive layer.

8. The display device according to claim 6, further comprising: a thin film transistor electrically connected to the first electrode of the display element in the display area; as well as a power supply line located in a region between an end portion of the second electrode of the display element and an edge of the substrate in the peripheral region, An end portion of the first conductive layer contacts the power line, and an end portion of the second conductive layer contacts the end portion of the first conductive layer.

9. The display device according to claim 1, wherein: The substrate and the window over the display element are flexible to enable the display area to be folded or bent.

10. The display device according to claim 1, wherein The planarization layer comprises: a first organic insulating layer comprising a first organic material; and A second organic insulating layer includes a second organic material different from the first organic material.

11. A display device comprising: a substrate comprising a display area and a peripheral area located outside the display area; a first conductive layer located on the substrate in the peripheral region and comprising a first hole; a second conductive layer located on and overlapping the first conductive layer in the peripheral region, the second conductive layer comprising a second hole; a first organic insulating layer, the first organic insulating layer extending from the display area to the peripheral area and arranged between the first conductive layer and the second conductive layer in the peripheral area; a second organic insulating layer located on the first organic insulating layer, wherein a portion of the second organic insulating layer located in the peripheral region is removed; and a display element, the display element being located on the second organic insulating layer in the display area, Part of the second conductive layer excluding the second hole contacts part of the first conductive layer excluding the first hole.

12. The display device according to claim 11, wherein The second hole of the second conductive layer overlaps with the first hole of the first conductive layer, The first organic insulating layer includes an insulating pattern overlapping the first hole of the first conductive layer, and The second conductive layer contacts a portion of the first conductive layer that is not covered by the insulating pattern of the first organic insulating layer.

13. The display device according to claim 11, wherein The second hole of the second conductive layer is staggered with the first hole of the first conductive layer, The first organic insulating layer includes a third hole that is staggered from each of the first hole of the first conductive layer and the second hole of the second conductive layer, and The second conductive layer contacts the first conductive layer at a position of the third hole of the first organic insulating layer.

14. The display device according to claim 11, wherein The second hole of the second conductive layer overlaps with the first hole of the first conductive layer, The first organic insulating layer includes a third hole that is staggered from each of the first hole of the first conductive layer and the second hole of the second conductive layer, and The second conductive layer contacts the first conductive layer at a position of the third hole of the first organic insulating layer.

15. The display device according to claim 11, wherein The display element includes a first electrode on the second organic insulating layer and a second electrode facing the first electrode and extending to the peripheral area.

16. The display device according to claim 15, further comprising: an insulating layer covering an edge of the first electrode of the display element in the display area and including an insulating pattern overlapping the second hole of the second conductive layer in the peripheral area, The second electrode of the display element is in contact with the second conductive layer.

17. The display device according to claim 15, further comprising: a power line located between an end of the second electrode and an edge of the substrate, An end portion of the first conductive layer contacts the power line, and an end portion of the second conductive layer contacts the end portion of the first conductive layer.

18. The display device according to claim 11, wherein The substrate and the window over the display element are flexible to enable the display area to be folded or bent.

19. The display device according to claim 11, wherein The first organic insulating layer includes a first organic material, and The second organic insulating layer includes a second organic material different from the first organic material.

20. A display device comprising: a substrate comprising a display area and a peripheral area located outside the display area; a first organic insulating layer, the first organic insulating layer being located on the substrate in the display area and the peripheral area; a first conductive layer located on the first organic insulating layer in the peripheral region and comprising a plurality of first holes; a second organic insulating layer, the second organic insulating layer covering the first conductive layer and being located on the first organic insulating layer; a third organic insulating layer, wherein the third organic insulating layer is located on the second organic insulating layer; a second conductive layer, the second conductive layer being located on the third organic insulating layer in the peripheral region and comprising a plurality of second holes, wherein centers of the second holes of the second conductive layer are offset from centers of the first holes of the first conductive layer; as well as A display element is located on the third organic insulating layer in the display area.

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