A non-destructive method for testing peak junction temperature of chips in a multi-chip parallel package module

Abstract

The application discloses a lossless testing method for peak chip temperature of parallel devices in a module, which realizes the peak junction temperature measurement of the parallel devices or the module by constructing a temperature-on voltage drop curve cluster based on current proportion under specific testing current. A temperature-on voltage drop three-dimensional database is obtained, and according to the testing current and the number of the parallel devices, a temperature-on voltage drop curve cluster based on current proportion under specific testing current is obtained by using a current conversion formula. The current proportion-temperature curve under different testing currents is obtained by using the curve cluster and the on voltage drop corresponding to the small current obtained by measuring the working state of the device. Finally, the peak junction temperature and the current proportion of the parallel devices or the module are determined according to the intersection of the current proportion-temperature curves under different testing currents. By using the method, the lossless measurement of the peak chip temperature of the parallel devices in the module can be realized on the basis of the mature small current voltage drop method without increasing additional equipment.

Description

Technical Field

[0001] This invention relates to a method for testing the peak junction temperature of chips within a multi-chip parallel package module, belonging to the field of power semiconductor device testing. Background Technology

[0002] Power semiconductor switching devices / modules, as key components in power electronic systems, are mainly used in inverters and rectifiers to control and convert electrical energy, forming the core of power conversion technology. Currently, they are widely used in new energy vehicles, railway transportation, wind power generation, and high-voltage power transmission and distribution, with ever-increasing demands for current, voltage, and power capacity in these applications. When addressing high-voltage, high-current, and high-power applications, the current capacity of existing single discrete devices is far from meeting the demands of large-capacity power conversion. Furthermore, manufacturing large-capacity single discrete devices is difficult and costly. Due to the limitations of power rating and current capacity of individual devices, current solutions often employ parallel connection of discrete devices or modular packaging of multi-chip parallel connections to expand current capacity or power. In parallel applications, due to differences in individual chips and varying heat dissipation conditions, the heat generated during operation results in uneven temperature distribution among the chips. The reliability and lifespan of the chip with the highest temperature determines the upper limit of the reliability of the parallel system or module. Therefore, measuring the peak junction temperature of parallel devices or modules is particularly important.

[0003] Currently, mature methods and systems exist for measuring the junction temperature of individual semiconductor devices. Non-destructive junction temperature measurement without damaging the package mainly relies on electrical methods such as small current voltage drop and thermal resistance calculation. However, in parallel applications, it is difficult to test each chip branch within the same module due to the parallel packaging of chips. Using traditional single-device testing methods to measure the main circuit of parallel devices results in significant errors between the test results and the peak junction temperature, making it difficult to assess the reliability of parallel devices or modules. Furthermore, current methods for measuring the peak junction temperature of parallel devices or modules can only employ destructive infrared measurement, lacking suitable non-destructive electrical testing methods. Especially for newer packages such as press-fit, damaging the package compromises electrical connection, rendering infrared measurement methods unsuitable. Summary of the Invention

[0004] To address the aforementioned problems, this invention proposes a method for testing the peak junction temperature of chips within a multi-chip parallel package module. Based on the low-current voltage drop method, this method achieves the measurement of the peak junction temperature of multiple parallel chips through transformation and evolution of a calibration curve library. This method requires no additional test circuitry and can utilize existing mature low-current testing equipment to determine the calibration curves and measure the peak junction temperature.

[0005] The technical solution adopted in this invention is as follows:

[0006] Under different temperatures and calibration currents, the on-state voltage drop of parallel devices or modules is measured as a whole, resulting in a three-dimensional database of temperature-calibration current-on-state voltage drop. A specific test current is selected, and based on the current percentage conversion formula, a cluster of temperature-on-state voltage drop calibration curves related to the current percentage under any specific test current is obtained. Then, during device operation, the voltage of the parallel device or module is measured according to the specific test current. These values ​​are then substituted into the voltage-temperature curve clusters corresponding to different current percentages for each specific test current, yielding a series of temperature values ​​under different current percentages for each specific test current. A fitted current percentage-temperature change curve is then plotted. Finally, the peak junction temperature of the parallel device or module is determined based on the intersection of the current percentage-temperature curves under at least two different specific test currents.

[0007] The device for implementing this method includes a module 1 containing multiple chips connected in parallel, a parallel test fixture 2, a temperature chamber or temperature control platform 3, and a test source meter 4; the temperature chamber or temperature control platform 3 is used to heat the module 1, and the test source meter 4 is used to apply different currents to the module 1 under test and measure the on-state voltage drop.

[0008] The present invention is characterized in that it further includes the following steps:

[0009] Step 1: Place module 1 on parallel test fixture 2, then place module 1 and parallel test fixture 2 in temperature chamber or temperature control platform 3, and use temperature chamber or temperature control platform 3 to heat module 1.

[0010] Step 2: Set the initial temperature of the temperature chamber or temperature control platform 3 so that the temperature of module 1 is stable at the set temperature of the temperature chamber or temperature control platform 3. After the temperature is stable, use the test source meter 4 to apply the temperature calibration current in a certain step size and test to obtain the on-state voltage drop of module 1 under different temperature calibration currents.

[0011] Step 3: Change the temperature of the temperature chamber or temperature control platform 3 in a certain step, repeat the temperature calibration current test in step 2, and measure the on-state voltage drop of module 1 under different temperatures and temperature calibration currents.

[0012] Step 4: Based on the specific test current (no less than two) and the number of parallel chips in module 1, convert the temperature calibration current into a current ratio, and then plot a cluster of voltage-temperature curves based on the specific test current (no less than two) under different current ratios.

[0013] Step 5: Apply normal operating current and specific test current (no less than two) to module 1. After the operation is stable, disconnect the operating current and obtain the on-state voltage drop of module 1 under the specific test current (no less than two).

[0014] Step 6: Based on the on-state voltage drop of the specific test current (no less than two) in Module 1, calibrate the voltage-temperature curve clusters under different current ratios, obtain the corresponding current ratio and temperature value, and plot the current ratio-temperature curves under specific currents (no less than two).

[0015] Step 7: Determine the peak junction temperature of the module under test and the corresponding current percentage based on the intersection of the current percentage-temperature curves under different specific test currents (no less than two).

[0016] Without measuring the electrical parameters of each chip in the module under test 1, the highest chip junction temperature of module 1, i.e. the peak junction temperature, can be obtained based on the on-state voltage drop of module 1 under a specific current (no less than two).

[0017] In the device heating described in step one, discrete devices are heated by being placed in parallel on a temperature chamber or temperature control platform 3 using a parallel test fixture 2, while multi-chip modules are heated by being placed directly on a temperature chamber or temperature control platform 3.

[0018] The temperature calibration current mentioned in step two is the small test current of module 1 and is also the total current of the main circuit of module 1. Since the temperature calibration current is small and the power consumption is low, the self-temperature rise of the device can be ignored.

[0019] The specific conversion formula for converting the temperature calibration current into a current ratio based on the specific test current (at least two) and the number of parallel modules 1, as described in step four, is as follows:

[0020]

[0021] The current percentage is P, and the temperature calibration current is I. A The specific test current is I. B The number of parallel devices is N.

[0022] The method for obtaining the current percentage-temperature curve under specific currents (no less than two) described in step six is ​​as follows: Substitute the on-state voltage drop value of module 1 measured under specific current into the voltage-temperature curve cluster corresponding to different current percentages for each specific test current to obtain a series of temperature values ​​under different current percentages for each specific test current, and then plot the fitted current percentage-temperature change curve.

[0023] The beneficial effects of the present invention are: the equipment and operation of the method described in the present invention are simple and convenient. Based on the mature small current voltage drop method, the peak junction temperature measurement of parallel devices or modules can be realized without adding additional equipment. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the testing device involved in the present invention. In the figure: 1-parallel chip, 2-parallel test fixture, 3-temperature chamber or constant temperature platform, 4-test source meter;

[0025] Figure 2 This is a flowchart of the method involved in the present invention;

[0026] Figure 3 A three-dimensional scatter plot of temperature-calibration current-on-state voltage drop;

[0027] Figure 4 A set of temperature-voltage calibration curves for the current ratio under a 10mA test current;

[0028] Figure 5 The intersection of the current percentage and temperature curves under 10mA and 20mA test currents; Detailed Implementation

[0029] The present invention will now be described in more detail with reference to the accompanying drawings and specific embodiments.

[0030] Taking parallel connection of discrete IGBT devices as an example, the testing device involved in this invention is as follows: Figure 1 As shown. The setup includes IGBT device 1, parallel test fixture 2, temperature chamber 3, and test source meter 4. The IGBT device 1 under test consists of two IKW30N60H3 insulated-gate bipolar transistors (IGBTs), packaged in a TO-247 package, with a maximum operating voltage of 600V and a maximum operating current of 30A. Temperature chamber 3 is a Despatch 900 series. Test source meter 4 uses a Keysight B1505A power device analyzer and a power source meter.

[0031] The flowchart of the method involved in this invention is as follows: Figure 2 As shown, it includes the following steps:

[0032] Step 1: Insert the two IGBTs under test 1 into the parallel test fixture, place them in the temperature chamber, and connect the three parallel terminals of the devices on the parallel test fixture to the corresponding test ports of the B1505A device through high-temperature wires. Heat the parallel devices using the temperature chamber, starting at 30℃ and increasing by 5℃ each time, i.e., the test temperatures are 30℃, 35℃, ..., 120℃.

[0033] Step 2: When the temperature chamber reaches the set temperature of 30℃ and stabilizes for 10 minutes, it is assumed that the parallel devices are at the same temperature as the temperature chamber. A fixed grid voltage V is then provided using B1505A. GE =15V, keeping the device gate on, and providing a continuous calibration temperature current I in 100µA steps with a test range of 0-50mA. A The on-state voltage drop V corresponding to different calibration currents at this temperature was obtained. CE ;

[0034] Step 3: Raise the temperature of the chamber by 5°C. Once the set value is reached, repeat Step 2 to obtain the calibration current I at 35°C, 40°C, ..., 120°C.A The corresponding on-state voltage drop V CE Finally, a three-dimensional database of calibration current-temperature-on-voltage drop was obtained.

[0035] Step 4: Set the test current I B1 =10mA,I B2 =20mA. Based on the current percentage conversion formula, a total of 100 temperature-on voltage drop curves with current percentages of 1%, 2%, ..., 100% were obtained for test currents of 10mA and 20mA respectively.

[0036] Step 5: Using a power source meter, provide a continuous operating current ICE of 40A for the parallel devices, and simultaneously provide a continuous test current of 10mA using the B1505A. Once the devices are operating stably, disconnect the power supply and use the B1505A to measure the forward voltage drop V of the parallel devices at 10mA. CE1 Repeat the above operation to obtain the on-state voltage drop V of the parallel devices at 20mA. CE2 ;

[0037] Step 6: Obtain the on-state voltage drop V corresponding to the 10mA and 20mA test currents. CE1 and V CE2 Substituting these values ​​into their respective temperature-on-voltage drop curve clusters, we obtain the current percentage-temperature curves for 10mA and 20mA, with current percentages ranging from 1% to 100%.

[0038] Step 7: Finally, based on the intersection of the current percentage-temperature curves at test currents of 10mA and 20mA with current percentages ranging from 1% to 100%, the peak junction temperature of the IGBT dual-transistor parallel device and the current percentage of the high-temperature chip at this time can be obtained.

Claims

1. A non-destructive testing method for the peak junction temperature of chips within a multi-chip parallel package module, the apparatus for implementing the method comprising a multi-chip parallel switch module under test (1), a parallel test fixture (2), a temperature chamber or temperature control platform (3), and a test source meter (4); wherein the temperature chamber or temperature control platform (3) is used to heat the module (1), and the test source meter (4) is used to apply different currents to the multi-chip parallel switch module under test (1) and measure the on-state voltage drop; characterized in that, The testing method includes the following steps: Step 1: Place the multi-chip parallel switch module (1) under test on the parallel test fixture (2), and then place the multi-chip parallel switch module (1) under test on the temperature chamber or temperature control platform (3) to heat the multi-chip parallel switch module (1) under test. Step 2: Set the initial temperature of the temperature chamber or temperature control platform (3) so that the temperature of the multi-chip parallel switch module (1) under test is stable at the set temperature of the temperature chamber or temperature control platform (3). After the temperature is stable, apply a calibration current in a certain step size using the test source meter (4) to test the on-state voltage drop of the multi-chip parallel switch module (1) under different calibration currents. Step 3: Change the temperature of the temperature chamber or temperature control platform (3) in a certain step size, repeat the temperature calibration current test in step 2, and measure the on-state voltage drop of the multi-chip parallel switch module (1) under different temperatures and temperature calibration currents. Step 4: Based on the specific test current and the number of parallel chips in the multi-chip parallel switch module (1) under test, convert the temperature calibration current into a current ratio, and then plot a cluster of voltage-temperature curves based on different current ratios of the specific test current. Step 5: Apply a normal operating current and a specific test current to the tested multi-chip parallel switch module (1). After the operation is stable, disconnect the operating current and obtain the on-state voltage drop of the tested multi-chip parallel switch module (1) under the specific test current. Step 6: Based on the on-state voltage drop of the multi-chip parallel switch module (1) under test with a specific test current, calibrate the voltage-temperature curve cluster under different current ratios, obtain the corresponding current ratio and temperature value, and draw the current ratio-temperature curve under a specific current. Step 7: Determine the peak junction temperature and corresponding current ratio of the tested multi-chip parallel switch module (1) based on the intersection of the current ratio-temperature curves under different specific test currents.

2. The non-destructive testing method for the peak junction temperature of chips within a multi-chip parallel packaging module according to claim 1, characterized in that, Without measuring the electrical parameters of each chip in the multi-chip parallel switch module (1) under test, the highest chip junction temperature, i.e. peak junction temperature, of the multi-chip parallel switch module (1) under test can be obtained based on the on-state voltage drop of the multi-chip parallel switch module (1) under a specific current.

3. The non-destructive testing method for the peak junction temperature of chips within a multi-chip parallel packaging module according to claim 1, characterized in that, In the heating of the multi-chip parallel switch module under test described in step one, discrete devices are heated by being placed in parallel on the temperature chamber or temperature control platform (3) through the parallel test fixture (2), while multi-chip modules are heated by being placed directly on the temperature chamber or temperature control platform (3).

4. The non-destructive testing method for the peak junction temperature of chips within a multi-chip parallel packaging module according to claim 1, characterized in that, The temperature calibration current mentioned in step two is a small current that does not cause the tested multi-chip parallel switch module (1) to generate a temperature rise. It is also the total current of the main circuit of the tested multi-chip parallel switch module (1). Since the temperature calibration current is small and the power consumption is low, the tested multi-chip parallel switch module is prevented from generating a temperature rise.

5. The non-destructive testing method for the peak junction temperature of chips within a multi-chip parallel packaging module according to claim 1, characterized in that, The specific conversion formula for converting the temperature calibration current into a current ratio based on the specific test current and the number of chips in the multi-chip parallel switch module (1) under test (1) is as follows: ； The current percentage is P, and the temperature calibration current is I. A The specific test current is I. B The number of parallel-connected multi-chip parallel switch modules under test is N.

6. The non-destructive testing method for the peak junction temperature of chips within a multi-chip parallel packaging module according to claim 1, characterized in that, The method for obtaining the current percentage-temperature curve under a specific current in step six is ​​as follows: Substitute the on-state voltage drop of the multi-chip parallel switch module (1) measured under a specific current into the voltage-temperature curve cluster corresponding to different current percentages for each specific test current to obtain a series of temperature values ​​under different current percentages for each specific test current, and then plot the fitted current percentage-temperature change curve.

7. The non-destructive testing method for the peak junction temperature of chips within a multi-chip parallel package module according to claim 1, characterized in that, There shall be no fewer than two test currents; there shall be no fewer than two specific currents.

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