Information processing device and information processing device control method

Abstract

The present invention relates to an information processing device and a control method of the information processing device. The device includes: a non-volatile semiconductor storage device storing identification information and first setting information related to an output signal; a memory for holding the identification information of the non-volatile semiconductor storage device and setting information related to the output signal associated with the identification information of the non-volatile semiconductor storage device, the identification information including the identification information of the non-volatile semiconductor storage device, and the setting information including at least second setting information related to the output signal; and a processor for acquiring the identification information of the non-volatile semiconductor storage device.

Description

Technical Field

[0001] Aspects of the embodiments relate to a technique for generating an optimal signal waveform by optimizing a slew rate of a signal waveform output from a nonvolatile memory. Background Art

[0002] In recent years, a main printed circuit board (hereinafter referred to as a main board) built into an information processing device such as a personal computer (PC) is designed to be connected to a printed circuit board (hereinafter referred to as a "board") in various types of printed circuit boards via a connector or a cable in various cases. For example, a peripheral component interconnect standard (PCIe) card slot or a dual in-line memory module (DIMM) connector can be used for such a connection. This allows the end user to realize a desired function by connecting a desired board (an integrated circuit (IC) mounted on the board) to the main board.

[0003] In this case, since the end user connects a desired board to the main board, when electrically connecting to the IC mounted on the main board, it is unknown what electrical characteristics the mounted IC has.

[0004] Generally, various vendors have designed and manufactured ICs in accordance with various standards such as the Joint Electronic Engineering Design Development Council (JEDEC), etc. However, electrical characteristics of ICs of each vendor or each product model are slightly different.

[0005] In other words, the slew rate of a signal waveform (the amount of potential change per unit time of a certain signal) may differ depending on conditions such as the output signal driving capability of an IC and a wiring pattern.

[0006] For example, international publication WO2012 / 095980 discusses a memory controller including a register configured to adjust the slew rate of an address line in a stepwise manner. This technique can accurately communicate with any DIMM having different address line topologies.

[0007] In the technology discussed in International Publication WO2012 / 095980, the slew rate of the address line is adjusted based on the type of DIMM (e.g., unbuffered dual in-line memory module (UDIMM) or registered dual in-line memory (RDIMM)). However, the technology does not involve adjustment of the slew rate of the data signal output from at least the IC. Therefore, due to different electrical characteristics of ICs from various suppliers or product models, this may cause a change in the slew rate of the output signal waveform.

[0008] There may be a case where a main board on which a central processing unit (CPU) is mounted is connected to a different board on which a nonvolatile semiconductor memory is mounted. In this case, if the driving capability for setting the slew rate is in an initial state, the slew rate of the output signal waveform may vary depending on the vendor or product model of the nonvolatile semiconductor memory mounted on the different boards. Depending on the degree of variation in the slew rate, it may not be possible to accurately sample the signal waveform using the reference clock output from the main board on which the CPU is mounted, and thus normal communication may not be achieved.

[0009] The present invention aims to suppress variations in the slew rate of a signal waveform output from a nonvolatile semiconductor memory regardless of device information related to the nonvolatile semiconductor memory arranged on a different board. Summary of the invention

[0010] According to a typical embodiment of the present invention, an information processing device includes: a non-volatile semiconductor storage device, which stores identification information and first setting information related to an output signal; a memory, which is configured to maintain identification information of multiple non-volatile semiconductor storage devices and setting information related to the output signal associated with the identification information of the multiple non-volatile semiconductor storage devices, the identification information at least includes the identification information of the non-volatile semiconductor storage device, and the setting information at least includes second setting information related to the output signal; and a processor, which is configured to obtain the identification information of the non-volatile semiconductor storage device, wherein the processor is configured to obtain the second setting information based on the obtained identification information, and wherein the processor is configured to change the first setting information of the non-volatile semiconductor storage device based on the second setting information.

[0011] According to a typical embodiment of the present invention, a control method for an information processing device includes a processor and a non-volatile semiconductor storage device for storing identification information and first setting information related to an output signal, the control method including: acquiring identification information of the non-volatile semiconductor storage device; based on the acquired identification information, acquiring second setting information related to the output signal from a memory configured to maintain identification information of multiple non-volatile semiconductor storage devices and setting information related to the output signal associated with the identification information, the identification information including at least the identification information of the non-volatile semiconductor storage device, the setting information including at least the second setting information; and changing the first setting information of the non-volatile semiconductor storage device based on the second setting information.

[0012] Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram showing a plurality of printed circuit boards connected to each other.

[0014] Figure 2 is a conceptual diagram illustrating a communication error caused by a difference in electrical characteristics between nonvolatile memories.

[0015] Figure 3 is a block diagram showing the hardware configuration of the image forming apparatus.

[0016] Figure 4 is a block diagram illustrating a principle of setting an output signal driving capability of an embedded multimedia card (eMMC).

[0017] Figure 5 Management information including a product name and an output signal driving capability setting value of a nonvolatile memory is shown.

[0018] Figure 6 is a flow chart for setting the output signal drive capability.

[0019] Figure 7 This is a flow chart for changing the output signal driving capability when the nonvolatile memory is used.

[0020] Figure 8 is a conceptual diagram showing improved signal waveforms and the resulting prevention of communication errors. DETAILED DESCRIPTION

[0021] Typical embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following typical embodiments are not intended to limit the present invention according to the claims, and all combinations of features described in the various typical embodiments are not necessarily necessary structures for the solution of the present invention. In the following typical embodiments, an image forming device is exemplified as an information processing device.

[0022] According to the first exemplary embodiment, a plurality of boards can be connected. Figure 1 A structure composed of a board 10 as a main board and a board 11 connected to each other is shown.

[0023] like Figure 1 As shown, a board 10 including a master device is connected to a board 11 including a slave device so that a connector 20 and a connector 21 are fitted together. The connector 20 is mounted on the surface of the board 10, and the connector 21 is mounted on the surface of the board 11. The connectors 20 and 21 allow a plurality of signals to pass through. The board 10 is fastened to the board 11 using a spacer 22 and a screw 23 each made of metal.

[0024] The board 10 has an integrated circuit (IC) 30 mounted thereon, and the board 11 has an IC 31 mounted thereon. The IC 30 communicates with the IC 31 via a plurality of signal lines 40. In the present exemplary embodiment, the IC 30 corresponds to a master device, and the IC 31 corresponds to a slave device.

[0025] The signal line 40 allows data signals, clock signals, and command signals to pass through. The signal line 40 establishes a connection between the board 10 and the board 11 via the connector 20 and the connector 21. Each line in the signal line 40 has a specific length on the board 10 and the board 11. Since the boards 10 and 11 are separately provided, the boards are interchangeable.

[0026] This board structure realizes the desired function by connecting boards including ICs capable of realizing the desired function. This board structure also has the following advantages: for example, if IC 30 fails, board 10 is detached from board 11, and then a new board 10 (a board with a normal IC 30 mounted thereon) is connected to board 11. Therefore, the information processing device becomes usable again.

[0027] In the case of designing a board for information processing equipment such as a PC, one of different kinds of ICs having the same function as IC 31 can be used. In this case, parameters such as wiring length and resistance of the signal line mounted on the board 11 on which the slave device is mounted are not changed.

[0028] For example, in a case where the cost of a currently used IC becomes high, replacing the IC with another IC manufactured by a different supplier can reduce costs or achieve a stable business continuity plan (BCP).

[0029] As described above, the electrical characteristics of IC 31 are designed to comply with given standards. However, the electrical characteristics may differ for each vendor or for each product. When different kinds of ICs are used without changing the signal line lengths and circuit constants of boards 10 and 11 for each characteristic of IC 31, differences in electrical characteristics depending on the device (IC 31) may change the signal waveform, thereby causing communication errors.

[0030] Reference Figure 2 Give a detailed description of the problem. Figure 2 The concept of a change in slew rate due to a difference in electrical characteristics between nonvolatile memories and a communication error caused by the change is shown.

[0031] exist Figure 2 It is assumed in FIG. 1 that three devices (device A, device B, and device C) are each prepared as IC 31. IC 31 transmits a bit string 0b011 to IC 30.

[0032] It is also assumed that IC 31 has an initialized output signal driving capability (ie, an initialized slew rate). Each device as IC 31 is, for example, an embedded MultiMediaCard (eMMC), which is a nonvolatile semiconductor memory described below. IC 30 is a central processing unit (CPU).

[0033] Although devices A, B and C have Figure 2 , but device C, for example, has a smaller slew rate than devices A and B. Figure 2 As shown, IC 30 outputs a reference clock to IC 31 .

[0034] At time T0, the device A, the device B, and the device C each output a low level. At time T1, in the case of the device A and the device B, when the IC 30 as the master device samples the bit string, the signals output from the device A and the device B have changed from a low level to a high level. However, with respect to the device C, when the IC 30 as the master device samples the bit string, the signal output from the device C has a low level. At time T2, the device A, the device B, and the device C each have a high level.

[0035] like Figure 2 As shown, the IC 30 as the master correctly interprets the bit string as 0b011 in the case of using the device A and the device B, but erroneously interprets the bit string as 0b001 in the case of using the device C.

[0036] The reasons are as follows. Figure 2 As shown, the signal output from the slave device C makes a low-to-high transition at the time T2 when the IC 30 as the master device samples the bit string. As a result, the IC 30 samples the bit string as a value below the threshold. At the time T2, the master device thus interprets the bit string as 0b001, where "1" is incorrectly interpreted as "0". In other words, the small gradient of the waveform (low to high, or high to low) during the transition of the signal output from the slave device C increases the possibility that the host will incorrectly interpret the signal.

[0037] In particular, in the case where IC 30 communicates with IC 31 in the range of several hundreds of MHz to several GHz, timing control of picosecond (ps) level is required for the clock signal. Therefore, the difference in gradient between slew rates may cause communication errors.

[0038] Now refer to Figure 3 A hardware configuration according to the present exemplary embodiment is described.

[0039] The image forming apparatus 100 includes a nonvolatile memory 101, a CPU 102, a volatile memory 103, a network communication control unit 104, an image processing unit 105, a volatile memory 106, an image reading unit 107, and an image forming unit 108. In the present exemplary embodiment, it is assumed that the CPU 102 corresponds to Figure 1 The IC 30 shown in FIG. 1 and the nonvolatile memory 101 correspond to Figure 1 The image forming apparatus 100 includes an IC 31 shown in FIG. Figure 1 Connect the two boards in the same manner as shown.

[0040] The nonvolatile memory 101 has a characteristic of being able to retain data even when the power is turned off. In the present exemplary embodiment, the nonvolatile memory 101 is an eMMC. The nonvolatile memory 101 is connected to the CPU 102 via four buses, and the CPU 102 is configured to perform various information processing in the image forming apparatus 100. One of the buses feeds a clock signal 1 from the CPU 102 as a master device to the nonvolatile memory 101.

[0041] eMMC is standardized to support communication at multiple clock frequencies. In normal operation, clock signal 1 is used for the reference clock in communication. In contrast, eMMC that supports a communication mode called HS400 needs to output a reference clock to the master device that allows the master device to sample data. The reference clock used in this case is clock signal 2. eMMC is standardized to exchange command signals and data signals with the master device. The command signal is used by the master device to send a request to the slave device, and is also used for the slave device to reply to the reception of the request to the master device. Then, the predetermined data is output as the data signal.

[0042] A specific description of the configuration of the eMMC will now be given. The eMMC has an area called a card identification (CID) register, an area called a card specific data (CSD) register, and an area called an extended card specific data (EXT_CSD) register.

[0043] The CID register stores basic information (hereinafter, CID information) including a manufacturer identification (ID) and a product name.

[0044] The CSD register stores information (hereinafter, CSD information) including a maximum frequency of a clock supported by the nonvolatile memory 101 and a maximum block guide length of a clock read by the nonvolatile memory 101 .

[0045] The EXT_CSD register has, for example, a register field called the DEVICE_TYPE field and a register field called the 8-bit HS_TIMING field. The transfer modes selectable in these register fields are named with a combination of a numerical value representing the transfer frequency and an alphabet representing the sampling timing. For example, in DDR50 mode (DDR: an abbreviation for "double data rate"), the master device samples data at both the rising and falling edges of the clock and operates at a clock frequency of 50 MHz. The clock frequency is not limited to 50 MHz as long as it falls within the range specified by the Joint Electronic Engineering Design Development Council (JEDEC).

[0046] The HS_TIMING field has an upper 4-bit drive strength region and a lower 4-bit timing interface region.

[0047] The timing interface area stores information indicating the currently set transfer mode. The drive strength area stores information about the current output signal drive capability setting value. Specifically, the drive capability setting value refers to information for setting the output impedance measured from the non-volatile memory side. The setting value can change the output signal drive capability.

[0048] When the eMMC receives a predetermined command signal and a predetermined data signal from the host device, the eMMC accesses the target register to set the received data signal to the register.

[0049] Reference Figure 4 A description is given of the principle of setting the output signal driving capability of the eMMC. Figure 4 The internal structure of the nonvolatile memory 101 is shown in a simplified manner.

[0050] The nonvolatile memory 101 includes a NAND flash memory 200. When the nonvolatile memory 101 receives a read request from the CPU 102 as a master device, the memory controller 201 reads data from the NAND flash memory 200 and saves the data in a cache memory (not shown) included in the memory controller 201. The memory controller 201 sequentially transmits the data held in the cache memory to the physical layer (PHY) 202.

[0051] A high-side field effect transistor (FET) 203, a low-side FET 204, and an impedance group 205 are configured on the PHY 202. When the high-side FET 203 is turned on, current flows from the power supply voltage of the PHY 202 into the output signal, causing the output signal to change from a low level to a high level. When the low-side FET 204 is turned on, current flows from the output signal portion into the ground terminal, causing the output signal to change from a high level to a low level.

[0052] The impedance group 205 includes an impedance Z1, an impedance Z2, and an impedance Z3 having different impedance values ​​from each other. One of the impedances Z1 to Z3 is selected based on the above-mentioned register setting. In the present exemplary embodiment, the impedance Z1 has an impedance value greater than the impedance value of the impedance Z2, and the impedance Z2 has an impedance value greater than the impedance value of the impedance Z3 (Z1>Z2>Z3).

[0053] When impedance Z1 is set to have a larger impedance value than impedances Z2 and Z3, a small amount of current flows from the power supply voltage of PHY 202, and a small amount of current flows into the ground terminal. In other words, the amount of energy appearing on the output signal decreases, and thus the slew rate decreases.

[0054] When impedance Z3 is set to have a smaller impedance value than impedances Z1 and Z2, a large amount of current flows from the power supply voltage of PHY 202 and a large amount of current flows into the ground terminal. In other words, the amount of energy appearing on the output signal increases, and thus the slew rate increases.

[0055] The change in driving capability caused by register setting involves clock signal 2 (frequency setting in transfer mode), command signal and data signal. Although the command signal and data signal are each on a bidirectional bus, the driving capability of the signal output from the host device to the eMMC does not change.

[0056] The nonvolatile memory 101 stores program data such as an operating system (OS) for controlling the image forming apparatus 100 .

[0057] The non-volatile memory 101 also stores Figure 5 Management information associating a product name with an output signal drive capability setting value is shown. The output signal drive capability setting value is associated with the product name to minimize the variation of the output waveform from the eMMC due to the difference in electrical characteristics of each vendor or each product model.

[0058] This management information can be updated by, for example, a service engineer. In the present exemplary embodiment, the drive capability setting value is associated with the product name. Alternatively, the drive capability setting value may be associated with any information capable of identifying the slave device.

[0059] The CPU 102 loads the program data stored in the nonvolatile memory 101 onto the volatile memory 103, and sequentially executes processing according to the operation of the program counter (not shown) of the CPU 102. The program data includes driver software for controlling the nonvolatile memory 101. In the present exemplary embodiment, the driver software is referred to as an eMMC driver. The eMMC driver initializes the bus between the nonvolatile memory 101 and the CPU 102, issues a read command and a write command to the nonvolatile memory 101, and sends data to the nonvolatile memory 101.

[0060] In the present exemplary embodiment, the eMMC driver reads the product name of the nonvolatile memory 101 when initializing the bus. The CPU 102 has the following functions: Figure 5 The management information shown in FIG. 1 is used to set the drive capability setting value associated with the product name in the register of the nonvolatile memory 101. Figure 6 Describes the details of the feature.

[0061] In addition to control of the eMMC, the CPU 102 has, for example, a function for controlling power supply to the image forming apparatus 100 and a function for transmitting page description language (PDL) data received from the network communication control unit 104 to the image processing unit 105 .

[0062] The volatile memory 103 is a dynamic random access memory (DRAM) into which the CPU 102 loads program data stored in the nonvolatile memory 101. The CPU 102 uses the volatile memory 103 as a working memory.

[0063] The network communication control unit 104 communicates with an external device (not shown) according to the Transmission Control Protocol / Internet Protocol (TCP / IP) suite to receive, for example, PDL data. In the present exemplary embodiment, it is assumed that the image forming apparatus 100 is connected to the external device via an Ethernet cable.

[0064] The image processing unit 105 receives image data from the image reading unit 107, and performs image processing such as packaging, compression, and rotation on the received image data. The image processing unit 105 includes a sub-CPU (not shown), and uses a volatile memory 106 as a working memory in image processing. The image processing unit 105 sends the image-processed data to the image forming unit 108. The image forming unit 108 forms a desired image on a paper sheet using a photoconductor and toner in the image forming apparatus 100.

[0065] Now refer to Figure 6 The following describes the flow of processing performed by the CPU 102 for changing the output signal driving capability of the nonvolatile memory 101. Figure 6 Flowchart shown.

[0066] In the following description, expressions such as CMDx and Rx are used for the eMMC communication protocol specified by JEDEC. CMDx represents a command output by CPU 102 to non-volatile memory 101. Rx represents a response output by non-volatile memory 101 to CPU 102. CMDx and Rx are sent via a command signal bus. Rx is only a response uniquely determined based on the received CMDx, so its description will not be given. After the exchange of CMDx and Rx, the required data is output as a data signal.

[0067] After the image forming apparatus 100 is turned on, the flowchart starts. In step S1000, the CPU 102 sets the clock signal 1 input to the nonvolatile memory 101 to a frequency of 400 kHz or less, and starts a process for initializing the bus. In step S1001, the CPU 102 sends CMD1 to the nonvolatile memory 101. The CPU 102 sends CMD1 to request transmission of information related to the standard of the nonvolatile memory 101. Specifically, the CPU 102 requests transmission of information on the power supply voltage range in which the nonvolatile memory 101 can operate and information for determining whether the nonvolatile memory 101 is in a busy state.

[0068] In step S1002 after sending CMD1 , the CPU 102 waits for reception of R3 as a response to CMD1 from the nonvolatile memory 101 .

[0069] When CPU 102 receives R3 ("Yes" in step S1002), the process proceeds to step S1003. In step S1003, CPU 102 receives data from nonvolatile memory 101. CPU 102 determines whether an operation condition register (OCR) busy bit (hereinafter, referred to as OCR bit) in the received data is "0". The OCR bit indicates whether nonvolatile memory 101 is in a busy state. OCR bit "1" indicates that nonvolatile memory 101 is in a busy state. OCR bit "0" indicates that nonvolatile memory 101 is in an idle state.

[0070] When the OCR bit is not "0" (i.e., when the OCR bit is "1") ("No" in step S1003), the nonvolatile memory 101 is processing (i.e., the nonvolatile memory 101 is busy), and thus the process cannot proceed to step S1004 but returns to step S1002. In step S1002, the CPU 102 waits for the OCR bit of R3 to become "0". When the CPU 102 determines that the OCR bit is "0" ("Yes" in step S1003), the process proceeds to step S1004.

[0071] In step S1004, the CPU 102 determines whether the nonvolatile memory 101 is a slave device capable of communicating with the CPU 102 based on the data obtained based on CMD1. Specifically, for example, the CPU 102 determines whether the nonvolatile memory 101 supports the power supply voltage supported by the CPU 102.

[0072] If the CPU 102 receives a setting value that invalidates communication from the nonvolatile memory 101 (No in step S1004), the process proceeds to step S1006. In step S1006, the CPU 102 stops supplying power to the bus (PHY 202) and performs error processing. When the CPU 102 determines that the CPU 102 can communicate with the nonvolatile memory 101 (Yes in step S1004), the process proceeds to step S1005.

[0073] In step S1005, the CPU 102 sends CMD2 to the nonvolatile memory 101. The CPU 102 sends CMD2 to acquire CID information (such as the manufacturer ID and product name of the nonvolatile memory 101) from the nonvolatile memory 101 as basic information.

[0074] After sending CMD2, the CPU 102 receives R2 as a response to CMD2 from the nonvolatile memory 101. In step S1007, the CPU 102 waits for complete transmission of CID information from the nonvolatile memory 101. If the CPU 102 receives all CID information (YES in step S1007), the process proceeds to step S1008.

[0075] In step S1008, the CPU 102 extracts the product name from the received CID information. The product name is stored in, for example, bit numbers 103 to 56 of the CID register. The value of the product name indicates one of the device A, device B, and device C stored in the management information for setting the drive capability.

[0076] In step S1009, the CPU 102 sends CMD3 to the nonvolatile memory 101, sets the relative card address, and shifts the nonvolatile memory 101 to the standby state. The setting of the relative card address means that the CPU 102 sets how to use the address in the nonvolatile memory 101.

[0077] In step S1010, the CPU 102 sends CMD9 to the nonvolatile memory 101 to acquire CSD information including the maximum frequency of the clock supported by the nonvolatile memory 101 and the maximum block lead length of the clock read by the nonvolatile memory 101. When the CPU 102 completely receives R2 and the CSD information as a response to CMD2 (YES in step S1011), the process proceeds to step S1012.

[0078] In step S1012, the CPU 102 issues CMD7 to the nonvolatile memory 101. The CPU 102 issues CMD7 to shift the nonvolatile memory 101 in the standby state after shifting in step S1009 to the transfer state (data transferable state).

[0079] In step S1013, the CPU 102 sends CMD8 to the nonvolatile memory 101 to obtain the information stored in the EXT_CSD register. The CPU 102 extracts information about the DEVICE_TYPE field and the HS_TIMING field from the acquired EXT_CSD register information. The DEVICE_TYPE field stores the transfer mode information. The HS_TIMING field stores the current transfer mode information and the drive capability setting value. Then, the process proceeds to step S1014.

[0080] In step S1014, the CPU 102 sends CMD6 to the nonvolatile memory 101. The CPU 102 sends CMD6 to set a value of 0x1 in the timing interface in the HS_TIMING field of the EXT_CSD register. Thus, the CPU 102 changes the transfer mode of the nonvolatile memory 101 to a high-speed mode (clock frequency of 52 MHz or less).

[0081] The upper 4-bit drive strength area stores the default value of the drive capability setting value. The default value of the drive capability setting value is, for example, 0x0. The nonvolatile memory 101 is set in the same way for each vendor or each product model, but the performance is different from each other despite the same settings.

[0082] In step S1015, the CPU 102 sends CMD19 and CMD14 to the non-volatile memory 101. The CPU 102 sends CMD19 and CMD14 to execute a test sequence for setting the bus width of the data signal. The bus width of the data signal can be increased to up to 8 bits. The CPU 102 thus completes the initialization of the bus in the eMMC.

[0083] After the CPU 102 completes the setting of the bus width, the process proceeds to step S1016. In step S1016, the CPU 102 sends CMD16 to the nonvolatile memory 101 to determine the data size of the block as the data unit when reading and writing data. The data size is, for example, 512 bytes. The data size is set to be greater than or equal to the data size required for the management information. After sending CMD16, the CPU 102 waits for a reply R1 from the nonvolatile memory 101 (step S1017).

[0084] In step S1018, the CPU 102 issues CMD17 to read Figure 5 The address to be specified in step S1018 is the beginning address of the memory area storing the management information. The management information thus read is held in the volatile memory 103. After the CPU 102 issues CMD17, the process proceeds to step S1019 to determine whether R1 and the management information are received. If the CPU 102 completes the reception ("Yes" in step S1019), the process proceeds to step S1020.

[0085] In step S1020 , the CPU 102 compares the product name extracted in step S1008 and the output signal driving capability setting value extracted in step S1013 with the management information held in the volatile memory 103 in step S1019 .

[0086] In step S1020, if the product name and the drive capability setting value are equal Figure 5 If the product name and the drive capability setting value in the management information shown in FIG. 1020 are the same as those in FIG. 1021 (“YES” in step S1020), the process proceeds to step S1021. Figure 5 If the product name and the drive capability setting value in the management information shown are different (NO in step S1020 ), the process proceeds to step S1022 .

[0087] In step S1021, the CPU 102 does not need to change the output signal driving capability setting value. Thus, as described above, the CPU 102 sets the highest performance transfer mode among the transfer modes supported by the nonvolatile memory 101 in the lower 4-bit area of ​​the HS_TIMING field.

[0088] A specific description will be given of a typical case where the process proceeds to step S1021. In the present exemplary embodiment, for example, in a case where the product name extracted in step S1008 is device A, the drive capability setting value in the management information is equal to the drive capability setting value of the actual device. Specifically, since the default value of the nonvolatile memory 101 is 0x0, the output signal drive capability setting value extracted in step S1013 is 0x0. Figure 5 The output signal drive capability setting value (reference information) shown in is 0x0. Therefore, the CPU 102 determines in step S1020 that the product name and drive capability setting value are equal to the product name and drive capability setting value in the management information. Then, the process proceeds to step S1021.

[0089] In step S1022 , the CPU 102 sends CMD6 to the nonvolatile memory 101 to set (rewrite) reference information (eg, change the damping resistance value from 50Ω to 33Ω) in the upper 4-bit area of ​​the HS_TIMING field.

[0090] The CPU 102 obtains the highest performance transfer mode supported by the nonvolatile memory 101 from the device type extracted in step S1013. Thus, the CPU 102 sets the transfer mode in the lower 4-bit area of ​​the HS_TIMING field. For example, when the nonvolatile memory 101 supports the transfer mode HS200, the CPU 102 sets 0x2.

[0091] Next, a specific description will be given of a typical case where the process proceeds to step S1022. In the present exemplary embodiment, for example, in the case where the product name extracted in step S1008 is device C, the drive capability setting value in the management information is different from the drive capability setting value of the actual device. Specifically, since the default value of the nonvolatile memory 101 is 0x0, the output signal drive capability setting value extracted in step S1013 is 0x0. On the other hand, in Figure 5 1 is 0x1. Thus, the CPU 102 determines in step S1020 that the product name and the drive capability setting value are different from the product name and the drive capability setting value in the management information. Then, the process proceeds to step S1022. In step S1022, the CPU 102 overwrites 0x0 as the default setting value with 0x1 as the reference information.

[0092] Next, a description will be given of the reason why the management information is different from the default value and the reason why the management information is referred to. As described above, the nonvolatile memory 101 as devices A to C has the same default setting. Therefore, device C is equivalent to devices A and B in terms of the default value stored in the drive strength area. Under the same setting conditions, as described above, the waveform is different for each vendor or each product. Figure 2 As shown in FIG. 1 , for example, device C with default setting values ​​is smaller in slew rate than devices A and B. Such differences between devices are known in advance when designing the devices. In order to reduce the damping resistor value of device C by one level to increase the slew rate of the signal, Figure 5 Set 0x1 in the drive strength area of ​​the management information shown in . Figure 5 According to the management information shown, the driving capability setting value stored in the register in the nonvolatile memory 101 is changed to the driving capability setting value associated with the product name so that a desired driving capability setting value is set.

[0093] Reference Figure 8 A detailed description of the effect of improving the signal waveform is given in the conceptual diagram of FIG.

[0094] From Figure 8 The output signal waveform of device C shown on the left is equal to Figure 2 The output signal waveform is shown in FIG. Figure 2 As described above, in the case of device C, CPU 102 erroneously recognizes the bit string 0b011 as 0b001.

[0095] like Figure 8 As shown on the right side of FIG. 1 , for device C having a structure according to the present exemplary embodiment, CPU 102 refers to Figure 5 , and sets the drive capability setting value associated with the product name for the register in the nonvolatile memory 101. The nonvolatile memory 101 (device C) thus outputs a signal waveform with a large slew rate that can exceed the threshold at the rising timing of the reference clock. Thus, the CPU 102 correctly recognizes the bit string 0b011.

[0096] If a maximum value is set for the driving capability supported by the device (if the slew rate is always maximized), communication errors are reduced, but a phenomenon of overshoot or undershoot may cause damage to components due to exceeding the rating of the CPU 102 .

[0097] An increase in the driving capability may also result in an increase in the amount of noise emitted from the image forming apparatus 100. In other words, the driving capability setting value needs to be set according to the product name.

[0098] When the processing ends, normal activation of the nonvolatile memory 101 ends, and normal activation of the image processing apparatus is performed.

[0099] Next, refer to Figure 7 The illustrated flowchart gives a description of processing to be performed by the nonvolatile memory 101 . Figure 7 The processing shown in the flowchart of FIG. 1 is executed by the nonvolatile memory 101. Specifically, the processing is executed by a memory CPU included in the nonvolatile memory 101.

[0100] The nonvolatile memory 101 as a slave device is basically based on Figure 6 The slave CPU 102 receives commands as shown and sends responses and expected data.

[0101] In step S2000, the nonvolatile memory 101 waits for reception of CMD1 from the CPU 102. When the nonvolatile memory 101 receives CMD1 ("YES" in step S2000), the process proceeds to step S2001. In step S2001, the nonvolatile memory 101 sends R3 to the CPU 102 in response to CMD1. In step S2002, the nonvolatile memory 101 sends an OCR value storing information such as the power supply voltage range supported by the nonvolatile memory 101 to the CPU 102, and determines whether the transmission of the OCR value has been completed.

[0102] If the nonvolatile memory 101 has not sent the OCR value (No in step S2002), the process proceeds to step S2003. In step S2003, the nonvolatile memory 101 sets 1 for the OCR bit to continue sending the OCR value. When the nonvolatile memory 101 has sent the OCR value (Yes in step S2002), the process proceeds to step S2004. In step S2004, the nonvolatile memory 101 clears the OCR bit to 0 and notifies the CPU 102 of the completion of the sending.

[0103] In step S2005, the nonvolatile memory 101 waits for reception of CMD2. When the nonvolatile memory 101 receives CMD2 ("Yes" in step S2005), the process proceeds to step S2006. In step S2006, the nonvolatile memory 101 sends R2 to the CPU 102 in response to CMD2, and sends CID information. When the sending of R2 and CID information is completed, the process proceeds to step S2007.

[0104] In step S2007, the nonvolatile memory 101 waits for transmission of CMD3. If the nonvolatile memory 101 receives CMD3 ("Yes" in step S2007), the process proceeds to step S2008. In step S2008, the nonvolatile memory 101 changes the operation state of the nonvolatile memory 101 to the standby state. Then, the process proceeds to step S2009.

[0105] In step S2009 , the nonvolatile memory 101 waits for transmission of CMD 9 . If the nonvolatile memory 101 receives CMD 9 (YES in step S2009 ), the process proceeds to step S2010 . In step S2010 , the nonvolatile memory 101 transmits CSD information to the CPU 102 .

[0106] In step S2011, the nonvolatile memory 101 waits for transmission of CMD 7. If the nonvolatile memory 101 receives CMD 7 (YES in step S2011), the process proceeds to step S2012. In step S2012, the nonvolatile memory 101 changes the operation state of the nonvolatile memory 101 to the transmission state.

[0107] In step S2013 , the nonvolatile memory 101 waits for transmission of CMD 8 . If the nonvolatile memory 101 receives CMD 8 (YES in step S2013 ), the process proceeds to step S2014 . In step S2014 , the nonvolatile memory 101 transmits EXT_CSD information to the CPU 102 .

[0108] In step S2015, the nonvolatile memory 101 determines whether CMD6 is received and whether the setting value in the HS_TIMING field is designated by the data after CMD6. At this time, the clock frequency is set to 52 MHz or less in the same manner as described above.

[0109] In step S2016, the nonvolatile memory 101 waits for reception of CMD19 and CMD14. If the nonvolatile memory 101 receives CMD19 and CMD14 ("Yes" in step S2016), the process proceeds to step S2017. In step S2017, the nonvolatile memory 101 performs training for sequentially setting the data bus width according to the standard of eMMC. After step S2017, the process proceeds to step S2018.

[0110] In step S2018, the nonvolatile memory 101 determines whether CMD16 and information on the data size for each block have been received. If reception has been completed ("Yes" in step S2018), the process proceeds to step S2019. In step S2019, the nonvolatile memory 101 sends R1 to the CPU 102.

[0111] In step S2020, the nonvolatile memory 101 waits for reception of CMD17. When the nonvolatile memory 101 receives CMD17 ("Yes" in step S2020), the process proceeds to step S2021. In step S2021, the nonvolatile memory 101 sends data to the CPU 102 according to the data size for each block determined based on CMD16, when the address specified based on CMD17 is defined as the head address. The data sent to the CPU 102 is management information.

[0112] According to the present exemplary embodiment, the CPU 102 Figure 6 In steps S1016 to S1022 shown in FIG. 10, the output signal drive capability setting value and the transfer mode of the nonvolatile memory 101 are set; thus, the nonvolatile memory 101 waits for the reception of CMD6 in step S2022. If the nonvolatile memory 101 receives CMD6, the nonvolatile memory 101 changes the drive capability setting value and the transfer mode based on the subsequent data. The process ends therewith.

[0113] Figure 6 The processing and Figure 7 The illustrated processing enables initialization of the bus between the CPU 102 and the nonvolatile memory 101 , and change of the setting of the output signal driving capability according to the product name of the nonvolatile memory 101 .

[0114] Specifically, Figure 6 and 7 Each shows an initialization process. Figure 6 Steps S1016 to S1022 and Figure 7 Step S2022 corresponds to a change in the output signal driving capability according to the product name of the nonvolatile memory 101 .

[0115] With the above-described structure in which a plurality of boards are connected to each other, a signal waveform of an optimum slew rate is generated based on the electrical characteristics of the nonvolatile memory electrically connected to the CPU, whereby the structure ensures communication stability.

[0116] The present invention has been described by various examples and typical embodiments; however, the scope of the present invention is not limited to the specific description.

[0117] The present invention may also be embodied as a system or device receiving a program implementing one or more functions in the above exemplary embodiments via a network or from a storage medium, and then one or more processors in a computer of the system or device read and execute the program. The present invention may also be embodied in a circuit (such as an application specific integrated circuit (ASIC)) that implements one or more functions.

[0118] Other embodiments

[0119] The embodiments of the present invention may also be implemented by providing software (program) for performing the functions of the above-described embodiments to a system or device via a network or various storage media, and a computer or a central processing unit (CPU) or a microprocessing unit (MPU) of the system or device reads and executes the program.

[0120] While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims

1. An information processing device, comprising: a nonvolatile semiconductor memory device storing first device information and having a slew rate of an output signal adjustable by setting impedance; a memory configured to hold device information of a plurality of nonvolatile semiconductor memory devices and setting information of impedance associated with the device information related to each of the plurality of nonvolatile semiconductor memory devices, the device information held by the memory including at least the first device information, and the setting information including at least first setting information of the impedance associated with the first device information; image processing circuitry configured to process image data; as well as a processor configured to send the image data to the image processing circuit, Wherein, the processor is further configured to: setting a bus for communicating with the nonvolatile semiconductor storage device based on activation of the information processing apparatus; acquiring the first device information from the nonvolatile semiconductor storage device based on completion of setting of the bus; acquiring the first setting information of the impedance from the memory based on the first device information; and The first setting information is set for the nonvolatile semiconductor storage device.

2. The information processing device according to claim 1, in, The processor and the memory are mounted on a first board, and The nonvolatile semiconductor storage device is mounted on a second board that can be connected to the first board.

3. The information processing device according to claim 1, in, The processor acquires second setting information from the nonvolatile semiconductor storage device, and The processor changes the second setting information under the condition that the second setting information is different from the first setting information.

4. The information processing device according to claim 3, wherein: The processor determines whether the second setting information is different from the first setting information based on activation of the information processing device.

5. The information processing device according to claim 1, in, The processor acquires second setting information from the nonvolatile semiconductor storage device, and Wherein, the processor does not change the second setting information under the condition that the second setting information is equal to the first setting information.

6. The information processing device according to claim 5, wherein: Based on activation of the information processing apparatus, device information of the plurality of nonvolatile semiconductor storage devices and setting information of impedance associated with the device information about each of the plurality of nonvolatile semiconductor storage devices are read from the plurality of nonvolatile semiconductor storage devices and held in the memory.

7. The information processing device according to claim 6, wherein: The device information of the plurality of nonvolatile semiconductor storage devices and the setting information of the impedance associated with the device information about each of the plurality of nonvolatile semiconductor storage devices are updateable.

8. The information processing device according to claim 2, wherein: The setting information of impedance associated with the device information about each of the plurality of nonvolatile semiconductor storage devices is information for setting the impedance between the first board and the second board.

9. The information processing device according to claim 1, wherein: The device information held by the memory is a product name of the nonvolatile semiconductor storage device or a manufacturer identification of the nonvolatile semiconductor storage device.

10. The information processing device according to claim 1, in, The nonvolatile semiconductor memory device has a plurality of transfer modes that are different in frequency from each other, and The processor sets the nonvolatile semiconductor memory device to a transfer mode having the highest frequency among the plurality of transfer modes.

11. The information processing device according to claim 1, wherein: The process for starting the information processing apparatus is completed according to the completion of the setting of the nonvolatile semiconductor storage device by the processor.

12. The information processing device according to claim 1, wherein: The setting of the bus includes setting a default value of the setting information of the impedance to the nonvolatile semiconductor memory device, Wherein, the processor is further configured to: acquiring the first device information from the nonvolatile semiconductor storage device based on completion of setting of the default value; acquiring the first setting information of the impedance from the memory based on the first device information; and The default value is rewritten as the first setting information for the nonvolatile semiconductor storage device.

13. The information processing device according to any one of claims 1 to 12, wherein: The non-volatile semiconductor storage device is an embedded multimedia card.

14. A control method for an information processing device, the information processing device comprising an image processing circuit configured to process image data, a processor configured to send the image data to the image processing circuit, and a nonvolatile semiconductor memory device for storing first device information and having a slew rate of an output signal that can be adjusted by setting impedance, the control method comprising: setting a bus for communicating with the nonvolatile semiconductor storage device based on activation of the information processing apparatus; acquiring the first device information from the nonvolatile semiconductor storage device based on completion of setting of the bus; acquiring first setting information of the impedance from a memory based on the first device information, the memory being used to retain device information of a plurality of nonvolatile semiconductor memory devices and setting information of the impedance associated with the device information related to each of the plurality of nonvolatile semiconductor memory devices, the device information retained by the memory at least including the first device information, and the setting information at least including the first setting information of the impedance associated with the first device information; as well as The first setting information is set for the nonvolatile semiconductor storage device.

15. The control method according to claim 14, further comprising: acquiring second setting information from the nonvolatile semiconductor storage device; as well as The second setting information is changed under a condition that the second setting information is different from the first setting information.

16. The control method according to claim 14, further comprising: acquiring second setting information from the nonvolatile semiconductor storage device; as well as The second setting information is not changed under the condition that the second setting information is equal to the first setting information.

17. The control method according to claim 14, wherein: The device information held by the memory is a product name of the nonvolatile semiconductor storage device or a manufacturer identification of the nonvolatile semiconductor storage device.

18. The control method according to claim 14, wherein: The process for starting the information processing apparatus is completed according to the completion of the setting of the nonvolatile semiconductor storage device by the processor.

19. The control method according to claim 14, further comprising: The setting information of the nonvolatile semiconductor storage device is rewritten based on the first setting information.

Images