Memory device

Abstract

A memory device is provided. The memory device includes a plurality of memory cells each including a switching element and a data storage element having a phase change material, and each connected to one of a plurality of word lines and one of a plurality of bit lines; a decoder circuit configured to determine at least one of the plurality of memory cells as a selected memory cell; and a programming circuit configured to input a programming current to the selected memory cell to perform a programming operation, detect a hold voltage of the selected memory cell, and adjust a magnitude of the programming current based on the detected hold voltage. The selected memory cell is turned off when a voltage across the selected memory cell is lower than the hold voltage.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0131417, filed October 22, 2019, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The disclosure relates to a memory device, and more particularly, to a resistive memory device. BACKGROUND

[0003] A resistive memory device includes a phase change random access memory (PRAM), a resistive RAM (ReRAM), and a magnetic RAM (MRAM). Unlike a memory device that writes data by charging or discharging an electric charge, a resistive memory device uses a change in resistance to write or erase data. The resistance of a memory cell in a resistive memory device can be changed when a current is applied to the memory cell.

[0004] The application of the current can heat the memory cell until a material within the memory cell changes its state from a first state having a first resistance to a second state having a second resistance that is different. However, as the resistance of the memory cell increases, heat can not be generated sufficiently. Thus, a program operation can not be performed normally on the memory cell. In addition, as the resistance of the memory cell decreases, heat can be generated excessively. Thus, the endurance of the memory cell can decrease. SUMMARY

[0005] Exemplary embodiments of the inventive concept provide a memory device in which a distribution of memory cells is prevented from being enlarged in a program operation.

[0006] According to an exemplary embodiment of the inventive concept, a memory device includes a plurality of memory cells each including a switching element and a data storage element including a phase change material, and each connected to one of a plurality of word lines and one of a plurality of bit lines; a decoder circuit configured to determine at least one of the plurality of memory cells as a selected memory cell; and a program circuit configured to input a program current to the selected memory cell to perform a program operation, detect a hold voltage of the selected memory cell, and adjust a size of the program current based on the detected hold voltage. The selected memory cell is turned off when a voltage across the selected memory cell is lower than the hold voltage.

[0007] According to exemplary embodiments of the inventive concept, a memory device includes: a memory cell array including a plurality of memory cells disposed at intersections of a plurality of word lines and a plurality of bit lines; a decoder circuit configured to determine at least one of the plurality of memory cells as a selected memory cell; and a programming circuit configured to: input a programming current to the selected memory cell to perform a programming operation, detect a hold voltage of the selected memory cell, and adjust a size of the programming current based on the detected hold voltage. The hold voltage is a voltage that prevents the selected memory cell from turning off. The programming circuit detects the hold voltage of the selected memory cell during a pre-read period, and supplies the programming current having the size adjusted by the hold voltage of the selected memory cell to the selected memory cell during a programming period after the pre-read period.

[0008] According to exemplary embodiments of the inventive concept, a memory device includes: a memory cell array including a plurality of memory cells disposed at intersections of a plurality of word lines and a plurality of bit lines; a decoder circuit configured to determine at least one of the plurality of memory cells as a selected memory cell; and a programming circuit configured to: input a programming current to the selected memory cell to perform a programming operation, detect a hold voltage of the selected memory cell, and adjust a size of the programming current based on the detected hold voltage. The hold voltage is a voltage that prevents the selected memory cell from turning off. The decoder circuit supplies a bias voltage to a selected word line and a selected bit line connected to the selected memory cell to set the selected memory cell to an on state during a cell-on period. The programming circuit supplies a minimum current required for the selected memory cell to be maintained in the on state during a hold period after the cell-on period, detects a hold voltage of the selected memory cell during a programming period after the hold period, and supplies the programming current having the size adjusted by the hold voltage to the selected memory cell. BRIEF DESCRIPTION OF DRAWINGS

[0009] The embodiments of the present disclosure will be understood more clearly from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 and Figure 2 is a schematic block diagram of a memory device according to exemplary embodiments of the inventive concept.

[0011] Figure 3A and Figure 3B is a schematic block diagram of a memory cell array according to exemplary embodiments of the inventive concept.

[0012] Figure 4A and Figure 4B shows a structure of a memory cell included in a memory device according to exemplary embodiments of the inventive concept.

[0013] Figure 5A and Figure 5B A structure of a memory cell included in a memory device according to an example embodiment of the inventive concept is shown.

[0014] Figure 6 An operation of a memory device according to an example embodiment of the inventive concept is shown.

[0015] Figure 7 A programming operation of a memory device according to an example embodiment of the inventive concept is shown.

[0016] Figure 8A A variation in programming current dependent on resistance of a memory cell according to an example embodiment of the inventive concept is shown, Figure 8B Joule heat dependent on resistance of a memory cell according to an example embodiment of the inventive concept is shown.

[0017] Figure 9A A voltage-current plot of a memory cell in a programming operation of a memory device according to an example embodiment of the inventive concept is shown, Figure 9B A distribution of a memory cell dependent on resistance of a memory cell according to an example embodiment of the inventive concept is shown.

[0018] Figure 10 A memory device according to an example embodiment of the inventive concept is shown.

[0019] Figure 11A A programming operation of a memory device according to an example embodiment of the inventive concept is shown, Figure 11B A circuit diagram of a memory device according to an example embodiment of the inventive concept is shown. Figure 11C is Figure 11B a circuit diagram of a hold voltage detector in, Figure 11D A programming operation of a memory device according to an example embodiment of the inventive concept is shown.

[0020] Figure 12A and Figure 12B A programming operation of a memory device according to an example embodiment of the inventive concept is shown, Figure 12C A circuit diagram of a memory device according to an example embodiment of the inventive concept is shown.

[0021] Figure 13 A programming operation of a memory device according to an example embodiment of the inventive concept is shown.

[0022] Figure 14A and Figure 14B An example of a programming operation according to an example embodiment of the inventive concept is shown.

[0023] Figure 15A andFigure 15B An example of a program operation according to an example embodiment of the inventive concept is shown.

[0024] Figure 13 An example of a program operation of a memory device according to an example embodiment of the inventive concept is shown.

[0025] Figure 13 and Figure 14A An example of a program operation according to an example embodiment of the inventive concept is shown.

[0026] Figure 12A and Figure 14A An example of a program operation according to an example embodiment of the inventive concept is shown.

[0027] Figure 14B An example of a program operation according to an example embodiment is shown.

[0028] Figure 15A An example of a program operation according to an example embodiment is shown.

[0029] Figure 14A is a schematic block diagram of an electronic device including a memory device according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0030] Hereinafter, disclosed example embodiments will be described with reference to the accompanying drawings.

[0031] Figure 15A and Figure 15B is a schematic block diagram of a memory device according to an example embodiment of the inventive concept.

[0032] Referring to Figure 16 , a memory device 1 according to an example embodiment includes a bank area 2, a circuit area 3, and a pad area (or referred to as a pad area) 4. The pad area 4 can be an area in which a plurality of pads are formed to input and output control signals or data. The circuit area 3 can be an area in which various circuits required for the operation of the memory device 1 are formed. In the bank area 2, memory cell arrays each having a plurality of memory cells are formed. The memory cell arrays can be divided into a plurality of banks.

[0033] According to an example embodiment, each of a plurality of banks formed in the bank area 2 is divided into a plurality of areas. For example, at least a part of the plurality of areas can share a decoder circuit and / or a read / write circuit included in the circuit area 3.

[0034] The circuit region 3 can include a decoder circuit, a read / write circuit, and a control logic configured to control the decoder circuit and the read / write circuit. The decoder circuit can determine at least one of the plurality of memory cells formed in the memory cell array region 2 as a selected memory cell in response to an address, and the read / write circuit can read data from or write data to the selected memory cell.

[0035] Referring to Figure 17A The memory device 10 according to an exemplary embodiment of the inventive concept includes a memory controller 20 (e.g., control circuit) and a memory cell array 30. The memory controller 20 includes decoder circuits 21 and 22, a read / write circuit 23, and a control logic 24. The memory cell array 30 can include a plurality of memory cells. The decoder circuits 21 and 22 include a first decoder circuit 21 connected to the plurality of memory cells through a word line WL (or a plurality of word lines), and a second decoder circuit 22 connected to the plurality of memory cells through a bit line BL (or a plurality of bit lines). Operations of the first decoder circuit 21, the second decoder circuit 22, and the read / write circuit 23 can be controlled by the control logic 24. In one exemplary embodiment, the read / write circuit 23 includes a program circuit configured to write data to at least one selected memory cell designated by the first decoder circuit 21 and the second decoder circuit 22, and a read circuit configured to read data from the selected memory cell.

[0036] The plurality of memory cells included in the memory cell array 30 can have different levels of resistance from each other. When the read / write circuit 23 programs data to the selected memory cell, the memory device 10 supplies a program current to the selected memory cell. When the program current flows through the selected memory cell, depending on the resistance of the selected memory cell, the program operation can not be properly performed or durability can be reduced.

[0037] According to an exemplary embodiment of the inventive concept, when the read / write circuit 23 programs data to the selected memory cell, the memory device 10 determines the program current according to the resistance of the selected memory cell. Since the memory device 10 can supply different program currents to each memory cell according to the resistance of each selected memory cell, the memory device 10 can compensate for a variation in program characteristics according to the resistance of the selected memory cell.

[0038] Figure 17B and Figure 18A is a schematic block diagram of a memory cell array according to an exemplary embodiment of the inventive concept.

[0039] Referring to Figure 18B and Figure 16The memory cell array 30A according to an exemplary embodiment includes a plurality of memory cells MC. The memory cell array 30A can be used to implement Figure 16 The memory cell array 30. Multiple memory cells MC can be arranged at the intersection of bit line BL and word line WL. For example, each of the multiple memory cells MC can be connected to a single bit line BL and a single word line WL.

[0040] As an example, each of the plurality of memory cells MC may include a switching element SW and a data storage element VR. In one exemplary embodiment, the switching element SW may include at least one of a PN junction diode, a Schottky diode, and a bidirectional threshold switch (OTS). In one exemplary embodiment, the data storage element VR may be formed of a phase change material comprising a chalcogenide material or a superlattice. For example, the data storage element VR may include a phase change material capable of transitioning between an amorphous phase (or state) and a crystalline phase (or state) depending on heating time or heating temperature. The data storage element VR and the switching element SW may be connected in series with each other.

[0041] The memory controller 20 can write or erase data by changing the phase change material of the data storage element VR included in each of the plurality of memory cells MCs to an amorphous or crystalline phase via bit lines BL and word lines WL. In one exemplary embodiment, the memory controller 20 increases the resistance of the data storage element VR to write data by changing the phase change material of the data storage element VR included in the memory cell MC to an amorphous phase. In another exemplary embodiment, the memory controller 20 decreases the resistance of the data storage element VR to erase data by changing the phase change material of the data storage element VR included in the memory cell MC to a crystalline phase. The relationship between the resistance value of the data storage element VR and whether data is written can be defined in various ways according to other exemplary embodiments of the inventive concept. The memory controller 20 can perform a read operation to read data from the plurality of memory cells MCs by comparing a read voltage detected from the plurality of memory cells MCs with a reference voltage.

[0042] Reference Figure 17A One end of the data storage element VR is connected to the bit line of each of the multiple memory cells MC, and one end of the switching element SW is connected to the word line. In this case, Figure 17A Each of the multiple memory cells MC shown has a second orientation (or orientation).

[0043] Reference Figure 17B conduct Figure 14A The description, while focusing on and Figure 14B The differences.Figure 14A The memory cell array 30B includes multiple memory cells MC. Figure 14B The memory cell array 30 can be used Figure 17A This is implemented using a memory cell array 30B. (Refer to...) Figure 17B One end of the data storage element VR is connected to the word line, and one end of the switching element SW is connected to the bit line in each of the multiple memory cells MC. In this case... Figure 18A Each of the multiple memory cells MC shown has a first orientation.

[0044] Figure 18A The memory cell array 30 shown in the exemplary embodiment according to the inventive concept may include a plurality of memory cells formed on different layers. For example, the memory cell array 30 may include a first layer and a second layer stacked on top of each other. Memory cells included in the first layer may have a first orientation. Memory cells included in the second layer may have a second orientation. However, according to the exemplary embodiment, the orientation of the memory cells included in each of the first and second layers may be changed.

[0045] Figure 18B and Figure 15A The diagram illustrates the structure of a memory cell included in a memory device according to an exemplary embodiment of the inventive concept.

[0046] Reference Figure 15B A memory device 100A according to an exemplary embodiment of the inventive concept includes a first memory cell MC1 and a second memory cell MC2 disposed between a plurality of wires 101 to 103. The first memory cell MC1 and the second memory cell MC2 can operate as independent memory cells, respectively. As an example, when the first wire 101 and the second wire 102 are word lines, the third wire 103 can be a bit line. Furthermore, when the first wire 101 and the second wire 102 are bit lines, the third wire 103 can be a word line. Hereinafter, for ease of description, it will be assumed that the first wire 101 and the second wire 102 are respectively the first word line and the second word line.

[0047] The first memory cell MC1 includes a first heating electrode 110, a first data storage element 120, and a first switching element 130. The first switching element 130 includes a first switching electrode 131, a second switching electrode 132, and a first selection layer 133 disposed between the first switching electrode 131 and the second switching electrode 132. In an exemplary embodiment, the first selection layer 133 includes a bidirectional threshold switch (OTS) material. When a voltage higher than a threshold voltage is supplied between the first switching electrode 131 and the second switching electrode 132, current can flow through the first selection layer 133.

[0048] The first data storage element 120 includes a phase change material. In one exemplary embodiment, the first data storage element 120 includes a chalcogenide material. As one example, the first data storage element 120 can include Ge-Sb-Te (GST). The phase change rate depending on the crystallization temperature, the melting point, and the crystallization energy of the first data storage element 120 can be determined according to the type and the chemical composition ratio of the elements included in the first data storage element 120.

[0049] The second memory cell MC2 can have a structure similar to that of the first memory cell MC1. Referring to Figure 15A , the second memory cell MC2 includes a second heating electrode 140, a second data storage element 150, and a second switching element 160. The structure and characteristics of the second heating electrode 140, the second data storage element 150, and the second switching element 160 can be similar to those of the first heating electrode 110, the first data storage element 120, and the first switching element 130. Hereinafter, a method of writing data and erasing data will be described by way of example with reference to the first memory cell MC1.

[0050] When a voltage is supplied through the first word line 101 and the bit line 103, Joule heat depending on the voltage can be generated on an interfacial surface between the first heating electrode 110 and the first data storage element 120. Due to the Joule heat, the phase of the phase change material included in the first data storage element 120 can be changed from an amorphous phase to a crystalline phase or from a crystalline phase to an amorphous phase. In one exemplary embodiment, the first data storage element 120 has a high resistance in the amorphous phase and a low resistance in the crystalline phase. In one example embodiment, a data "0" or "1" can be defined according to the resistance value of the first data storage element 120.

[0051] To write data into the first memory cell MC1, a program voltage is supplied through the first word line 101 and the bit line 103. In one exemplary embodiment, the program voltage is higher than the threshold voltage of the bidirectional threshold switching material included in the first switching element 130. Accordingly, a current can flow through the first switching element 130. The phase of the phase change material included in the first data storage element 120 can be changed from an amorphous phase to a crystalline phase due to the program voltage to write data into the first memory region. In one exemplary embodiment, when the phase change material included in the first data storage element 120 has a crystalline phase, the state of the first memory cell MC1 is defined as a set state SET.

[0052] To erase data written in the first memory cell MC1, the phase of the phase-change material included in the first data storage element 120 is changed from a crystal phase to an amorphous phase. As one example, a predetermined erase voltage can be supplied through the first word line 101 and the bit line 103. Due to the erase voltage, the phase of the phase-change material included in the first data storage element 120 can be changed from a crystal phase to an amorphous phase. When the phase-change material included in the first data storage element 120 has an amorphous phase, the state of the first memory cell MC1 can be defined as a reset state RESET. In one exemplary embodiment, a maximum value of the erase voltage is higher than a maximum value of the program voltage, and a time for which the erase voltage is supplied is shorter than a time for which the program voltage is supplied.

[0053] As described above, the resistance values of the data storage elements 120 and 150 can change according to the states of the phase-change materials included in the data storage elements 120 and 150. The memory controller can distinguish data "0" and data "1" from each other based on the resistance values of the data storage elements 120 and 150. Thus, the more the difference in resistance between the data storage elements 120 and 150 caused by the phases of the phase-change materials included in the data storage elements 120 and 150, the more accurately the memory controller reads data.

[0054] will be described with Figure 15B focus on the differences from Figure 18A . Referring to Figure 18B , a memory device 100B according to an exemplary embodiment of the inventive concept includes a first memory cell MC1 and a second memory cell MC2 disposed between a plurality of conductive lines 101 to 103. As Figure 19 and Figure 20 illustrate, when the first conductive line 101 and the second conductive line 102 are a first word line and a second word line, respectively, the first memory cell MC1 and the second memory cell MC2 can have different orientations from each other. Referring to Figure 19 , each of the first memory cell MC1 and the second memory cell MC2 can have a first orientation. Referring to Figure 19 , the first memory cell MC1 can have a first orientation, and the second memory cell MC2 can have a second orientation.

[0055] Figure 20 and Figure 19 illustrate structures of memory cells included in a memory device according to exemplary embodiments of the inventive concept.

[0056] Figure 20 and Figure 16 , structures and features of the first memory cell MC1 and the second memory cell MC2 can be similar to Figure 19 and Figure 20The structure and characteristics of the first memory cell MC1 and the second memory cell MC2 in the memory. However, as Figure 21 and Figure 21 As shown, the first memory cell MC1, which is connected to the first word line formed on the first layer, and the second memory cell MC2, which is connected to the second word line formed on the second layer, do not share bit lines with each other.

[0057] Reference Figure 21 The first memory cell MC1 is disposed at the intersection of the first word line 101 and the first bit line 102 formed on the first layer, which intersect each other. The second memory cell MC2 may be disposed at the intersection of the second word line 103 and the second bit line 104 formed on the second layer. The first memory cell MC1 has a first orientation, and the second memory cell MC2 has a second orientation.

[0058] Reference Figure 21 Describe it, while paying attention to and Figures 1-20 The differences. (Refer to...) ​ Each of the first memory cell MC1 and the second memory cell MC2 has a first orientation.

[0059] ​ The operation of a memory device according to an exemplary embodiment of the inventive concept is shown.

[0060] The memory device 200 according to an exemplary embodiment operates using power supplied from the memory controller 220 to the memory cell 210. (See also...) ​ The memory cell 210 includes a lower electrode 211, a heating electrode 212, a data storage element 214, a switching element 215, and an upper electrode 216. The lower electrode 211 and the upper electrode 216 can receive voltages output via word lines or bit lines from the memory controller 220. An insulating layer 213 may be disposed around the heating electrode 212. In a region 214a of the data storage element 214 adjacent to the heating electrode 212, a phase transition may occur due to the power supplied by the memory controller 220. ​ The memory controller 20 can be used to implement ​ The memory controller 220.

[0061] In one exemplary embodiment, a predetermined bias voltage is input to each of the lower electrode 211 and the upper electrode 216 during a programming operation to write data to the memory cell 210. Since the bias voltage is higher than a threshold voltage of the bidirectional threshold switching material included in the switching element 215, the memory cell 210 is turned on. Then, a programming operation can be performed on the memory cell 210. The phase change material included in the data storage element 214 can be changed from an amorphous phase to a crystalline phase due to the programming operation. Accordingly, data can be written to the memory region of the memory cell 210.

[0062] ​ A programming operation of a memory device according to an exemplary embodiment of the inventive concept is illustrated. Referring to ​ The memory device 300 includes a memory cell array 310, a first decoder circuit 320, a second decoder circuit 330, a read / write circuit 340, and control logic 350. The memory cell array 310 includes first to fourth bit lines BL1 to BL4, first to fourth word lines WL1 to WL4, and a plurality of memory cells MC. The memory cell array 310 can include additional bit lines and word lines, and is illustrated as having four bit lines and four word lines only for ease of discussion. The plurality of memory cells MC can be disposed at intersections of the first to fourth bit lines BL1 to BL4 and the first to fourth word lines WL1 to WL4.

[0063] The plurality of memory cells MC included in the memory cell array 310 can have different current paths from each other. The current path can represent a distance between the decoder circuits 320 and 330 and a given memory cell MC. A memory cell having a long current path can have a relatively high path resistance than a path resistance of a memory cell having a short current path. Conversely, a memory cell having a short current path can have a relatively low path resistance than a path resistance of a memory cell having a long current path. The path resistance can have a bit line resistance, a word line resistance, and a switching resistance existing in the word lines and the bit lines.

[0064] The memory cell array 310 can include a first memory cell MC1 and a second memory cell MC2. The first memory cell MC1 is a memory cell farthest from the first decoder circuit 320 and the second decoder circuit 330. The second memory cell MC2 is a memory cell closest to the first decoder circuit 320 and the second decoder circuit 330. The first memory cell MC1 farthest from the first decoder circuit 320 and the second decoder circuit 330 can have a highest path resistance, and the second memory cell MC2 closest to the first decoder circuit 320 and the second decoder circuit 330 can have a lowest path resistance.

[0065] The plurality of memory cells included in the memory cell array 310 can have different levels of resistance regardless of the current path. For example, the resistance levels of the memory cells can be classified as low resistance, medium resistance, and high resistance according to their sizes.

[0066] The first decoder circuit 320 and the second decoder circuit 330 can select memory cells to be programmed from among the memory cells in response to an address in a program operation. The memory cells to be programmed by the memory device 300 can be referred to as selected memory cells. The word line and the bit line connected to the selected memory cells can be referred to as a selected word line and a selected bit line, respectively.

[0067] When the read / write circuit 340 programs the selected memory cells, the current source connected to the selected word line can supply a program current to the selected memory cells. The program current can flow from the selected bit line to the selected word line through the selected memory cells.

[0068] The resistance of the memory cells can vary according to a process or deterioration. When the selected memory cells are programmed, a program characteristic can change as the resistance of the memory cells varies. For example, according to the resistance of the selected memory cells, a program operation can not be normally performed or durability can decrease.

[0069] For example, sufficient Joule heat can be required to change a phase-change material constituting the selected memory cells from a crystalline phase to an amorphous phase. However, when a program operation is performed on the selected memory cells, Joule heat can not reach a target melting point of the selected memory cells due to a difference between the resistance of the selected memory cells and the path resistance. Accordingly, a distribution of the selected memory cells can be expanded.

[0070] In one embodiment, a program current having the same size is supplied to memory cells having different program characteristics from each other.

[0071] ​ A variation amount of a program current depending on the resistance of a memory cell according to an exemplary embodiment is shown, ​ Joule heat depending on the resistance of a memory cell according to an exemplary embodiment is shown.

[0072] The selected memory cells receive a program current from the current source connected to the selected word line. However, as ​ As shown in Equation 1, even when a program current of a constant size is supplied to the selected memory cells, the program current (e.g., ipgm) flowing through the selected memory cells can decrease as the resistance (e.g., Rdyn) of the selected memory cells increases. In addition, Joule heat generated in the selected memory cells can decrease as the resistance of the selected memory cells increases.

[0073] Returning to ​When the memory device 300 according to an exemplary embodiment programs a selected memory cell of the memory cell array 310, a programming current for programming the selected memory cell is determined according to a resistance of the selected memory cell. The determined programming current can be supplied to the selected memory cell. Accordingly, the memory device 300 can compensate for a change in programming characteristics during a programming operation according to a resistance of the selected memory cell.

[0074] ​ A voltage-current graph of a memory cell during a programming operation of a memory device according to an exemplary embodiment is shown, ​ A distribution of memory cells depending on a resistance of the memory cells according to an exemplary embodiment is shown. For example, ​ A distribution of on cells and off cells among memory cells based on a resistance of the memory cells is shown.

[0075] Referring to ​ As a bias voltage is supplied to the selected word line and the selected bit line, a voltage across the selected memory cell increases to a threshold voltage Vth. Accordingly, the selected memory cell turns on.

[0076] In one exemplary embodiment, a holding current is supplied to the selected memory cell to prevent the selected memory cell from turning off after the selected memory cell turns on. The holding current can represent a minimum current required to prevent the selected memory cell CELL from turning off (e.g., a minimum current required for the selected memory cell to be maintained in an on state). In this case, the voltage across the selected memory cell CELL can be referred to as a holding voltage. When the voltage across the selected memory cell is lower than the holding voltage, the selected memory cell turns off.

[0077] However, the holding current flowing to the selected memory cell can vary according to a resistance of the selected memory cell. For example, when the resistance of the selected memory cell is a low resistance (a), a first holding current Ia flows through the selected memory cell, and a voltage across the selected memory cell is a first holding voltage Va. When the resistance of the selected memory cell is a medium resistance (b), a second holding current Ib flows through the selected memory cell, and a voltage across the selected memory cell is a second holding voltage Vb. When the resistance of the selected memory cell is a high resistance (c), a third holding current Ic flows through the selected memory cell, and a voltage across the selected memory cell is a third holding voltage Vc.

[0078] The second holding current Ib is lower than the first holding current Ia and higher than the third holding current Ic. The second holding voltage Vb is higher than the first holding voltage Va and lower than the third holding voltage Vc. For example, the holding voltage across the selected memory cell can be changed according to the resistance of the selected memory cell. For example, the lower the resistance of the selected memory cell, the lower the holding voltage across the selected memory cell, and the higher the resistance of the selected memory cell, the higher the holding voltage across the selected memory cell.

[0079] According to an exemplary embodiment, when the selected memory cell is programmed, the holding voltage of the selected memory cell is detected to detect the resistance of the selected memory cell. Further, the programming current can be determined according to the detected resistance of the selected memory cell, and the determined programming current can be supplied to the selected memory cell. Accordingly, the memory device of the present disclosure can compensate for a variation in programming characteristics according to the resistance of the selected memory cell.

[0080] Referring to ​ and ​ , the distribution of the memory cells can vary according to whether the resistance of the selected memory cell is low (a), medium (b), or high (c). For example, in the case of off-cell, when the resistance of the selected memory cell is low (a), the selected memory cell can be distributed in the area a'. When the resistance of the selected memory cell is medium (b), the selected memory cell can be distributed in the area b'. When the resistance of the selected memory cell is high (c), the selected memory cell can be distributed in the area c'. In one exemplary embodiment, the threshold voltage Vth of the selected memory cell having the medium resistance (b) is higher than the threshold voltage Vth of the selected memory cell having the low resistance (a), and is lower than the threshold voltage Vth of the selected memory cell having the high resistance (c). In ​ , Ion,a, Ion,b, and Ion,c respectively denote the current corresponding to the threshold voltage of the memory cell having the low resistance (a), the memory cell having the medium resistance (b), and the memory cell having the high resistance (c).

[0081] As described with reference to ​ and ​ , the programming current flowing through the selected memory cell increases as the resistance of the selected memory cell decreases, so that excessive heat can be generated in the selected memory cell. Accordingly, as the resistance of the selected memory cell decreases, the selected memory cell can be distributed in the area a'.

[0082] In contrast, a programming current flowing through the selected memory cell decreases as the resistance of the selected memory cell increases, so that sufficient Joule heat can not be generated in the selected memory cell. Accordingly, as the resistance of the selected memory cell increases, the selected memory cell can be distributed in the region c'.

[0083] As a result, the distribution of the selected memory cell can be enlarged according to the resistance of the selected memory cell during the programming operation.

[0084] ​ A memory device according to an exemplary embodiment of the inventive concept is illustrated.

[0085] Referring to ​ The memory device 300A includes memory cells MC, a first switch SW1 (e.g., a transistor), a second switch SW2 (e.g., a transistor), a node ND, an NMOS transistor NM, a write driver WD (e.g., a driver circuit), a hold voltage detector HD (e.g., a voltage detection circuit), and a current adjustment circuit CC.

[0086] The NMOS transistor NM, the write driver WD, the hold voltage detector HD, and the current adjustment circuit CC can be included in a programming circuit PC. The programming circuit PC can be disposed below a memory cell array including the memory cells MC. The programming circuit PC can be connected to a word line WL of the memory cells MC through the node ND. When the word line WL is a selected word line, a voltage of the node ND can represent a voltage of the selected word line.

[0087] The first switch SW1 can control turn-on / off of the bit line BL in response to a first control signal CTRL1, and the second switch SW2 can control turn-on / off of the word line WL in response to a second control signal CTRL2. When the selected memory cell MC is programmed, the NMOS transistor NM can be turned on in response to a program enable signal WREN.

[0088] According to an exemplary embodiment, the hold voltage detector HD detects a hold voltage of the selected memory cell MC to detect a resistance of the selected memory cell MC. The current adjustment circuit CC can determine an additional programming current according to the detected resistance. The write driver WD can perform a final programming operation based on the additional programming current, and can perform the final programming operation on the selected memory cell MC. Accordingly, the memory device 300A can prevent the distribution of the selected memory cell MC from being enlarged during the programming operation.

[0089] Hereinafter, a memory device according to an exemplary embodiment of the inventive concept will be described with reference to FIGS. 11 to ​ A memory device according to an exemplary embodiment of the inventive concept is illustrated.

[0090] ​ A programming operation of a memory device according to an exemplary embodiment is illustrated,​ is a circuit diagram of a memory device according to an exemplary embodiment, ​ is ​ is a circuit diagram of a hold voltage detector in ​ shows a programming operation of a memory device according to an exemplary embodiment. ​ shows an embodiment of digitally detecting a hold voltage of a selected memory cell.

[0091] ​ shows an embodiment of a memory device detecting a resistance of a selected memory cell during a pre-read period. Referring to ​ , the pre-read period includes a cell-on period, a hold period, and a word line floating period. As a bias voltage is supplied to a selected word line and a selected bit line in the cell-on period, a voltage across the selected memory cell increases to a threshold voltage Vth. Accordingly, the selected memory cell turns on.

[0092] In one exemplary embodiment, a hold current is supplied to the selected memory cell to prevent the selected memory cell from turning off in the hold period after the cell-on period. In one exemplary embodiment, a current source is connected to the selected word line to supply the hold current to the selected memory cell.

[0093] In one exemplary embodiment, a selected word line switch connected to the selected word line turns off during a word line floating period after the hold period. Accordingly, the selected word line is in a floating state during the word line floating period. During the word line floating period, hold voltages Vhold,a, Vhold,b, and Vhold,c of the selected memory cell can be detected, and a resistance of the selected memory cell can be detected.

[0094] Specifically, when the selected word line is in the floating state, a charge pre-charged in the word line can be discharged. When the charge pre-charged in the word line is discharged, a voltage across the selected memory cell can decrease. When the voltage across the selected memory cell decreases below the hold voltages Vhold,a, Vhold,b, and Vhold,c, the selected memory cell turns off.

[0095] The time point at which the selected memory cell turns off can be different from one another depending on the resistance level of the selected memory cell. For example, in the case that the resistance of the selected memory cell is a low resistance (case 1), the hold voltage of the selected memory cell is a first hold voltage Vhold,a, and the selected memory cell turns off at a first time point tl. In the case that the resistance of the selected memory cell is a medium resistance (case 2), the hold voltage of the selected memory cell is a second hold voltage Vhold,b, and the selected memory cell turns off at a second time point t2. When the resistance of the selected memory cell is a high resistance (case 3), the hold voltage of the selected memory cell is a third hold voltage Vhold,c, and the selected memory cell turns off at a third time point t3. In one exemplary embodiment, the first time point tl precedes the second time point t2, and the third time point t3 lags behind the second time point t2.

[0096] For example, the hold voltage of the selected memory cell can be detected by detecting the time point at which the selected memory cell turns off. Since the resistance of the selected memory cell can be detected when the hold voltage is detected, the resistance of the selected memory cell can be detected by detecting the time point at which the selected memory cell turns off.

[0097] Referring to ​ The memory device 400 includes a first node ND1, a first NMOS transistor NM1, a hold voltage detector 410, a write driver 420, and a current regulation circuit 430. The first NMOS transistor NM1, the hold voltage detector 410, the write driver 420, and the current regulation circuit 430 can be included in a program circuit. The program circuit can be disposed under a memory cell array. The program circuit can be connected to a word line of the memory cell array through the first node ND1. When the word line is a selected word line, the voltage of the first node ND1 can represent the voltage of the selected word line.

[0098] In a program operation for a selected memory cell, the memory device 400 can operate in a case that its operation mode is divided into a first mode and a second mode. In one exemplary embodiment, when the memory device 400 operates in the first mode, the memory device 400 regulates the magnitude of the program current depending on the resistance of the selected memory cell. In one exemplary embodiment, when the memory device 400 operates in the second mode, the memory device 400 does not regulate the magnitude of the program current depending on the resistance of the selected memory cell. When the memory device 400 operates in the first mode, the program operation for the selected memory cell includes a pre-read period, a cell-on period, a hold period, and a program period.

[0099] ​ An exemplary embodiment in which the hold voltage detector 410 detects the resistance of the selected memory cell in the pre-read period is illustrated. Referring to​ The hold voltage detector 410 operates only in the first mode. When the memory device 400 operates in the first mode, the option enable signal OptEn can be a signal having a logic '1'. When the memory device 400 operates in the second mode, the option enable signal OptEn can be a signal having a logic '0'.

[0100] The hold voltage detector 410 includes first to third flip-flops FF1 to FF3 and first to third AND gates G1 to G3 (e.g., gate circuits, logic gates, or logic circuits). For example, the AND gates can be implemented by NAND gates and inverters. Each of the first to third flip-flops FF1 to FF3 receives a detector signal Detector_signal. The detector signal Detector_signal can be a voltage of the selected word line (e.g., a voltage of the first node ND1 in ​ ).

[0101] The first flip-flop FF1 outputs the detector signal Detector_signal in response to a first clock signal Clk_t1. The output of the first flip-flop FF1 can be a voltage of the selected word line at a time point A in ​ . ​ In the first case, the current can always be flowing to the selected word line regardless of whether the resistance of the selected memory cell is a low resistance, a medium resistance, or a high resistance (case 1, case 2, and case 3). Thus, the output of the first flip-flop FF1 can be a logic '1' regardless of whether the resistance of the selected memory cell is a low resistance, a medium resistance, or a high resistance.

[0102] The first AND gate G1 receives the output signal of the first flip-flop FF1 and the option enable signal OptEn, and outputs a first control signal En_A. When the output of the first flip-flop FF1 is a logic '1', the first control signal En_A is a logic '1'. Thus, the output En_A of the first AND gate G1 can be a logic '1' regardless of whether the resistance of the selected memory cell is a low resistance, a medium resistance, or a high resistance.

[0103] The second flip-flop FF2 outputs the detector signal Detector_signal in response to a second clock signal CLK_T2. The output of the second flip-flop FF2 can be a voltage of the selected word line at a time point B in ​ . ​ In the second case, the current can always be flowing to the selected word line regardless of whether the resistance of the selected memory cell is a low resistance, a medium resistance, or a high resistance (case 1, case 2, and case 3). Thus, the output of the second flip-flop FF2 can be a logic '1' regardless of whether the resistance of the selected memory cell is a low resistance, a medium resistance, or a high resistance.When the resistance of the selected memory cell is a low resistance, no current flows to the selected word line (Case 1). When the resistance of the selected memory cell is a medium resistance or a high resistance, current can flow to the selected word line (Case 2 and Case 3). Thus, the output of the second flip-flop FF2 can be a logic '0' when the resistance of the selected memory cell is a low resistance, and a logic '1' when the resistance of the selected memory cell is a medium resistance or a high resistance.

[0104] The second AND gate G2 receives the output signal of the second flip-flop FF2 and the option enable signal OptEn, and outputs a second control signal En_B. When the output of the second flip-flop FF2 is a logic '0', the second control signal En_B is a logic '0'. Thus, the output En_B of the second AND gate G2 is a logic '0' when the resistance of the selected memory cell is a low resistance. When the output of the second flip-flop FF2 is a logic '1', the second control signal En_B is a logic '1'. Thus, the output En_B of the second AND gate G2 is a logic '1' when the resistance of the selected memory cell is a medium resistance or a high resistance.

[0105] The third flip-flop FF3 outputs a detector signal Detector signal in response to a third clock signal Clk_t3. The output of the third flip-flop FF3 can be a voltage of the selected word line at the time point C in ​ ​ In the case of the selected memory cell, when the resistance of the selected memory cell is a low resistance or a medium resistance, no current flows to the selected word line (Case 1 and Case 2). When the resistance of the selected memory cell is a high resistance, current flows to the selected word line (Case 3). Thus, the output of the third flip-flop FF3 is a logic '0' when the resistance of the selected memory cell is a low resistance or a medium resistance, and a logic '1' when the resistance of the selected memory cell is a high resistance.

[0106] The third AND gate G3 receives the output signal of the third flip-flop FF3 and the option enable signal OptEn, and outputs a third control signal En_C. When the output of the third flip-flop FF3 is a logic '0', the third control signal En_C is a logic '0'. Thus, the output En_C of the third AND gate G3 is a logic '0' when the resistance of the selected memory cell is a low resistance or a medium resistance. When the output of the third flip-flop FF3 is a logic '1', the third control signal En_C is a logic '1'. Thus, the output En_C of the third AND gate G3 is a logic '1' when the resistance of the selected memory cell is a high resistance.

[0107] The logic values of the control signals En_A, En_B, and En_C depending on the resistance of the selected memory cell are shown in Table 1. ​

[0108] ​

[0109]

[0110] Returning to ​ The operation of the memory device 400 during the cell turn-on period, the hold period, and the program period after the pre-read period will be described. The write driver 420 includes a second NMOS transistor NM2, a third NMOS transistor NM3, a second current source CS2, and a third current source CS3. In the cell turn-on period, the first NMOS transistor NM1 turns on in response to the program enable signal WREN, and the second NMOS transistor NM2 turns on in response to the bias voltage enable signal VNEGH EN. As the first NMOS transistor NM1 and the second NMOS transistor NM2 turn on, the bias voltage is supplied to the selected word line and the selected bit line. As the decoder circuit supplies the bias voltage to the selected word line and the selected bit line, the voltage across the selected memory cell increases to the threshold voltage. Thus, the selected memory cell turns on.

[0111] The decoder circuit of the memory device 400 can include a bias circuit and a selection circuit. The selection circuit can select the memory cell to be programmed, and the bias circuit can supply a bias voltage to the selected word line and the selected bit line connected to the selected memory cell to turn on the selected memory cell.

[0112] In one exemplary embodiment, a hold current is supplied to the selected memory cell to prevent the selected memory cell from turning off during the hold period after the cell turn-on period. To supply the hold current to the selected memory cell, the second NMOS transistor NM2 turns off in response to the bias voltage enable signal VNEGH EN, and the third NMOS transistor NM3 turns on in response to the hold enable signal HOLD EN. As the third NMOS transistor NM3 turns on, the second current source CS2 is connected to the selected memory cell. Thus, the hold current Ihold can be supplied to the selected memory cell.

[0113] In the program period after the hold period, an initial program current Ipgm_rst is supplied to the selected word line connected to the selected memory cell. The third NMOS transistor NM3 turns off in response to the hold enable signal HOLD EN to supply the initial program current Ipgm_rst to the selected word line connected to the selected memory cell, and the fourth NMOS transistor NM4 turns on in response to the program enable signal IPGM EN. As the fourth NMOS transistor NM4 turns on, the third current source CS3 is connected to the selected word line. Thus, the initial program current Ipgm_rst is supplied to the selected memory cell.

[0114] In one exemplary embodiment, the second supply voltage VNEG has a lower level than the level of the first supply voltage VNEGH. Thus, the difference between the voltages applied across the selected memory cell CELL during the program period can be greater than the difference between the voltages applied across the selected memory cell CELL during the cell-on period and the hold period.

[0115] The current regulation circuit 430 includes a fifth NMOS transistor NM5 to a seventh NMOS transistor NM7 and a first current source CS1. The fifth NMOS transistor NM5 turns on in response to a first control signal En_A, the sixth NMOS transistor NM6 turns on in response to a second control signal En_B, and the seventh NMOS transistor NM7 turns on in response to a third control signal En_C. The current driving capabilities of the fifth NMOS transistor NM5 to the seventh NMOS transistor NM7 can be different from each other.

[0116] As described with reference to ​ When the resistance of the selected memory cell is a low resistance, the first control signal En_A is a logic '1', and the second control signal En_B and the third control signal En_C are logic '0'. In response to the first control signal En_A to the third control signal En_C, the fifth NMOS transistor NM5 turns on, and the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 turn off. Thus, the additional programming current Ipgm_rst_a flowing to the selected memory cell due to the first current source CS1 has a first size.

[0117] When the resistance of the selected memory cell is a medium resistance, the first control signal En_A and the second control signal En_B are logic '1', and the third control signal En_C is logic '0'. In response to the first control signal En_A to the third control signal En_C, the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 turn on, and the seventh NMOS transistor NM7 turns off. Thus, the additional programming current Ipgm_rst_a flowing to the selected memory cell due to the first current source CS1 has a second size.

[0118] When the resistance of the selected memory cell is a high resistance, the first control signal En_A, the second control signal En_B, and the third control signal En_C are logic '1'. The fifth NMOS transistor NM5, the sixth NMOS transistor NM6, and the seventh NMOS transistor NM7 turn on in response to the first control signal En_A to the third control signal En_C. Thus, the additional programming current Ipgm_rst_a flowing to the selected memory cell due to the first current source CS1 has a third size.

[0119] The first size, the second size, and the third size can be different from each other in accordance with the current driving capability of each of the fifth NMOS transistor NM5 to the seventh NMOS transistor NM7. For example, the higher the resistance of the selected memory cell, the larger the size of the additional programming current Ipgm_rst_a supplied to the selected memory cell.

[0120] The final programming current supplied to the selected memory cell can correspond to the sum of the initial programming current Ipgm_rst and the additional programming current Ipgm_rst_a. Since the size of the additional programming current Ipgm_rst_a supplied to the selected memory cell can increase as the resistance of the selected memory cell increases, the final programming current supplied to the selected memory cell can increase as the resistance of the selected memory cell increases.

[0121] Referring to ​ The size of the additional programming current depending on the resistance of the selected memory cell can be determined by detecting the point in time at which the selected memory cell turns off during the pre-read period t1 to t2. The selected memory cell turns on as the voltage across the selected memory cell increases to the threshold voltage during the cell-on period t2 to t3. In the hold period t3 to t4, a hold current is supplied to the selected memory cell.

[0122] During the programming periods t4 and t5, a final programming current can be supplied to the selected memory cell. The final programming current can correspond to the sum of the initial programming current and the additional programming current. The additional programming current can have a size determined in the pre-read periods t1 and t2. For example, the higher the resistance of the selected memory cell, the larger the size of the additional programming current. Thus, the higher the resistance of the selected memory cell, the higher the final programming current supplied to the selected memory cell.

[0123] As shown in ​ When the resistance of the selected memory cell is a low resistance, the final programming current supplied to the selected memory cell is Ia. When the resistance of the selected memory cell is a medium resistance, the final programming current supplied to the selected memory cell is Ib. When the resistance of the selected memory cell is a high resistance, the final programming current supplied to the selected memory cell is Ic. In one exemplary embodiment, Ib has a size larger than that of Ia and smaller than that of Ic.

[0124] ​ and ​ shows a programming operation of a memory device according to an exemplary embodiment of the inventive concept, ​ is a circuit diagram of a memory device according to an exemplary embodiment of the inventive concept. ​ shows an embodiment in which the hold voltage of the selected memory cell is detected in an analog manner.

[0125] Referring to ​ As the bias voltage is supplied to the selected word line and the selected bit line during the cell turn-on period, the voltage across the selected memory cell increases to the threshold voltage Vth. Accordingly, the selected memory cell turns on.

[0126] In one exemplary embodiment, a holding current is supplied to the selected memory cell to prevent the selected memory cell from turning off during a holding period after the cell turn-on period. In a word line floating period after the holding period, the holding voltages Vhold,a, Vhold,b, and Vhold,c of the selected memory cell can be detected, and the resistance of the selected memory cell can be detected.

[0127] As the selected word line switch is turned off in the word line floating period, the selected word line can have a floating state. When the selected word line has the floating state, the charge pre-charged in the selected word line is discharged. When the charge pre-charged in the selected word line is discharged, the voltage across the selected memory cell decreases. When the voltage across the selected memory cell is lower than the holding voltages Vhold,a, Vhold,b, and Vhold,c, the selected memory cell turns off. Until the selected memory cell turns off, the amount of charge output from the selected word line can vary according to the resistance of the selected memory cell.

[0128] Referring to ​ and ​ When the resistance of the selected memory cell is a low resistance (a), the amount of charge output from the selected word line until the selected memory cell turns off is a first amount of charge Charge1 (Case 1). When the resistance of the selected memory cell is a medium resistance (b), the amount of charge output from the selected word line until the selected memory cell turns off is a second amount of charge Charge2 (Case 2). When the resistance of the selected memory cell is a high resistance (c), the amount of charge output from the selected word line until the selected memory cell turns off is a third amount of charge Charge3 (Case 3).

[0129] Since the time points at which the selected memory cell turns off differ from each other according to the resistance level of the selected memory cell, the first amount of charge Charge1, the second amount of charge Charge2, and the third amount of charge Charge3 can differ from each other. For example, as the resistance of the selected memory cell increases, the amount of charge output from the selected word line can increase until the selected memory cell turns off.

[0130] Referring to ​The memory device 500 includes a second node ND2, a first NMOS transistor NM1, a hold voltage detector 510, a write driver 520, and a current regulation circuit 530. The first NMOS transistor NM1, the hold voltage detector 510, the write driver 520, and the current regulation circuit 530 can be included in a program circuit. The program circuit can be disposed below a memory cell array. The program circuit can be connected to a word line of the memory cell array through the second node ND2. When the word line is a selected word line, a voltage of the second node ND2 can represent a voltage of the selected word line.

[0131] In the pre-read period, the hold voltage detector 510 detects a resistance of a selected memory cell. The hold voltage detector 510 includes a comparator SA and a NOR gate NOR.

[0132] The comparator SA has a first terminal that receives a voltage of the second node ND2 and a second terminal that receives a reference voltage Vref. The comparator SA can compare the voltage of the second node ND2 with the reference voltage Vref and can output a result of the comparison as an output signal SAOUT. For example, the comparator SA can output a logic '0' when the voltage of the second node ND2 is not the reference voltage Vref and can output a logic '1' when the voltage of the second node ND2 is the reference voltage Vref.

[0133] For example, as shown in FIG. 4A, the reference voltage Vref can have a level that is higher than a level of the first hold voltage Vhold,a and a level of the second hold voltage Vhold,b and is lower than a level of the third hold voltage Vhold,c. ​

[0134] The NOR gate NOR can receive a complementary signal Outb of the output signal SAOUT of the comparator SA and a complementary signal OptEnb of the option enable signal. The option enable signal can be a logic '1' in the first mode. The NOR gate NOR outputs a logic '1' when the complementary signal Outb of the output signal SAOUT of the comparator SA is a logic '0' and the complementary signal OptEnb of the option enable signal is a logic '0'.

[0135] For example, in the first mode, the NOR gate NOR outputs a logic '1' when the voltage of the second node ND2 is not the reference voltage Vref. Alternatively, in the first mode, the NOR gate NOR outputs a logic '0' when the voltage of the second node ND2 is the reference voltage Vref.

[0136] ​The point in time at which the NOR gate NOR outputs a logic '0' can vary depending on whether the resistance of the selected memory cell is a low resistance (a), a medium resistance (b), or a high resistance (c). For example, when the resistance of the selected memory cell is a high resistance (c), the point in time at which the NOR gate NOR outputs a logic '0' can lag behind the point in time at which the NOR gate NOR outputs a logic '0' when the resistance of the selected memory cell is a low resistance (a) or a medium resistance (b).

[0137] The write driver 520 includes a second NMOS transistor NM2 to a fourth NMOS transistor NM4, a first current source CS1, and a second current source CS2. In the cell turn-on period, the first NMOS transistor NM1 turns on in response to a program enable signal WREN, and the second NMOS transistor NM2 turns on in response to a bias voltage enable signal VNEGH EN. As the first NMOS transistor NM1 and the second NMOS transistor NM2 turn on, a bias voltage is supplied to the selected word line and the selected bit line. As the bias voltage is supplied to the selected word line and the selected bit line, a voltage across the selected memory cell increases to a threshold voltage. Accordingly, the selected memory cell turns on.

[0138] In one exemplary embodiment, a hold current is supplied to the selected memory cell to prevent the selected memory cell from turning off in a hold period after the cell turn-on period. To supply the hold current to the selected memory cell, the second NMOS transistor NM2 turns off in response to the bias voltage enable signal VNEGH EN, and the third NMOS transistor NM3 turns on in response to a hold enable signal HOLD EN. As the third NMOS transistor NM3 turns on, the first current source CS1 is connected to the selected memory cell. Accordingly, the hold current Ihold is supplied to the selected memory cell.

[0139] In a program period after the hold period, an initial program current is supplied to the selected word line connected to the selected memory cell. The third NMOS transistor NM3 turns off in response to the hold enable signal HOLD EN to supply the initial program current to the selected word line connected to the selected memory cell, and the fourth NMOS transistor NM4 turns on in response to a program enable signal IPGM EN. As the fourth NMOS transistor NM4 turns on, the second current source CS2 is connected to the selected word line. Accordingly, the initial program current Ipgm_rst is supplied to the selected memory cell. In one exemplary embodiment, the second power voltage VNEG has a level higher than a level of the first power voltage VNEGH.

[0140] The current regulation circuit 530 includes a fifth NMOS transistor NM5 to a seventh NMOS transistor NM7 and a capacitor C. The fifth NMOS transistor NM5 turns on in response to a program enable signal IPGM EN, and the seventh NMOS transistor turns on in response to an output signal of a NOR gate NOR.

[0141] When the seventh NMOS transistor NM7 enters the on state and the NOR gate NOR outputs a logic '1', the capacitor C stores the charge output from the selected word line. When the seventh NMOS transistor NM7 enters the on state and the NOR gate NOR outputs a logic '0', the capacitor C does not store the charge output from the selected word line. The timing point at which the NOR gate NOR outputs a logic '0' when the resistance of the selected memory cell is a high resistance (c) lags behind the timing point at which the NOR gate NOR outputs a logic '0' when the resistance of the selected memory cell is a low resistance (a) or a medium resistance (b).

[0142] Therefore, the amount of charge stored in the capacitor C when the resistance of the selected memory cell is a high resistance (c) is greater than the amount of charge stored in the capacitor C when the resistance of the selected memory cell is a low resistance (a) or a medium resistance (b).

[0143] The sixth NMOS transistor NM6 turns on in response to the voltage across the capacitor C. When the sixth NMOS transistor NM6 turns on, an additional program current Ipgm_rst_a is supplied to the selected memory cell while discharging the charge accumulated in the capacitor C. Therefore, the additional program current Ipgm_rst_a supplied to the selected memory cell increases as the resistance of the selected memory cell increases.

[0144] In one exemplary embodiment, the final program current supplied to the selected memory cell corresponds to the sum of the initial program current Ipgm_rst and the additional program current Ipgm_rst_a. Therefore, the final program current supplied to the selected memory cell increases as the resistance of the selected memory cell increases.

[0145] As described with reference to ​ Since the timing points at which the selected memory cells turn off differ from each other, the resistance level of the selected memory cell can be detected by detecting the timing point at which the selected word line turns off. As described with reference to ​ Since the timing points at which the selected memory cells turn off differ from each other, the resistance of the selected memory cell can be detected by detecting the amount of charge output from the selected word line.

[0146] Since the time points at which the selected memory cells turn off are different from each other, the time at which the current flows to the selected memory cells can vary. For example, the hold voltage of the selected memory cell can be detected by detecting the time at which the current flows to the selected memory cell. Thus, the resistance of the selected memory cell can be detected by detecting the time at which the current flows to the selected memory cell.

[0147] ​ A programming operation of a memory device according to an example embodiment of the inventive concept is shown. ​ and ​ An example of a programming operation according to an example embodiment of the inventive concept is shown. ​ and ​ An example of a programming operation according to an example embodiment of the inventive concept is shown.

[0148] Reference will be made to ​ In the word line float period of the pre-read period, as the selected word line switch turns off, the selected word line enters a floating state. When the state of the selected word line is the floating state, the charge pre-charged in the selected word line is discharged. When the charge pre-charged in the selected word line is discharged, the voltage across the selected memory cell decreases. When the voltage across the selected memory cell is lower than the hold voltage, the selected memory cell turns off. Until the selected memory cell turns off, the amount of charge output from the selected word line can vary according to the resistance of the selected memory cell.

[0149] For example, the amount of charge Qc output from the selected word line when the resistance of the selected memory cell is a high resistance (c) can be greater than the amount of charge Qa output from the selected word line when the resistance of the selected memory cell is a low resistance (a). In ​ In the example, Rdyn_low, Rdyn_mid, and Rdyn_high can represent a low resistance, a medium resistance, and a high resistance, respectively.

[0150] Reference will be made to ​ with focus on the differences from ​ Reference will be made to ​ The memory device 600A includes a third node ND3, a first NMOS transistor NM1, a hold voltage detector 610A, a write driver 620A, and a current regulation circuit 630A. The first NMOS transistor NM1, the hold voltage detector 610A, the write driver 620A, and the current regulation circuit 630A can be included in a program circuit. The program circuit can be disposed below a memory cell array. The program circuit can be connected to a word line of the memory cell array through the third node ND3. When the word line is a selected word line, the voltage of the third node ND3 represents the voltage of the selected word line.

[0151] The first or NOR gate NOR1 receives the complement of the program enable signal nIPGMEN and the complement of the option enable signal nOptEN. Thus, the current regulation circuit 630A operates only when the memory device 600 is operated in the first mode during a program operation for a selected memory cell.

[0152] ​ The voltages illustrated in the middle can indicate the amount of time-dependent change of the word line voltage. The reference voltage Vref has a level higher than that of the first voltage Va and lower than that of the third voltage Vc. In the word line floating period, when the resistance of the selected memory cell is the low resistance (a), the selected memory cell turns off at the third time point t3, and when the resistance of the selected memory cell is the high resistance (c), the selected memory cell turns off at the fourth time point t4.

[0153] In the pre-read period, when the resistance of the selected memory cell is the low resistance (a), the output signal SAOUT of the comparator SA is always logic '0', and the complement of the output signal SAOUT of the comparator SA Outb is always logic '1'. When the complement of the option enable signal nOptEN is logic '1' and the complement of the output signal SAOUT of the comparator SA Outb is logic '1', the second or NOR gate NOR2 outputs logic '0'. Since the second or NOR gate NOR2 outputs always logic '0' in the pre-read period when the resistance of the selected memory cell is the low resistance (a), the additional program current Ipgm_extra does not flow to the selected word line during the program period.

[0154] In the pre-read period, when the resistance of the selected memory cell is the high resistance (c), the output signal SAOUT of the comparator SA is logic '1' and the complement of the output signal SAOUT of the comparator SA Outb is logic '0' in the case where the selected word line voltage V is the reference voltage Vref. When the complement of the option enable signal nOptEN is logic '1' and the complement of the output signal SAOUT of the comparator SA Outb is logic '0', the second or NOR gate NOR2 outputs logic '1'. Since the second or NOR gate NOR2 outputs logic '1' in the pre-read period when the resistance of the selected memory cell is the high resistance (c), the additional program current Ipgm_extra flows to the selected word line in the program period.

[0155] In the program period, the additional program current Ipgm_extra does not flow to the selected word line when the resistance of the selected memory cell is the low resistance (a), and the additional program current Ipgm_extra flows to the selected word line when the resistance of the selected memory cell is the high resistance (c). Thus, the final program current supplied to the selected memory cell increases as the resistance of the selected memory cell increases. In the case where the resistance of the selected memory cell is the low resistance (a), the final program current supplied to the selected memory cell is the program current Ipgm. In the case where the resistance of the selected memory cell is the high resistance (c), the final program current supplied to the selected memory cell is the sum of the program current Ipgm and the additional program current Ipgm_extra.​ In the embodiment, Ioff can indicate that the hold voltage detection is in a stop state.

[0156] will be described with attention to differences from ​ will be described with attention to differences from ​ will be described with attention to differences from ​ Referring to FIG. 6B, the memory device 600B includes three hold voltage detectors 610-1B to 610-3B and three current regulation circuits 630-1B to 630-3B. The first NMOS transistor NM1, the hold voltage detectors 610-1B to 610-3B, the write driver, and the current regulation circuits 630-1B to 630-3B can be included in a program circuit. The current regulation circuit 630-1B includes NMOS transistors NM5 and NM6, the current regulation circuit 630-2B includes NMOS transistors NM7 and NM8, and the current regulation circuit 630-3B includes NMOS transistors NM9 and NM10. The program circuit can be disposed under a memory cell array. The program circuit can be connected to a word line of the memory cell array through a fourth node ND4. When the word line is a selected word line, a voltage of the fourth node ND4 can represent a voltage of the selected word line.

[0157] ​ The voltages shown in the embodiment can indicate amounts of time-dependent changes in the word line voltage. The first reference voltage Vref1 has a level lower than that of the first voltage Va. The second reference voltage Vref2 has a level higher than that of the first voltage Va and lower than that of the third voltage Vc. The third reference voltage Vref3 has a level higher than that of the third voltage Vc. In the word line float period, when the resistance of the selected memory cell is the low resistance (a), the selected memory cell is turned off at a third time point t3. In the word line float period, when the resistance of the selected memory cell is the high resistance (c), the selected memory cell is turned off at a fourth time point t4.

[0158] In the pre-read period, when the resistance of the selected memory cell is the low resistance (a) or the high resistance (c), in a case where the selected word line voltage is the reference voltage, the output signal SAOUT1 of the first comparator SA1 is logic '1', and a complementary signal Outb1 of the output signal SAOUT of the first comparator SA1 is logic '0'. Accordingly, the first NOR gate NOR1 outputs logic '1'. As a result, the first additional program current Ipgm_extra1 flows to the selected word line during the program period.

[0159] In the pre-read period, when the resistance of the selected memory cell is the low resistance (a), the output signal SAOUT2 of the second comparator SA2 is always a logic '0', and the complementary signal Outb2 of the output signal SAOUT2 of the second comparator SA2 is always a logic '1'. Thus, the second NOR gate NOR2 outputs a logic '0'. As a result, the second additional programming current Ipgm_extra2 does not flow to the selected word line during the programming period. However, when the resistance of the selected memory cell is the high resistance (c), the output signal SAOUT2 of the second comparator SA2 can be a logic '1' in the case where the selected word line voltage is the reference voltage, and the complementary signal Outb2 of the output signal SAOUT2 of the second comparator SA2 can be a logic '0'. Thus, the second NOR gate NOR2 outputs a logic '1'. As a result, the second additional programming current Ipgm_extra2 flows to the selected word line during the programming period.

[0160] In the pre-read period, when the resistance of the selected memory cell is the low resistance (a) or the high resistance (c), the output signal SAOUT3 of the third comparator SA3 is always a logic '0', and the complementary signal Outb3 of the output signal SAOUT3 of the third comparator SA3 is always a logic '1'. Thus, the third NOR gate NOR3 outputs a logic '0'. As a result, the third additional programming current Ipgm_extra3 does not flow to the selected word line during the programming period.

[0161] In the programming period, when the resistance of the selected memory cell is the low resistance (a), the final programming current flowing to the word line can correspond to the sum of the initial programming current Ipgm_rst and the first additional programming current Ipgm_extra1. In the programming period, when the resistance of the selected memory cell is the high resistance (c), the final programming current flowing to the word line can correspond to the sum of the initial programming current Ipgm_rst, the first additional programming current Ipgm_extra1, and the second additional programming current Ipgm_extra2. Thus, the final programming current supplied to the selected memory cell can increase as the resistance of the selected memory cell increases.

[0162] ​ a programming operation of a memory device according to example embodiments of the inventive concept, ​ and ​ an example of a programming operation according to example embodiments of the inventive concept, ​ and ​ an example of a programming operation according to example embodiments of the inventive concept.

[0163] Reference is made to ​The programming operation for the selected memory cell includes a cell on-time period, a hold period, and a programming period, but excludes a pre-fetch period. When the selected memory cell enters the on-state, the amount of charge output from the selected word line can be detected. Since the amount of charge output from the selected word line depends on the resistance of the selected memory cell, the programming operation can be adjusted according to the resistance of the selected memory cell by detecting the amount of charge output from the selected word line.

[0164] For example, the amount of charge Qc output from the selected word line when the resistance of the selected memory cell is high (c) can be greater than the amount of charge Qa output from the selected word line when the resistance of the selected memory cell is low (a). ​ In the diagram, Rdyn_a, Rdyn_b, and Rdyn_c can represent low resistance, medium resistance, and high resistance, respectively.

[0165] exist ​ In the circuit diagram, the voltage at the fifth node ND5 represents the voltage of the selected word line. Regarding circuit configuration and operating principles, ​ and ​ Structurally similar to ​ and ​ However, with ​ and ​ Different, see reference ​ and ​ The voltage detector 710A detects the amount of charge output from the selected word line when the selected memory cell enters the on state.

[0166] exist ​ In the circuit diagram, the voltage at the sixth node ND6 represents the voltage of the selected word line. Regarding circuit configuration and operating principles, ​ and ​ Structurally similar to ​ and ​ However, with ​ and ​ Different, see reference ​ and ​ The voltage detectors 710-1B to 710-3B detect the amount of charge output from the selected word line when the selected memory cell enters the on state.

[0167] ​ Examples of programming operations according to exemplary embodiments of the inventive concept are shown. ​ Examples of programming operations according to exemplary embodiments of the inventive concept are shown.

[0168] exist ​ In the diagram, the voltage at the seventh node ND7 represents the voltage of the selected word line. (Refer to...) ​The second or NOR gate NOR2 receives a complement of the program enable signal nIPGMEN and a complement of the option enable signal nOptEN. Thus, the current regulation circuit operates only when the memory device 800 operates in the first mode in a program operation for the selected memory cell.

[0169] As the resistance of the selected memory cell increases, the amount of charge output from the selected word line can increase until the selected memory cell turns off. Thus, the point in time at which the first or NOR gate NOR1 outputs a logic '0' can be delayed as the resistance of the selected memory cell increases. Thus, the amount of charge stored in the capacitor C can increase as the resistance of the selected memory cell increases. The charge stored in the capacitor C can be discharged to supply the additional program current Ipgm_extra to the selected memory cell.

[0170] In one exemplary embodiment, the final program current supplied to the selected memory cell corresponds to a sum of the initial program current Ipgm_rst and the additional program current Ipgm_extra. Thus, the final program current supplied to the selected memory cell can increase as the resistance of the selected memory cell increases.

[0171] In ​ , the voltage of the eighth node ND8 represents the voltage of the selected word line. As in ​ , the memory device 800, ​ , the memory device 900 detects the amount of charge output from the selected word line when the selected memory cell enters the on state. The first or NOR gate NOR1 also receives a store enable signal EN_Store. The store enable signal EN_Store can be a logic '0' at any point in time while the selected memory cell remains in the on state.

[0172] For example, with reference to ​ , when the store enable signal EN_Store is a logic '1' at the fourth point in time t4, the first or NOR gate NOR1 outputs a logic '0'. The amount of charge stored in the capacitor C at the fourth point in time t4 can increase as the resistance of the selected memory cell increases. The charge stored in the capacitor C can be discharged to supply the additional program current Ipgm_extra to the selected memory cell. In ​ and ​ , Vsaref can represent a reference voltage.

[0173] In one exemplary embodiment, the final program current supplied to the selected memory cell corresponds to a sum of the initial program current Ipgm_rst and the additional program current Ipgm_extra. Thus, the final program current supplied to the selected memory cell can increase as the resistance of the selected memory cell increases.

[0174] ​ is a schematic block diagram of an electronic device including a memory device according to exemplary embodiments of the inventive concept.

[0175] According to ​ The electronic device 1000 according to an exemplary embodiment shown in FIG. 1A includes a display 1010, a sensor unit 1020, a memory 1030, a processor 1040, a port 1050, and other elements. The electronic device 1000 can further include wired and wireless communication devices and a power supply. Among the elements shown in ​ The port 1050 can be provided to the electronic device 1000 to communicate with a video card, a sound card, a memory card, or a USB device. The electronic device 1000 can include a desktop computer, a laptop computer, a smart phone, a tablet personal computer (PC), or a smart wearable device.

[0176] The memory 1030 can be a storage medium that stores data or multimedia data for the operation of the electronic device 1000. The memory 1030 can include a volatile memory such as a random access memory (RAM) or a non-volatile memory such as a flash memory. The memory 1030 can include at least one of a solid state drive (SSD), a hard disk drive (HDD), and an optical disk drive (ODD). The sensor unit 1020 can include an input device such as a keyboard, a mouse, or a touch screen, and an output device such as a display or an audio output unit.

[0177] The memory 1030 can include a phase change memory device that uses a change in resistance of a phase change material to write, erase, and read data. Further, in an exemplary embodiment shown in ​ The memory 1030 can include a memory device described above in various exemplary embodiments with reference to FIGS. 2 to 7. ​

[0178] As described above, when a selected memory cell is programmed, a hold voltage of the selected memory cell is detected to detect a resistance of the selected memory cell. Further, a programming current is determined according to the detected resistance of the selected memory cell, and the determined programming current is supplied to the selected memory cell. As a result, a distribution of the selected memory cell can be prevented from being enlarged.

[0179] While exemplary embodiments of the inventive concept have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept.​

Claims

1. A memory device comprising: a plurality of memory cells each including a switching element and a data storage element including a phase change material, and each connected to one of a plurality of word lines and one of a plurality of bit lines; a decoder circuit configured to determine at least one of the plurality of memory cells as a selected memory cell in response to an address; and a programming circuit configured to perform a programming operation by turning on the selected memory cell in a cell-on period, supplying a hold current to the selected memory cell to prevent the selected memory cell from turning off during a hold period, detecting a hold voltage of the selected memory cell during a word line floating period after the hold period, adjusting a size of a programming current based on the detected hold voltage, and supplying the adjusted programming current to the selected memory cell, wherein the selected memory cell turns off when a voltage across the selected memory cell is lower than the hold voltage. The programming circuit includes:

2. The memory device of claim 1, wherein, a hold voltage detector configured to detect the hold voltage of the selected memory cell and output a control signal corresponding to the detected hold voltage; a current adjustment circuit configured to generate an additional programming current having a size adjusted in response to the control signal; and a write driver configured to input a bias current to a selected word line connected to the selected memory cell among the plurality of word lines and generate an initial programming current corresponding to the bias current. The adjusted programming current is a sum of the initial programming current and the additional programming current in the programming operation for the selected memory cell.

3. The memory device of claim 2, wherein, The additional programming current has a size varied according to a resistance of the selected memory cell.

4. The memory device of claim 2, wherein, The hold voltage detector detects voltages of the selected word line at different points in time from each other and outputs the control signal according to levels of the voltages of the selected word line at the different points in time.

5. The memory device of any one of claims 2-4, wherein, The hold voltage detector includes:

6. The memory device of claim 5, wherein, at least one flip-flop configured to receive the voltages of the selected word line and output the voltages of the selected word line in response to a clock signal; and a logic gate configured to output the control signal based on an output of the at least one flip-flop and an enable signal. The current adjustment circuit includes:

7. The memory device of claim 5, wherein, a current source configured to supply the additional programming current to the selected memory cell; and at least one switch configured to connect the current source and the selected word line to each other, and wherein the current adjustment circuit controls the at least one switch in response to the control signal. The hold voltage detector compares the voltage of the selected word line with a reference voltage to output the control signal.

8. The memory device of any one of claims 2-4, wherein, The hold voltage detector includes:

9. The memory device of claim 8, wherein, a comparator including a first terminal receiving the voltage of the selected word line and a second terminal receiving a reference voltage; and a logic gate configured to output the control signal based on an output of the comparator and an enable signal. The current adjustment circuit includes:

10. The memory device of claim 8, wherein, a capacitor configured to store a charge output from the selected word line based on the control signal; and at least one switch configured to supply the additional programming current having a size adjusted based on an amount of the charge stored in the capacitor to the selected memory cell. 11.A memory device comprising: ​ a memory cell array including a plurality of memory cells disposed at intersections of a plurality of word lines and a plurality of bit lines; a decoder circuit configured to determine at least one of the plurality of memory cells as a selected memory cell in response to an address; and a programming circuit configured to perform a programming operation by turning on the selected memory cell during a first cell turn-on period of a pre-read period, supplying a hold current to the selected memory cell to prevent the selected memory cell from turning off during a first hold period of the pre-read period, detecting a hold voltage of the selected memory cell during a word line float period of the pre-read period after the first hold period, adjusting a size of a programming current based on the detected hold voltage, and supplying the adjusted programming current to the selected memory cell during a programming period after the pre-read period, wherein the hold voltage is a voltage to prevent the selected memory cell from turning off.

12. The memory device of claim 11, wherein, The programming circuit increases the size of the programming current as a resistance of the selected memory cell increases.

13. The memory device of claim 11 or 12, wherein, The decoder circuit supplies a bias voltage to a selected word line connected to the selected memory cell among the plurality of word lines and a selected bit line connected to the selected memory cell among the plurality of bit lines during the pre-read period to set the selected memory cell to an on state, and wherein the programming circuit supplies a minimum current required to maintain the selected memory cell in the on state, turns on a word line switch connected to the selected word line, and detects the hold voltage of the selected memory cell.

14. The memory device of claim 13, wherein, The decoder circuit supplies the bias voltage to the selected word line connected to the selected memory cell and the selected bit line during a second cell turn-on period after the pre-read period to set the selected memory cell to the on state, and wherein the programming circuit supplies the minimum current required to maintain the selected memory cell in the on state during a second hold period after the second cell turn-on period, and supplies the adjusted programming current to the selected memory cell during a programming period after the second hold period.

15. The memory device of claim 11, wherein, The programming circuit inputs a bias current to a selected word line connected to the selected memory cell among the plurality of word lines and generates an initial programming current corresponding to the bias current, and wherein the adjusted programming current is a sum of the initial programming current and an additional programming current having a size adjusted by the hold voltage.

16. A memory device, comprising: a memory cell array including a plurality of memory cells disposed at intersections of a plurality of word lines and a plurality of bit lines; a decoder circuit configured to determine at least one of the plurality of memory cells as a selected memory cell; and a programming circuit configured to perform a programming operation by turning on the selected memory cell during a cell turn-on period, supplying a minimum current required to maintain the selected memory cell in an on state during a hold period after the cell turn-on period, detecting a hold voltage of the selected memory cell during a word line float period after the hold period, adjusting a size of a programming current based on the detected hold voltage, and supplying the adjusted programming current to the selected memory cell during a programming period after the hold period, wherein the hold voltage prevents the selected memory cell from being turned off, wherein the decoder circuit supplies a bias voltage to a selected word line connected to the selected memory cell among the plurality of word lines and a selected bit line connected to the selected memory cell among the plurality of bit lines during the cell turn-on period to set the selected memory cell to the turn-on state.

17. The memory device of claim 16, wherein, As the resistance of the selected memory cell increases, the programming circuit increases the magnitude of the programming current.

18. The memory device of claim 16 or 17, wherein, The programming circuit inputs a bias current to a selected word line connected to the selected memory cell among the plurality of word lines and generates an initial programming current corresponding to the bias current.

19. The memory device of claim 18, wherein, The adjusted programming current is a sum of the initial programming current and an additional programming current having a magnitude adjusted by the hold voltage.

20. The memory device of claim 19, wherein, The additional programming current has a magnitude adjusted according to the resistance of the selected memory cell.

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