Surge protection device

Abstract

In general, the present disclosure discloses a surge protection device that can include a semiconductor layer of a first conductivity type and a lateral bipolar device disposed in the semiconductor layer. The surge protection device can further include an isolation trench disposed in the semiconductor layer in a base region of the lateral bipolar device. The isolation trench can be disposed between an emitter implant of the lateral bipolar device and a collector implant of the lateral bipolar device. The emitter implant and the collector implant can be a second conductivity type opposite the first conductivity type.

Description

Technical Field

[0001] This application relates to surge protection devices. Background Technology

[0002] Semiconductor processing and related packaging technologies continue to scale down to smaller sizes, posing challenges to achieving electrostatic discharge (ESD) and electrical (voltage and / or current) surge protection target specifications. For example, even with their size scaling, small packages and semiconductor devices for mobile applications must still maintain acceptable ESD and surge protection (collectively referred to as surge protection) performance. Current protection methods cannot provide sufficient surge protection in such small packages and also struggle to provide sufficiently low residual voltage during surge events to prevent damage (e.g., thermal damage) to associated semiconductor devices, particularly those used in power applications (e.g., devices implemented in USB Type-C mobile power applications with fast charging). Summary of the Invention

[0003] In general, an apparatus may include a semiconductor layer of a first conductivity type and a lateral bipolar device disposed in the semiconductor layer. The apparatus may further include an isolation trench disposed in the semiconductor layer in the base region of the lateral bipolar device. The isolation trench may be disposed between an emitter implant and a collector implant of the lateral bipolar device. The emitter implant and the collector implant may be of a second conductivity type opposite to the first conductivity type. Attached Figure Description

[0004] FIG. 1A and FIG. 2A This is a schematic block diagram illustrating a lateral surge protection device.

[0005] FIG. 1B and FIG. 2B They are shown separately. FIG. 1A and FIG. 2A The diagram shows the electrical schematic of a transverse surge protection device.

[0006] FIG. 3 It is shown FIG. 1A and FIG. 1B A cross-sectional view of an embodiment of a transverse surge protection device.

[0007] FIG. 4 It is shown FIG. 2A and FIG. 2B A cross-sectional view of an embodiment of a transverse surge protection device.

[0008] FIG. 5 This shows a comparison. FIG. 3 and FIG. 4The graph shows the simulation results of the surge protection performance of the device and the current implementation.

[0009] FIG. 6A and FIG. 6B This shows the effect of doping concentration and isolation trench depth on... FIG. 3 A graph showing the impact of the implementation of the device on the operation.

[0010] FIG. 7A , FIG. 7B and FIG. 8 It is shown FIG. 4 The operation curves of the device implementation method.

[0011] FIG. 9 This shows the effect of layout, doping concentration, and trench depth on FIG. 3 A graph showing the impact of the implementation of the device on the operation.

[0012] FIG. 10 , FIG. 11 , FIG. 12 , FIG. 13 , FIG. 14 , FIG. 15 The implementation is shown as a lateral NPN transistor (such as...) FIG. 3 Various implementations of transverse surge protection devices (variations of the device).

[0013] FIG. 16 , FIG. 17 , FIG. 18 , FIG. 19 , FIG. 20 , FIG. 21 , FIG. 22 , FIG. 23 The implementation is shown as a lateral silicon controlled rectifier (SCR) (such as...) FIG. 4 Various implementations of transverse surge protection devices (variations of the device).

[0014] FIG. 24 It shows a lateral SCR device (such as...) FIG. 21 A diagram showing the design layout of a part of the device. Detailed Implementation

[0015] Several exemplary embodiments of lateral surge protection devices (and their operation) are described and illustrated in the following detailed description (and in the accompanying drawings). The illustrated devices include several similar aspects and several variations from one illustrated embodiment to another. In the embodiments disclosed herein, the lateral surge protection device may include an isolation trench disposed in the base (e.g., base region) of a lateral (e.g., parasitic) bipolar device (e.g., a bipolar transistor, a silicon controlled rectifier (SCR), etc.) for surge protection.

[0016] In the example embodiments described herein, such isolation trenches can be configured to adjust (e.g., tune, change, regulate, etc.) the operation of lateral surge protection devices to provide improved surge protection performance compared to current methods. For example, such isolation trenches can be used to adjust the beta (β) of bipolar transistors included in the surge protection device, which can be used to establish desired breakdown voltage and / or fast retraction operation characteristics. Further, such isolation trenches can increase the current density capability (e.g., current per square meter) of the surge protection device by changing the geometry of the base of the surge protection device (e.g., the base current flows below the isolation trench rather than laterally). Further, in the embodiments disclosed herein, other aspects of the lateral surge protection device can also be implemented to adjust the operation of the device. Such aspects may include substrate (or epitaxial layer) doping concentration, implant layout and size design, well region location, etc.

[0017] In some embodiments, one or more aspects of one implementation may be implemented in one or more other implementations in the same way. For example, the arrangement and relative dimensions of the implants (e.g., collector, emitter, and / or base implants) shown in one example implementation may also be implemented in other implementations. Furthermore, for the purposes of brevity and clarity, it may not be necessary to discuss every element and aspect of the embodiments shown in the figures with respect to each figure in the figures.

[0018] Additionally, for clarity, in the embodiments illustrated in the accompanying drawings and described below (in a single drawing and from drawing to drawing), each instance of a given element or aspect may not be referred to by a dedicated reference numeral. Furthermore, in all drawings, similar and / or analogous elements and aspects of various embodiments may (although not necessarily) be referred to by similar reference numerals or similar reference numerals.

[0019] Furthermore, the example lateral surge protection devices described herein are implemented with a specific conductivity type (e.g., n-type or p-type) for a particular implant and / or region. The doping concentration of each of these implants and / or regions may vary based on a particular implementation. For illustrative purposes, and as an example, quantitative examples of doping concentration are given in some instances, while qualitative examples of doping concentration (e.g., lightly doped, heavily doped, very heavily doped, etc.) are given in other instances. Further, in some implementations, the conductivity type of the various regions described may be reversed. That is, a region of the example device described as n-type may be implemented as p-type, and vice versa.

[0020] FIG. 1AThis is a block diagram schematically illustrating a lateral surge protection device 100. In this example, a lateral bipolar transistor (e.g., an NPN transistor 110) is used to implement the lateral surge protection device 100. FIG. 1A As shown, an NPN transistor 110 is coupled between node 120 and electrical ground 130. As described herein, node 120 can be a node (e.g., a signal node, signal pad, etc.) of a semiconductor device protected from electrical surge events (e.g., electrostatic discharge (ESD) events, voltage surge events, and / or current surge events) by a protection device (e.g., the NPN transistor 110 in this example). For the purposes of this disclosure, the node to be protected in the semiconductor device (e.g., a transistor gate terminal, etc.) will be referred to as node 120, and the electrical ground coupled to the example protection device will be referred to as 130. In such embodiments, the surge protection device can be configured to absorb (conduct, communicate, etc.) electrical surge events between the protected node 120 and electrical ground 130, resulting in protection of the corresponding semiconductor device elements (e.g., gate dielectric, transistor, etc.) from damage by such surge events.

[0021] exist FIG. 1A In an example implementation, the NPN transistor 110 includes a collector 112 (e.g., an n-type collector region), an emitter 114 (e.g., an n-type emitter region), and a base 116 (e.g., a p-type base region). Although these regions are in... FIG. 1A The diagram is schematic, but in the embodiments described herein, each of the collector 112, emitter 114, and base 116 may respectively include multiple portions of the corresponding lateral surge protection device 100. That is, each of the collector 112, emitter 114, and base 116 may include one or more injectors, one or more traps, and / or for implementing, for example, at least in FIG. 3 and FIG. 10 to FIG. 15 A portion of the substrate or epitaxial layer of the lateral surge protection device 100 (or other lateral surge protection device) in the example embodiment shown.

[0022] Similarly, FIG. 1A As shown, the NPN transistor 110 includes an isolation trench 118 disposed in the base 116 (base region). As described above, the isolation trench 118 can be configured to adjust the operation of the lateral surge protection device 100 to provide desired surge protection performance in the corresponding semiconductor device (e.g., integrated circuit).

[0023] FIG. 1B It is shown FIG. 1A The diagram shows the electrical schematic of the transverse surge protection device 100. FIG. 1BAs shown, the lateral surge protection device 100 includes an NPN transistor 110 coupled between node 120 and electrical ground 130. Similarly, as... FIG. 1B As shown, the lateral surge protection device 100 also includes a resistor 111 coupled between the base 116 and the electrical ground 130. In this example (and other example embodiments described herein, such as...) FIG. 3 and FIG. 10 to FIG. 15 In the (middle) section, resistor 111 can be, for example, in FIG. 3 The example implementation shows the combined resistance of the base 116 (e.g., base region) and emitter 114 (e.g., emitter region) of the NPN transistor 110.

[0024] FIG. 2A This is a block diagram schematically illustrating another lateral surge protection device 140. In this example, a lateral bipolar SCR (e.g., SCR 150) is used to implement the lateral surge protection device 140, which can be implemented as a PNPN bipolar device (e.g., in a back-to-back arrangement, it may include a PNP transistor 160 and an NPN transistor 170). FIG. 2A As shown, with FIG. 1A and FIG. 1B Like the NPN transistor 110, the SCR 150 is coupled between node 120 (the protected node) and electrical ground 130 to protect the components of the corresponding semiconductor device coupled to node 120 (e.g., gate dielectric, transistor, etc.) from damage caused by electrical surge events.

[0025] exist FIG. 2A In an example implementation, the PNP transistor 160 of the SCR 150 includes a collector 162 (e.g., a p-type collector region), an emitter 164 (e.g., a p-type emitter region), and a base 166 (e.g., an n-type base region). Further, the NPN transistor 170 includes a collector 172 (e.g., an n-type collector region), an emitter 174 (e.g., an n-type emitter region), and a base 176 (e.g., a p-type base region), shared with the base 166 of the PNP transistor 160 (e.g., defined by the same elements as the lateral surge protection device 200).

[0026] Similar to the lateral surge protection device 100, in FIG. 2AThe regions of PNP transistor 160 and NPN transistor 170 are schematically shown. In the embodiments described herein, each of these regions may include corresponding portions of the corresponding lateral surge protection device 200. That is, each of the collectors 162 and 172, emitters 164 and 174, and bases 166 and 176 may respectively include one or more injectors, one or more wells, and / or for implementing, for example, at least in FIG. 4 and FIG. 16 to FIG. 24 A portion of the substrate or epitaxial layer of the lateral surge protection device 200 in the example embodiment shown.

[0027] Similarly, FIG. 2A As shown, SCR 150 includes an isolation trench 158 disposed (e.g., in, located, etc.) in the base 166 (base region) of PNP transistor 160 and the collector 172 (collector region) of NPN transistor 170. As described above with respect to the isolation trench 118 of lateral surge protection device 100, the isolation trench 158 of lateral surge protection device 200 can be configured to adjust (e.g., tune, change, regulate, etc.) the operation of lateral surge protection device 200 to provide desired surge protection performance in the corresponding semiconductor device (e.g., integrated circuit).

[0028] FIG. 2B It is shown FIG. 2A The diagram shows the electrical schematic of the transverse surge protection device 200. FIG. 2B As shown, the lateral surge protection device 200 includes an SCR 150 coupled between node 120 and electrical ground 130. Similarly, as... FIG. 2B As shown, the lateral surge protection device 200 also includes resistors 161 and 171. In the lateral surge protection device 200, resistor 161 is coupled between the base 166 of the PNP transistor 160 and node 120 (e.g., the protected node), while resistor 171 is coupled between the base 176 of the NPN transistor 170 and electrical ground 130. In this example (and other example embodiments described herein, such as...), FIG. 4 and FIG. 16 to FIG. 24In the above, resistor 161 can be a combined resistor of the base 166 (e.g., base region) and emitter 164 (e.g., emitter) of PNP transistor 160, while resistor 171 can be a combined resistor of the base 176 (e.g., base region) and emitter 174 (e.g., emitter region) of NPN transistor 170. Note that resistor 161 can also be considered to include the resistance of the collector 172 of NPN transistor 172, since the collector 172 is shared with the base 166 of PNP transistor 160. Similarly, resistor 171 can also be considered to include the resistance of the collector 162 of PNP transistor 160, since the collector 162 is shared with the base 176 of NPN transistor 170.

[0029] FIG. 3 This shows that it can be implemented. FIG. 1A and FIG. 1B A cross-sectional view of a lateral surge protection device 300 (e.g., including an NPN transistor 110) of a lateral surge protection device 100. In some embodiments, FIG. 3 The lateral surge protection device 300 shown may be a segment (e.g., a cell, etc.) of an NPN transistor. That is, in some embodiments, FIG. 3 Multiple instances of the NPN transistor 110 shown can be interconnected to form a single NPN transistor, or to form multiple NPN transistors. For example... FIG. 3 As shown, the NPN transistor 110 can have a pitch P in the range of 10μm-15μm. Note that... FIG. 3 The NPN transistor 110 can extend into and out of the page, and features (such as trenches 318 and / or trenches 319) can form corresponding stripes and / or perimeters. For example, in some embodiments, trenches 318 and 319 can be at least partially around each cell of the NPN transistor 110 or in the area including... FIG. 3 The NPN transistors of multiple instances of the cell shown are surrounded by a perimeter. Examples of such trench implementations are shown in... FIG. 24 As shown in the image.

[0030] as FIG. 1A to FIG. 1B Lateral surge protection device 100 and FIG. 2A to FIG. 2B 140 transverse surge protection device, FIG. 3 The NPN transistor 110 is coupled between node 120 (the protected node) and electrical ground 130. In the lateral surge protection device 300, node 120 is implemented using a first signal metal (indicated as 120), a via 124, a second signal metal 122, and a contact 126. Similarly, in FIG. 3In this embodiment, a third signal metal (indicated as 130), a via 134, a fourth signal metal 132, and a contact 136 are used to implement the electrical ground 130. In some embodiments, the first signal metal of node 120 and the third signal metal of electrical ground 130 may be portions of a first patterned signal metal layer, while the second signal metal 122 of node 120 and the third signal metal 132 of electrical ground 130 may be portions of a second patterned signal metal layer. In some embodiments, each signal metal layer in the transverse surge protection device 300 may be 2-3 micrometers (μm) thick or thicker. Using two or more such signal metal layers for each of node 120 and electrical ground 130 allows for increased current carrying capacity compared to surge protection devices using fewer or thinner signal metal layers. This increased current carrying capacity can prevent damage to the transverse surge protection device 300 during electrical surge events (e.g., thermal damage).

[0031] like FIG. 3 As shown, the NPN transistor 110 can be implemented in the semiconductor layer 310. In some embodiments, the semiconductor layer 310 can be a lightly doped p-type substrate, or it can be a lightly doped p-type epitaxial layer (e.g., disposed on a p-type substrate or an n-type substrate). FIG. 3 The lateral surge protection device 300 also includes a collector implant 312 (e.g., a heavily doped n-type implant), an emitter implant 314 (e.g., a heavily doped n-type implant), and a base implant 316 (e.g., a heavily doped p-type implant). In the lateral surge protection device 300, the collector implant 312 is electrically coupled to node 120, while the collector implant 314 and base implant 316 are electrically coupled to ground 130.

[0032] In the lateral surge protection device 300, the base region of the NPN transistor 110 may include a base implant 316 and a portion of the semiconductor layer 310 (e.g., a portion of the semiconductor layer 310 between the collector implant 312 and the emitter implant 314). FIG. 3 As shown, the isolation trench 318 may be disposed in a portion of the semiconductor layer 310 included in the base region of the NPN transistor 110. Depending on the specific implementation, the isolation trench 318 may have a dielectric and / or undoped polysilicon disposed therein.

[0033] In the lateral surge protection device 300, a trench 318 is disposed between the collector implant 312 and the emitter implant 314 and base implant 316. As discussed above with respect to the isolation trench 118, the trench 318 can be configured to adjust (e.g., tune, modify, control, etc.) the operation of the lateral surge protection device 300, for example, to achieve the desired performance behavior of the lateral surge protection device 300. That is, the trench 318 can be configured to modify the base region of the NPN transistor 110, for example, by adjusting the β of the NPN transistor 110, guiding the base current below the trench 318 (e.g., between the emitter implant 314 and the collector implant 312), thereby achieving the desired operation of the lateral surge protection device 300. As described above, other aspects of the lateral surge protection device 300, such as the doping concentration of the semiconductor layer 310, the arrangement and size of the implants, etc., can also be configured (created, utilized, etc.) to adjust the operation of the lateral surge protection device 300 to achieve the desired surge protection performance.

[0034] FIG. 4 This shows that it can be implemented. FIG. 2A and FIG. 2B A cross-sectional view of a lateral surge protection device 140 and a lateral surge protection device 400 (e.g., including an SCR 150). In some embodiments, FIG. 4 The lateral surge protection device 400 shown may be a segment (e.g., a unit, etc.) of the SCR 150. That is, in some embodiments, FIG. 4 Multiple instances of the SCR 150 shown can be interconnected to form a single SCR or to form multiple SCRs. For example... FIG. 4 As shown, as FIG. 3 The lateral surge protection device 300, SCR150 can have a pitch P in the range of 10μm-15μm. Note that, like the lateral surge protection device 300, FIG. 4 The features of the SCR 150 shown can extend into and out of the page, and features (such as grooves 458 and / or 459) can form corresponding stripes and / or perimeters. For example, in some embodiments, grooves 418 and 419 may be at least partially around each unit of the lateral surge protection device 140 or in the area including... FIG. 4 The SCRs of multiple instances of the shown unit form a perimeter. As mentioned above regarding... FIG. 3 As mentioned above, in FIG. 24 An example of such a trench implementation is shown in the figure.

[0035] as FIG. 1A to FIG. IB Lateral surge protection device 100 and FIG. 2A to FIG. 2B 140 transverse surge protection device, FIG. 4The SCR 150 is coupled between node 120 (the protected node) and electrical ground 130. In the lateral surge protection device 400, node 120 and electrical ground are implemented using multilayer signal metal, vias, and contacts as described with respect to lateral surge protection device 300. For the sake of brevity, those details will not be described in detail with respect to lateral surge protection device 400.

[0036] like FIG. 4 As shown, a lateral surge protection device 400 can be implemented in semiconductor layer 450. In some embodiments, semiconductor layer 450 may be a lightly doped n-type substrate, or it may be a lightly doped n-type epitaxial layer (e.g., disposed on a p-type or n-type substrate). The lateral surge protection device 400 of FIG. 400 also includes a plurality of implants defining PNP transistors and NPN transistors of SCR150. Due to the back-to-back arrangement of the PNP transistors and NPN transistors (the collector of the PNP transistor and the base of the NPN transistor are shared, while the collector of the NPN transistor and the base of the PNP transistor are shared), they... FIG. 4 They are not specifically mentioned in the text. However, their components (collector, emitter, and base) will be described below.

[0037] ​ The SCR 150 includes implants 462, 464, 466, and 474. In this example, implants 462 and 464 can be heavily doped p-type implants, while implants 466 and 474 can be heavily doped n-type implants. The lateral surge protection device 400 also includes heavily doped p-type wells 463 and 467 disposed in the semiconductor layer 450. ​ In the transverse surge protection device 400, injectors 462 and 464 are disposed in p-type well 463, while injectors 464 and 466 are disposed in n-type well 467.

[0038] In this example, the collector of the PNP transistor in SCR 150 may be defined by implant 464, while the emitter of the NPN transistor in SCR 150 may be defined by implant 474. Further, implant 466, n-well 467, and a portion of the semiconductor layer 450 (e.g., between n-well 467 and p-well 463) may be included in the base of the PNP transistor and the collector of the NPN transistor. Even further, implant 462 and p-well 463 may be included in the base of the NPN transistor and the emitter of the PNP transistor. That is, the base of the PNP transistor and the collector of the NPN transistor may be shared, and vice versa. In the lateral surge protection device 400, implants 464 and 466 are electrically coupled to node 120, while implants 462 and 474 are electrically coupled to ground 130.

[0039] like ​ As shown, isolation trench 458 may be disposed in portions of semiconductor layer 450 including the base region of the PNP transistor and the collector region of the NPN transistor. Like isolation trench 318, depending on the specific implementation, isolation trench 458 may have a dielectric and / or undoped polysilicon disposed therein. As discussed above with respect to isolation trench 158, isolation trench 458 may be configured to regulate (tune, modify, control, etc.) the operation of lateral surge protection device 400, for example, to achieve desired performance behavior of lateral surge protection device 400. That is, trench 458 may be configured to modify the base region of the PNP transistor of SCR 150, for example, by adjusting the β of the PNP transistor, guiding the base current of the PNP transistor below trench 458 (e.g., between n-well 467 and n-well 467), etc., to achieve desired operation of lateral surge protection device 400 (e.g., fast retraction operation). As described above, other aspects of the lateral surge protection device 400, such as the doping concentration of the semiconductor layer 450, the arrangement and size of the implants, can also be configured (established, utilized, etc.) to adjust the operation of the lateral surge protection device 400 to achieve the desired surge protection performance.

[0040] ​ This shows a comparison. ​ and ​ The simulation results of the surge protection performance of the device versus the current implementation (e.g., surge protection device excluding isolation trenches) are shown in graph 500. In graph 500, the values ​​of surge current (IPP(A) shown on the X-axis) and associated clamping voltage (Vclamp(V) shown on the Y-axis) are normalized because the specific values ​​will depend on the particular implementation. ​The illustrated zone 502 shows an example of a safe operating zone, which specifies the current and voltage values ​​of electrical surges that should be tolerated, where values ​​outside zone 502 would be considered to exceed those specifications. In an example implementation, zone 502 might correspond to a surge current of 6.5 amperes (A) and a clamping voltage of 20 volts (V).

[0041] In graph 500, the current-voltage (IV) characteristics of the current (conventional) protection structure are shown by trace 505. ​ The IV characteristics of an embodiment of the transverse surge protection device 300 are shown by trace 510, and ​ The IV characteristics of an embodiment of the lateral surge protection device 400 are shown by trace 520. For example... ​ As shown, although the IV characteristics shown by trace 505 are outside region 502, the clamping voltage increases with the increase of current IPP, which may lead to damage to the semiconductor device, for example, due to overheating caused by the associated power consumption.

[0042] Compared to the IV characteristics shown by trace 505, the IV characteristics of trace 510 (e.g., for an embodiment of lateral surge protection device 300) are relatively flat, with the clamping voltage initially decreasing at a normalized current value between 0 and 3. Furthermore, the IV characteristics of trace 520 (e.g., for an embodiment of lateral surge protection device 400) show a continuous decrease in clamping voltage after an initial increase in clamping voltage with increasing current IPP, for example due to the rapid retraction operation of lateral surge protection device 400. Therefore, the operation of embodiments for lateral surge protection devices 300 and 400 is superior to the current-based method because they do not exhibit a continuous increase in clamping voltage.

[0043] ​ This shows the effect of doping concentration on ​ The graph 600 shows the impact of the implementation of device 300 on operation. Specifically, ​ The breakdown voltage behavior (on the X-axis) and associated current behavior (on the Y-axis) of the semiconductor layer 310 with different doping concentrations in an embodiment of the lateral surge protection device 300 are shown. As with graph 500, the voltage and current values ​​in graph 600 are normalized or not indicated, and the specific values ​​will depend on the particular embodiment. Example values ​​for the embodiments are given below for illustrative purposes. Further references are made in the discussion of graph 600. ​ .

[0044] In graph 600, traces 610, 620, and 630 respectively illustrate the voltage breakdown and fast recovery behavior of corresponding embodiments of the lateral surge protection device 300 with three different doping concentrations of the semiconductor layer 310. Specifically, trace 610 shows the highest doping concentration (e.g., 1 × 10⁻⁶). 17 Trajectory 620 shows a moderate doping concentration (e.g., 5 × 10⁻⁶). 16 Trajectory 630 shows the lowest doping concentration (e.g., 1 × 10⁻⁶). 16 As can be seen from graph 600, while higher doping concentrations (e.g., traces 610 and 620) exhibit lower breakdown voltages (e.g., 15V and 21V, respectively), they also exhibit less extreme fast retraction characteristics. As shown by trace 630 (doping concentration of the lowest semiconductor layer 310), although it has a higher breakdown voltage (e.g., 27V) than embodiments with higher doping concentrations, the embodiment of trace 630 also exhibits the most extreme fast retraction characteristics.

[0045] ​ The curve 600 (640) shows the effect of the isolation trench depth on... ​ The impact of the implementation of the transverse surge protection device 300 on operation. Specifically, ​ The breakdown voltage behavior (on the X-axis) and associated current behavior (on the Y-axis) for different depths of the isolation trench 318 at a constant doping concentration of the semiconductor layer 310 are shown. Like plots 500 and 600, the voltage and current values ​​in plot 640 are normalized or not indicated, and the specific values ​​will depend on the particular implementation. In plot 640, the doping concentration of the semiconductor layer 310 corresponds to... ​ The trace 620 in the middle is associated with a medium doping concentration (e.g., 5 × 10⁻⁶). 16 ).

[0046] In graph 640, trace 650 corresponds to the operation of the lateral surge protection device 300 (where the depth of the isolation trench 318 is approximately 1 μm), trace 660 corresponds to the operation of the lateral surge protection device 300 (where the depth of the isolation trench 318 is approximately 3 μm), trace 670 corresponds to the operation of the lateral surge protection device 300 (where the depth of the isolation trench 318 is approximately 5 μm), and trace 680 corresponds to the operation of the lateral surge protection device 300 (where the depth of the isolation trench 318 is approximately 9 μm). ​ and ​ In the embodiment of the lateral surge protection device 300 shown (and other embodiments), the depth of the implant (collector, base and emitter) in the semiconductor layer 310 can be approximately 0.5 μm.

[0047] like ​As shown, although the depth of the isolation trench 318 may not have a significant effect on the breakdown voltage (approximately 21V in this example), the trench depth does affect the fast pullback behavior, and a deeper trench 318 indicates a smaller extreme fast pullback behavior. Therefore, given the correlation between breakdown voltage and doping concentration (e.g., ​ (as shown) and the correlation between the depth of the isolation trench and the rapid retraction behavior (e.g.) ​ As shown, the breakdown voltage and fast retraction behavior of embodiments of lateral surge protection devices such as those described herein can be established at least in one order by selecting the doping concentration (e.g., the doping concentration of the semiconductor substrate or epitaxial layer in which the lateral surge protection device is implemented) and the isolation trench depth (e.g., in the base region of the lateral surge protection device).

[0048] ​ and 7B It is shown ​ The operation curves 700 and 730 show the implementation of the transverse surge protection device 400. Specifically, ​ The breakdown voltage behavior (on the X-axis) and associated current behavior (on the Y-axis) of an embodiment for a lateral surge protection device 400 (e.g., SCR150) are shown. ​ It shows that it has a much larger SCR 150 (e.g., is). ​ Graph 750 shows the operation of an embodiment of the lateral surge protection device 400 (approximately 14,000 times that of SCR 150). Like graphs 500, 600, and 640, the voltage and current values ​​in graphs 700 and 730 are normalized or not indicated, and the specific values ​​will depend on the particular embodiment. In graph 700, the doping concentration of the semiconductor layer 450 corresponds to... ​ and ​ Examples of medium doping concentrations (e.g., 5 × 10⁻⁶) 16 ).

[0049] In graph 700, trace 710 illustrates the operation of an example embodiment of the lateral surge protection device 400 discussed above. As a comparison with lateral surge protection device 300, for the same semiconductor layer (e.g., substrate) doping concentration, the breakdown voltage of lateral surge protection device 400 can be greater than that of lateral surge protection device 300 (e.g., 24V vs. 21V in the example above). However, the rapid retraction behavior of lateral surge protection device 400 (in...) ​(Indicated by 720) This differs from the fast retraction behavior of the lateral surge protection device 300. This difference in fast retraction behavior is at least partly due to the structure of the SCR 150 of the lateral surge protection device 400, which has a two-step fast retraction operation. For example, in this example, the first fast retraction 730 arises from the fast retraction of the NPN transistor when the base current of the NPN transistor is high enough to turn on its base to emitter junction. ​ As shown, the second fast retraction 720 originates from the conduction of the PNP transistor of the SCR 150 of the lateral surge protection device 400. This conduction is triggered by the collector current of the NPN transistor (e.g., after its fast retraction).

[0050] exist ​ In the middle, trace 760 shows a larger SCR 150 (e.g., is ​ The IV characteristics of the lateral surge protection device 400 (14,000 times the size of the device) are shown. In the figure, the current scale shows the difference between the two devices. ​ The current in the medium is higher (e.g., at least one order of magnitude larger). For example... ​ As shown, even at higher currents, only a single rapid retraction of 770 occurs. That is, when compared with... ​ In comparison, ​ This illustrates that as the device size scales up significantly (14,000 times larger), a rapid shrinkage (first rapid shrinkage) occurs at much higher currents, and in the example implementation, even... ​ No second rapid retraction occurred even at higher currents.

[0051] ​ It is shown ​ The operation of the transverse surge protection device 400 is illustrated in graph 800. Specifically, ​ The time-domain representation of the surge protection performance of embodiments of the transverse surge protection device 400 under different currents and associated voltages is shown. ​ The diagram shows the surge voltage (represented by a solid line on the left, representing the Y-axis) versus the surge current (represented by a dashed line on the right, representing the Y-axis) over time (on the X-axis). (Similar to...) ​ The voltage, current, and time values ​​in graph 800 are normalized or not indicated, and the specific values ​​will depend on the particular implementation. For illustrative purposes, example values ​​for an implementation of the transverse surge protection device 400 are given below. Therefore, in the discussion of graph 800, further reference is made to... ​ In graph 800, the target holding (clamping) current Ihold is indicated, where in this example implementation, Ihold can be 20A.

[0052] exist ​In the diagram, traces 810, 820, 830, 840, and 850 show example surge currents, while traces 810a, 820a, 830a, 840a, and 850 show the corresponding surge voltages. (See diagram for example.) ​ As shown, the peak values ​​of the surge currents represented by traces 810, 820, and 830 are below Ihold and just above Ihold, respectively (this indicates that no surge event occurred outside the safe operating range). As shown by the corresponding voltage traces 810a, 820a, and 830a, the associated surge voltages are substantially the same (e.g., no rapid recoil occurred in the SCR of the transverse surge protection device 400).

[0053] Compared to surge currents 810, 820, and 830, the corresponding peak values ​​of the surge currents represented by traces 840a and 840b are significantly greater than Ihold (approximately six and nine times greater, respectively). As shown by the corresponding voltage traces 840a and 850a, when the corresponding surge current exceeds approximately twice the value of Ihold, the surge voltage of traces 840a and 850a decreases (e.g., to approximately 30% of the surge voltage shown by traces 810a, 820a, and 830a). This decrease in surge voltage (holding voltage) can be achieved as a rapid retraction behavior of the SCR 150 of the lateral surge protection device 400. This behavior also prevents overheating of the lateral surge protection device 400 due to the lower power dissipation associated with the reduced holding voltage. This prevents abrupt changes in the base β of the PNP transistor of the SCR 150 (due to temperature variations), which can provide more predictable behavior of the lateral surge protection device 400 and prevent damage (e.g., thermal damage) to the lateral surge protection device 400 and associated semiconductor devices (e.g., devices connected to node 120 protected by the lateral surge protection device 400).

[0054] ​ This shows the effect of layout, doping concentration, and trench depth on ​ A graph showing the impact of the device implementation method on operation. Traces 910, 920, and 930 are... ​ Variations of the lateral surge protection device 300 shown (such as...) ​ Simulation results of surge protection operation (considering thermal variations) are shown, including variations with different layouts. As shown in traces 910, 920, and 920, such layout variations can be used to adjust (tune, modify, etc.) the clamping voltage of the illustrated lateral surge protection device. For example, layout variations can be used to obtain more or less fast retraction operation, as shown in traces 910 to 930. Such modifications can also be achieved by changing the trench depth and / or doping concentration, as discussed herein.

[0055] ​Various embodiments of lateral surge protection devices implemented as (including) lateral NPN transistors are shown, such as ​ Variations and / or combinations of the NPN transistor 110. Due to ​ The implementation method is ​ Variations (including combinations) of the NPN transistor 110, therefore, for the sake of brevity, ​ Details about the NPN transistor 110 ​ No further repetition. That is, ​ The discussion involves ​ The NPN transistor 110 shown and ​ The differences between the implementation methods and / or combinations of the NPN transistor 110 shown in the accompanying drawings. ​ In each of the embodiments shown, node 120 (the protected node) and electrical ground 130 are indicated for reference only, and those connections may not be discussed further. In cases where multiple nodes are protected by a given structure, those nodes are enumerated as node 120a, node 120b, etc.

[0056] Reference ​ This illustrates a lateral surge protection device 1000 including an emitter implant 1014 and a base implant 1016. Compared to an NPN transistor 110, the emitter implant 1014 and base implant 1016 of the lateral surge protection device 1000 are located at... ​ The emitter implant 314 and the base implant 316 are positioned in opposite directions. This arrangement alters the configuration of the base and collector of the NPN transistor, which allows for adjustment of the clamping voltage (adjusting fast retraction), such as... ​ As shown.

[0057] Reference ​ and ​ compared to, ​ The lateral surge protection device 1100 includes a very heavily doped p-type implant 1110 near the surface of its isolation trench 1118 (e.g., at least partially surrounding the isolation trench 1118), while ​ The lateral surge protection device 1200 includes a heavily doped p-type implant 1210 formed along the sidewall of its isolation trench 1218. ​ and ​ In some embodiments, the p-type injectors 1110 and 1210 can reduce leakage in those lateral surge protection devices compared to device 300.

[0058] Reference ​ The diagram illustrates a lateral surge protection device 1300, which includes multiple NPN transistor segments that implement a single protection device coupled between node 120 and electrical ground 130. (See diagram for reference.)​ As shown, the lateral surge protection device 1300 includes two collector injectors 1312a and 1312b, two emitter injectors 1314a and 1314b, and two base injectors 1316a and 1316b. In some embodiments, ​ The pattern shown can continue to the left and / or right. This configuration allows for larger surge events without damage because it can absorb more surge current. Similarly... ​ As shown, emitter implants 1314a and 1314b are disposed on both sides of the corresponding base implants 1316a and 1316b (and may surround the corresponding perimeter of the base implants, e.g., in a raceway configuration). This arrangement allows sections of the NPN transistor to efficiently conduct current to the left and right sides, wherein the corresponding collector implants are configured to be adjacent to the emitter implants and base implants (e.g., with an isolation trench disposed between them).

[0059] Reference ​ The diagram illustrates a lateral surge protection device 1400 that provides bidirectional surge protection (e.g., protection against both positive and negative surges). ​ As shown, the lateral surge protection device 1400 includes a first NPN transistor 110a connected in series with a second NPN transistor 110b, wherein the collectors and bases of NPN transistors 110a and 110b are electrically coupled to each other via node 1425. This arrangement can provide protection against surges from node 120 to electrical ground 130 or from electrical ground 130 to node 120. ​ As shown, in order to provide electrical isolation (e.g., to prevent cross current flow) between NPN transistors 110a and 110b in semiconductor layer 1410 (e.g., p-type epitaxial layer), lateral surge protection device 1400 may include a cell isolation trench 1418 that extends through semiconductor layer 1410 and into substrate 1410a (e.g., n-type substrate) on which semiconductor layer 1410 is disposed.

[0060] Reference ​ The diagram illustrates a lateral surge protection device 1500 that can provide surge protection to multiple nodes 120a and 120b. (See diagram for reference.) ​ As shown, the lateral surge protection device 1500 includes a first NPN transistor 110a coupled between node 120a and electrical ground 130, and a second NPN transistor 110b coupled between node 120b and electrical ground 130. As ​The lateral surge protection device 1400 shown may include a cell isolation trench 1518 extending through the semiconductor layer 1510 and into the substrate 1510a (e.g., an n-type substrate) where the semiconductor layer 1510 is disposed, in order to provide electrical isolation (e.g., to prevent cross current flow) between NPN transistors 110a and 110b in the semiconductor layer 1510.

[0061] ​ The implementation is shown as a lateral silicon controlled rectifier (SCR) (such as...) ​ Various implementations of transverse surge protection devices (variations of the device). Due to ​ The implementation method is ​ The SCR 150 variants (including combinations), therefore for the sake of brevity, ​ Details about the SCR150 are no longer available. ​ Repeat. That is, ​ The discussion involves ​ The SCR150 shown and ​ The differences between the implementation methods and / or combinations of the SCR 150 shown in the accompanying drawings. ​ In each of the embodiments shown, node 120 (the protected node) and electrical ground 130 are indicated for reference purposes only, and those connections may not be discussed further. In cases where multiple nodes are protected by a given structure, those nodes are enumerated as node 120a, node 120b, etc.

[0062] Reference ​ The diagram illustrates a lateral surge protection device 1600, which includes a p-type injector 1664 and an n-type injector 1666. Unlike the p-type and n-type injectors 464 and 466 of the SCR 150, injectors 1664 and 1666 are not disposed in an n-type well. This arrangement alters the base configuration of the PNP transistor in the SCR 150, which can increase the β of the PNP transistor in the SCR. In this example, due to the elimination of... ​ The n-type trap in this implementation reduces associated manufacturing costs. Similar modifications can also be made to other SCR implementations.

[0063] Reference ​ and ​ In contrast, SCR injections are arranged and / or can have different sizes. For example, in ​ Lateral surge protection device 1700 and ​ In the lateral surge protection device 1900, with ​Compared to injectables 464 and 466, the positions and relative sizes of the corresponding p-type injectables 1764 and 1964 and the corresponding n-type injectables 1766 and 1966 are interchanged. Further in ​ and ​ In the lateral surge protection device 1800, with ​ Compared to implants 462 and 474, the positions of the corresponding p-type implants 1762 and 1862 and the corresponding n-type implants 1774 and 1874 are interchanged. This arrangement can change the configuration of the corresponding SCR, which can change the corresponding beta and base resistance of the NPN and / or PNP transistors of the SCR, thereby shaping the clamping voltage profile of the device.

[0064] Reference ​ The diagram shows a lateral surge protection device 2000, which is similar to... ​ The lateral surge protection device 1200 includes a heavily doped n-type implant 1210 formed along the sidewall of its isolation trench 2018, which in some embodiments can reduce leakage of device 2000 compared to device 400.

[0065] Reference ​ The diagram illustrates a transverse surge protection device 2100, which includes multiple SCR sections that implement a single protection device coupled between node 120 and electrical ground 130. (See diagram for reference.) ​ As shown, the transverse surge protection device 2100 includes injection elements 2162a and 2162b (corresponding to injection element 462), injection elements 2164a and 2164b (corresponding to injection element 464), injection elements 2166a and 2166b (corresponding to injection element 466), and injection elements 2174a and 2174b (corresponding to injection element 474). In some embodiments, ​ The pattern shown can continue to the left and / or right. This configuration allows for larger surge events without damage because it can absorb more surge current.

[0066] Similarly, ​ As shown, injectors 2164a and 2164b are disposed on both sides of the corresponding injectors 2166a and 2116b (and may surround the corresponding perimeter of those injectors, such as in a runway configuration). Similarly, in ​ In this configuration, injectors 2162a and 2162b are disposed on both sides of the corresponding injectors 2174a and 2174b (and may surround the corresponding perimeters of those injectors, as in a runway configuration). Such an arrangement allows the SCR segment to effectively conduct current to the left and right sides, wherein the corresponding injectors of the SCR segment are disposed adjacent to each other (e.g., with an isolation trench disposed between them).

[0067] Reference ​ The diagram illustrates a lateral surge protection device 2200, which can provide bidirectional surge protection (e.g., protection against both positive and negative surges). ​ As shown, the lateral surge protection device 2100 includes a first SCR 2250a connected in series with a second SCR 2250b, wherein the emitters and bases of the NPN transistors of SCRs 2250a and 2250b are electrically coupled to each other via node 125. This arrangement can provide protection against surges from node 120 to electrical ground 130 or from electrical ground 130 to node 120. ​ As shown, in order to provide electrical isolation (e.g., to prevent cross current flow) between SCRs 2250a and 2250b in semiconductor layer 2210 (e.g., n-type epitaxial layer), lateral surge protection device 2200 may include a cell isolation trench 2218 that extends through semiconductor layer 2210 and into substrate 2210a (e.g., p-type substrate) on which semiconductor layer 2210 is disposed.

[0068] Reference ​ This illustrates a lateral surge protection device 2300, which can provide surge protection to multiple nodes 120a and 120b. (Example) ​ As shown, the lateral surge protection device 2300 includes a first SCR 2350a coupled between node 120a and electrical ground 130, and a second SCR 2350b coupled between node 120b and electrical ground 130. As ​ The lateral surge protection device 2200 shown may include a cell isolation trench 2318 extending through the semiconductor layer 2310 and into the substrate 2310a (e.g., a p-type substrate) where the semiconductor layer 2310 is disposed, in order to provide electrical isolation (e.g., to prevent cross current flow) between SCRs 2350a and 3250b in the semiconductor layer 2310.

[0069] ​ It shows a lateral SCR device (such as, as ​ The device 400 variant ​ This is a cross-sectional view of a portion of the design layout 2400 for device 2100 shown. For illustrative and reference purposes, the part with the 2400 serial number is shown. ​ Components and ​ The components used correspond to those with the serial number 400. For example... ​As shown, the SCR device 2400 includes a p-type well 2463 and an n-type well 2467. The device 2400 further includes an n-type injector 2474 surrounded by (e.g., runway-configured) p-type injector 2462, both disposed within the well 2463. The device 2400 further includes an n-type injector 2466 surrounded by p-type injector 2464, both disposed within the well 2467. An isolation trench 2458 surrounds (e.g., well 2467) and is disposed between wells 2463 and 2467. Similarly, as... ​ As shown, the SCR includes unit isolation trenches 2418, such as those related to... ​ , ​ , ​ and ​ The unit isolation trench is described.

[0070] The various devices and techniques described herein can be implemented using a variety of semiconductor processing and / or packaging techniques. Some embodiments can be implemented using various types of semiconductor processing techniques associated with semiconductor substrates, including but not limited to, silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), etc.

[0071] While certain features of the described embodiments have been illustrated herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations falling within the scope of the embodiments. It should be understood that these modifications and variations are presented by way of example only and not limitation, and various changes in form and detail are possible. Any parts of the apparatus and / or methods described herein can be combined in any arbitrary combination, except for mutually exclusive combinations. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A surge protection device, the surge protection device comprising: A semiconductor layer, wherein the semiconductor layer is of a first conductivity type; A lateral bipolar device, wherein the lateral bipolar device is disposed in the semiconductor layer, and the lateral bipolar device is a lateral thyristor rectifier; and An isolation trench is disposed in the semiconductor layer in the base region of the PNP transistor of the lateral thyristor rectifier. The isolation trench is disposed between the emitter implant and the collector implant of the PNP transistor, wherein the emitter implant and the collector implant are of a second conductivity type opposite to the first conductivity type.

2. The surge protection device according to claim 1, wherein: The base region of the PNP transistor is the first base region of the lateral thyristor rectifier; and The lateral thyristor rectifier further includes a second base region, which is the base region of the NPN transistor in the lateral thyristor rectifier. The semiconductor layer at least partially defines the base region of the PNP transistor.

3. The surge protection device according to claim 1, wherein the surge protection device further comprises: The first type of conductive material is injected along the sidewall of the isolation trench; and At least one of a dielectric material or undoped polysilicon, wherein the dielectric material or the undoped polysilicon is disposed within the isolation trench. The isolation trench terminates within the semiconductor layer.

4. A surge protection device, the surge protection device comprising: A semiconductor layer, wherein the semiconductor layer is P-type conductive; A first lateral NPN transistor and a second lateral NPN transistor are disposed in the semiconductor layer, each comprising: A collector implant, wherein the collector implant is disposed in the semiconductor layer, and the collector implant is n-type conductive; An emitter implant, wherein the emitter implant is disposed in the semiconductor layer, and the emitter implant is of n-type conductivity; and A base implant, wherein the base implant is disposed in the semiconductor layer adjacent to the emitter implant, and the base implant is p-type conductive; and An isolation trench is disposed in the base region of the lateral NPN transistor in the semiconductor layer, the isolation trench being disposed between the collector implant and the emitter implant, and also between the collector implant and the base implant. The first lateral NPN transistor and the second lateral NPN transistor are respectively the first segment and the second segment of the same NPN transistor.

5. The surge protection device of claim 4, wherein for each of the first lateral NPN transistor and the second lateral NPN transistor, the emitter implant is disposed between the isolation trench and the base implant, the surge protection device further comprising: For each of the first lateral NPN transistor and the second lateral NPN transistor, A first signal metal, which is electrically coupled to the emitter implant and the base implant; A second signal metal, which is electrically coupled to the first signal metal; A third signal metal, which is electrically coupled to the current collector implant; and A fourth signal metal, which is electrically coupled to the third signal metal.

6. The surge protection device of claim 4, wherein for each of the first lateral NPN transistor and the second lateral NPN transistor, the base implant is disposed between the isolation trench and the emitter implant, the surge protection device further comprising: For each of the first lateral NPN transistor and the second lateral NPN transistor, A first signal metal, which is electrically coupled to the emitter implant and the base implant; A second signal metal, which is electrically coupled to the first signal metal; A third signal metal, which is electrically coupled to the current collector implant; and A fourth signal metal, which is electrically coupled to the third signal metal.

7. A surge protection device, the surge protection device comprising: A semiconductor layer, wherein the semiconductor layer is P-type conductive; A first lateral NPN transistor and a second lateral NPN transistor are disposed in the semiconductor layer, each comprising: A collector implant, wherein the collector implant is disposed in the semiconductor layer, and the collector implant is n-type conductive; An emitter implant, wherein the emitter implant is disposed in the semiconductor layer, and the emitter implant is of n-type conductivity; and A base implant, wherein the base implant is disposed in the semiconductor layer adjacent to the emitter implant, and the base implant is p-type conductive; and An isolation trench is disposed in the base region of the lateral NPN transistor in the semiconductor layer, the isolation trench being disposed between the collector implant and the emitter implant, and also between the collector implant and the base implant. The emitter implant of the first lateral NPN transistor, the base implant of the first lateral NPN transistor, the emitter implant of the second lateral NPN transistor, and the base implant of the second lateral NPN transistor are electrically coupled to each other via at least a first signal metal.

8. The surge protection device according to claim 7, wherein, For each of the first lateral NPN transistor and the second lateral NPN transistor, the base implant is disposed between the isolation trench and the emitter implant, and the surge protection device further includes: for each of the first lateral NPN transistor and the second lateral NPN transistor A first signal metal, which is electrically coupled to the emitter implant and the base implant; A second signal metal, which is electrically coupled to the first signal metal; A third signal metal, the third signal metal being electrically coupled to the collector implant; and A fourth signal metal, which is electrically coupled to the third signal metal.

9. A surge protection device, the surge protection device comprising: A semiconductor layer, wherein the semiconductor layer is N-type conductive; A lateral thyristor rectifier, wherein the lateral thyristor rectifier is disposed in the semiconductor layer, the lateral thyristor rectifier comprising: A first p-type implant is disposed in the semiconductor layer and is included in the emitter of the PNP transistor of the lateral thyristor rectifier. The first n-type implant is disposed in the semiconductor layer and is included in the base of the PNP transistor and the collector of the NPN transistor of the lateral thyristor rectifier. The second p-type implant is disposed in the semiconductor layer and is included in the collector of the PNP transistor and the base of the NPN transistor. A second n-type implant, disposed in the semiconductor layer, and included in the emitter of the NPN transistor; and An isolation trench is disposed in the semiconductor layer in the base region of the PNP transistor and the collector region of the NPN transistor, wherein at least a portion of the semiconductor layer is included in the base region of the PNP transistor and the collector region of the NPN transistor.

10. The surge protection device according to claim 9, wherein the surge protection device further comprises: The n-type well is disposed in the semiconductor layer, the first p-type implant and the first n-type implant are disposed in the n-type well, and the n-type well is included in the base of the PNP transistor and the collector of the NPN transistor. and A p-type well is disposed in the semiconductor layer, and the second p-type implant and the second n-type implant are disposed in the p-type well. The p-type well is included in the collector of the PNP transistor and the base of the NPN transistor. The isolation trench is disposed between the n-type well and the p-type well.

11. The surge protection device according to claim 9, wherein the lateral thyristor rectifier is a first lateral thyristor rectifier, the PNP transistor is a first PNP transistor, the NPN transistor is a first NPN transistor, and the isolation trench is a first isolation trench, the surge protection device further comprising a second lateral thyristor rectifier, the second lateral thyristor rectifier comprising: The third p-type implant is disposed in the semiconductor layer and is included in the emitter of the second PNP transistor, which is included in the second lateral thyristor rectifier. The third n-type implant is disposed in the semiconductor layer and is included in the base of the second PNP transistor and the collector of the second NPN transistor, the second NPN transistor being included in the second lateral thyristor rectifier; A fourth p-type implant, wherein the fourth p-type implant is disposed in the semiconductor layer, and the fourth p-type implant is included in the collector of the second PNP transistor and the base of the second NPN transistor; A fourth n-type implant, wherein the fourth n-type implant is disposed in the semiconductor layer and the fourth n-type implant is included in the emitter of the second NPN transistor; and A second isolation trench is disposed in the semiconductor layer in the base region of the second PNP transistor and the collector region of the second NPN transistor, wherein at least a portion of the semiconductor layer is included in the base region of the second PNP transistor and the collector region of the second NPN transistor.

12. The surge protection device of claim 11, wherein the second p-type injector, the second n-type injector, the fourth p-type injector, and the fourth n-type injector are electrically coupled to each other via at least a first signal metal.

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