Semiconductor device, method for manufacturing a semiconductor device

Abstract

To provide semiconductor devices with small warpage.SOLUTION: A semiconductor device has a semiconductor substrate having a first surface, a second surface opposite the first surface, and an outer contour, and an impurity region located on the first surface side in the semiconductor substrate, and the second surface has a plurality of recesses, each of the plurality of recesses opening toward the side opposite the first surface and extending along a direction perpendicular to the direction in which the semiconductor substrate is most likely to warp.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

Background Art

[0002] A semiconductor device is manufactured by forming semiconductor elements on a semiconductor substrate. The semiconductor substrate has a thin flat plate shape and is commonly referred to as a wafer. Flatness is desired for the semiconductor substrate.

[0003] Patent Document 1 discloses a technique for forming a mesh-shaped convex wall and a plurality of concave portions on the back surface of a semiconductor substrate to reduce substrate resistance while suppressing warping of the substrate. Patent Document 2 discloses a trench for discretely partitioning a semiconductor on one surface of a semiconductor substrate. Patent Document 3 is related to the present disclosure.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] Photogravure is used when forming semiconductor devices on a wafer. In this photogravure process, flatness is desired on the wafer surface on which the semiconductor device is formed. This surface is curved due to various factors. When photogravure is applied to a curved wafer surface, the exposure focus shifts. This shift in focus causes the dimensions of the resist used for patterning in the photogravure process to differ from the expected dimensions. This difference degrades the electrical characteristics of the manufactured semiconductor device. The larger the wafer diameter, the greater the effect of the curvature on the focus shift. From the viewpoint of improving the yield of semiconductor devices, a larger wafer diameter is desirable.

[0006] It is presumed that the process of forming the striped trenches disclosed in Patent Document 2 is easier than the process of forming the mesh-like protruding walls disclosed in Patent Document 1. However, Patent Document 2 does not consider warping and does not mention the direction in which the striped trenches are aligned.

[0007] This disclosure aims to provide semiconductor devices with minimal warping. [Means for solving the problem]

[0008] The semiconductor device according to this disclosure comprises a semiconductor substrate having a first surface, a second surface facing the first surface, and an outer shell, and an impurity region located on the first surface side of the semiconductor substrate, wherein the semiconductor element is From the first surface to the second surface The provided region's second surface has a plurality of recesses, each of which opens toward the opposite side of the first surface, extends along a direction perpendicular to the direction in which the semiconductor substrate is most prone to warping, penetrates the impurity region from the first surface toward the second surface along the direction from the first surface toward the second surface, and is further provided with a second electrode located without overlapping with the plurality of recesses when viewed along the direction from the first surface toward the second surface.

[0009] A method for manufacturing a semiconductor device according to this disclosure comprises a first step, a second step, a third step, and a fourth step. In the first step, a semiconductor substrate having a first surface and a second surface facing the first surface is made to form a plurality of recesses, each opening toward the opposite side from the first surface, into which a semiconductor element is formed. From the first surface to the second surface The impurity region is formed on the second surface of the region to be provided. The second step is to form an impurity region on the first surface after the first step. The third step is to form a first electrode on the second surface after the second step. The fourth step is to form a second electrode that penetrates the impurity region from the first surface towards the second surface in the direction from the first surface towards the second surface, and is positioned without overlapping with the plurality of recesses when viewed in the direction from the first surface towards the second surface. [Effects of the Invention]

[0010] The semiconductor device of this disclosure has low warping. The method for manufacturing the semiconductor device of this disclosure manufactures a semiconductor device with low warping. [Brief explanation of the drawing]

[0011] [Figure 1] This is a cross-sectional view illustrating a semiconductor device according to Embodiment 1. [Figure 2] This is a plan view illustrating a semiconductor substrate. [Figure 3] This is a plan view illustrating a semiconductor substrate. [Figure 4] This is a cross-sectional view at position AA in Figure 3. [Figure 5] This is a cross-sectional view at position BB in Figure 3. [Figure 6] This is a cross-sectional view at position CC in Figure 3. [Figure 7] This is a cross-sectional view illustrating a semiconductor device to be compared with Embodiment 1. [Figure 8] This is a plan view showing another example of a groove. [Figure 9] This is a cross-sectional view showing the vicinity of the terminal end. [Figure 10] This is a cross-sectional view showing the deformation of the positional relationship between the groove and the drain electrode. [Figure 11] It is a plan view illustrating a semiconductor substrate according to Embodiment 2. [Figure 12] It is a cross-sectional view when the semiconductor substrate is curved into a dome shape. [Figure 13] It is a cross-sectional view when the semiconductor substrate is curved into a dome shape. [Figure 14] It is a cross-sectional view illustrating a semiconductor device according to Embodiment 3. [Figure 15] It is a cross-sectional view illustrating another semiconductor device according to Embodiment 3. [Figure 16] It is a plan view showing a semiconductor substrate according to Embodiment 4. [Figure 17] It is a plan view showing another semiconductor substrate according to Embodiment 4. [Figure 18] It is a cross-sectional view showing a semiconductor substrate according to Embodiment 5. [Figure 19] It is a cross-sectional view showing a semiconductor substrate according to Embodiment 5. [Figure 20] It is a flowchart illustrating an outline of a method for manufacturing a semiconductor device according to Embodiment 6. [Figure 21] It is a cross-sectional view explaining the first step. [Figure 22] It is a cross-sectional view explaining the first step. [Figure 23] It is a cross-sectional view explaining the second step. [Figure 24] It is a cross-sectional view explaining the second step. [Figure 25] It is a cross-sectional view explaining the second step. [Figure 26] It is a cross-sectional view explaining the second and third steps. [Figure 27] It is a cross-sectional view explaining the second step. [Figure 28] It is a cross-sectional view explaining the second step. [Figure 29] It is a cross-sectional view explaining the second step. [Figure 30] It is a cross-sectional view explaining the second and third steps.

BEST MODE FOR CARRYING OUT THE INVENTION

[0012] <Embodiment 1> Figure 1 is a cross-sectional view illustrating a semiconductor device 300 according to Embodiment 1 of the present disclosure. The semiconductor device 300 has a semiconductor substrate 100 and a semiconductor element 21. The semiconductor element 21 is formed on the semiconductor substrate 100.

[0013] The semiconductor substrate 100 has a surface 101 and a surface 102. Surface 102 faces surface 101. For convenience in the following description, the Z-axis is defined as the positive direction from surface 102 to surface 101. A right-handed XYZ coordinate system is set with respect to the Z-axis. Figure 1 is a cross-sectional view of the semiconductor device 300 as seen along the positive direction of the Y-axis (hereinafter referred to as "direction Y").

[0014] For example, silicon is used as the material for the semiconductor substrate 100. For example, silicon carbide is used as the material for the semiconductor substrate 100. For example, the semiconductor substrate 100 is a silicon carbide substrate composed of epitaxial layers. Silicon carbide is a so-called wide-bandgap semiconductor.

[0015] Surface 102 has multiple grooves 10. The grooves 10 can be described as recesses that open on the side opposite to surface 101. Figure 1 illustrates a case where the grooves 10 extend along direction Y and are aligned along the positive direction of the X axis (hereinafter referred to as "direction X").

[0016] In Figure 1, the semiconductor element 21 is exemplified as a field-effect transistor having a MOS (Metal Oxide Semiconductor) structure. Specifically, the semiconductor element 21 includes a drain electrode 1, a semiconductor layer 2, a well region 3, a source region 4, a gate electrode 6, and a source electrode 8. In Figure 1, an example is shown where the semiconductor element 21 further includes a contact region 5, an interlayer insulating film 7, and a barrier metal 9.

[0017] The semiconductor substrate 100 has the same conductivity type on surface 101 and surface 102. The semiconductor substrate 100 functions as a semiconductor layer 2. The semiconductor layer 2 is, for example, n -This is an epitaxial layer of type 2. The impurity concentration of semiconductor layer 2 is appropriately selected, for example, taking into consideration the breakdown voltage required for semiconductor device 300.

[0018] Well region 3 is, for example, a p-type impurity region. Source region 4 is, for example, an n-type impurity region. Contact region 5 is, for example, p + This is the impurity region of the type.

[0019] Well region 3 is selectively located on the surface 101 side in the semiconductor layer 2. In cross-sectional view, a pair of source regions 4 is selectively located on the surface 101 side for each well region 3.

[0020] In Figure 1, the contact region 5 is sandwiched between a pair of source regions 4 facing direction X and surrounded by the well region 3. The contact region 5 is adjacent to the source electrode 8 in the positive Z-axis direction (hereinafter referred to as "direction Z") via the barrier metal 9. The contact region 5 may be omitted.

[0021] The gate electrode 6 is adjacent to the semiconductor layer 2, the well region 3, and the source region 4 from the opposite side of the surface 102, via a gate oxide film (not shown).

[0022] The interlayer insulating film 7 covers the gate electrode 6 from the side opposite to the surface 102. The interlayer insulating film 7 is adjacent to the source electrode 8 via a barrier metal 9. For the interlayer insulating film 7, materials such as TEOS (tetraethyl orthosilicate) or BPSG (borophosphosilicate glass) are used.

[0023] The drain electrode 1 is positioned in contact with surface 102 from the opposite side of surface 101. Figure 1 illustrates the case where the drain electrode 1 is also located in groove 10.

[0024] Figure 2 is a plan view illustrating a semiconductor substrate 100A, which is used as the semiconductor substrate 100. Figure 2 is a plan view taken along the direction opposite to direction Z. Since surface 101 is on the Z side of surface 102, a dashed line is used for the leader line indicating surface 101 in Figure 2.

[0025] The semiconductor substrate 100A has an outer casing 103. In plan view, the outer casing 103 has a curve 103r and an orientation flat 103c. The curve 103r is approximately a circular arc. The central axis 100Q of this arc is exemplified. In Figure 2, the orientation flat 103c shows a straight line parallel to the Y-axis. Whether or not the groove 10 passes through the central axis 100Q is irrelevant.

[0026] The orientation flat 103c is formed parallel to the <11-20> axis of the crystal orientation when the semiconductor substrate 100A is a silicon carbide substrate. However, the relationship between the direction of the orientation flat 103c and the crystal orientation is not essential to obtain the effects described later.

[0027] In Figure 2, consistent with Figure 1, an example is shown where the grooves 10 extend along direction Y and are aligned along direction X. However, in Figure 2, the number of grooves 10 is omitted compared to the example in Figure 1.

[0028] The more grooves 10 there are, the greater the effect in reducing the warping of the semiconductor substrate 100A and, consequently, the semiconductor device 300, as described later. The fewer grooves 10 there are, the higher the rigidity of the semiconductor substrate 100A and, consequently, the semiconductor device 300.

[0029] The width of the groove 10 is, for example, several micrometers to several millimeters. The width of the groove 10 may widen or narrow as it moves away from the surface 101. The case in which the width of the groove 10 widens as it moves away from the surface 101 will be described later as a variation of this embodiment.

[0030] The spacing between the grooves 10 is, for example, several micrometers to several tens of millimeters. The spacing between the grooves 10 may or may not be equal. The case where the spacing between the grooves 10 is not equal will be explained in Embodiment 4.

[0031] The depth of the groove 10 is, for example, 1 μm to 10 μm. The deeper the groove 10, the greater the effect in reducing the warping described later. The shallower the groove 10, the higher the rigidity of the semiconductor substrate 100A, and consequently the semiconductor device 300.

[0032] The depths of the grooves 10 may be equal or different. The case where the grooves 10 have different depths will be explained in Embodiment 5.

[0033] If the semiconductor substrate 100 does not have grooves 10, the semiconductor substrate 100 will bend due to various factors. For example, ion implantation and thermal oxidation, which will be described later, when forming the semiconductor element 21, can be factors that cause the semiconductor substrate 100 to bend. By using a semiconductor substrate 100A having grooves 10, the bending of the semiconductor substrate 100 is reduced. It is desirable that the grooves 10 extend in a direction that has a specific relationship with the direction in which the semiconductor substrate 100 is prone to warping. Before explaining this specific relationship, the direction in which warping is likely will be explained below.

[0034] Figure 3 is a plan view illustrating semiconductor substrate 100B. Semiconductor substrate 100B differs from semiconductor substrate 100A in that surface 102 does not have grooves 10. Figure 3 is a plan view along direction Z. Since surface 102 is on the opposite side of direction Z from surface 101, a dashed line is used to indicate surface 102 in Figure 3.

[0035] Figure 4 is a cross-sectional view at position AA in Figure 3. Figure 4 shows a cross-section including the central axis 100Q of the semiconductor substrate 100B as viewed along direction X. Figure 5 is a cross-sectional view at position BB in Figure 3. Figure 5 shows a cross-section including the central axis 100Q of the semiconductor substrate 100B as viewed along the (X+Y) direction. Here, "(X+Y) direction" is a provisional name for the direction that makes a 45-degree angle to both direction X and direction Y when viewed along direction Z. In Figure 5, "(XY)" indicates the (XY) direction. Here, "(XY) direction" is a provisional name for the direction that makes a 45-degree angle to direction X and a 135-degree angle to direction Y when viewed along direction Z. Figure 6 is a cross-sectional view at position CC in Figure 3. Figure 6 shows a cross-section including the central axis 100Q of the semiconductor substrate 100B as viewed along direction Y.

[0036] In Figures 3 to 6, the direction Z is adopted when the semiconductor substrate 100B is not curved. Figures 3 to 6 illustrate a curve in which the surface 101 is convex along a direction perpendicular to the orientation flat 103c.

[0037] In Figure 4, position 20a indicates the position of the semiconductor substrate 100B that is furthest to the Z-direction side in the cross-sectional view. Distance Δa is the distance along the Z-direction between position 20a and the position furthest away from the Z-direction side in the cross-sectional view.

[0038] In Figure 5, position 20b indicates the position of the semiconductor substrate 100B that is furthest to the Z-direction side in the cross-sectional view. Distance Δb is the distance along the Z-direction between the position furthest away from the Z-direction side in the cross-sectional view and position 20b.

[0039] In Figure 6, position 20c indicates the position of the semiconductor substrate 100B that is furthest to the Z-direction side in the cross-sectional view. Distance Δc is the distance along the Z-direction between the position furthest away from the Z-direction side in the cross-sectional view and position 20c.

[0040] The distances Δa, Δb, and Δc are quantitative indicators of the warpage of the semiconductor substrate 100B. In the examples shown in Figures 3 to 6, Δa < Δb < Δc, indicating that the semiconductor substrate 100B has almost no warpage along direction Y and warps most along direction X. It can be said that the semiconductor substrate 100B is most prone to warping along direction X.

[0041] Such warping of the semiconductor substrate 100B is caused by factors such as the method of holding the semiconductor substrate 100B. Regardless of whether it is semiconductor substrate 100A or 100B, the semiconductor substrate 100 is often stored with the orientation flat 103c facing vertically upward or vertically downward. When removing the semiconductor substrate 100 stored in this manner from its storage position, air tweezers, for example, are used.

[0042] When the semiconductor substrate 100 is stored with the orientation flat 103c facing vertically upward, the air tweezers hold the semiconductor substrate 100 horizontally, straddling the vicinity of the orientation flat 103c. Due to this holding, the semiconductor substrate 100B moves vertically downward as it moves away from the orientation flat 103c due to its own weight. Due to this holding, the semiconductor substrate 100 is prone to significant warping near the curve 103r opposite to the orientation flat 103c.

[0043] When the semiconductor substrate 100 is stored with the orientation flat 103c facing vertically downward, the air tweezers hold the semiconductor substrate 100 horizontally, straddling the vicinity of the curve 103r on the opposite side of the orientation flat 103c. Due to this holding, the semiconductor substrate 100B is directed vertically downward as it approaches the orientation flat 103c due to its own weight. This holding makes the semiconductor substrate 100 prone to significant warping near the orientation flat 103c.

[0044] As can be seen from the examples using semiconductor substrate 100B in Figures 4 to 6, for example, when the vicinity of the orientation flat 103c of the semiconductor substrate 100 is grasped with air tweezers and held with surface 101 facing upwards, surface 101 becomes convex and the semiconductor substrate 100 is prone to warping.

[0045] When the semiconductor substrate 100 is held with air tweezers gripping the vicinity of the orientation flat 103c and with the surface 102 facing upwards, the surface 102 becomes convex, making the semiconductor substrate 100 prone to warping.

[0046] By holding the semiconductor substrate 100 in this manner, the semiconductor substrate 100 is most prone to warping in the direction perpendicular to the orientation flat 103c, whether surface 101 is convex or surface 102 is convex. It can also be said that the direction in which the semiconductor substrate 100 is most prone to warping is the direction perpendicular to the orientation flat 103c. This tendency of the semiconductor substrate 100 to warp becomes more pronounced as the diameter of the semiconductor substrate 100 increases.

[0047] When the semiconductor substrate 100 is made of silicon carbide, warping is likely to occur due to the influence of the precision required when cutting the silicon carbide as a wafer, residual strain during processing and polishing of the front and back surfaces, and internal stress in the silicon carbide crystals.

[0048] As illustrated in Figure 2, the grooves 10 of the semiconductor substrate 100A extend parallel to the orientation flat 103c. The grooves 10 are aligned along a direction perpendicular to the orientation flat 103c. When the semiconductor substrate 100 is most prone to warping in the direction perpendicular to the orientation flat 103c, using semiconductor substrate 100A as the semiconductor substrate 100 allows each of the grooves 10 to reduce the warping of the semiconductor substrate 100. Regardless of whether the surface 101 or 102 warps convexly, the grooves 10 reduce the warping of the semiconductor substrate 100.

[0049] Figure 7 is a cross-sectional view illustrating a semiconductor device 300B compared to Embodiment 1 of the present disclosure. Figure 7 is a cross-sectional view of the semiconductor device 300B viewed along direction Y.

[0050] The semiconductor device 300B differs from the semiconductor device 300 in that a semiconductor substrate 100B is used instead of the semiconductor substrate 100. The semiconductor device 300B also differs from the semiconductor device 300 in that there is no groove 10 on surface 102.

[0051] The semiconductor substrate 100 used in the semiconductor device 300 is less prone to warping than the semiconductor substrate 100B used in the semiconductor device 300B. Both the well region 3 and the source region 4 in the semiconductor device 300B are common in that they are impurity regions formed on the surface 101. From this perspective, the term "surface impurity region" is used below to refer to "one or both of the well region 3 and the source region 4." Surface impurity regions tend to form wider than expected, for example, due to focus misalignment in photolithography. The formation of surface impurity regions outside the expected range is a factor in the electrical characteristics, including the voltage threshold characteristics of the field-effect transistor realized by the semiconductor element 21, differing from the expected values, and can lead to defects.

[0052] The semiconductor substrate 100, which has grooves 10 on surface 102, exhibits less focus shift in the photogravure process that forms surface impurity regions on surface 101 compared to the semiconductor substrate 100B, which does not have grooves 10. This reduced shift reduces the degree to which the electrical characteristics of the field-effect transistor realized by the semiconductor element 21 differ from the expected values, and also reduces the degree of defect occurrence.

[0053] The grooves 10 on surface 102 reduce the warping of the semiconductor substrate 100 and, consequently, the semiconductor device 300 using the semiconductor substrate 100. Reducing the warping of the semiconductor device 300 reduces the variation in the range over which the surface impurity region extends. Reducing the variation in this range reduces the variation in the characteristics of the semiconductor element 21, which includes the surface impurity region.

[0054] Figure 8 is a plan view showing another example of groove 10. Figure 8 is a plan view of the semiconductor substrate 100C viewed along direction Z.

[0055] Figure 8 differs from the semiconductor substrate 100A in that it contains not only grooves 10 extending parallel to the orientation flat 103c, but also grooves 10C extending perpendicular to the orientation flat 103c.

[0056] The semiconductor substrate 100C can be used as the semiconductor substrate 100. When the semiconductor substrate 100 is most prone to warping in the direction perpendicular to the orientation flat 103c, the groove 10C may increase the warping of the semiconductor substrate 100. From the standpoint of reducing this possibility and simplifying the process of forming the groove 10, the semiconductor substrate 100A is more suitable than the semiconductor substrate 100C for use as the semiconductor substrate 100.

[0057] For example, the groove 10 exists even at a location away from the semiconductor element 21. Figure 9 is a cross-sectional view showing the vicinity of the termination portion 23 of the semiconductor device 300.

[0058] The termination portion 23 includes a semiconductor layer 2, a well region 3, a guard ring 51, and a source electrode 8. The well region 3 is selectively located on the surface 101 side of the semiconductor layer 2. The guard ring 51 is selectively located on the surface 101 in the well region 3. The guard ring 51 is, for example, P + This is the impurity region of the type. The well region 3 and guard ring 51 are covered from the opposite side of surface 102 by the interlayer insulating film 7. The interlayer insulating film 7 is interposed between the source electrode 8 and barrier metal 9 and the well region 3 and guard ring 51.

[0059] The groove 10 reduces warping of the semiconductor substrate 100, and consequently the semiconductor device 300, near the termination portion 23.

[0060] Figure 10 is a cross-sectional view showing a deformation in the positional relationship between the groove 10 and the drain electrode 1. Figure 10 is a cross-sectional view along direction Y. In this deformation, the drain electrode 1 does not fill the groove 10. In this deformation, the drain electrode 1 exhibits an uneven surface that reflects the shape of the groove 10. This uneven surface of the drain electrode 1 improves the heat dissipation of the semiconductor device 300 that has been diced into a chip shape. Specifically, for heat dissipation of the semiconductor device 300 that has been diced into a chip shape, elements for heat dissipation, such as die bonding of the drain electrode 1 to a heat sink, are employed. The bonding material used for die bonding, such as solder, enters the recesses of the drain electrode 1, improving the adhesion between the heat sink and the drain electrode 1. This improvement in adhesion improves heat dissipation.

[0061] As the groove 10 moves away from the surface 101, its width increases, making it easier for the solder to enter the recess of the drain electrode 1. The groove 10 does not necessarily need to have a drain electrode 1 at all.

[0062] The above description of the modifications can be applied to all of the following embodiments.

[0063] <Embodiment 2> The process of forming impurity regions on the semiconductor substrate 100 can also be a factor in the warping of the semiconductor substrate 100. For example, the well region 3, source region 4, and contact region 5 are formed using photolithography and ion implantation. Photolithography and ion implantation are performed on the semiconductor substrate 100 from the surface 101 side. Ion implantation disrupts the atomic arrangement of the semiconductor substrate 100 material, such as silicon carbide. This disruption of atomic arrangement can cause the surface 101 to expand, and consequently, the semiconductor substrate 100 to warp with the surface 101 convex.

[0064] The interlayer insulating film 7 is formed by heat treatment of the semiconductor substrate 100. The thermal expansion coefficient of silicon oxide is smaller than that of silicon or silicon carbide. The amount by which the interlayer insulating film 7, formed at high temperature, shrinks at room temperature is smaller than the amount by which the semiconductor substrate 100, exposed to high temperature during the formation of the interlayer insulating film 7, shrinks at room temperature. The interlayer insulating film 7 is formed on the surface 101 side of the semiconductor substrate 100. The difference in the amount of shrinkage described above can cause the semiconductor substrate 100 to warp with its surface 101 convex.

[0065] The formation of a metal film with a thickness of several micrometers on the semiconductor substrate 100 from the surface 101 side can also be a factor in the semiconductor substrate 100 warping with its surface 101 convex.

[0066] Due to these factors, the semiconductor substrate 100 tends to bend into a dome shape with its surface 101 convex around the central axis 100Q. It can also be said that the semiconductor substrate 100 is most prone to warping along the radial direction, away from the central axis 100Q, where the surface 101 becomes convex.

[0067] Figure 11 is a plan view illustrating a semiconductor substrate 100D according to Embodiment 2. Figure 11 is a plan view along direction Z. Since surface 101 is on the Z side of surface 102, a dashed line is used for the leader line indicating surface 102 in Figure 11. The description of the outer frame 103 and central axis 100Q for semiconductor substrate 100A also applies to semiconductor substrate 100D. Semiconductor substrate 100D can be used as semiconductor substrate 100 of semiconductor device 300.

[0068] The semiconductor substrate 100D differs from the semiconductor substrate 100A in the shape of the grooves 10. In the semiconductor substrate 100D, each of the multiple grooves 10 extends in an annular shape. The multiple grooves 10 do not intersect each other on the surface 102. The multiple grooves 10 are, for example, concentric ellipses or concentric circles centered on the central axis 100Q. Figure 11 illustrates the radial direction R and the circumferential direction θ. The circumferential direction θ is the direction of rotation around the central axis 100Q and is counterclockwise when viewed along direction Z.

[0069] Figures 12 and 13 are cross-sectional views of the semiconductor substrate 100B when it is curved in a dome shape with the surface 101 convex around the central axis 100Q. Figure 12 is a cross-sectional view at position AA in Figure 3. Figure 12 shows a cross-section of the semiconductor substrate 100B including the central axis 100Q as viewed along direction X. Figure 13 is a cross-sectional view at position BB in Figure 3. Figure 13 shows a cross-section of the semiconductor substrate 100B including the central axis 100Q as viewed along the (X+Y) direction. In Figures 11 to 13, direction Z is used when the semiconductor substrate 100 is not curved.

[0070] In Figure 12, position 20d indicates the position of the semiconductor substrate 100B that is furthest towards the Z direction in a cross-sectional view. Here, position 20d represents the position in the Z direction relative to the central axis 100Q. Distance Δd1 is the distance along the Z direction between position 20d and the position furthest from the central axis 100Q in the Y direction in a cross-sectional view. Distance Δd2 is the distance along the Z direction between position 20d and the position furthest from the central axis 100Q in the direction opposite to the Y direction in a cross-sectional view.

[0071] In Figure 13, position 20e indicates the position of the semiconductor substrate 100B that is furthest towards the Z direction in the cross-sectional view. Here, position 20e indicates the position in the Z direction relative to the central axis 100Q. Distance Δe1 is the distance along the Z direction between position 20e and the position furthest from the central axis 100Q in the direction opposite to the (XY) direction in the cross-sectional view. Distance Δe2 is the distance along the Z direction between position 20e and the position furthest from the central axis 100Q in the (XY) direction in the cross-sectional view.

[0072] The semiconductor substrate 100B curves along the radial direction, and the distances Δd1, Δd2, Δe1, and Δe2 are approximately the same value. It can also be said that the direction in which the semiconductor substrate 100 is most prone to warping is the radial direction R. This tendency of the semiconductor substrate 100 to warp becomes more pronounced as the diameter of the semiconductor substrate 100 increases. Furthermore, if the material of the semiconductor substrate 100 is silicon carbide, this warping is more likely to occur for the reasons mentioned above.

[0073] In this embodiment, the grooves 10 extend along the circumferential direction θ and are aligned along the radial direction R. The grooves 10 are, for example, concentric ellipses or concentric circles centered on the central axis 100Q and extend perpendicular to the radial direction R.

[0074] The grooves 10 in this embodiment and the grooves 10 in Embodiment 1 are similar in that they extend in a direction perpendicular to the direction in which the semiconductor substrate 100 is most prone to warping and are aligned along the direction in which it is most prone to warping. In this embodiment, each of the grooves 10 on the surface 102 reduces warping when the semiconductor substrate 100 is most prone to warping in the radial direction. This reduction in warping reduces the warping of the semiconductor device 300 using semiconductor substrate 100D as the semiconductor substrate 100. This reduction in warping of the semiconductor device 300 reduces the variation in the range over which the surface impurity region extends. This reduction in variation in the range reduces the variation in the characteristics of the semiconductor element 21 including the surface impurity region.

[0075] <Embodiment 3> In Embodiment 1, the semiconductor element 21 formed on the semiconductor substrate 100 has a planar structure. In this embodiment, an example is given in which an element having a trench structure is formed on the semiconductor substrate 100. In this embodiment, any of semiconductor substrates 100A, 100C, or 100D may be used for the semiconductor substrate 100.

[0076] Figure 14 is a cross-sectional view illustrating a semiconductor device 400A according to Embodiment 3. Figure 14 is a cross-sectional view of the semiconductor device 400A viewed along direction Y. The semiconductor device 400A has a semiconductor substrate 100 and a semiconductor element 22. The semiconductor element 22 is formed on the semiconductor substrate 100.

[0077] The semiconductor device 400A differs from the semiconductor device 300 in that it is equipped with semiconductor element 22 instead of semiconductor element 21. Regarding the semiconductor device 400A, explanations that apply to the semiconductor device 300 are omitted.

[0078] In Figure 14, the semiconductor element 22 is exemplified as a field-effect transistor having a MOS structure. Specifically, the semiconductor element 22 includes a drain electrode 1, a semiconductor layer 2, a well region 3, a source region 4, a gate electrode 13, and a source electrode 8. In Figure 14, an example is shown where the semiconductor element 22 further includes an interlayer insulating film 7 and a barrier metal 9.

[0079] In Figure 14, the gate electrode 13 penetrates from surface 101 through the well region 3 and source region 4 in the direction opposite to direction Z, reaching a portion of the semiconductor layer 2 on the surface 101 side. However, the gate electrode 13 is adjacent to the semiconductor layer 2, well region 3, and source region 4 via a gate oxide film (not shown). The semiconductor element 22 has a trench structure.

[0080] The interlayer insulating film 7 covers the source region 4, a portion of the well region 3 adjacent to the source region 4, and the gate electrode 13 from the side opposite to the surface 102.

[0081] In such a semiconductor device 400A, the variation in the characteristics of the semiconductor element 22 is reduced by using the groove 10 described in Embodiment 1 or Embodiment 2.

[0082] Figure 15 is a cross-sectional view illustrating another semiconductor device 400B according to Embodiment 3. Figure 15 is a cross-sectional view of the semiconductor device 400B as seen along direction Y. The position of the groove 10 differs between semiconductor device 400B and semiconductor device 400A. Specifically, the groove 10 and the gate electrode 13 do not overlap when viewed along the Z direction.

[0083] In this embodiment, the multiple grooves 10 are aligned along direction X, and each of them extends along direction Y. There are no grooves 10 in the region S occupied by the gate electrode 13 in direction X. The absence of grooves 10 facing the gate electrode 13 contributes to not reducing the strength of the semiconductor substrate 100.

[0084] In both semiconductor devices 400A and 400B, a termination section 23 is provided, for example, similar to semiconductor device 300.

[0085] In either semiconductor device 400A or 400B, semiconductor substrates 100A, 100C, or 100D can be used as the semiconductor substrate 100.

[0086] <Embodiment 4> Figure 16 is a plan view showing semiconductor substrate 100E according to Embodiment 4 of the present disclosure. Figure 17 is a plan view showing semiconductor substrate 100F according to Embodiment 4 of the present disclosure. Both Figure 16 and Figure 17 are plan views along direction Z. Semiconductor substrate 100E and semiconductor substrate 100F differ in the non-uniformity of the spacing between the grooves 10. Except for the non-uniformity of the spacing between the grooves 10, both semiconductor substrate 100E and 100F are common to semiconductor substrate 100A.

[0087] In semiconductor substrate 100E, the spacing between adjacent first pairs of grooves 10 is greater than the spacing between adjacent first pairs of grooves 10, and the spacing between adjacent second pairs of grooves 10 is greater than the spacing between adjacent first pairs of grooves 10. In semiconductor substrate 100F, the spacing between adjacent first pairs of grooves 10 is greater than the spacing between adjacent first pairs of grooves 10, and the spacing between adjacent second pairs of grooves 10 is narrower than the spacing between adjacent first pairs of grooves 10.

[0088] Both semiconductor substrates 100E and 100F have higher rigidity compared to substrates where the spacing between grooves 10 is uniform, due to the non-uniformity of the spacing between the grooves 10. This high rigidity facilitates handling during the transport of semiconductor substrates 100E and 100F.

[0089] When the semiconductor substrate 100 is held in place near the orientation flat 103c, the curve 103r on the opposite side of the orientation flat 103c is prone to significant warping.

[0090] The semiconductor substrate 100F reduces either or both of the warpage near the orientation flat 103c and the opposite curve 103r, and the warpage near the orientation flat 103c.

[0091] The non-uniformity of the spacing between the grooves 10 may be applied to the semiconductor substrates 100C and 100D.

[0092] In a dome-shaped curvature, the vicinity of the outer edge 103 of the semiconductor substrate 100D is more prone to warping than the vicinity of the central axis 100Q. In the semiconductor substrate 100D, the distance between adjacent first pairs of grooves 10 in the radial direction R is narrower than the distance between adjacent first pairs of grooves 10, and the distance between adjacent second pairs of grooves 10 in the radial direction R is narrower than the distance between first pairs of grooves 10, and is closer to the outer edge 103 than first pairs, which reduces such dome-shaped curvature.

[0093] Both semiconductor substrates 100E and 100F can be used as semiconductor substrate 100 in semiconductor devices 300, 400A, and 400B, respectively.

[0094] <Embodiment 5> Figures 18 and 19 are cross-sectional views showing a semiconductor substrate 100G according to Embodiment 5 of the present disclosure. Figure 18 is a cross-sectional view of a cross section including the central axis 100Q, viewed along direction X. Figure 19 is a cross-sectional view of a cross section including the central axis 100Q, viewed along the direction opposite to direction Y. Whether or not the groove 10 passes through the central axis 100Q is irrelevant. Figures 18 and 19 illustrate the case where the groove 10 passes through the central axis 100Q.

[0095] Except for the non-uniformity of the depths of the grooves 10, semiconductor substrates 100H and 100A are common to semiconductor substrate 100G. In semiconductor substrate 100G, the depth of the grooves 10 is deeper the closer they are to the outer edge 103. Specifically, referring to Figure 18, the depth d2 of the grooves 10 near the outer edge 103 (which appears as curve 103r in Figure 18) is deeper than the depth d1 of the grooves 10 near the central axis 100Q in the direction Y. The same applies to the depth of the grooves 10 near the outer edge 103 (which appears as curve 103r in Figure 18) in the direction opposite to direction Y.

[0096] Referring to Figure 19, the depth d3 of the groove 10 near the outer rim 103 (which appears as curve 103r in Figure 19) on the side opposite to direction X is deeper than the depth d1 of the groove 10 near the central axis 100Q. The same is true for the depth of the groove 10 near the outer rim 103 (which appears as orientation flat 103c in Figure 19) on the side of direction X.

[0097] When the semiconductor substrate 100 is held by being sandwiched near the orientation flat 103c, the curve 103r on the opposite side of the orientation flat 103c is prone to significant warping. When the semiconductor substrate 100 is held by being sandwiched near the curve 103r on the opposite side of the orientation flat 103c, the area near the orientation flat 103c is prone to significant warping. In a dome-shaped curve, the semiconductor substrate 100 is prone to significant warping near the outer edge 103.

[0098] In the semiconductor substrate 100G, the grooves 10 are deeper closer to the outer edge 103. The spacing between them is narrow. The semiconductor substrate 100G reduces either or both of the warpage near the curve 103r opposite the orientation flat 103c and the warpage near the orientation flat 103c. In a dome-shaped curvature, the semiconductor substrate 100G reduces the warpage near the outer edge 103.

[0099] In the semiconductor substrate 100C, the depth of the groove 10 may be greater as it approaches the outer casing 103.

[0100] In the semiconductor substrate 100D, the depth of the groove 10 may be deeper as it approaches the outer edge 103. This is because, in a dome-shaped curvature, the area near the outer edge 103 of the semiconductor substrate 100D is more prone to warping than the area near the central axis 100Q.

[0101] <Embodiment 6> Embodiment 6 of this disclosure describes a method for manufacturing semiconductor devices 300, 400A, and 400B.

[0102] Figure 20 is a flowchart illustrating the general outline of the semiconductor device manufacturing method according to Embodiment 6. This manufacturing method broadly comprises a first step 91, a second step 92, and a third step 93, which are executed in this order.

[0103] The first step 91 is the step of forming grooves 10. Grooves 10 are formed on the surface 102 of the semiconductor substrate 100B, which does not have grooves 10 formed on it. This gives rise to the semiconductor substrate 100. Examples of semiconductor substrates 100 include semiconductor substrates 100A, 100C, 100D, 100E, 100F, and 100G.

[0104] The second step 92 is a step of forming a surface impurity region on surface 101. The third step 93 is a step of forming the drain electrode 1 on surface 102.

[0105] Figures 21 and 22 are cross-sectional views illustrating the first step 91. For convenience, the following explanation will illustrate the case where semiconductor substrate 100A is used as semiconductor substrate 100.

[0106] Figure 21 shows a cross-section of semiconductor substrate 100B viewed along direction Y. Figure 22 shows a cross-section of semiconductor substrate 100A viewed along direction Y.

[0107] The semiconductor substrate 100B is, for example, a silicon substrate or a silicon carbide substrate composed of an epitaxial layer. For example, the semiconductor substrate 100B is n - This is an epitaxial layer of silicon carbide in a mold.

[0108] A resist pattern (not shown) corresponding to the shape of the groove 10 is formed by photogravure processing on the surface 102. For example, a resist is applied to the surface 102, and an opening is formed in a predetermined area of ​​the resist using photogravure technology, thereby forming the resist pattern.

[0109] A resist pattern is used as a mask to etch silicon or silicon carbide to form grooves 10. After the grooves 10 are formed, the resist pattern is removed to obtain a semiconductor substrate 100A.

[0110] Semiconductor substrates 100C, 100D, 100E, 100F, and 100G are also obtained by the process described above. Compared to semiconductor substrate 100C, semiconductor substrates 100A, 100D, 100E, and 100F are easier to obtain with simpler processing.

[0111] Grooves 10 may be formed in the semiconductor substrate 100 by processing using dicing or laser dicing. For example, grooves 10 for obtaining the semiconductor substrate 100G are formed by processing using dicing or laser dicing.

[0112] Figures 23 to 26 are cross-sectional views illustrating the second process 92 in the manufacturing of the semiconductor device 300. All of Figures 23 to 26 are cross-sectional views along the direction Y.

[0113] Referring to Figures 22 and 23, well regions 3 are selectively formed on surface 101 of the semiconductor substrate 100A.

[0114] A mask (not shown) is formed to selectively cover surface 101, and p-type impurities, such as boron (B), are implanted using the mask. For example, a resist pattern is used for the mask. After the impurities are implanted, the impurity ions are diffused by post-heat treatment. This diffusion selectively forms, for example, multiple well regions 3 on surface 101.

[0115] The concentrations of p-type impurities in the well regions 3 can be the same. In this case, ion implantation can be performed simultaneously, which improves the productivity of the semiconductor device 300.

[0116] The depths of the well regions 3 may be the same. In this case, the electric field concentration in the well regions 3 is mitigated, and the breakdown voltage of the semiconductor device 300 is suppressed.

[0117] Multiple well regions 3 may be formed individually by using different masks. In this case, the depth of the well regions 3 and the concentration of p-type impurities can be varied by individually implanting p-type impurities into them.

[0118] Referring to Figures 23 and 24, a source region 4 and a contact region 5 are selectively formed on surface 101 of the semiconductor substrate 100A. As described above, the contact region 5 can be omitted. The step of forming the contact region 5 may be omitted.

[0119] By selectively injecting n-type impurities using a mask, an n-type source region 4 is formed on the surface 101 side of the well region 3. The injected n-type impurities are, for example, arsenic (As) or phosphorus (P).

[0120] By selectively injecting p-type impurities using a mask, p-type impurities are introduced into the surface 101 side of well region 3. + A contact region 5 of the specified type is formed.

[0121] In the structure shown in Figure 24, an oxide film (SiO2) is formed on the surface 101 side of the semiconductor substrate 100A by heating in an oxygen-containing atmosphere (not shown). On this oxide film, a polysilicon doped with n-type or p-type impurities is deposited, for example, by CVD (Chemical Vapor Deposition), to form the gate electrode 6.

[0122] Referring to Figures 24 and 25, an interlayer insulating film 7 is formed covering the gate electrode 6. The interlayer insulating film 7 is, for example, silicon dioxide (SiO2). The interlayer insulating film 7 is formed, for example, by thermal oxidation.

[0123] The portion of the oxide film formed before the formation of the gate electrode 6 that is not covered by the interlayer insulating film 7 is removed. The interlayer insulating film 7 forms a contact hole 70 that exposes the contact region 5 and a portion of the source region 4 that contacts the contact region 5.

[0124] Referring to Figures 25 and 26, a barrier metal 9 is formed on the surface 101 and the interlayer insulating film 7. The barrier metal 9 is formed, for example, by depositing titanium by PVD (Physical Vapor Deposition) or CVD.

[0125] A source electrode 8 is formed on the barrier metal 9. The source electrode 8 is formed, for example, by depositing an aluminum-silicon alloy (Al-Si alloy) onto the barrier metal 9 by PVD. Examples of PVD include sputtering and vapor deposition.

[0126] The semiconductor element 21A is shown in Figure 26. The semiconductor element 21A has a configuration in which the drain electrode 1 is absent from the semiconductor element 21. The semiconductor element 21A includes a surface impurity region. The termination portion 23 is formed in the same manner as the semiconductor element 21A.

[0127] A nickel alloy (Ni alloy) may be further formed on the formed aluminum-silicon alloy by electroless plating or electrolytic plating, and this configuration may be used as the source electrode 8. When the source electrode 8 is formed by plating, a thick metal film is easily formed for the source electrode 8. Using a thick metal film for the source electrode 8 increases its heat capacity and improves its heat resistance. Such plating may be performed in parallel with the third step 93, or after the third step 93.

[0128] The third step 93 will be described with reference to Figure 26, Figures 1 and 9. A drain electrode 1 is formed in contact with the surface 102 of the structure shown in Figure 26. The drain electrode 1 is formed across the semiconductor element 21A and the terminal portion 23. The drain electrode 1 is formed by PVD, for example, by depositing an aluminum-silicon alloy (Ai-Si alloy) or titanium (Ti). Examples of PVD include sputtering and vapor deposition. The drain electrode 1 may also be formed by volumes of multiple metals such as aluminum-silicon alloy, titanium, nickel, or gold.

[0129] A configuration in which a metal film is formed by electroless plating or electrolytic plating on a metal film formed by PVD may be used as the drain electrode 1. In this case, the plating of the source electrode 8 described above may be carried out in parallel.

[0130] The formation of the drain electrode 1 in this manner creates the semiconductor element 21 and the termination portion 23, thereby manufacturing the semiconductor device 300.

[0131] The drain electrode 1 does not necessarily need to have the groove 10 embedded. For example, by forming the groove 10 to a depth of several μm and forming the drain electrode 1 to a thickness of several nm, a drain electrode 1 without embedding the groove 10 can be obtained (see Figure 10).

[0132] Figures 27 to 30 are cross-sectional views illustrating the second process 92 in the manufacturing of the semiconductor device 400A. All of Figures 27 to 30 are cross-sectional views along the direction Y.

[0133] Referring to Figures 22 and 27, a well region 3 and a source region 4 are formed on the surface 101 of the semiconductor substrate 100A. A method for forming these is, for example, a method for forming the well region 3 and source region 4 when manufacturing the semiconductor device 300.

[0134] Referring to Figures 27 and 28, a trench 130 is formed from surface 101, penetrating the well region 3 and the source region 4 to the semiconductor layer 2. A gate electrode 13 is formed adjacent to the semiconductor layer 2, the well region 3, and the source region 4, via a gate oxide film (not shown) that fills the trench 130. Polysilicon is used as the material for the gate electrode 13. The methods for forming the gate oxide film and the gate electrode 13 are well known, so their explanation is omitted.

[0135] Referring to Figures 28 and 29, an interlayer insulating film 7 is selectively formed on surface 101, covering the source region 4, a portion of the well region 3 adjacent to the source region 4, and the gate electrode 13 from the side opposite to surface 102.

[0136] Referring to Figures 29 and 30, the barrier metal 9 and source electrode 8 are formed in the same manner as when manufacturing the semiconductor device 300. For example, the method used to form the barrier metal 9 and source electrode 8 when manufacturing the semiconductor device 300 is employed.

[0137] Figure 30 shows the semiconductor element 22A. The semiconductor element 22A has a configuration in which the drain electrode 1 is absent from the semiconductor element 22. The semiconductor element 22A includes a surface impurity region.

[0138] The third step 93 will be described with reference to Figures 30 and 14. A drain electrode 1 is formed on the surface 102 of the structure shown in Figure 30. A method for forming the drain electrode 1 is, for example, a method for forming the drain electrode 1 when manufacturing the semiconductor device 300.

[0139] The formation of the drain electrode 1 in this manner leads to the formation of the semiconductor element 22, and ultimately to the manufacture of the semiconductor device 400A.

[0140] When manufacturing the semiconductor device 400B, the position in which the grooves 10 are formed is restricted in the first step 91. Specifically, the grooves 10 are not formed in positions opposite to the region S where the trenches 130 will be formed later. This restriction on the position of the grooves 10 is achieved by appropriately setting the resist pattern used in the first step 91.

[0141] In the case of the semiconductor device 300, multiple semiconductor elements 21 and termination portions 23 are fabricated on a single semiconductor substrate 100, for example, in a matrix arrangement. These are then appropriately cut by laser dicing or blade dicing. The same applies to semiconductor devices 400A and 400B.

[0142] Furthermore, it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate.

[0143] The various aspects of this disclosure are summarized below as an appendix.

[0144] (Note 1) A semiconductor substrate having a first surface, a second surface opposite the first surface, and an outer shell, In the semiconductor substrate, the impurity region located on the first surface side and Equipped with, A semiconductor device wherein the second surface has a plurality of recesses, each of which opens toward the opposite side from the first surface and extends along a direction perpendicular to the direction in which the semiconductor substrate is most prone to warping.

[0145] (Note 2) The semiconductor substrate has the same conductivity type on the first surface and the second surface. The first electrode in contact with the second surface A semiconductor device as described in Appendix 1, further comprising the features described above.

[0146] (Note 3) The semiconductor device described in Appendix 2, wherein the first electrode does not fill the recess.

[0147] (Note 4) The aforementioned outer enclosure includes an orientation flat. Each of the plurality of recesses extends parallel to the orientation flat, according to any one of the appendices 1 to 3, the semiconductor device.

[0148] (Note 5) The semiconductor device according to any one of the appendices 1 to 3, wherein each of the plurality of recesses extends in an annular shape and does not intersect with each other on the second surface.

[0149] (Note 6) A semiconductor device according to any one of the appendices 1 to 5, wherein the spacing between adjacent first pairs of the plurality of recesses is narrower than the spacing between adjacent first pairs of the plurality of recesses between adjacent second pairs of the plurality of recesses, and the spacing between adjacent second pairs of the plurality of recesses is narrower than the spacing between adjacent first pairs of the plurality of recesses.

[0150] (Note 7) The second electrode penetrates the impurity region from the first surface towards the second surface along the direction from the first surface towards the second surface, and is located without overlapping with the plurality of recesses when viewed along that direction. A semiconductor device as described in any one of appendices 1 to 6, further comprising the features described.

[0151] (Note 8) The semiconductor device according to any one of the appendices 1 to 7, wherein the depth of the plurality of recesses is deeper the closer they are to the outer shell.

[0152] (Note 9) A semiconductor substrate having a first surface and a second surface facing the first surface, the first step is to form a plurality of recesses on the second surface, each of which opens toward the opposite side from the first surface, A second step is performed after the first step, in which an impurity region is formed on the first surface. A third step is to form electrodes on the second surface after the second step. A method for manufacturing a semiconductor device, comprising:

[0153] (Note 10) The semiconductor substrate has the same conductivity type on the first surface and the second surface. The method for manufacturing a semiconductor device according to Appendix 9, wherein the electrode is in contact with the second surface.

[0154] (Note 11) The method for manufacturing a semiconductor device as described in Appendix 10, wherein the electrode does not fill the recess.

[0155] (Note 12) The semiconductor substrate further has an outer shell including an orientation flat, Each of the plurality of recesses extends parallel to the orientation flat, the method for manufacturing a semiconductor device according to any one of appendices 9 to 11.

[0156] (Note 13) A method for manufacturing a semiconductor device according to any one of appendices 9 to 11, wherein each of the plurality of recesses extends in an annular shape and does not intersect with each other on the second surface. [Explanation of symbols]

[0157] 1 Drain electrode, 2 Semiconductor layer, 3 Well region, 4 Source region, 5 Contact region, 10 Groove, 13 Token electrode, 91 First process, 92 Second process, 93 Third process, 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G Semiconductor substrate, 101, 102 Surface, 103 Outline, 103c Orientation flat, R Radial direction, X, Y, Z directions, θ Circumferential direction.

Claims

1. A semiconductor substrate having a first surface, a second surface opposite the first surface, and an outer shell, In the semiconductor substrate, the impurity region located on the first surface side and Equipped with, The second surface of the region where the semiconductor element is provided from the first surface to the second surface has a plurality of recesses, each of which opens toward the opposite side from the first surface and extends along a direction perpendicular to the direction in which the semiconductor substrate is most prone to warping. The second electrode penetrates the impurity region from the first surface towards the second surface along the direction from the first surface towards the second surface, and is located without overlapping with the plurality of recesses when viewed along the direction from the first surface towards the second surface. A semiconductor device that further incorporates the following features.

2. A semiconductor substrate having a first surface, a second surface opposite the first surface, and an outer shell, In the semiconductor substrate, the impurity region located on the first surface side and Equipped with, The second surface has a plurality of recesses, each of which opens toward the opposite side from the first surface and extends along a direction perpendicular to the direction in which the semiconductor substrate is most prone to warping. A semiconductor device in which the depth of the plurality of recesses increases as they get closer to the outer casing.

3. The semiconductor substrate has the same conductivity type on the first surface and the second surface. The first electrode in contact with the second surface The semiconductor device according to claim 1 or 2, further comprising the above.

4. The semiconductor device according to claim 3, wherein the first electrode does not fill the recess.

5. The aforementioned outer enclosure includes an orientation flat. The semiconductor device according to claim 1 or 2, wherein each of the plurality of recesses extends parallel to the orientation flat.

6. The semiconductor device according to claim 1 or 2, wherein each of the plurality of recesses extends in an annular shape and does not intersect with each other on the second surface.

7. The semiconductor device according to claim 1 or 2, wherein the spacing between adjacent first pairs of the plurality of recesses is narrower than the spacing between adjacent first pairs of the plurality of recesses between adjacent second pairs of the plurality of recesses, and the spacing between adjacent second pairs of the plurality of recesses is narrower than the spacing between adjacent first pairs of the plurality of recesses.

8. A first step is to form a plurality of recesses on a semiconductor substrate having a first surface and a second surface facing the first surface, each recess opening toward the opposite side from the first surface, on the second surface in a region where a semiconductor element is provided extending from the first surface to the second surface. A second step is performed after the first step, in which an impurity region is formed on the first surface. A third step is performed after the second step, in which a first electrode is formed on the second surface. A fourth step is to form a second electrode that penetrates the impurity region from the first surface towards the second surface along the direction from the first surface towards the second surface, and is positioned without overlapping with the plurality of recesses when viewed along the direction from the first surface towards the second surface. A method for manufacturing a semiconductor device, comprising:

9. A semiconductor substrate having a first surface, a second surface facing the first surface, and an outer casing, is given a first step of forming a plurality of recesses on the second surface, each of which opens toward the opposite side from the first surface. A second step is performed after the first step, in which an impurity region is formed on the first surface. A third step is to form electrodes on the second surface after the second step. Equipped with, A method for manufacturing a semiconductor device, wherein the depth of the plurality of recesses is deeper the closer they are to the outer casing.

10. The semiconductor substrate has the same conductivity type on the first surface and the second surface. The method for manufacturing a semiconductor device according to claim 9, wherein the electrode is in contact with the second surface.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the electrode does not fill the recess.

12. The semiconductor substrate further has an outer shell including an orientation flat, The method for manufacturing a semiconductor device according to claim 8 or 9, wherein each of the plurality of recesses extends parallel to the orientation flat.

13. The method for manufacturing a semiconductor device according to claim 8 or 9, wherein each of the plurality of recesses extends in an annular shape and does not intersect with each other on the second surface.

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