An infinite impulse response filter and a method for implementing IIR filtering

Abstract

The present application discloses an infinite pulse response filter and a method for implementing the filtering thereof. The IIR filter provided in the embodiment of the present application utilizes synchronous sampling technology to perform IIR calculation on multi-channel parallel input data in a time-sharing manner, thereby improving the IIR calculation speed, thereby reducing resource consumption, and greatly expanding the application scope of the IIR filter.

Description

Technical Field

[0001] The present application relates to but is not limited to a digital filter, and in particular to an infinite impulse response (IIR) filter and a method for implementing IIR filtering. Background Art

[0002] With the rapid development of semiconductor technology, digital signal processing technology has made great progress, and it has also become increasingly miniaturized, thinner, and lower-power. Digital filters are an important part of modern digital signal processing systems, which can reduce noise, improve signal-to-noise ratio, and enhance the spectral purity of signals. Digital filters are widely used in communications, voice and image processing, and other fields.

[0003] IIR filter is a digital filter. It has good amplitude-frequency characteristics and can achieve good filtering with a small number of orders. In situations where linear phase requirements are not high, IIR filter can reduce resource consumption to a certain extent. However, IIR filter calculation usually requires a large amount of digital signal processor (DSP) resources. Summary of the invention

[0004] The present application provides an infinite impulse response filter and a method for implementing IIR filtering, which can improve the IIR calculation speed, thereby reducing resource consumption and greatly expanding the application scope of the IIR filter.

[0005] The embodiment of the present invention provides an infinite impulse response (IIR) filter, comprising: a control circuit, a time-division multiplexing processing circuit, a coefficient reloading circuit, and an IIR calculation circuit; wherein:

[0006] a coefficient reloading circuit, configured to store the reloaded coefficients and output them to the IIR calculation circuit under the control of the control circuit;

[0007] A time-division multiplexing processing circuit is configured to input the multi-channel parallel input data to the IIR calculation circuit in a time-division manner through a synchronous sampling technique under the control of a synchronization signal from the control circuit;

[0008] The IIR calculation circuit is configured to perform IIR calculation and truncation processing on input data and then output calculation results according to the reloaded coefficients under the control of the control circuit.

[0009] In an exemplary embodiment, the control circuit is further configured to:

[0010] A bus bridge is used to unify different bus interfaces into a register interface, and the signal is input into the control register to perform read and write operations on the control register.

[0011] In an exemplary embodiment, the IIR calculation circuit is further configured to:

[0012] The calculation result is output after compensating the truncation result by rounding off.

[0013] In an exemplary embodiment, the time-division multiplexing processing circuit includes: a channel signal detector, a data shift register, and an output circuit; wherein,

[0014] A channel signal detector is configured to sample the channel signal through a shift register driven by a high-speed clock from the control circuit, and to generate a valid signal each time a specified number of bits is shifted to obtain the current channel number;

[0015] A data shift register is configured to use a multi-bit shift register, driven by a high-speed clock from the control circuit to sample the data of the multi-channel parallel input; and store the data of the channel according to the channel signal from the channel signal detector;

[0016] The output circuit is configured to input the multi-channel parallel input data to the IIR calculation circuit in a time-sharing manner through a synchronous sampling technology under the control of a synchronous signal from the control circuit.

[0017] In an exemplary embodiment, the data shift register includes: a first address generation judgment circuit, a first address generator, and a shift register; wherein,

[0018] A first address generation judgment circuit is configured to receive a channel signal from the channel signal detector and determine that an address needs to be generated;

[0019] An address generator configured to generate a first address;

[0020] The shift register is configured to be driven by a high-speed clock from the control circuit, samples the data of the multi-channel parallel input according to the first address, obtains the data of the current channel signal and stores it.

[0021] In an exemplary embodiment, the output circuit is specifically configured as follows:

[0022] When the synchronization signal from the control circuit arrives, the data of the multi-channel parallel input is sampled and output as input data to the IIR calculation circuit in a time-sharing manner.

[0023] In an exemplary embodiment, the output circuit includes: a second address generation judgment circuit, a second address generator, and a data register; wherein,

[0024] A second address generation judgment circuit is configured to receive data of a channel corresponding to a channel signal from the data shift register and determine that an address needs to be generated;

[0025] A second address generator, configured to generate a second address;

[0026] The data register is configured to input the multi-channel parallel input data into the IIR calculation circuit in a time-sharing manner according to the second address through a synchronous sampling technique under the control of a synchronous signal from the control circuit.

[0027] In an exemplary embodiment, the IIR calculation circuit includes: a first multiplication circuit, a second multiplication circuit, an addition circuit, and a truncation circuit; wherein,

[0028] a first multiplication circuit, configured to perform a multiplication operation on the reloaded coefficient and the feedback result from the truncation circuit and then output the multiplication operation to the addition circuit;

[0029] a second multiplication circuit, configured to perform a multiplication operation on the reloaded coefficient and the multi-channel time-sharing input data and then output the multiplication operation to the addition circuit;

[0030] an adding circuit, configured to perform an addition operation on the operation results from the first multiplication circuit and the second multiplication circuit and then output the result to the truncation circuit;

[0031] The truncation circuit is configured to truncate the calculation result from the addition circuit, and output the calculation result after compensating the truncation result by rounding off.

[0032] In an exemplary embodiment, the truncation circuit includes: a truncation judgment circuit, a truncation calculation circuit, a compensation calculation circuit, and a truncation compensation circuit; wherein,

[0033] A truncation bit determination circuit, configured to determine the number of truncated bits for the operation result from the addition circuit;

[0034] A truncation calculation circuit, configured to perform a truncation operation on the calculation result of the addition circuit according to a determination result of the truncation bit number;

[0035] A compensation calculation circuit is configured to calculate compensation data according to a determination result of the number of truncated bits;

[0036] The truncation compensation circuit is configured to compensate the data after the truncation operation according to the compensation data and output the IIR calculation result.

[0037] In an exemplary embodiment, the truncation judgment circuit includes: a first data judgment circuit and a first data splitting circuit, wherein:

[0038] A first data determination circuit is configured to calculate the parameters of the multiplier according to the macro definition parameters preselected by the user;

[0039] The first data splitting circuit is configured to calculate a truncation result according to the calculated parameters to perform the truncation bit number judgment.

[0040] In an exemplary embodiment, the truncation calculation circuit includes a second data determination circuit and a second data splitting circuit, wherein:

[0041] a second data judgment circuit, configured to retain a valid sign bit according to the sign bit in the judgment result;

[0042] The second data splitting circuit is configured to determine whether to discard the lower bit of the truncated bit according to the lower bit of the truncated bit in the judgment result.

[0043] In an exemplary embodiment, the compensation calculation circuit includes a third data judgment circuit and a first adder, wherein:

[0044] A third data judgment circuit is configured to calculate the truncated and discarded part according to the value of the lower one of the truncated bits in the judgment result;

[0045] A first adder, configured to determine to perform a +1 carry process on the retained part when the lower one of the truncated bits in the judgment result is 1;

[0046] The truncation compensation circuit includes a second adder configured as follows:

[0047] The high-order part obtained after the truncation operation is added to the low-order part obtained by the compensation calculation to obtain the IIR calculation result.

[0048] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings are used to provide further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0050] Figure 1 This is a schematic diagram of the structure of the IIR filter in the embodiment of the present application;

[0051] Figure 2 A schematic diagram of the composition of an embodiment of the control circuit of the present application;

[0052] Figure 3 This is a schematic diagram of the composition of an embodiment of a time-division multiplexing processing circuit of the present application;

[0053] Figure 4 A schematic diagram of the composition of an embodiment of the truncation circuit of the present application;

[0054] Figure 5 A flow chart of a method for implementing IIR filtering by an IIR filter in an embodiment of the present application;

[0055] Figure 6 A schematic diagram of the circuit composition of an embodiment of the time-division multiplexing processing circuit of the present application;

[0056] Figure 7 A schematic diagram of the circuit composition of an embodiment of the IIR calculation circuit of the present application;

[0057] Figure 8 The figure is a circuit diagram of an embodiment of the truncation circuit of the present application. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0059] In a typical configuration of the present application, a computing device includes one or more processors (CPU), an input / output interface, a network interface, and a memory.

[0060] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0061] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include non-transitory media such as modulated data signals and carrier waves.

[0062] The steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions. Also, although a logical sequence is shown in the flowchart, in some cases, the steps shown or described can be performed in a sequence different from that shown here.

[0063] Figure 1 Schematic diagram of the structure of the IIR filter in the embodiment of the present application. Figure 1 As shown, it at least includes: a control circuit, a time-division multiplexing processing circuit, a coefficient reloading circuit, and an IIR calculation circuit; wherein,

[0064] The control circuit is configured to control the component circuits in the IIR filter, such as starting or shutting down each component circuit, reloading coefficients, time-division multiplexing synchronization signals, processing received data streams, preparing sent data streams, etc.

[0065] The coefficient reloading circuit is configured to store the reloaded coefficients and output them to the IIR calculation circuit under the control of the control circuit.

[0066] The time-division multiplexing processing circuit is configured to input the multi-channel parallel input data to the IIR calculation circuit in a time-division manner through a synchronous sampling technology under the control of a synchronous signal from a control circuit.

[0067] The IIR calculation circuit is configured to perform IIR calculation and truncation processing on input data and then output calculation results according to the reloaded coefficients under the control of the control circuit.

[0068] The IIR filter provided in the embodiment of the present application uses synchronous sampling technology to perform IIR calculations on multi-channel parallel input data in a time-sharing manner, thereby improving the IIR calculation speed, thereby reducing resource consumption, and greatly expanding the application scope of the IIR filter.

[0069] In an exemplary embodiment, the control circuit is further configured to:

[0070] The bus bridge is used to unify different bus interfaces into register interfaces, and the signal is input into the control register for reading and writing the control register. In other words, after being processed by the control circuit, the bus signal from the outside can be used to read and write the control register to generate the corresponding internal selection control signal (Ctrl_sel signal), thus improving the flexibility of the configuration of the IIR filter.

[0071] In an exemplary embodiment, the coefficient reloading circuit can reload the coefficients by configuring the macro parameters, or by writing to the bus port.

[0072] In an exemplary embodiment, the IIR calculation circuit is further configured to:

[0073] The calculation result is output after compensating the truncation result by rounding off.

[0074] In an exemplary instance, since truncation processing will produce errors, and the errors will gradually increase with the increase in the number of feedback times, the results after truncation processing are optimized in the embodiment of the present application, that is, compensation processing is used to judge the lost accuracy, and compensation is performed through rounding, thereby improving the accuracy of the calculation.

[0075] Figure 2 FIG. 1 is a schematic diagram of a composition of an embodiment of the control circuit of the present application. In an exemplary embodiment, the control circuit can select one of a plurality of bus interfaces by macro-defined parameter configuration, such as Figure 2 As shown, the working principle includes: using a bus bridge to unify different bus interfaces into a register interface, and inputting signals into a control register to perform read and write operations on the control register. Figure 2 The processing of the control circuit shown realizes the use of external bus signals to read and write control registers and generate corresponding internal selection control signals (Ctrl_sel signals), thereby improving the configuration flexibility of the IIR filter.

[0076] In order to control the flexible operation of the IIR filter circuit, the embodiments of the present application may support commonly used bus interfaces and some control signals. For example, the bus interfaces that can be selected through macro definition may include: Advanced eXtensible Interface (AXI) bus interface, Advanced High-performance Bus (AHB) interface, Advanced Peripheral Bus (APB) interface, Wishbone bus interface, register (REG) interface, etc.; and some control signals, such as: channel control signal, which opens or closes the corresponding channel by reading and writing the control register; coefficient reload signal, which can reload the coefficient by reading and writing the control register; delay control signal, which controls the output delay of data by reading and writing the control register. Figure 2 As shown, taking the REG interface as an example, the input write wr signal is connected to the bus port and driven by it; external data is provided to the REG bus interface: the input write address waddr signal is connected to the bus waddr end and driven by it; the input write data wdata is connected to the bus wdata end and driven by it; the bus conversion within the IP is converted from the external bus to the internal REG interface: the input write address waddr is connected to the address input end ADDR of the control register; the input write data wdata is connected to the data input end DATA of the control register. Each ctrl_sel signal is output through the read and write of the ADDR and DATA signal ends.

[0077] Figure 3 FIG. 1 is a schematic diagram of a time-division multiplexing processing circuit embodiment of the present application. In an exemplary embodiment, as shown in FIG. Figure 3 As shown, the time-division multiplexing processing circuit may include: a channel signal detector, a data shift register, and an output circuit; wherein,

[0078] The channel signal detector is configured to sample the channel signal through a one-bit shift register, driven by a high-speed clock from a control circuit, and generates a valid signal each time a specified number of bits is shifted to obtain the current channel number.

[0079] The data shift register is configured to use a multi-bit shift register, driven by a high-speed clock from a control circuit to sample input data signals, i.e., data inputted in parallel from multiple channels; and store the data of the channel according to the channel signal from a channel signal detector;

[0080] The output circuit is configured to input the multi-channel parallel input data to the IIR calculation circuit in a time-sharing manner through a synchronous sampling technology under the control of a synchronous signal from a control circuit, thereby ensuring the uniformity and stability of the multi-channel time-sharing input data.

[0081] In an exemplary embodiment, the output circuit is specifically configured as follows:

[0082] When the synchronization signal from the control circuit arrives, the multi-channel parallel input data is sampled and output as input data to the IIR calculation circuit in time-sharing to participate in the calculation, ensuring the uniformity and stability of the multi-channel time-sharing input data.

[0083] In an exemplary embodiment, the channel signal detector can be implemented using a counter, such as Figure 6 As shown, in one embodiment, the ibstart signal is used to mark channel 0, and the inpvalid signal is used to mark whether it is valid input data. In one embodiment, assuming that the ibstart signal is at a high level, it indicates that the number of channels starts counting from 0. When the inpvalid signal is at a high level and accumulates to a preset number of channels, the counter pauses counting until the next high level of the ibstart signal arrives, the counter is cleared and the current number of channels is recalculated.

[0084] In an exemplary embodiment, the data shift register may include: a first address generation judgment circuit, a first address generator, and a shift register; wherein the first address generation judgment circuit is configured to receive a channel signal from a channel signal detector and determine that an address needs to be generated; the address generator is configured to generate a first address (such as Figure 6 The shift register is configured to be driven by a high-speed clock from a control circuit, samples the input data signal, i.e., the data of multi-channel parallel input, according to the generated address, obtains the data of the current channel signal and stores it.

[0085] In an exemplary embodiment, the output circuit may include: a second address generation judgment circuit, a second address generator, and a data register; wherein the second address generation judgment circuit is configured to receive channel signal data from a channel signal detector and determine that an address needs to be generated; the second address generator is configured to generate a second address (such as Figure 6 Address B in the data register, which is set to input the multi-channel parallel input data into the IIR calculation circuit in a time-sharing manner through a synchronous sampling technology under the control of a synchronous signal from a control circuit.

[0086] In the embodiment of the present application, the data address operation and the data operation are realized in parallel through the address generator.

[0087] Through the output circuit provided in the embodiment of the present application, after the IIR calculation circuit completes the calculation, the control circuit will again send a synchronization signal to the time-division multiplexing processing circuit to indicate that the calculation has been completed and the next data can be input. In this way, through the stable alternation of the synchronization signal, it is ensured that the data input in parallel by multiple channels is input to the IIR calculation circuit in a time-division and stable manner at the appropriate time, thereby realizing multi-channel time-division multiplexing.

[0088] Even in high-speed mode, due to the negative feedback characteristics of the IIR algorithm, it is difficult to complete a filter within one clock cycle. Therefore, in order to ensure the accuracy of the IIR calculation results, in the embodiment of the present application, the synchronous sampling technology is used to ensure that the input data remains stable within a certain clock cycle, thereby ensuring the uniformity and stability of the input data.

[0089] In an exemplary embodiment, Figure 1 As shown, the IIR calculation circuit may include: a first multiplication circuit, a second multiplication circuit, an addition circuit, and a truncation circuit; wherein,

[0090] A first multiplication circuit is configured to perform a multiplication operation on the overloaded coefficient and the feedback result from the truncation circuit and then output the result to the addition circuit;

[0091] A second multiplication circuit is configured to perform multiplication on the overloaded coefficient and the multi-channel time-sharing input data and then output the multiplication to the addition circuit;

[0092] an adding circuit, configured to perform an addition operation on the operation results from the first multiplication circuit and the second multiplication circuit and then output the result to the truncation circuit;

[0093] The truncation circuit is configured to truncate the calculation result from the addition circuit, and output the calculation result after compensating the truncation result by rounding off.

[0094] In an exemplary embodiment, Figure 4 As shown, the truncation circuit may include: a truncation judgment circuit, a truncation calculation circuit, a compensation calculation circuit, and a truncation compensation circuit; wherein,

[0095] A truncation bit determination circuit is configured to determine the number of truncation bits for the operation result from the addition circuit;

[0096] A truncation calculation circuit is configured to perform a truncation operation on the operation result from the addition circuit according to the judgment result of the truncation bit number judgment;

[0097] A compensation calculation circuit is configured to calculate compensation data according to a determination result of the number of truncated bits;

[0098] The truncation compensation circuit is configured to compensate the data after the truncation operation according to the compensation data and output the final IIR calculation result.

[0099] The embodiment of the present application improves the accuracy of calculation by rounding compensation after truncation and optimizes the IIR calculation result from the algorithm.

[0100] Figure 7 FIG. 1 is a schematic diagram of a circuit composition of an embodiment of the IIR calculation circuit of the present application, as shown in FIG. Figure 7 As shown, Figure 1 Compared with the IIR calculation circuit in Figure 7 In the illustrated embodiment, the first multiplication circuit includes a first delay circuit, a second delay circuit and a first multiplier, forming a feedback calculation branch to generate a feedback calculation result. The second multiplication circuit includes a third delay circuit, a fourth delay circuit and a second multiplier, forming a feedforward calculation branch to generate a feedforward calculation result.

[0101] In an exemplary embodiment, Figure 8 FIG. 1 is a schematic diagram of an embodiment of a truncated circuit, wherein:

[0102] The truncation judgment circuit includes: a first data judgment circuit and a first data splitting circuit, wherein:

[0103] The first data judgment circuit is configured to calculate the parameters of the multiplier, such as the output bit width, the output data high reserved bit, the output data truncation bit, etc., according to the macro definition parameters pre-selected by the user, such as the input data bit width, the coefficient bit width, the output data bit width, the magnification factor, etc.;

[0104] The first data splitting circuit is configured to calculate a truncation result according to the calculated parameters to perform the truncation bit number judgment, wherein the truncation result may include the number of bits that need to be retained and the number of bits that need to be retained for the feedback data.

[0105] In an exemplary embodiment, the truncation bit number determination is to determine whether three special bits are 0 or 1, wherein the three special bits are a sign bit, a truncation bit, and a bit lower than the truncation bit.

[0106] The truncation calculation circuit includes a second data judgment circuit and a second data splitting circuit, wherein:

[0107] a second data determination circuit, configured to retain a valid sign bit according to the sign bit in the determination result;

[0108] The second data splitting circuit is configured to determine whether to discard the low-order part of the truncated bit according to the low-order one of the truncated bit in the judgment result, for example, when the low-order one of the truncated bit is 0, it is determined to discard the low-order part of the truncated bit. In this way, the sign bit is retained and rounded.

[0109] The compensation calculation circuit includes a third data judgment circuit and a first adder, wherein:

[0110] A third data judgment circuit is configured to calculate the truncated and discarded part according to the value of the lower bit of the truncation bit;

[0111] The first adder is set to determine to perform +1 carry processing on the retained part when the lower bit of the truncation bit is 1. In this way, the sign bit retention and rounding are achieved.

[0112] The truncation compensation circuit includes a second adder configured as follows:

[0113] The high-order part obtained after the truncation operation is added to the low-order part obtained by the compensation operation to obtain the final IIR calculation result. In this way, the high-order operation result and the low-order operation result of the data are obtained by segmented calculation, and then the results at both ends are spliced ​​to obtain new data.

[0114] Through the processing of the IIR calculation circuit of the present application, the result with a larger bit width obtained after calculation is reduced to a smaller bit width, and the accuracy of calculation is improved compared with the original result of intercepting high bits, and the calculation result is optimized from the algorithm.

[0115] The full name of IP core is Intellectual Property Core, which refers to a chip design module provided by a certain party. Designers can use IP cores as a basis for logic design of application-specific integrated circuits or field programmable gate arrays (FPGAs) to shorten the design cycle and improve design quality and efficiency. The IIR filter provided in the embodiment of the present application implements a universal IIR IP-core and its related calculation and control circuits. In one embodiment, in order to improve the versatility of the IIR filter of the present application and make it flexible in configuration, the protocol control function should be carried out according to the design control core state machine.

[0116] Figure 5 FIG. 1 is a flow chart of a method for implementing IIR filtering by an IIR filter in an embodiment of the present application. Figure 5 As shown, including:

[0117] Step 500: using synchronous sampling technology to acquire data of each channel in time-sharing from multi-channel parallel input data to be filtered.

[0118] In an exemplary embodiment, this step may include:

[0119] Determine the current number of channels according to the specified number of bits each shift of the shift register;

[0120] According to the current number of channels, the data of each channel is acquired from the multi-channel parallel input data to be filtered in a time-sharing manner through synchronous sampling technology.

[0121] Step 501: Perform IIR calculation and truncation processing on the obtained data according to the reloaded coefficients.

[0122] In an exemplary embodiment, before step 501, the following steps may also be included:

[0123] Reload the coefficients by means of macro-defined parameter configuration or by writing to the bus port.

[0124] In an exemplary embodiment, this step may include:

[0125] A first multiplication operation is performed on the overloaded coefficient and the feedback result after IIR filtering, and a second multiplication operation is performed on the overloaded coefficient and the multi-channel time-sharing input data;

[0126] Performing an addition operation on the result of the first multiplication operation and the result of the second multiplication operation;

[0127] The result of the addition operation is truncated.

[0128] In an exemplary embodiment, performing truncation processing on the result of the addition operation includes:

[0129] The result of the addition operation is truncated to determine the number of digits;

[0130] The truncation operation is performed according to the judgment result of the number of truncation digits.

[0131] In an exemplary embodiment, determining the number of truncated digits of the result of the addition operation may include:

[0132] According to the macro definition parameters pre-selected by the user, such as input data bit width, coefficient bit width, output data bit width, magnification, etc., calculate the parameters of the multiplication calculation, such as output bit width, output data high-order reserved bits, output data truncation bits, etc.;

[0133] The truncation result is calculated according to the calculated parameters to perform the truncation bit number judgment, wherein the stage result may include the number of bits that need to be retained and the number of bits that need to be retained for the feedback data.

[0134] In an exemplary embodiment, performing a truncation operation according to a result of determining the number of truncation bits may include:

[0135] Retain the valid sign bit according to the sign bit in the judgment result;

[0136] Whether to discard the low-order part of the truncation bit is determined according to the low-order part of the truncation bit in the judgment result.

[0137] Step 502: Compensate the result of the truncation process by rounding to obtain the result of the IIR filtering.

[0138] In an exemplary embodiment, this step may include:

[0139] Calculate compensation data based on the result of the addition operation according to the judgment result of the truncated digit judgment;

[0140] The data after the truncation operation is compensated according to the compensation data to obtain the result of IIR filtering.

[0141] In an exemplary embodiment, calculating the compensation data according to the result of determining the number of truncated bits for the result of the addition operation may include:

[0142] The truncated and discarded part is calculated according to the value of the lower truncated bit;

[0143] When the lower bit of the truncated bit is 1, it is determined that the retained part is processed by +1 carry. In this way, the sign bit is retained and rounded.

[0144] In an exemplary embodiment, compensating the data after the truncation operation according to the compensation data to obtain the result of IIR filtering may include:

[0145] The high-order part obtained by the truncation calculation is added to the low-order part obtained by the compensation calculation to obtain the final IIR calculation result.

[0146] The embodiment of the present application improves the accuracy of calculation by rounding compensation after truncation and optimizes the IIR calculation result from the algorithm.

[0147] The method for implementing filtering by an IIR filter provided in the embodiment of the present application utilizes synchronous sampling technology to perform IIR calculations on multi-channel parallel input data in a time-sharing manner, thereby improving the IIR calculation speed, thereby reducing resource consumption, and greatly expanding the application scope of the IIR filter.

[0148] The present application also provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute any of the above methods for implementing IIR filtering.

[0149] The present application further provides a device for implementing filtering, including a memory and a processor, wherein the memory stores the following instructions executable by the processor: used to execute the steps of any of the above-mentioned methods for implementing IIR filtering.

[0150] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of patent protection of this application shall still be based on the scope defined in the attached claims.

Claims

1. An infinite impulse response IIR filter, comprising: control circuit, time-division multiplexing processing circuit, coefficient reloading circuit, and IIR calculation circuit; wherein, a coefficient reloading circuit, configured to store the reloaded coefficients and output them to the IIR calculation circuit under the control of the control circuit; A time-division multiplexing processing circuit is configured to input the multi-channel parallel input data to the IIR calculation circuit in a time-division manner through a synchronous sampling technique under the control of a synchronization signal from the control circuit; An IIR calculation circuit is configured to perform IIR calculation and truncation processing on input data and output calculation results after performing calculation under the control of the control circuit according to the reloaded coefficients; The time-division multiplexing processing circuit includes: a channel signal detector, a data shift register, and an output circuit; wherein, A channel signal detector is configured to sample the channel signal through a shift register driven by a high-speed clock from the control circuit, and to generate a valid signal each time a specified number of bits is shifted to obtain the current channel number; A data shift register is configured to use a multi-bit shift register, driven by a high-speed clock from the control circuit to sample the data of the multi-channel parallel input; and store the data of the channel according to the channel signal from the channel signal detector; An output circuit is configured to input the multi-channel parallel input data to the IIR calculation circuit in a time-sharing manner through a synchronous sampling technique under the control of a synchronous signal from the control circuit; The data shift register comprises: a first address generation judgment circuit, a first address generator, and a shift register; wherein, A first address generation judgment circuit is configured to receive a channel signal from the channel signal detector and determine that an address needs to be generated; An address generator configured to generate a first address; The shift register is configured to be driven by a high-speed clock from the control circuit, samples the data of the multi-channel parallel input according to the first address, obtains the data of the current channel signal and stores it.

2. The IIR filter according to claim 1, wherein the control circuit is further configured to: A bus bridge is used to unify different bus interfaces into a register interface, and the signal is input into the control register to perform read and write operations on the control register.

3. The IIR filter according to claim 1, wherein the IIR calculation circuit is further configured to: The calculation result is output after compensating the truncation result by rounding off.

4. The IIR filter according to claim 1, wherein: The output circuit is specifically configured as follows: When the synchronization signal from the control circuit arrives, the data input in parallel from the multi-channels are sampled and output as input data to the IIR calculation circuit in a time-sharing manner.

5. The IIR filter according to claim 4, wherein: The output circuit includes: a second address generation judgment circuit, a second address generator, and a data register; wherein, A second address generation judgment circuit is configured to receive data of a channel corresponding to a channel signal from the data shift register and determine that an address needs to be generated; A second address generator, configured to generate a second address; The data register is configured to input the multi-channel parallel input data into the IIR calculation circuit in a time-sharing manner according to the second address through a synchronous sampling technique under the control of a synchronous signal from the control circuit.

6. The IIR filter according to claim 1, 2 or 3, wherein: The IIR calculation circuit includes: a first multiplication circuit, a second multiplication circuit, an addition circuit, and a truncation circuit; wherein, a first multiplication circuit, configured to perform a multiplication operation on the reloaded coefficient and the feedback result from the truncation circuit and then output the multiplication operation to the addition circuit; a second multiplication circuit, configured to perform a multiplication operation on the reloaded coefficient and the multi-channel time-sharing input data and then output the multiplication operation to the addition circuit; an adding circuit, configured to perform an addition operation on the operation results from the first multiplication circuit and the second multiplication circuit and then output the result to the truncation circuit; The truncation circuit is configured to truncate the calculation result from the addition circuit, and output the calculation result after compensating the truncation result by rounding off.

7. The IIR filter according to claim 6, wherein: The truncation circuit includes: a truncation judgment circuit, a truncation calculation circuit, a compensation calculation circuit, and a truncation compensation circuit; wherein, A truncation bit determination circuit, configured to determine the number of truncated bits for the operation result from the addition circuit; A truncation calculation circuit, configured to perform a truncation operation on the calculation result of the addition circuit according to a determination result of the truncation bit number; A compensation calculation circuit is configured to calculate compensation data according to a determination result of the number of truncated bits; The truncation compensation circuit is configured to compensate the data after the truncation operation according to the compensation data and output the IIR calculation result.

8. The IIR filter according to claim 7, wherein: The truncation judgment circuit comprises: a first data judgment circuit and a first data splitting circuit, wherein: A first data determination circuit is configured to calculate the parameters of the multiplier according to the macro definition parameters preselected by the user; The first data splitting circuit is configured to calculate a truncation result according to the calculated parameters to perform the truncation bit number judgment.

9. The IIR filter according to claim 7, wherein: The truncation calculation circuit includes a second data judgment circuit and a second data splitting circuit, wherein: a second data judgment circuit, configured to retain a valid sign bit according to the sign bit in the judgment result; The second data splitting circuit is configured to determine whether to discard the lower bit of the truncated bit according to the lower bit of the truncated bit in the judgment result.

10. The IIR filter according to claim 7, wherein: The compensation calculation circuit includes a third data judgment circuit and a first adder, wherein: A third data judgment circuit is configured to calculate the truncated and discarded part according to the value of the lower one of the truncated bits in the judgment result; A first adder, configured to determine to perform a +1 carry process on the retained part when the lower one of the truncated bits in the judgment result is 1; The truncation compensation circuit includes a second adder configured as follows: The high-order part obtained after the truncation operation is added to the low-order part obtained by the compensation calculation to obtain the IIR calculation result.

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