A multiplication operation circuit and method in an SSD master control chip

Abstract

The present invention discloses a multiplication circuit and method in an SSD main control chip, wherein the multiplication circuit includes a bit selector, a compensation value memory, a partial product operation unit, a shift register and a cache adder, wherein the input end of the bit selector is connected to the multiplier end, the number output end of the bit selector is connected to the compensation value memory, the shift register and the cache adder, the result output end of the bit selector is connected to the partial product operation unit, the input end of the partial product operation unit is connected to the multiplicand end, the output end of the partial product operation unit is connected to the shift register, the output end of the compensation value memory is connected to the shift register, and the output end of the shift register is connected to the input end of the cache adder. The present invention can avoid generating negative values ​​in the multiplier operation result, thereby reducing a large number of complement operation circuits. Thus, the hardware implementation cost of the algorithm is greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of SSD master control chip operation acceleration, and in particular to a multiplication operation circuit and method in an SSD master control chip. Background Art

[0002] SSD (Solid State Disk) data storage has gradually become the main storage medium for consumer device data storage and cloud storage. As the brain of SSD storage devices, the error correction performance and encryption and decryption performance of the SSD main control chip directly determine the durability and performance of the SSD hard disk. Therefore, it is of great significance to optimize the encryption and decryption circuit in the SSD main control chip. At present, the use of radix 4-booth multipliers in SSD is relatively common, but since the partial product may be negative after each table lookup in the original algorithm, it is necessary to design a complement circuit to complete the subtraction operation when each partial product is added during circuit implementation, which increases the circuit cost. Summary of the invention

[0003] To this end, it is necessary to provide a multiplication operation circuit and method in an SSD main control chip to solve the problem that a negative number may appear in the partial product after each table lookup during encryption and decryption of the current SSD storage device. Therefore, when implementing the circuit, a complement circuit needs to be designed to complete the subtraction operation when each partial product is added, thereby causing an increase in circuit cost.

[0004] To achieve the above object, the present invention provides a multiplication circuit in an SSD main control chip, comprising the following units:

[0005] A bit selector, a compensation value memory, a partial product operation unit, a shift register and a cache adder, wherein the input end of the bit selector is connected to the multiplier end, the number output end of the bit selector is connected to the compensation value memory, the shift register and the cache adder, the result output end of the bit selector is connected to the partial product operation unit, the input end of the partial product operation unit is connected to the multiplicand end, the output end of the partial product operation unit is connected to the shift register, the output end of the compensation value memory is connected to the shift register, the output end of the shift register is connected to the input end of the cache adder, and the output end of the cache adder is connected to the output end of the multiplication circuit;

[0006] The compensation value memory stores a compensation value -1<<(N+1), and the partial product operation unit stores a preset table and obtains the corresponding partial product according to the preset table matching, and the table is as follows:

[0007]

[0008] Furthermore, the partial product operation unit includes a table lookup unit and a splicing and combining unit, the table lookup unit stores the table, the output end of the table lookup unit is connected to the splicing and combining unit, and the output end of the splicing and combining unit is connected to the shift register.

[0009] Furthermore, the table lookup unit also stores a complement code, the partial product operation unit also includes a first adder, the output end of the splicing combination unit is connected to the shift register through the first adder, and the complement code output end of the table lookup unit is connected to the first adder.

[0010] Furthermore, the SSD master control chip also includes a patch selection unit and a second adder, the input end of the patch selection unit is connected to the operation precision end, the output end of the patch selection unit is connected to the second adder, the output end of the multiplication circuit is connected to the second adder, and the output end of the second adder is connected to the operation result end.

[0011] Furthermore, the patch selection unit includes a plurality of precision patches and a gate, the plurality of precision patches are connected to an input end of the gate, a control end of the gate is connected to an operation precision end, and an output end of the gate is connected to the second adder.

[0012] Furthermore, the compensation value is -1<<(N+1) minus an additional value greater than 0, and each partial product in the table is also added with the additional value.

[0013] The present invention provides a multiplication operation method in an SSD master control chip, which is applied to a multiplication operation circuit in an SSD master control chip described in any one of the embodiments of the present invention, and comprises the following steps:

[0014] The bit selector sequentially obtains the value of each adjacent three-digit number in the binary value of the multiplier X according to the input multiplier and outputs it to the partial product operation unit, and outputs the number of times i corresponding to each adjacent three-digit number, where the value of i is an integer from ((N+1) / 2)-1 to 0, and N is the number of digits of the multiplier X;

[0015] The partial product operation unit obtains the corresponding partial product by looking up the table according to the values ​​of the adjacent three-digit values ​​and outputs it to the shift register;

[0016] The compensation value memory outputs the compensation value after obtaining the number of times i;

[0017] The shift register shifts the input compensation value or partial product according to the number of times i, and inputs the compensation value or partial product into the cache adder after shifting it left by 2i bits;

[0018] The cache adder obtains the shifted value, performs addition operation and caches it, and outputs the cached result after performing addition operation after the number of times obtained is 0.

[0019] Different from the prior art, the above technical solution proposes an optimized radix-4 Booth multiplication algorithm design circuit, which can eliminate the possibility of negative numbers appearing in the partial products after each table lookup in the original algorithm, so that when the circuit is implemented, it is not necessary to perform subtraction when each partial product is added, thereby reducing a large number of complement operation circuits. After all partial products are added, the present invention performs a unified subtraction at the end, and subtracts the negative numbers owed by all partial products at the end. Thereby greatly reducing the hardware implementation cost of the algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The multiplication operation circuit diagram of the present invention;

[0021] Figure 2 A circuit diagram of a partial product operation unit according to the present invention;

[0022] Figure 3 The present invention is a circuit diagram of an application embodiment of the multiplication circuit described in the present invention. DETAILED DESCRIPTION

[0023] In order to explain the technical content, structural features, achieved objectives and effects of the technical solution in detail, the following is a detailed description in conjunction with specific embodiments and accompanying drawings.

[0024] See also Figures 1 to 3 This embodiment provides a multiplication circuit and method in an SSD master control chip, which is used to optimize the existing radix-4 Bus multiplier. The operation formula of the existing radix-4 Bus multiplier is as follows:

[0025]

[0026] The original calculation table is shown in Table 1:

[0027] Table 1: Original radix-4 Booth multiplier operation table

[0028]

[0029] In the original radix-4 Booth algorithm, negative En may appear, such as -2, -1, and then the complement needs to be calculated for partial accumulation and addition.

[0030] In order to avoid the situation of negative En, the present invention provides a multiplication circuit in an SSD main control chip, including the following units: a bit selector, a compensation value memory, a partial product operation unit, a shift register and a cache adder, the input end of the bit selector is connected to the multiplier end, the number output end of the bit selector is connected to the compensation value memory, the shift register and the cache adder, the result output end of the bit selector is connected to the partial product operation unit, the input end of the partial product operation unit is connected to the multiplicand end, the output end of the partial product operation unit is connected to the shift register, the output end of the compensation value memory is connected to the shift register, the output end of the shift register is connected to the input end of the cache adder, and the output end of the cache adder is connected to the output end of the multiplication circuit; the compensation value memory stores a compensation value -1<<(N+1), and 1<<(N+1) in the compensation value means that 1 bit is shifted left by N+1 bits. The partial product operation unit stores a preset table and obtains the corresponding partial product according to the preset table matching, and the table is the following Table 2:

[0031] Table 2: Operation table of the radix-4 Booth multiplier of the present invention

[0032]

[0033] In the partial product of Table 2, the part in the curly brackets {} is the partial product expression. The comma "," inside the curly brackets is used to distinguish different bit components before and after. The symbol 1' represents 1 bit, N' represents N bits, b0 represents bit 0, b1 represents bit 1, and ~ represents the inversion of the following bits. Y[N-1] represents the Nth bit of the multiplicand Y, and Y[N-1:0] represents the N-1 to 0 bits of the multiplicand Y. For example, the expression {Y[N-1], ~Y[N-1:0], 1'b1}, that is, the N-1 bit value of Y, the inversion of the N-1 to 0 bits of Y, and the bit 1 component product E. If Y is 000111, the result of the expression is: 01110001. The complement indicates whether the complement needs to be added by 1 in the subsequent operation. The signal partial product E (result) represents the result of adding the compensation value in advance, excluding the operation of adding the complement. It can be expressed as follows:

[0034] result = E n *Y+1<<(N+1))

[0035] When the circuit of the above embodiment is specifically operated, the internal operation method can adopt the multiplication operation method in the SSD main control chip provided by the present invention, including the following steps: used to operate the input multiplicand Y and multiplier X, the multiplicand Y and multiplier X are binary values, the multiplicand Y bit width and the multiplier X bit width are both N bits, wherein the highest bit of the multiplier Y and the multiplier X is the sign bit, and the other bits except the highest bit represent the value size. The multiplicand Y and the multiplier X here can be input from an external chip into the SSD main control chip where the method of the present invention is running, or generated by the SSD main control chip. The bit selector obtains the value of each adjacent three-digit value in the binary value of the multiplier X in turn according to the input multiplier and outputs it to the partial product operation unit, and outputs the number of times i corresponding to each adjacent three-digit number, the value of i is an integer from ((N+1) / 2)-1 to 0, and N is the number of bits of the multiplier X. The positions of the adjacent three-digit values ​​are based on X 2i+1 , X 2i , X 2i-1 OK, the X 2i+1 is the 2i+1th bit of the multiplier X, where X 2i is the 2i-th bit of the multiplier X, 2i-1 is the 2i-1th bit of the multiplier X; X -1 It is determined to be 0. The partial product operation unit looks up Table 2 according to the values ​​of the adjacent three-digit numbers to obtain the corresponding partial product and outputs it to the shift register.

[0036] For example, if N=6, the multiplier X, and the values ​​of i are 2, 1, and 0, the bit selector first selects the highest consecutive three-digit number X. 5 , X 4 , X 3 The value is output, and the value of i is 2, and then the next group of adjacent three-digit numbers X is selected. 3 , X 2 , X 1 The value is output, and the value of i is 1. Finally, the three-digit number X is selected. 1 , X 0 , X -1 The partial product operation unit outputs the corresponding partial product according to the input three-digit number and the multiplicand Y.

[0037] During the table lookup operation, the compensation value memory may be processed and outputted with priority, and the compensation value memory outputs the compensation value after obtaining the number of times i when the input has changed.

[0038] The shift register shifts the input compensation value or partial product according to the number of times i, and inputs the compensation value or partial product into the cache adder after shifting the compensation value or partial product left by 2i bits. When the compensation value is first input into the shift register, the shift register first performs a shift operation on the compensation value and inputs the result into the cache adder. After the partial product is input into the shift register, the shift register performs a shift operation and inputs the result into the cache adder.

[0039] The cache adder obtains the shifted value, performs addition operation and caches it, and outputs the cached result after performing addition operation after obtaining the number of times 0. The cache adder will add the results 6 times, including the addition of the compensation value shift result and the partial product shift result when i=2, 1, and 0.

[0040] The final algorithm formula of the present invention is as follows:

[0041]

[0042] In this way, the partial products E in the table of the present invention are all first added with a compensation value of 1<<(N+1), which can eliminate the possibility of negative numbers appearing in the partial products after each table lookup in the original algorithm, so that when the circuit is implemented, it is not necessary to perform subtraction when each partial product is added, thereby reducing a large number of complement operation circuits. After all partial products are added, the present invention performs a unified subtraction at the end, and subtracts the negative numbers owed by all partial products at the end. This greatly reduces the hardware implementation cost of the algorithm.

[0043] In some embodiments, in order to implement the logic operation of the partial product result, the partial product operation unit includes a table lookup unit and a splicing and combining unit, wherein the table lookup unit stores the table, the output end of the table lookup unit is connected to the splicing and combining unit, and the output end of the splicing and combining unit is connected to the shift register. The splicing and combining unit is used to perform splicing and combining according to the partial products in Table 2 to generate the final partial product result.

[0044] In order to realize the complement operation, the table lookup unit also stores the complement, the partial product operation unit also includes a first adder, the output end of the splicing and combining unit is connected to the shift register through the first adder, and the complement output end of the table lookup unit is connected to the first adder. The first adder is used to add the complement to the result of the splicing and combining unit and then output it to realize the complement operation.

[0045] In order to achieve precision compensation, the SSD main control chip also includes a patch selection unit and a second adder, the input end of the patch selection unit is connected to the operation precision end, the output end of the patch selection unit is connected to the second adder, the output end of the multiplication operation circuit is connected to the second adder, and the output end of the second adder is connected to the operation result end. The second adder is used to add the multiplication result and the precision patch result and then output the operation result to achieve precision compensation.

[0046] Furthermore, the patch selection unit includes a plurality of precision patches and a gate, the plurality of precision patches are connected to the input end of the gate, the control end of the gate is connected to the operation precision end, and the output end of the gate is connected to the second adder. The gate can select the corresponding precision patch according to the result of the operation precision end, and then the second adder adds the patch value to the multiplication result and outputs it to realize the precision patch.

[0047] In the present invention, the value of the compensation value may be greater than 1<<(N+1), then the compensation value is -1<<(N+1) minus an additional value greater than 0, and each partial product in the table is also added with the additional value. This also ensures that no negative numbers will appear when looking up the table.

[0048] In some embodiments, when the accumulation is performed, it is necessary to expand the high-bit number, and negative numbers are not considered, so the high-bit number of the accumulation calculation result is compensated to 0. This can be applicable to the operation of high-bit numbers.

[0049] It should be noted that, although the above embodiments have been described in this article, the patent protection scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, changes and modifications made to the embodiments described herein, or equivalent structures or equivalent process changes made using the contents of the present invention specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields, are all included in the patent protection scope of the present invention.

Claims

1. The multiplication circuit in the SSD main control chip is characterized by: The following units are included: A bit selector, a compensation value memory, a partial product operation unit, a shift register and a cache adder, wherein the input end of the bit selector is connected to the multiplier end, the number output end of the bit selector is connected to the compensation value memory, the shift register and the cache adder, the result output end of the bit selector is connected to the partial product operation unit, the input end of the partial product operation unit is connected to the multiplicand end, the output end of the partial product operation unit is connected to the shift register, the output end of the compensation value memory is connected to the shift register, the output end of the shift register is connected to the input end of the cache adder, and the output end of the cache adder is connected to the output end of the multiplication circuit; The compensation value memory stores a compensation value -1<<(N+1), and the partial product operation unit stores a preset table and obtains the corresponding partial product according to the preset table matching, and the table is as follows: Where N is the number of bits of the multiplier X, the part in the curly brackets {} is the partial product expression, the comma "," inside the curly brackets is used to distinguish the different bit components before and after, the symbol 1' represents 1 bit, N' represents N bits, b0 represents bit 0, b1 represents bit 1, ~ represents the inversion of the following bits, Y[N-1] represents the Nth bit of the multiplicand Y, and Y[N-1:0] represents the value of the multiplicand Y from N-1 to 0 bits.

2. The multiplication circuit in the SSD main control chip according to claim 1, characterized in that: The partial product operation unit includes a table lookup unit and a splicing and combining unit. The table lookup unit stores the table. The output end of the table lookup unit is connected to the splicing and combining unit. The output end of the splicing and combining unit is connected to the shift register.

3. The multiplication circuit in the SSD main control chip according to claim 2, characterized in that: The table lookup unit also stores a complement code, the partial product operation unit also includes a first adder, the output end of the splicing combination unit is connected to the shift register through the first adder, and the complement code output end of the table lookup unit is connected to the first adder.

4. The multiplication circuit in the SSD main control chip according to claim 1, characterized in that: The SSD master control chip also includes a patch selection unit and a second adder, the input end of the patch selection unit is connected to the operation precision end, the output end of the patch selection unit is connected to the second adder, the output end of the multiplication circuit is connected to the second adder, and the output end of the second adder is connected to the operation result end.

5. The multiplication circuit in the SSD main control chip according to claim 4, characterized in that: The patch selection unit includes a plurality of precision patches and a gate, the plurality of precision patches are connected to the input end of the gate, the control end of the gate is connected to the operation precision end, and the output end of the gate is connected to the second adder.

6. The multiplication circuit in the SSD main control chip according to claim 1, characterized in that: The compensation value is -1<<(N+1) minus an additional value greater than 0, and each partial product in the table is also added with the additional value.

7. A multiplication operation method in an SSD master control chip, applied to a multiplication operation circuit in an SSD master control chip according to any one of claims 1 to 6, characterized in that: The steps include: The bit selector sequentially obtains the value of each adjacent three-digit number in the binary value of the multiplier X according to the input multiplier and outputs it to the partial product operation unit, and outputs the number of times i corresponding to each adjacent three-digit number, where the value of i is an integer from ((N+1) / 2)-1 to 0, and N is the number of digits of the multiplier X; The partial product operation unit obtains the corresponding partial product by looking up the table according to the values ​​of the adjacent three-digit values ​​and outputs it to the shift register; The compensation value memory outputs the compensation value after obtaining the number of times i; The shift register shifts the input compensation value or partial product according to the number of times i, and inputs the compensation value or partial product into the cache adder after shifting it left by 2i bits; The cache adder obtains the shifted value, performs addition operation and caches it, and outputs the cached result after performing addition operation after the number of times obtained is 0.

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