Multiplier, method, integrated circuit chip and computing device for floating-point operation

Abstract

The present invention relates to a multiplier, method, integrated circuit chip, and computing device for floating-point operations, wherein the computing device may be included in a combined processing device, which may also include a universal interconnect interface and other processing devices. The computing device interacts with the other processing devices to jointly complete user-specified computing operations. The combined processing device may also include a storage device, which is connected to the computing device and the other processing devices, respectively, for storing data from the computing device and the other processing devices. The solution of the present invention can be widely applied to various floating-point data operations.

Description

Technical Field

[0001] The present disclosure generally relates to the field of floating-point operations. More specifically, the present disclosure relates to a method, a multiplier, an integrated circuit chip, and a computing device for floating-point operations. Background Art

[0002] Current signal processing algorithms, such as inner products between vectors and convolution operations on matrices, utilize numerous multiplication-and-add operations. The efficiency of these multiplication-and-add operations often depends on the execution speed of the multiplier. While current multipliers have achieved significant improvements in execution efficiency, there is still room for improvement when it comes to processing floating-point data. Therefore, finding a high-efficiency, low-power, and low-cost multiplier for performing floating-point multiplication operations has become a challenge in the prior art. Summary of the Invention

[0003] In order to at least partially solve the technical problems mentioned in the background technology, the solution disclosed herein provides a multiplier for floating-point operations, a method, an integrated circuit chip including the multiplier, and a computing device.

[0004] In one aspect, the present disclosure provides a multiplier for performing floating-point multiplication operations, wherein the multiplier includes: a mantissa processing unit for obtaining a mantissa after the multiplication operation based on the mantissa of the floating-point number, and the mantissa processing unit includes a control circuit, and the control circuit is used to call the mantissa processing unit multiple times when the mantissa bit width of at least one of two floating-point numbers is greater than the data bit width that can be processed by the mantissa processing unit at one time.

[0005] In another aspect, the present disclosure provides a method for performing floating-point multiplication operations using a multiplier, wherein a mantissa processing unit of the multiplier is used to obtain the mantissa after the multiplication operation based on the mantissa of the floating-point number, and the mantissa processing unit includes a control circuit, which is used to call the mantissa processing unit multiple times when the mantissa bit width of at least one of the two floating-point numbers is greater than the data bit width that can be processed by the mantissa processing unit at one time.

[0006] In another aspect, the present disclosure provides an integrated circuit chip including the multiplier. In one or more embodiments, the multiplier can be implemented as a standalone integrated circuit chip or on an integrated circuit chip or computing device to perform operations on floating-point numbers in a variety of different data formats.

[0007] The disclosed multiplier, corresponding calculation method, integrated circuit chip, and computing device can support operations on various floating-point data types without requiring multiple separate multipliers for different floating-point data types. Thus, the disclosed multiplier is flexible and can be widely applied to various floating-point data operations. Furthermore, when processing input data with a large bit width, the disclosed multiplier supports round-robin operations, eliminating the need for additional processing chips and reducing the integrated circuit layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts.

[0009] Figure 1 is a schematic diagram illustrating a floating-point data format according to an embodiment of the present disclosure;

[0010] Figure 2 is a schematic structural block diagram showing a multiplier according to an embodiment of the present disclosure;

[0011] Figure 3 is a block diagram showing more details of a multiplier according to an embodiment of the present disclosure;

[0012] Figure 4 is a schematic block diagram illustrating a mantissa processing unit according to an embodiment of the present disclosure;

[0013] Figure 5 is a schematic diagram illustrating a partial product operation according to an embodiment of the present disclosure;

[0014] Figure 6 is a schematic block diagram illustrating an operation flow of a Wallace tree compressor according to an embodiment of the present disclosure;

[0015] Figure 7 is an overall schematic block diagram showing a multiplier according to an embodiment of the present disclosure;

[0016] Figure 8 is a flow chart illustrating a method for performing floating-point multiplication operations using a multiplier according to an embodiment of the present disclosure;

[0017] Figure 9 is a structural diagram illustrating a combined processing device according to an embodiment of the present disclosure; and

[0018] Figure 10 2 is a schematic diagram showing the structure of a board according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] The technical solution disclosed herein generally provides a multiplier, method, integrated circuit chip, and computing device for floating-point operations. Unlike the floating-point operation multipliers of the prior art, the present disclosure provides a multiplier that supports multiple operation modes, thereby overcoming the defect that the existing multipliers can only support one type of floating-point operation. In particular, the present disclosure utilizes multiple operation modes to indicate different floating-point data types, and in the multiplication calculation process of floating-point numbers, various operations on the data are performed based on one of the operation modes, including, for example, encoding, compression, summation, normalization, and rounding operations, thereby realizing operations associated with one of the multiple floating-point data types. As a result, the multiplier disclosed herein can support operations in multiple modes, further improving the flexibility of floating-point operations and reducing the cost of operations.

[0020] The technical solution of the present disclosure and its multiple embodiments will be described in detail below with reference to the accompanying drawings. It should be understood that many specific details will be described with respect to floating-point operations in order to provide a thorough understanding of the multiple embodiments described in the present disclosure. However, those of ordinary skill in the art can practice the multiple embodiments described in the present disclosure without these specific details under the guidance of the disclosure. In other cases, the disclosure does not describe well-known methods, processes, and components in detail to avoid unnecessarily obscuring the embodiments described in the present disclosure. In addition, the description should not be considered to limit the scope of the multiple embodiments of the present disclosure.

[0021] Figure 1 FIG. 1 is a schematic diagram illustrating a floating point data format 100 according to an embodiment of the present disclosure. Figure 1As shown in , the floating-point number to which the technical solution of the present disclosure can be applied may include three parts, such as a sign (or sign bit) 102, an exponent (or exponent bit) 104, and a mantissa (or mantissa bit) 106, wherein for an unsigned floating-point number, there may not be a sign or a sign bit. In some embodiments, the floating-point number applicable to the multiplier of the present disclosure may include at least one of a half-precision floating-point number, a single-precision floating-point number, a brain floating-point number, a double-precision floating-point number, and a custom floating-point number. Specifically, in some embodiments, the floating-point number format to which the technical solution of the present disclosure can be applied may be a floating-point format that conforms to the IEEE754 standard, such as a double-precision floating-point number (float64, abbreviated as "FP64"), a single-precision floating-point number (float32, abbreviated as "FP32"), or a half-precision floating-point number (float16, abbreviated as "FP16"). In other embodiments, the floating-point format may be an existing 16-bit floating-point number (bfloat16, abbreviated as "BF16"), or a custom floating-point number format, such as an 8-bit floating-point number (bfloat8, abbreviated as "BF8"), an unsigned half-precision floating-point number (unsigned float16, abbreviated as "UFP16"), or an unsigned 16-bit floating-point number (unsigned bfloat16, abbreviated as "UBF16"). For ease of understanding, Table 1 below shows some of the above-mentioned data formats, where the sign bit width, exponent bit width, and mantissa bit width are only for exemplary purposes.

[0022] Table 1

[0023]

[0024] For the various floating-point number formats mentioned above, the multiplier disclosed herein can at least support a multiplication operation between two floating-point numbers having any of the above formats, wherein the two floating-point numbers can have the same or different floating-point data formats. For example, the multiplication operation between the two floating-point numbers can be a multiplication operation between two floating-point numbers such as FP16×FP16, BF16×BF16, FP32×FP32, FP32×BF16, FP16×BF16, FP32×FP16, BF8×BF16, UBF16×UFP16, or UBF16×FP16.

[0025] Figure 2 2 is a schematic block diagram illustrating a multiplier 200 according to an embodiment of the present disclosure. As previously mentioned, the multiplier of the present disclosure supports multiplication operations of floating-point numbers in various data formats, and these data formats can be indicated by the operation modes of the present disclosure, so that the multiplier operates in one of the multiple operation modes.

[0026] like Figure 2As shown in , the multiplier of the present disclosure may generally include an exponent processing unit 202 and a mantissa processing unit 204, wherein the exponent processing unit is used to process the exponent bit of the floating-point number, and the mantissa processing unit is used to process the mantissa bit of the floating-point number. Optionally or additionally, in some embodiments, when the floating-point number processed by the multiplier has a sign bit, the multiplier may further include a sign processing unit 206, which may be used to process the floating-point number including the sign bit.

[0027] In operation, the multiplier can perform floating-point operations on a first floating-point number and a second floating-point number received, input or cached according to one of the operation modes, and the first floating-point number and the second floating-point number have one of the floating-point data formats discussed above. For example, when the multiplier is in the first operation mode, it can support the multiplication operation of two floating-point numbers FP16×FP16, and when the multiplier is in the second operation mode, it can support the multiplication operation of two floating-point numbers BF16×BF16. Similarly, when the multiplier is in the third operation mode, it can support the multiplication operation of two floating-point numbers FP32×FP32, and when the multiplier is in the fourth operation mode, it can support the multiplication operation of two floating-point numbers FP32×BF16. Here, the example operation modes and floating-point number correspondences are shown in Table 2 below.

[0028] Table 2

[0029]

[0030] In one embodiment, the above Table 2 may be stored in a memory of the multiplier, and the multiplier selects one of the operation modes in the table according to an instruction received from an external device, which may be, for example, Figure 10 In another embodiment, the input of the operation mode can also be via the external device 1012 shown in FIG. Figure 3 . For example, when two FP16 floating-point numbers are input to the multiplier of the present disclosure, the mode selection unit may select the multiplier to operate in the first operation mode according to the data formats of the two floating-point numbers. For another example, when one FP32 floating-point number and one BF16 floating-point number are input to the multiplier of the present disclosure, the mode selection unit may select the multiplier to operate in the fourth operation mode according to the data formats of the two floating-point numbers.

[0031] It can be seen that the different operation modes of the present disclosure are associated with corresponding floating-point data. In other words, the operation mode of the present disclosure can be used to indicate the data format of the first floating-point number and the data format of the second floating-point number. In another embodiment, the operation mode of the present disclosure can not only indicate the data format of the first floating-point number and the data format of the second floating-point number, but also can be used to indicate the data format after the multiplication operation. The operation mode expanded in conjunction with Table 2 is shown in Table 3 below.

[0032] Table 3

[0033]

[0034] Unlike the operation mode numbers shown in Table 2, the operation modes in Table 3 are extended by one bit to indicate the data format after the floating-point multiplication operation. For example, when the multiplier operates in operation mode 21, it performs a floating-point operation on the two floating-point numbers input (BF16×BF16) and outputs the floating-point multiplication result in the FP16 data format.

[0035] The above operation modes in the form of numbers to indicate the floating-point data format are merely exemplary and non-restrictive. According to the teachings of the present disclosure, it is also conceivable to establish an index according to the operation mode to determine the format of the multiplier and the multiplicand. For example, the operation mode includes two indexes, the first index is used to indicate the type of the first floating-point number, and the second index is used to indicate the type of the second floating-point number. For example, the first index "1" in the operation mode 13 indicates that the first floating-point number (or multiplicand) is in the first floating-point format, i.e., FP16, and the second index "3" indicates that the second floating-point number (or multiplier) is in the second floating-point format, i.e., FP32. Furthermore, a third index can also be added to the operation mode, and the third index indicates the data format of the output result. For example, for the third index "1" in the operation mode 131, it can indicate that the data format of the output result is the first floating-point format, i.e., FP16. When the number of operation modes increases, the corresponding index or index level can be added as needed to facilitate the establishment of the relationship between the operation mode and the data format.

[0036] In addition, although the operation mode is exemplarily referred to here with digital numbering, in other examples, the operation mode can also be referred to with other symbols or codings according to application needs, for example, by letters, symbols or numbers and combinations thereof, etc., and the expression of such letters, numbers, symbols or their combinations refers to the operation mode and identifies the data format of the first floating-point number, the second floating-point number and the output result. In addition, when these expressions are formed in the form of instructions, the instruction can include three domains or fields, the first domain being used to indicate the data format of the first floating-point number, the second domain being used to indicate the data format of the second floating-point number, and the third domain being used to indicate the data format of the output result. Of course, these domains can also be merged into one domain, or new domains can be added to indicate more content related to the floating-point data format. It can be seen that the operation mode of the present disclosure can not only be associated with the floating-point number data format of the input, but also can be used to normalize the output result to obtain the product result of the desired data format.

[0037] Figure 3 FIG. 1 is a block diagram showing a more detailed structure of the multiplier 300 according to an embodiment of the present disclosure. Figure 3 As can be seen from the content shown, it not only includes Figure 2 The exponent processing unit 202, the mantissa processing unit 204 and the optional sign processing unit 206 are shown in FIG, and the internal components that these units may include and the units related to the operation of these units are also shown. Figure 3 The exemplary operations of these units are described in detail.

[0038] To perform a floating-point multiplication operation, an exponent processing unit may be configured to obtain an exponent after the multiplication operation based on the aforementioned operation mode, the exponent of the first floating-point number, and the exponent of the second floating-point number. In one embodiment, the exponent processing unit may be implemented by an addition and subtraction circuit. For example, the exponent processing unit may be configured to add the exponent of the first floating-point number, the exponent of the second floating-point number, and the offset value of the corresponding input floating-point data format, and then subtract the offset value of the output floating-point data format to obtain the exponent of the first floating-point number and the second floating-point number after the multiplication operation.

[0039] Furthermore, the mantissa processing unit of the multiplier can be used to obtain the mantissa after the multiplication operation according to the aforementioned operation mode, the first floating-point number and the second floating-point number. In one embodiment, the mantissa processing unit may include a partial product operation unit 312 and a partial product summing unit 314, wherein the partial product operation unit is used to obtain an intermediate result according to the mantissa of the first floating-point number and the mantissa of the second floating-point number. In some embodiments, the intermediate result can be a plurality of partial products (such as the product of the first floating-point number and the product of the second floating-point number) obtained during the multiplication operation. Figure 5 and Figure 6The partial product summing unit is configured to perform a sum operation on the intermediate results to obtain a sum result, and use the sum result as the mantissa after the multiplication operation.

[0040] To obtain an intermediate result, in one embodiment, the present disclosure utilizes a Booth encoding circuit to pad the high and low bits of the mantissa of the second floating-point number (e.g., serving as a multiplier in a floating-point operation) with zeros (where padding the high bits with zeros converts the mantissa from an unsigned number to a signed number) to obtain the intermediate result. It should be understood that, depending on the encoding method, the mantissa of the first floating-point number (e.g., serving as a multiplicand in a floating-point operation) may also be encoded (e.g., padding the high and low bits with zeros), or both may be encoded to obtain multiple partial products. More description of the partial products will be provided later in conjunction with the accompanying drawings.

[0041] In another embodiment, the partial product summation unit may include an adder configured to sum the intermediate results to obtain the summed result. In yet another embodiment, the partial product summation unit includes a Wallace tree and an adder, wherein the Wallace tree is configured to sum the intermediate results to obtain a second intermediate result, and the adder is configured to sum the second intermediate results to obtain the summed result. In these embodiments, the adder may include at least one of a full adder, a serial adder, and a carry look-ahead adder.

[0042] In one embodiment, the multiplier disclosed herein further includes a second normalization unit 318 and a rounding unit 320. The second normalization unit can be configured to perform floating-point normalization processing on the mantissa and exponent after the multiplication operation to obtain a normalized exponent result and a normalized mantissa result, and use the normalized exponent result and the normalized mantissa result as the exponent and mantissa after the multiplication operation. For example, based on the data format indicated by the operation mode, the second normalization unit can adjust the bit width of the exponent and mantissa to conform to the requirements of the data format indicated above. Furthermore, the second normalization unit can also make other adjustments to the exponent or mantissa. For example, in some application scenarios, when the mantissa value is not 0, the most significant bit of the mantissa should be 1; otherwise, the exponent bits can be modified and the mantissa bits can be shifted simultaneously to form a normalized number. In another embodiment, the second normalization unit can also adjust the exponent after the multiplication operation based on the mantissa after the multiplication operation. For example, when the most significant bit of the mantissa after the multiplication operation is 1, the exponent obtained after the multiplication operation can be increased by 1. Accordingly, the rounding unit can be configured to perform a rounding operation on the regularized mantissa result according to a rounding mode, and use the mantissa after the rounding operation as the mantissa after the multiplication operation. Depending on different application scenarios, the rounding unit can perform rounding operations including, for example, rounding down, rounding up, rounding to the nearest significant figure, etc. In some application scenarios, the rounding unit can also round off 1s that are shifted out during the right shift of the mantissa.

[0043] In addition to the exponent processing unit and the mantissa processing unit, the multiplier disclosed herein may optionally include a sign processing unit. When the input floating-point number is a floating-point number with a sign bit, the sign processing unit may be used to obtain the sign after the multiplication operation based on the sign of the first floating-point number and the sign of the second floating-point number. For example, in one embodiment, the sign processing unit may include an exclusive-OR logic circuit 322, which is used to perform an exclusive-OR operation based on the sign of the first floating-point number and the sign of the second floating-point number to obtain the sign after the multiplication operation. In another embodiment, the sign processing unit may also be implemented by a truth table or logical judgment.

[0044] In addition, in order to make the first and second floating-point numbers input or received conform to the prescribed format, in one embodiment, the multiplier disclosed herein may further include a first normalization processing unit 324 for performing normalization processing on the first floating-point number or the second floating-point number according to the operation mode when the first floating-point number or the second floating-point number is a non-normalized non-zero floating-point number to obtain the corresponding exponent and mantissa. For example, when the selected operation mode is the second operation mode shown in Table 2, and the first and second floating-point numbers input are FP16 type data, the first normalization processing unit can be used to normalize the FP16 type data to BF16 type data so that the multiplier operates in the second operation mode. In one or more embodiments, the first normalization processing unit may also be used to pre-process the mantissa of the normalized floating-point number with implicit 1 and the non-normalized floating-point number without implicit 1 (e.g., expansion of the mantissa) to facilitate the operation of the subsequent mantissa processing unit. Based on the above description, it can be understood that the first normalization processing unit 324 here and the aforementioned second normalization processing unit 318 can also perform the same or similar operations in some embodiments. The difference is that the first normalization processing unit 324 performs normalization processing on the input floating-point data, while the second normalization processing unit 318 performs regularization processing on the mantissa and exponent to be output.

[0045] Combination of the above Figure 3 The multiplier of the present disclosure and its multiple embodiments are described. Based on the above description, those skilled in the art will appreciate that the scheme of the present disclosure obtains the result (including exponent, mantissa and optional symbol) after the multiplication operation by the execution of the multiplier. Depending on the application scenario, for example, when the aforementioned regularization and rounding are not needed, the result obtained by the mantissa processing unit and the exponent processing unit can be regarded as the final operation result. Further, when the aforementioned regularization and rounding are needed, the exponent and mantissa obtained after the regularization and rounding can be regarded as the final operation result, or a part of the final operation result (when considering the final symbol). Further, the scheme of the present disclosure enables the multiplier to support the operation of floating-point numbers of different types or data formats through a variety of operation modes, thereby realizing the reuse of the multiplier, thereby saving the overhead of chip design and saving computing cost. In addition, through the multiple call mechanism, the multiplier of the present disclosure also supports the calculation of floating-point numbers with high bit width. In view of the fact that the multiplication operation of the mantissa (or mantissa bit or mantissa part) is crucial to the performance of the entire floating-point operation in the floating-point multiplication operation, the following will combine Figure 4 To describe the mantissa operation of the present disclosure.

[0046] Figure 4 FIG. 4 is a schematic block diagram illustrating the operation of a mantissa processing unit 400 according to an embodiment of the present disclosure. Figure 4As shown in , the mantissa processing operation of the present disclosure can mainly involve two units, namely the aforementioned combined Figure 3 The partial product operation unit and the partial product summation unit discussed. From the perspective of operation timing, the mantissa processing operation can be roughly divided into a first stage and a second stage. In the first stage, the mantissa processing operation will obtain an intermediate result, and in the second stage, the mantissa processing operation will obtain the mantissa result output from the adder 408.

[0047] In an exemplary specific operation, the first floating point number and the second floating point number received by the multiplier can be divided into a plurality of parts, namely the aforementioned sign (optional), exponent and mantissa. Optionally, after normalization, the mantissa parts of the two floating point numbers will be input into the mantissa processing unit (e.g. Figure 2 or Figure 3 The mantissa processing unit in the , and specifically enters the partial product operation unit. Figure 4 As shown in FIG, the present disclosure utilizes Booth encoding circuit 402 to pad the high and low bits of the mantissa of the second floating-point number (i.e., the multiplier in the floating-point operation) with zeros and performs Booth encoding processing, thereby obtaining the intermediate result in partial product generation circuit 404. Of course, the first floating-point number and the second floating-point number here are merely for illustrative and non-restrictive purposes. Therefore, in some application scenarios, the first floating-point number may be the multiplier and the second floating-point number may be the multiplicand. Accordingly, in some encoding processes, the encoding operation may also be performed on the floating-point number serving as the multiplicand.

[0048] In order to better understand the technical solution disclosed in the present invention, Booth coding is briefly introduced below. Generally, when two binary numbers are multiplied, a large number of intermediate results called partial products are generated through the multiplication operation, and then these partial products are accumulated to obtain the final result of the multiplication of the two binary numbers. The more partial products there are, the larger the area and power consumption of the array multiplier will be, the slower the execution speed will be, and the more difficult it will be to implement the circuit. The purpose of Booth coding is to effectively reduce the number of summation terms of the partial products, thereby reducing the circuit area. The algorithm is to first encode the input multiplier according to the corresponding rules. In one embodiment, the encoding rules can be, for example, the rules shown in Table 4 below:

[0049] Table 4

[0050]

[0051] Among them, y in Table 4 2i+1 ,y 2i and y 2i-1It can represent the numerical value corresponding to each group of sub-data to be encoded (i.e., multiplier), and X can represent the mantissa in the first floating-point number (i.e., multiplicand). After Booth encoding is performed on each corresponding group of data to be encoded, the corresponding encoded signal PPi (i=0, 1, 2, ..., n) is obtained. As shown schematically in Table 4, the encoded signal obtained after Booth encoding can include five categories, namely -2X, 2X, -X, X and 0. For example, based on the above encoding rules, if the received multiplicand is 8-bit data " ", we can obtain the following partial products:

[0052] 1) When the multiplier digits include the three consecutive data "001" in the table above, the partial product is X, which can be expressed as " ", the 9th bit is the sign bit, that is ;

[0053] 2) When the multiplier includes the three consecutive data "011" in the table above, the partial product is 2X, which can be expressed as X shifted left by one bit to obtain " 0", that is

[0054] 3) When the multiplier digits include the three consecutive digits "101" in the table above, the partial product is -X, which can be expressed as " ", indicating that "Complement the bit and add 1, that is

[0055] 4) When the multiplier includes three consecutive digits "100" in the table above, the partial product is -2X, which can be expressed as , indicating that "Shift left one bit, invert it and add 1, that is +1;

[0056] 5) When the multiplier digits include three consecutive data "111" or "000" in the table above, the partial product is 0, that is, .

[0057] It should be understood that the description of the process of obtaining partial products in conjunction with Table 4 above is merely illustrative and non-limiting. Based on the teachings of this disclosure, those skilled in the art may modify the rules in Table 4 to obtain partial products different from those shown in Table 4. For example, when the multiplier contains a specific number of consecutive digits (e.g., 3 or more digits), the obtained partial product may be the complement of the multiplicand, or the "add 1" operation in items 3) and 4) above may be performed after the partial products are added.

[0058] Based on the above introductory description, it can be understood that by encoding the mantissa of the second floating-point number using a Booth encoding circuit and using the mantissa of the first floating-point number, multiple partial products can be generated from the partial product generation circuit as intermediate results, and the intermediate results are input to the Wallace Tree compressor 406 in the partial product summation unit. It should be understood that the use of Booth encoding to obtain partial products here is only a preferred method for obtaining partial products in the present disclosure, and those skilled in the art can also obtain such partial products in other ways. For example, they can also be obtained through shift operations, that is, according to whether the bit value of the multiplier is 1 or 0, the multiplicand is shifted and added or 0 is added to obtain the corresponding partial products. Similarly, the use of a Wallace Tree compressor to implement the addition operation of partial products is merely exemplary and non-limiting. Those skilled in the art can also conceive of using other types of adders to implement such partial product addition operations. The adder can, for example, be one or more full adders, half adders, or various combinations of the two.

[0059] The Wallace tree compressor (or simply Wallace tree) is primarily used to sum the aforementioned intermediate results (i.e., multiple partial products) to reduce the number of partial product accumulations (i.e., compression). Typically, a Wallace tree compressor employs a carry-save CAS (carry-save) architecture and a Wallace tree algorithm. This utilizes a Wallace tree array, resulting in computational speeds much faster than traditional carry-propagation additions.

[0060] Specifically, the Wallace tree compressor can calculate the sum of the partial products of each row in parallel. For example, the number of accumulations of N partial products can be reduced from N-1 times to Log2N times, thereby improving the speed of the multiplier, which is of great significance for the effective use of resources. According to different application needs, the Wallace tree compressor can be designed into various types, such as 7-2 Wallace tree, 4-2 Wallace tree and 3-2 Wallace tree. In one or more embodiments, the present disclosure uses the 7-2 Wallace tree as an example to implement various floating-point operations of the present disclosure, which will be combined later. Figure 5 and Figure 6 Describe it in detail.

[0061] In some embodiments, the Wallace tree compression operation disclosed herein can be arranged to have M inputs and N outputs, which can be no less than K, where N is a preset positive integer less than M, and K is a positive integer no less than the maximum bit width of the intermediate result. For example, M can be 7 and N can be 2, i.e., a 7-2 Wallace tree, described in detail below. When the maximum bit width of the intermediate result is 48, K can be a positive integer 48, which means that the number of Wallace trees can be 48.

[0062] In some embodiments, according to the operation mode, one or more groups of the Wallace trees can be selected to sum the intermediate results, wherein each group has X Wallace trees, and X is the number of bits of the intermediate result. Furthermore, there can be a carry relationship between the Wallace trees within each group, while there is no carry relationship between the groups. In an exemplary connection, the Wallace tree compressors can be connected through the carry, for example, the carry output from the low-order Wallace tree compressor (such as Figure 6 Middle C in ) to the high-order Wallace tree, and the carry output of the high-order Wallace tree compressor (C out ) can also become a higher-order Wallace tree compressor that receives the carry input from the lower-order Wallace tree compressor. Furthermore, when selecting one or more Wallace tree compressors from multiple Wallace tree compressors, any selection can be made. For example, they can be selected in the order of 0, 1, 2, and 3, or they can be connected in the order of 0, 2, 4, and 6, as long as the selected Wallace tree compressors are selected according to the above-mentioned carry relationship.

[0063] The following example describes the Wallace tree and its operation. Assume that the first and second floating-point numbers are 16-bit data (e.g., FP16×FP16), the multiplier supports a 32-bit data width (thus supporting parallel multiplication of two 16-bit data sets), and the Wallace tree is a 7-2 Wallace tree compressor with 7 inputs (i.e., an example value for M above) and 2 outputs (i.e., an example value for N above). In this example scenario, 48 Wallace trees (i.e., an example value for K above) can be used to perform the multiplication of the two data sets in parallel.

[0064] Among the 48 Wallace trees described above, the 0th to 23rd Wallace trees (i.e., the 24 Wallace trees in the first group of Wallace trees) can complete the partial product-addition sum operation of the first group of multiplications, and each Wallace tree in this group can be sequentially connected by a carry. Furthermore, the 24th to 47th Wallace trees (i.e., the 24 Wallace trees in the second group of Wallace trees) can complete the partial product-addition sum operation of the second group of multiplications, where each Wallace tree in this group is sequentially connected by a carry. In addition, there is no carry relationship between the 23rd Wallace tree in the first group and the 24th Wallace tree in the second group, that is, there is no carry relationship between Wallace trees in different groups.

[0065] Return to Figure 4After the partial products are added and compressed by the Wallace tree compressor, the compressed partial products are summed by an adder to obtain the result of the mantissa multiplication operation. Regarding the adder, in one or more embodiments of the present disclosure, it may include one of a full adder, a serial adder, and a carry-lookahead adder, and is configured to sum the last two rows of partial products obtained by the Wallace tree compressor to obtain the result of the mantissa multiplication operation.

[0066] Understandably, through Figure 4 The mantissa multiplication operation shown, particularly the exemplary use of Booth encoding and Wallace trees, can efficiently achieve the result of the mantissa multiplication operation. Specifically, the Booth encoding process can effectively reduce the number of partial product summation terms, thereby reducing circuit area, while the Wallace compression tree can parallelize the calculation of the partial product sums for each row, thereby increasing the speed of the multiplier.

[0067] The following will be combined Figure 5 and Figure 6 The exemplary operation process of the partial product and 7-2 Wallace tree is described in detail. It is understood that the description here is merely illustrative and not restrictive, and is intended only to provide a better understanding of the disclosed solution.

[0068] Figure 5 Shown in the above combination Figure 2-Figure 4 The partial product 500 obtained after the partial product generation circuit in the mantissa processing unit is shown as four rows of white dots between two dotted lines in the figure, where each row of white dots identifies a partial product. In order to facilitate the subsequent execution of the Wallace tree compressor, the number of bits can be expanded in advance. For example, Figure 5 The black dots in the figure are the most significant bit values ​​of each replicated 9-bit partial product. It can be seen that the partial products are aligned to 16(8+8) bits (i.e., 8 bits of the multiplicand's mantissa + 8 bits of the multiplier's mantissa). In another embodiment, for example, for a partial product of a 25×13 binary multiplication, the partial products are aligned to 38(25+13) bits (i.e., 25 bits of the multiplicand's mantissa + 13 bits of the multiplier's mantissa).

[0069] Figure 6 FIG6 is a schematic block diagram 600 illustrating an operation flow of a Wallace tree compressor according to an embodiment of the present disclosure.

[0070] like Figure 6 As shown in , after performing a multiplication operation on the mantissas of two floating-point numbers, for example, as described above, by Booth encoding the multiplier and by the multiplicand, we can obtain Figure 6The 7 partial products shown in . Due to the use of the Booth coding algorithm, the number of partial products generated is reduced. For ease of understanding, a Wallace tree consisting of 7 elements is marked with a dotted box in the partial product part of the figure, and the process of compression from 7 elements to 2 elements is further shown with arrows. In one embodiment, the compression process (or addition process) can be implemented with the help of a full adder, that is, three elements are input and two elements are output (that is, a sum and a carry to the high position). 7-2 Schematic block diagram of the Wallace tree compressor is in Figure 6 As shown on the right side of , it can be understood that the Wallace tree compressor includes 7 inputs from a column of partial products (such as Figure 6 The seven elements are marked in the dotted box on the left. In operation, the carry input of the 0th column of the Wallace tree is 0, and the carry output Cout of each column of the Wallace tree serves as the carry input Cin of the next column of the Wallace tree.

[0071] from Figure 6 As can be seen in the left portion, after four compressions, the Wallace tree consisting of 7 elements can be compressed to consist of 2 elements. As mentioned above, the present disclosure utilizes a 7-2 Wallace tree compressor to ultimately compress the partial products of 7 rows into partial products having two rows (i.e., the second intermediate result of the present disclosure), and utilizes an adder (e.g., a carry lookahead adder) to obtain the mantissa result.

[0072] To further illustrate the principles of the disclosed solution, the following describes, by way of example, how the disclosed multiplier performs operations in the first stage under the four operation modes of FP16×FP16, FP16×FP16, FP32×FP32, and FP32×BF16, i.e., until the Wallace tree compressor completes the summation of the intermediate results to obtain the second intermediate result:

[0073] (1) FP16×FP16

[0074] In this operation mode of the multiplier, the mantissa of the floating-point number is 10 bits. Considering the non-normalized non-zero number under the IEEE754 standard, the mantissa can be extended by 1 bit, so that the mantissa is 11 bits. In addition, since the mantissa is an unsigned number, the Booth encoding algorithm can be used to extend the high-order 1-bit 0, so the total number of mantissa bits is 12 bits. When Booth encoding is performed on the second floating-point number, i.e., the multiplier, and with reference to the first floating-point number, the partial product generation circuit can obtain 7 partial products in the high and low parts respectively, of which the seventh partial product is 0. The bit width of each partial product is 24 bits. At this time, it can be compressed using 48 7-2 Wallace trees, and the carry from the 23rd to the 24th Wallace tree is 0.

[0075] (2)BF16×BF16

[0076] In this multiplier operation mode, the floating-point number's mantissa is 7 bits. Considering the denormalization of non-zero numbers and the extension to signed numbers under the IEEE 754 standard, the mantissa can be expanded to 9 bits. When Booth encoding is performed on the second floating-point number, the multiplier, and referenced to the first floating-point number, the partial product generation circuit generates seven significant partial products in the high and low parts, respectively. The sixth and seventh partial products are 0, and each partial product has an 18-bit bit width. Compression is performed using two groups of 7-2 Wallace trees, the 0th to 17th and the 24th to 41st, with the carry from the 23rd to 24th Wallace tree being 0.

[0077] (3) FP32×FP32

[0078] In this operation mode of the multiplier, the mantissa of the floating-point number can be 23 bits. Considering the non-normalized non-zero number and the extension to the signed number under the IEEE754 standard, the mantissa can be extended to 25 bits. In order to save the area of ​​the multiplication unit, for example, the bit width supported by the multiplier can be designed to be smaller, and the multiplier disclosed in this operation mode can be called twice to complete an operation. To this end, the multiplication performed on the mantissa each time is 25bit×13bit, that is, the first floating-point number ina is expanded by 1 bit 0 to become a 25-bit signed number, and the 24-bit mantissa of the second floating-point number inb is divided into two parts, 12 bits high and low, and each part is expanded by 1 bit 0 to obtain two 13-bit multipliers, expressed as inb_high13 and inb_low13 high and low parts. In the specific operation, the multiplier disclosed in this disclosure is called for the first time to calculate ina×inb_low13, and the multiplier is called for the second time to calculate ina×inb_high13. In each calculation, 7 effective partial products are generated by Booth coding. The bit width of each partial product is 38 bits, and they are compressed by the 7-2 Wallace tree from 0 to 37.

[0079] (4)FP32×BF16

[0080] In this operation mode of the multiplier, the mantissa of the first floating-point number ina is 23 bits, and the mantissa of the second floating-point number inb is 7 bits. Considering the denormalized non-zero number and the extension to the signed number under the IEEE754 standard, the mantissa can be expanded to 25 bits and 9 bits respectively. 25-bit × 9-bit multiplication is performed to obtain 7 valid partial products, of which the 6th and 7th partial products are 0. The bit width of each partial product is 34 bits, which is compressed through the 0th to 33rd Wallace trees.

[0081] The above describes, through specific examples, how the disclosed multiplier performs the first-stage operation in four operation modes, preferably using the Booth encoding algorithm and the 7-2 Wallace tree. Based on the above description, those skilled in the art will understand that the disclosed multiplier utilizes seven partial products, enabling the reuse of the 7-2 Wallace tree in different operation modes.

[0082] The following describes in more detail the case where the multiplier (mantissa processing unit and exponent processing unit) of the present disclosure is called multiple times.

[0083] According to another aspect of the present disclosure, Figure 3 As shown, the mantissa processing unit may include a control circuit 316, and the control circuit 316 may be configured to call the mantissa processing unit multiple times when the mantissa bit width of at least one of the two floating-point numbers is greater than the data bit width that the mantissa processing unit can process at one time. The data bit width that the mantissa processing unit can process at one time refers to the two bit widths supported by the mantissa processing unit (e.g., the multiplier bit width and the multiplicand bit width). Therefore, it can be understood that the control circuit is configured to determine whether to call the mantissa processing unit multiple times to obtain the mantissa after the multiplication operation based on the mantissa bit width of one of the two floating-point numbers and one of the two bit widths supported by the mantissa processing unit, or based on the mantissa bit width of the two floating-point numbers and the two bit widths supported by the mantissa processing unit. Therefore, this repeated calling of the mantissa processing unit in the multiplier avoids the need to deploy a large-area multiplier component to process large-bitwidth mantissa operations and avoids the need to deploy a small-area multiplier component that is unable to process large-bitwidth mantissa operations, thereby improving applicability and reducing chip area.

[0084] According to a first embodiment of the present disclosure, the two floating-point numbers include a first floating-point number and a second floating-point number, the mantissa processing unit supports a first bit width and a second bit width, the mantissa of the first floating-point number serves as a first input corresponding to the first bit width, the mantissa of the second floating-point number serves as a second input corresponding to the second bit width, the bit width of the first input is less than or equal to the first bit width, and the control circuit is used to call the mantissa processing unit multiple times to obtain the mantissa after the multiplication operation when the bit width of the second input is greater than the second bit width. According to this embodiment, it is known that the bit width of one of the two inputs is fixedly less than or equal to a bit width supported by the corresponding mantissa processing unit. Therefore, it is only necessary to judge the size relationship between the other input and the bit width supported by the corresponding mantissa processing unit to determine whether to call the mantissa processing unit multiple times.

[0085] According to a second embodiment of the present disclosure, the two floating-point numbers include a first floating-point number and a second floating-point number, the mantissa processing unit supports a first bit width and a second bit width, the mantissa of the first floating-point number is used as a first input corresponding to the first bit width, and the mantissa of the second floating-point number is used as a second input corresponding to the second bit width, and the control circuit is used to call the mantissa processing unit multiple times to obtain the mantissa after the multiplication operation when the bit width of the first input is greater than the first bit width and the bit width of the second input is less than or equal to the second bit width, when the bit width of the second input is greater than the second bit width and the bit width of the first input is less than or equal to the first bit width, or when the bit width of the first input is greater than the first bit width and the bit width of the second input is greater than the second bit width. According to this embodiment, the size relationship between the bit widths of the two inputs and the two bit widths supported by the mantissa processing unit is uncertain, and it is necessary to judge the size relationship between the two inputs and the bit widths supported by their respective corresponding mantissa processing units to determine whether to call the mantissa processing unit multiple times.

[0086] According to the second embodiment, when the mantissa bit width of the first floating-point number is less than the mantissa bit width of the second floating-point number and the first bit width is greater than the second bit width, or when the mantissa bit width of the first floating-point number is greater than the mantissa bit width of the second floating-point number and the first bit width is less than the second bit width, the control circuit selects the mantissa of the first floating-point number as the second input corresponding to the second bit width and selects the mantissa of the second floating-point number as the first input corresponding to the first bit width. It should be understood that when the mantissas of the two floating-point numbers are input irregularly, the mantissas of the two floating-point numbers input can be matched with the two bit widths supported by the mantissa processing unit according to the strategy of large bit width to large bit width and small bit width to small bit width, so as to avoid the mantissa operation of the two floating-point numbers that can be completed in one process being called multiple times.

[0087] Furthermore, when the bit width of the first input is greater than the first bit width and the bit width of the second input is less than or equal to the second bit width, the control circuit determines the number of times the mantissa processing unit is called and the data to be input to the mantissa processing unit in each call based on the bit width of the first input and the first bit width. When the bit width of the second input is greater than the second bit width and the bit width of the first input is less than or equal to the first bit width, the control circuit determines the number of times the mantissa processing unit is called and the data to be input to the mantissa processing unit in each call based on the bit width of the second input and the second bit width. When the bit width of the first input is greater than the first bit width and the bit width of the second input is greater than the second bit width, the control circuit determines the number of times the mantissa processing unit is called and the data to be input to the mantissa processing unit in each call based on the bit width of the first input and the first bit width, and the bit width of the second input and the second bit width.

[0088] In this disclosure, the description of a first floating-point number and a second floating-point number is merely for distinguishing the two floating-point numbers, wherein "first" and "second" do not have a limiting effect. Similarly, the description of a first bit width and a second bit width is merely for distinguishing the two maximum processing bit widths supported by the mantissa processing unit, and the description of a first input and a second input is merely for distinguishing the two inputs of the mantissa processing unit corresponding to the two maximum processing bit widths, and therefore, "first" and "second" do not have a limiting effect.

[0089] It is noteworthy that the floating-point numbers input to the multiplier described in the above embodiments are floating-point numbers that meet the required format for the operation and are applicable to the internal and external components of the multiplier, that is, floating-point numbers that have undergone preprocessing such as normalization. It should be understood that the floating-point numbers input to the multiplier can be normalized or non-normalized floating-point numbers. In combination with the above description of the first normalization processing unit, it can be seen that if at least one of the two floating-point numbers input is a non-normalized non-zero floating-point number, the at least one floating-point number can be first normalized by the first normalization processing unit to obtain a normalized exponent and mantissa, and then the normalized mantissa is used as the input of the mantissa processing unit to perform the above-mentioned floating-point multiplication operation. In addition, the Booth encoding circuit mentioned earlier in this disclosure performs signed fixed-point multiplication calculations, so it is also necessary to extend the mantissa by 1 bit 0, that is, to convert the mantissa into a signed positive number, and then use the extended signed mantissa as the input of the mantissa processing unit to perform the above-mentioned floating-point multiplication operation. Of course, other preprocessing can also be performed on the floating-point numbers, and the mantissa of the preprocessed floating-point numbers can be used as the input of the mantissa processing unit to perform the above-mentioned floating-point multiplication operation. For example, the normalization of floating-point numbers for the purpose of adapting the operation mode mentioned in the above description of the first normalization processing unit, the first embodiment and the second embodiment of the present disclosure are also applicable to the floating-point operations according to the operation mode as described above.

[0090] Three examples of multiple calls to the mantissa processing unit according to the second embodiment of the present disclosure are described in detail below. To more clearly and intuitively understand these three examples, the first input may be, for example, a multiplier, the second input may be, for example, a multiplicand, the first bit width may be, for example, the maximum multiplier bit width supported by the mantissa processing unit, and the second bit width may be, for example, the maximum multiplicand bit width supported by the mantissa processing unit.

[0091] According to the first example of multiple calls to the mantissa processing unit of the present disclosure, in combination with the floating-point multiplication operation according to the operation mode described above, taking the case where the two floating-point numbers input to the multiplier of the present disclosure are non-normalized non-zero floating-point numbers as an example, and in combination with the case where the Booth encoding circuit used in the present disclosure performs a signed fixed-point multiplication operation, the two floating-point numbers are first normalized, so that the mantissas of the two floating-point numbers are extended by 1 bit. In addition, to be suitable for the Booth encoding circuit in the embodiment of the present disclosure, the two mantissas are further extended by 1 bit to form signed numbers. After these preprocessing, the mantissas of the two floating-point numbers are matched with the input of the mantissa processing unit. Therefore, when the bit width of the multiplier is greater than the maximum multiplier bit width and the bit width of the multiplicand is less than or equal to the maximum multiplicand, the control circuit uses the mantissa formed by normalizing the original mantissa corresponding to the multiplier as the mantissa to be truncated, and to be suitable for the Booth encoding circuit in the embodiment of the present disclosure, the sign bit is extended for each truncated portion. In order to enable the mantissa processing unit to process the mantissa to be truncated, a portion with a bit width of A-1 is truncated from the mantissa to be truncated in each call, where A represents the maximum multiplier bit width supported by the mantissa processing unit. A 0 is added to the high bit of the truncated portion with a bit width of A as a sign to form a multiplier portion with a bit width of A. This multiplier portion serves as an input to the mantissa processing unit in each call. In addition, the multiplicand (in this embodiment, the multiplicand is a normalized and sign-extended mantissa) is input to the mantissa processing unit as another input in each call. Therefore, the following formula can be used to determine the number of calls to the mantissa processing unit:

[0092] n=ceil((B+1) / (A-1)),

[0093] Where n represents the number of times the mantissa processing unit is called, B represents the bit width of the unnormalized and unsigned mantissa, B+1 represents the bit width of the normalized mantissa, and B+1 can also be understood as B+2-1, that is, the bit width of the multiplier minus the bit width of the sign bit, A represents the bit width of the multiplier part (the maximum multiplier bit width supported by the mantissa processing unit), and A-1 represents the bit width of the part of the mantissa to be truncated in each call.

[0094] For example, the maximum multiplier bit width supported by the mantissa processing unit is, for example, 8 bits, and the maximum multiplicand bit width is, for example, 32 bits. The two floating-point numbers input to the multiplier are FP32 and BF16 floating-point numbers, respectively. Therefore, the multiplication operation is performed in FP32×BF16 operation mode. The two floating-point numbers are denormalized non-zero numbers, so the mantissas of the two floating-point numbers have bit widths of 23 bits and 7 bits, respectively. Considering the IEEE754 standard, the bit widths of the two mantissas can be expanded to 24 bits and 8 bits. To be applicable to the Booth encoding circuit in the embodiment of the present disclosure, the two mantissas are further expanded by 1 bit 0 to become 25-bit and 9-bit signed numbers. Therefore, the control circuit uses the mantissa with a bit width of 9 bits as the multiplier corresponding to the maximum multiplier bit width and uses the mantissa with a bit width of 25 bits as the multiplicand corresponding to the maximum multiplicand bit width. Since only the bit width of the multiplier (9 bits) is greater than the maximum multiplier bit width (8 bits), and the bit width of the multiplicand (25 bits) is less than the maximum multiplicand bit width (32 bits), the mantissa formed after normalization of the original mantissa corresponding to the multiplier is used as the mantissa to be truncated inb, and the multiplicand is used as the multiplicand ina of the input mantissa processing unit. According to the above formula, ceil((7+1) / (8-1))=2, so it is necessary to call the mantissa processing unit twice, and in each call, 7 bits of data are intercepted each time in inb. In the last call (the second call), if there is less than 7 bits of data, all the remaining data will be intercepted and padded with 0 to make up 7 bits, and each time the intercepted 7-bit data is expanded by 1 bit 0 (sign bit) to become 8 bits as the multiplier part inb_m. Therefore, the calculation performed in each call is ina×inb_m, that is, the multiplication of the multiplicand with a bit width of 25 bits and the multiplier part with a bit width of 8 bits, so that the mantissa result obtained by this call can be calculated. It is worth noting that the interception of the mantissa to be intercepted can be performed in order from high to low, or in order from low to high. It is worth noting that this example is also applicable to the above-mentioned first embodiment of the present disclosure.

[0095] According to the second example of the multiple calls to the mantissa processing unit of the present disclosure, in combination with the floating-point multiplication operation according to the operation mode described above, taking the case where the two floating-point numbers input to the multiplier of the present disclosure are non-normalized non-zero floating-point numbers as an example, and in combination with the case where the Booth encoding circuit used in the present disclosure performs a signed fixed-point multiplication operation, the two floating-point numbers are first normalized, so that the mantissas of the two floating-point numbers are extended by 1 bit. In addition, to be suitable for the Booth encoding circuit in the embodiment of the present disclosure, the two mantissas are further extended by 1 bit to form signed numbers. After these preprocessing, the mantissas of the two floating-point numbers are matched with the input of the mantissa processing unit. Therefore, when the bit width of the multiplicand is greater than the maximum multiplicand bit width and the bit width of the multiplier is less than or equal to the maximum multiplier bit width, the control circuit uses the mantissa formed by normalizing the original mantissa corresponding to the multiplicand as the mantissa to be truncated, and to be suitable for the Booth encoding circuit in the embodiment of the present disclosure, the sign bit is extended for each truncated portion. In order to enable the mantissa processing unit to process the mantissa to be truncated, a portion with a bit width of C-1 is truncated from the mantissa in each call, where C represents the maximum multiplicand bit width supported by the mantissa processing unit. A 0 is added to the upper bit of the truncated portion with a bit width of C as a sign to form a multiplicand portion with a bit width of C. This multiplicand portion serves as an input to the mantissa processing unit in each call. In addition, the multiplier (in this embodiment, the multiplier is a normalized and sign-extended mantissa) is input to the mantissa processing unit as another input in each call. Therefore, the following formula can be used to determine the number of calls to the mantissa processing unit:

[0096] n=ceil((D+1) / (C-1)),

[0097] Where n represents the number of times the mantissa processing unit is called, D represents the bit width of the unnormalized and unsigned mantissa, D+1 represents the bit width of the normalized mantissa, and D+1 can also be understood as D+2-1, that is, the bit width of the multiplicand minus the bit width of the sign bit, C represents the bit width of the multiplicand (the maximum multiplicand bit width supported by the mantissa processing unit), and C-1 represents the bit width of the part of the mantissa to be truncated in each call.

[0098] For example, the maximum multiplier bit width supported by the mantissa processing unit is, for example, 12 bits, and the maximum multiplicand bit width is, for example, 16 bits. The two floating-point numbers input to the multiplier are FP32 and BF16 floating-point numbers, respectively. Therefore, the multiplication operation is performed in FP32×BF16 operation mode. The two floating-point numbers are denormalized non-zero numbers, so the mantissas of the two floating-point numbers have bit widths of 23 bits and 7 bits, respectively. Considering the IEEE754 standard, the bit widths of the two mantissas can be expanded to 24 bits and 8 bits. To be applicable to the Booth encoding circuit in the embodiment of the present disclosure, the two mantissas are further expanded by 1 bit 0 to become 25-bit and 9-bit signed numbers. Therefore, the control circuit uses the mantissa with a bit width of 9 bits as the multiplier corresponding to the maximum multiplier bit width and uses the mantissa with a bit width of 25 bits as the multiplicand corresponding to the maximum multiplicand bit width. Since only the bit width of the multiplicand (25 bits) is larger than the maximum multiplicand bit width (16 bits) supported by the mantissa processing unit, and the bit width of the multiplier (9 bits) is smaller than the maximum multiplier bit width (12 bits), the mantissa formed after normalization of the original mantissa corresponding to the multiplicand is used as the mantissa to be truncated ina, and the multiplier is used as the multiplier inb input to the mantissa processing unit. According to the above formula, ceil((23+1) / (16-1))=2, so it is necessary to call the mantissa processing unit twice, and in each call, 15 bits of data are intercepted each time in ina. In the last call (the second call), if the data is less than 15 bits, 0 is added to the front to make up 15 bits, and the 15-bit data intercepted each time is expanded by 1 bit 0 (sign bit) to become 16 bits as the multiplicand part ina_m. Therefore, the calculation performed in each call is ina_m×inb, that is, the multiplication of the multiplicand part with a bit width of 16 bits and the multiplier with a bit width of 9 bits, so that the mantissa result obtained by the call can be calculated. It is worth noting that the interception of the mantissa to be intercepted can be performed in order from high to low, or in order from low to high. It is worth noting that this example is also applicable to the above-mentioned first embodiment of the present disclosure.

[0099] According to the third example of multiple calls to the mantissa processing unit of the present disclosure, in conjunction with the floating-point multiplication operation according to the operation mode described above, taking the case where two floating-point numbers input to the multiplier of the present disclosure are non-zero non-normalized floating-point numbers as an example, and in conjunction with the case where the Booth encoding circuit used in the present disclosure performs a signed fixed-point multiplication operation, the two floating-point numbers are first normalized, thereby extending the mantissas of the two floating-point numbers by one bit. Furthermore, to be suitable for the Booth encoding circuit in the embodiment of the present disclosure, the two mantissas are further extended by one bit to form signed numbers. After these pre-processing steps, the mantissas of the two floating-point numbers are matched with the input of the mantissa processing unit. Therefore, when the bit width of the multiplier is greater than the maximum multiplier bit width and the bit width of the multiplicand (in this embodiment, the multiplicand is a normalized mantissa with the sign bit extended) is greater than the maximum multiplicand bit width, the control circuit uses the mantissa formed by normalizing the original mantissa corresponding to the multiplier and the mantissa formed by normalizing the original mantissa corresponding to the multiplicand as the mantissas to be truncated, and in order to be applicable to the Booth encoding circuit in the embodiment of the present disclosure, extends the sign bit of the portion truncated each time. In order to enable the mantissa processing unit to process these two mantissas to be truncated, in each call, a portion with a bit width of A-1 is truncated from the mantissa corresponding to the multiplier, and a portion with a bit width of C-1 is truncated from the mantissa corresponding to the multiplicand, where A represents the maximum multiplier bit width supported by the mantissa processing unit, and C represents the maximum multiplicand bit width supported by the mantissa processing unit. A 0 is added to the high bit of the portion with a bit width of A each time it is truncated as a sign to form a multiplier portion with a bit width of A. This multiplier portion serves as one input to the mantissa processing unit in each call, and a 0 is added to the high bit of the portion with a bit width of C-1 each time it is truncated as a sign to form a multiplicand portion with a bit width of C. This multiplicand portion serves as another input to the mantissa processing unit in each call. Therefore, the following formula can be used to determine the number of calls to the mantissa processing unit:

[0100] n=ceil((B+1) / (A-1))×ceil((D+1) / (C-1))

[0101] Where n represents the number of times the mantissa processing unit is called, B represents the bit width of the unnormalized, unsigned mantissa, B+1 represents the bit width of the normalized mantissa, which can also be understood as B+2-1, that is, the bit width of the multiplier minus the bit width of the sign bit, A represents the bit width of the multiplier portion (the maximum multiplier bit width supported by the mantissa processing unit), A-1 represents the bit width of the portion of the mantissa to be truncated corresponding to the multiplier in each call, D represents the bit width of the unnormalized, unsigned mantissa, D+1 represents the bit width of the normalized mantissa, D+1 can also be understood as D+2-1, that is, the bit width of the multiplicand minus the bit width of the sign bit, C represents the bit width of the multiplicand portion (the maximum multiplicand bit width supported by the mantissa processing unit), and C-1 represents the bit width of the portion of the mantissa to be truncated in each call.

[0102] For example, the maximum multiplier bit width supported by the mantissa processing unit is, for example, 8 bits, and the maximum multiplicand bit width is, for example, 16 bits. Both floating-point numbers input to the multiplier are FP32 floating-point numbers, so the multiplication operation is performed in FP32×FP32 operation mode. Furthermore, both floating-point numbers are denormalized non-zero numbers, so the mantissa bit widths of both floating-point numbers are 23 bits. Considering the IEEE 754 standard, the bit widths of both mantissas can be expanded to 24 bits. To accommodate the Booth encoding circuit in the disclosed embodiment, both mantissas are further expanded by one bit of 0 to become 25-bit signed numbers. Therefore, the control circuit selects the mantissas of the two floating-point numbers as the multiplier corresponding to the maximum multiplier bit width and the multiplicand corresponding to the maximum multiplicand bit width, respectively. (Since the mantissas of the two floating-point numbers have the same bit width after expansion, one is selected as the multiplier and the other as the multiplicand.) Since the bit width of the multiplier (25 bits) is greater than the maximum multiplier bit width (8 bits), and the bit width of the multiplicand (25 bits) is greater than the maximum multiplicand bit width (16 bits), the mantissa corresponding to the normalized original mantissa of the multiplier is used as the mantissa to be truncated (inb), and the mantissa corresponding to the normalized original mantissa of the multiplicand is used as the mantissa to be truncated (ina). According to the above formula, ceil((23+1) / (8-1)) × ceil((23+1) / (16-1)) = 8, so the mantissa processing unit needs to be called eight times. In each call, 7 bits of data are intercepted in inb each time. If there are less than 7 bits of data in the last call, all the remaining data are intercepted and padded with 0 to make up 7 bits. Each time the 7 bits of data are intercepted, 1 bit of 0 (sign bit) is expanded to 8 bits as the multiplier part inb_m. Since inb is intercepted into four parts, there can be four multiplier parts inb_m1, inb_m2, inb_m3, and inb_m4. In addition, in each call, 15 bits of data are intercepted in ina each time. If there are less than 15 bits of data in the last call, all the remaining data are intercepted and padded with 0 to make up 15 bits. Each time the 15 bits of data are intercepted, 1 bit of 0 (sign bit) is expanded to 16 bits as the multiplicand part ina_m. Since ina is intercepted into two parts, there can be two multiplicand parts ina_m1 and ina_m2.Therefore, for example, when the mantissa processing unit is called eight times, the following calculations can be performed in sequence: ina_m1×inb_m1, ina_m1×inb_m2, ina_m1×inb_m3, ina_m1×inb_m4, ina_m2×inb_m1, ina_m2×inb_m2, ina_m2×inb_m3, ina_m2×inb_m4. Of course, the following calculations can also be performed in sequence: inb_m1×ina_m1, inb_m1×ina_m2, inb_m2×ina_m1, inb_m2×ina_m2, inb_m3×ina_m1, inb_m3×ina_m2, inb_m4×ina_m1, inb_m4×ina_m2. Each call performs a multiplication of the 16-bit multiplicand and the 8-bit multiplier, yielding the mantissa for that call. It's worth noting that the mantissa can be truncated either from high to low or from low to high.

[0103] The above examples are for illustrative purposes only and are not restrictive. Based on these examples, those skilled in the art can conceive of calling the floating-point multiplication operation performed by the mantissa processing unit that supports any bit width multiple times in other operation modes.

[0104] With respect to the above multiple calls to the mantissa processing unit, the mantissa processing unit may further include a shift-addition circuit, and the shift-addition circuit is configured to obtain the mantissa after the multiplication operation according to the mantissa result obtained by each call to the mantissa processing unit.

[0105] Furthermore, the shift-and-add circuit includes a shifter, an intermediate memory, and an adder. When the control circuit calls the mantissa processing unit multiple times according to the operation mode, after the first call, the shifter shifts the mantissa result obtained in the first call to obtain a shifted mantissa result and stores the shifted mantissa result in the intermediate memory. Starting from the second call, the shifter shifts the mantissa result obtained in the current call to obtain the current mantissa result. The adder adds the current mantissa result to the result stored in the intermediate memory and stores the added result in the intermediate memory to update the intermediate memory. After the last call, the result stored in the intermediate memory is used as the mantissa after the multiplication operation.

[0106] In this embodiment, for example, the interception of the mantissa to be intercepted is carried out in the order from high to low. Each time the mantissa processing unit is called, the shifter shifts the mantissa result obtained in the current call according to the following formula:

[0107] Y=k+j

[0108] Wherein, Y represents the number of shifts required for the mantissa result obtained in the current call, k represents the sum of the number of bits of all data following the truncated portion used in the current call in the mantissa to be truncated corresponding to the multiplier, and j represents the sum of the number of bits of all data following the truncated portion used in the current call in the mantissa to be truncated corresponding to the multiplicand. It should be understood that if only the bit width of the multiplier is greater than the maximum multiplier bit width or only the bit width of the multiplicand is greater than the maximum multiplicand bit width, then only the mantissa to be truncated corresponding to the multiplier or the mantissa to be truncated corresponding to the multiplicand needs to be truncated, and the entire data of the mantissa to be truncated is used each time the mantissa is called. Therefore, there is no data following it, and the value of k or j is 0. It can be seen that for the case where only the bit width of the multiplier is greater than the maximum multiplier bit width, the above formula for calculating the number of shifts can be written as: Y=k, and for the case where only the bit width of the multiplicand is greater than the maximum multiplicand bit width, the above formula for calculating the number of shifts can be written as: Y=j.

[0109] For example, as mentioned above, in the FP32×BF16 operation mode, when only the bit width of the multiplier is greater than the maximum multiplier bit width, the mantissa processing unit is called twice, and for example, the truncation of the mantissa to be truncated is performed in order from high to low. Specifically, for example, the multiplier parts in the two calls are inb_m1 and inb_m2 respectively. After the first call, the shifter shifts the result of ina×inb_m1 to the left. Since 7-bit data is intercepted in the first call, the sum of the number of bits of all data after the 7-bit data used in this call is k=8-7=1bit. According to the above formula, Y=1, so the number of bits shifted to the left is 1 bit, thereby obtaining the result R1 after shifting 1 bit, and the adder stores R1 in the intermediate memory; after the second call (the last call), the shifter shifts ina The result of ×inb_m2 is shifted left. Since the last bit of data has been truncated in the second call, there is no data after the 1-bit data used in this call. According to the above formula, Y=0. Therefore, the number of bits shifted left is 0, that is, no shift is made, thereby obtaining the result R2. The adder adds R2 to R1 stored in the intermediate memory and stores the result of the addition in the intermediate memory to update the intermediate memory. Since this second call is the last call, the result stored in the intermediate memory after the second call is the mantissa after the multiplication operation. For the above case when only the bit width of the multiplicand is greater than the bit width of the maximum multiplicand, the shift-and-add circuit can also operate in the same manner.

[0110] For example, as described above, in the FP32×FP32 operation mode, when the bit width of the multiplier is greater than the maximum multiplier bit width and the bit width of the multiplicand is greater than the maximum multiplicand bit width, the mantissa processing unit is called eight times, and, for example, the truncation of the mantissa to be truncated is performed in order from high to low bits. Specifically, for example, the multiplier parts in the eight calls are inb_m1, inb_m2, inb_m3, and inb_m4, and the multiplicand parts are ina_m1 and ina_m2. For example, when the mantissa processing unit is called eight times, the following calculations are performed in sequence: ina_m1×inb_m1, ina_m1×inb_m2, ina_m1×inb_m3, ina_m1×inb_m4, ina_m2×inb_m1, ina_m2×inb_m2, ina_m2×inb_m3, ina_m2×inb_m4. In the first call, the shifter shifts the result of ina_m1×inb_m1 to the left. Since 7-bit data is intercepted in the mantissa to be truncated corresponding to the multiplier in the first call, the sum of the number of bits of all data after the 7-bit data used in this call in the mantissa to be truncated is k=24-7=17 bits, and 15-bit data is intercepted in the mantissa to be truncated corresponding to the multiplicand. Therefore, the sum of the number of bits of all data after the 15-bit data used in this call in the mantissa to be truncated is j=24-15=9 bits. According to the above formula, Y=17+9=26, so the number of bits shifted to the left is 26 bits, thereby obtaining the result S1 after shifting 26 bits, and the adder stores S1 in the intermediate memory; after the second call, the shifter shifts the result of ina_m1×inb_m2 to the left. , since the next 7-bit data is intercepted in the mantissa to be truncated corresponding to the multiplier in the second call, the sum of the number of bits of all data after the 7-bit data used in the call in the mantissa to be truncated is k=24-7-7=10 bits, and the same 7-bit data as in the previous call is intercepted in the mantissa to be truncated corresponding to the multiplicand (the same 7-bit data as in the previous call is used), so the sum of the number of bits of all data after the 7-bit data used in the call in the mantissa to be truncated is still j=24-15=9 bits. According to the above formula, Y=10+9=19, so the number of bits shifted to the left is 19 bits, thereby obtaining the result S2 after shifting by 19 bits, and the adder adds S2 to S1 stored in the intermediate memory, and stores the result of the addition in the intermediate memory to update the intermediate memory;The mantissa processing unit is called repeatedly in this way until the fourth call. In the fourth call, the shifter shifts the result of ina_m1×inb_m4 to the left. Since the last 3 bits of the mantissa to be truncated corresponding to the multiplier are intercepted in the fourth call, there is no data after the 3 bits used in the call in the mantissa to be truncated, so k=0, and the same 7 bits of data as in the previous call are intercepted in the mantissa to be truncated corresponding to the multiplicand. Therefore, the sum of the bits of all the data after the 7 bits used in the call in the mantissa to be truncated is still j=24-15=9 bits. According to the above formula It can be seen that Y=0+9=9, so the number of bits shifted to the left is 9, thereby obtaining the result S4 after shifting 9 bits, and the adder adds S4 to the result stored in the intermediate memory, and stores the added result in the intermediate memory to update the intermediate memory; since in the fifth to eighth calls, the last 9-bit data of the mantissa to be intercepted corresponding to the multiplicand is intercepted, and there is no data after the 9-bit data, so in the fifth to eighth calls, j=0, in the fifth call, the shifter shifts the result of ina_m2×inb_m1 to the left, since in the fifth call, the last 9-bit data of the mantissa to be intercepted corresponding to the multiplicand is intercepted, and there is no data after the 9-bit data, so in the fifth to eighth calls, j=0, in the fifth call, the shifter shifts the result of ina_m2×inb_m1 to the left, The same 7-bit data as in the first call is intercepted from the mantissa to be intercepted corresponding to the number, so k=24-7=17bit. According to the above formula, Y=17+0=17, so the number of bits shifted left is 17 bits, thereby obtaining the result S5 after shifting 17 bits. The adder adds the result S5 to the result stored in the intermediate memory, and stores the added result in the intermediate memory to update the intermediate memory; the mantissa processing unit is called repeatedly in this way until the eighth call. In the eighth call, the shifter shifts the result of ina_m2×inb_m4 to the left. Since in the eighth call The last 3 bits of the mantissa to be truncated corresponding to the multiplier are truncated. Therefore, there is no data in the mantissa to be truncated after the 3 bits used in this call, so k=0. According to the above formula, Y=0+0=0. Therefore, the number of bits shifted left is 0, that is, no shift is performed. The unshifted result S8 is obtained, and the adder adds S8 to the result stored in the intermediate memory and stores the added result in the intermediate memory to update the intermediate memory. Since this eighth call is the last call, the result stored in the intermediate memory after the eighth call is the mantissa after the multiplication operation.

[0111] On the other hand, in order to further reduce the area of ​​the multiplier, the exponent processing unit includes a second control circuit (not shown in the figure), which is used to determine multiple calls to the exponent processing unit to obtain the exponent after the multiplication operation based on the exponent bit width of one of the two floating-point numbers and one of the two bit widths supported by the exponent processing unit, or based on the exponent bit width of the two floating-point numbers and the two bit widths supported by the exponent processing unit.

[0112] According to a third embodiment of the present disclosure, the two floating-point numbers include a first floating-point number and a second floating-point number, the exponent processing unit supports a third bit width and a fourth bit width, the exponent of the first floating-point number serves as a third input corresponding to the third bit width, the exponent of the second floating-point number serves as a fourth input corresponding to the fourth bit width, the bit width of the third input is less than or equal to the third bit width, and the second control circuit is used to call the exponent processing unit multiple times to obtain the exponent after the multiplication operation when the bit width of the fourth input is greater than the fourth bit width. According to this embodiment, it is known that the bit width of one of the two inputs is fixedly less than or equal to a bit width supported by the corresponding exponent processing unit. Therefore, it is only necessary to judge the size relationship between the other input and the bit width supported by the corresponding exponent processing unit to determine whether to call the exponent processing unit multiple times.

[0113] According to a fourth embodiment of the present disclosure, the two floating-point numbers include a first floating-point number and a second floating-point number, the exponent processing unit supports a third bit width and a fourth bit width, the exponent of the first floating-point number is used as a third input corresponding to the third bit width, and the exponent of the second floating-point number is used as a fourth input corresponding to the fourth bit width, and the second control circuit is used to call the exponent processing unit multiple times to obtain the exponent after the multiplication operation when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is less than or equal to the fourth bit width, when the bit width of the fourth input is greater than the fourth bit width and the bit width of the third input is less than or equal to the third bit width, or when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is greater than the fourth bit width. According to this embodiment, the size relationship between the bit widths of the two inputs and the two bit widths supported by the exponent processing unit is uncertain, and it is necessary to judge the size relationship between the two inputs and the bit widths supported by their respective corresponding exponent processing units to determine whether to call the exponent processing unit multiple times.

[0114] According to the fourth embodiment, when the exponent bit width of the first floating-point number is smaller than the exponent bit width of the second floating-point number and the third bit width is larger than the fourth bit width, or when the exponent bit width of the first floating-point number is larger than the exponent bit width of the second floating-point number and the third bit width is smaller than the fourth bit width, the second control circuit selects the exponent of the first floating-point number as the fourth input corresponding to the fourth bit width and selects the exponent of the second floating-point number as the third input corresponding to the third bit width. It should be understood that when the exponents of the two floating-point numbers are input irregularly, the exponents of the two floating-point numbers input can be matched with the two bit widths supported by the exponent processing unit according to the strategy of large bit width to large bit width and small bit width to small bit width, so as to avoid multiple calls when the exponent operation of the two floating-point numbers can be completed in one process.

[0115] Furthermore, when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is less than or equal to the fourth bit width, when the bit width of the fourth input is greater than the fourth bit width and the bit width of the third input is less than or equal to the third bit width, or when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is greater than the fourth bit width, the second control circuit is configured to determine the number of times the exponential processing unit is called and the data to be input to the exponential processing unit in each call based on the bit width of the fourth input and the third bit width when the bit width of the third input is less than or equal to the bit width of the fourth input and the third bit width is less than or equal to the fourth bit width. It is worth noting that in the above three cases, the number of times the exponential processing unit is called and the data to be input to the exponential processing unit in each call are determined based on the larger of the bit widths of the third and fourth inputs and the smaller of the third and fourth bit widths. Of course, when the bit widths of the third and fourth inputs are the same or the third and fourth bit widths are the same, either of the two bit widths may be selected.

[0116] In this embodiment, the description of the first floating-point number and the second floating-point number is merely to distinguish the two floating-point numbers, and the terms "third" and "fourth" do not have a limiting effect. Similarly, the description of the third input and the fourth input is merely to distinguish the two inputs of the exponent processing unit, and the description of the third bit width and the fourth bit width is merely to distinguish the two maximum processing bit widths supported by the exponent processing unit corresponding to the two inputs of the exponent processing unit. Therefore, the terms "third" and "fourth" do not have a limiting effect.

[0117] It is noteworthy that the floating-point number input to the multiplier described in the above embodiment is a floating-point number that meets the operation requirement format and is applicable to the internal and external components of the multiplier, that is, a floating-point number that has been pre-processed such as normalization. It should be understood that the floating-point number input to the multiplier can be a normalized or non-normalized floating-point number. In combination with the above description of the first normalization processing unit, it is known that if at least one of the two floating-point numbers input is a non-normalized non-zero floating-point number, the at least one floating-point number can be first normalized by the first normalization processing unit to obtain a normalized exponent and mantissa, and then the normalized exponent is used as the input of the exponent processing unit to perform the above-mentioned floating-point multiplication operation. Of course, other pre-processing can also be performed on the floating-point number, and the exponent of the pre-processed floating-point number can be used as the input of the exponent processing unit to perform the above-mentioned floating-point multiplication operation, such as the normalization of the floating-point number performed for the applicable operation mode mentioned in the above description of the first normalization processing unit. The third and fourth embodiments of the present disclosure are also applicable to the operation of floating-point numbers according to the operation mode as described above.

[0118] The following describes an example of multiple calls to the exponent processing unit. To provide a clearer and more intuitive understanding of this example, the third input may be, for example, an addend, the fourth input may be, for example, an augend, the third bit width may be, for example, the maximum addend bit width supported by the exponent processing unit, and the fourth bit width may be, for example, the maximum augend bit width supported by the exponent processing unit.

[0119] According to the example of multiple calls to the exponential processing unit disclosed in the present invention, in combination with the floating-point multiplication operation according to the operation mode described above, taking the two floating-point numbers input to the multiplier of the present invention as non-normalized non-zero floating-point numbers as an example, the two floating-point numbers are first normalized, so that the mantissas of the two floating-point numbers are extended by 1 bit. After this preprocessing, the exponents of the two floating-point numbers are matched with the input of the exponential processing unit. Therefore, when the bit width of the addend is greater than the maximum addend bit width and the bit width of the addend is less than or equal to the maximum addend bit width, when the bit width of the addend is greater than the maximum addend bit width and the bit width of the addend is less than or equal to the maximum addend bit width, or when the bit width of the addend is greater than the maximum addend bit width and the bit width of the addend is greater than the maximum addend bit width, the control circuit can determine the number of calls to the exponential processing unit according to the following formula:

[0120] m = ceil(P / (Q-1)),

[0121] Here, m represents the number of times the exponent processing unit is called, P represents the bit width of the addend, Q represents the maximum addend bit width, and Q-1 represents the bit width of the portion truncated from the addend and addend during each call. During each call, a portion of the addend and addend with a bit width of Q-1 is truncated, allowing the addition operation to be performed on the portions of the addend and addend with the same bit width and digits. If the portion truncated during a call has less than Q-1 bits of data or is missing, it is padded with zeros to make up the Q-1 bits. After extending the truncated portion of the addend and addend by a carry bit, the addend and addend portions are formed as input to the exponent processing unit. Therefore, Q also represents the bit width of the addend and addend portions input to the exponent processing unit during each call.

[0122] Thus, each time the exponent processing unit is called, the second control circuit can intercept the Q-1-bit portion from the addend and the augend in the same order as the input to the exponent processing unit, obtain the exponential result for that call through the exponent processing unit, and obtain the final exponent after calling the exponent processing unit m times. It is worth noting that the above-mentioned same order can be from high-order to low-order or from low-order to high-order.

[0123] For example, the addend is 6 bits wide and the augend is 9 bits wide. The maximum addend and augend supported by the exponent processing unit are both 8 bits wide. Therefore, the exponent processing unit is called ceil(9 / (8-1)) = 2 times. First, the addend is padded with leading zeros to make the addend and augend the same width. Then, in each call, 7-bit portions of the addend and augend are truncated from the addend and augend in descending order. Each of these truncated portions is extended by one carry bit, forming two 8-bit data with carry, which are then added together. In the second (and final) call, only 2 bits of data are truncated from the addend and augend. Therefore, the 2-bit data is padded with leading zeros to make it 7 bits wide and extended by one carry bit, forming two 8-bit data with carry, which are then added together.

[0124] It is worth noting that the calling of the exponent processing unit in this example when the bit width of the addend is greater than the maximum addend bit width and the bit width of the addend is less than or equal to the maximum addend bit width and when the bit width of the addend is greater than the maximum addend bit width and the bit width of the addend is less than or equal to the maximum addend bit width is also applicable to the above-mentioned third embodiment of the present disclosure.

[0125] According to an embodiment, the exponent processing unit may further include a second shift-and-add circuit, and the second shift-and-add circuit is configured to obtain the exponent after the multiplication operation according to the exponent result obtained each time the exponent processing unit is called.

[0126] Furthermore, the second shift-and-add circuit includes a second shifter, a second intermediate memory, and a second adder. When the second control circuit calls the exponential processing unit multiple times, after the first call, the second shifter shifts the exponential result obtained in the first call and stores the shifted exponential result in the second intermediate memory. Starting from the second call of the exponential processing unit, the second shifter shifts the exponential result obtained in the current call, and the second adder adds the shifted exponential result to the value stored in the second intermediate memory and stores the added result in the second intermediate memory to update the second intermediate memory, and uses the value stored in the second intermediate memory in the last call as the exponent after the multiplication operation.

[0127] Each time the exponential processing unit is called, the second shifter shifts the exponential result obtained in the current call in the following manner: if the addends and augends are truncated in order from high to low bits when the exponential processing unit is called, the parts truncated from the addends and augends in the current call are shifted left by the number of bits of the part following the part truncated from the augend in the current call.

[0128] For example, combining the above example, for example, the addend has a bit width of 6 bits and the addend has a bit width of 9 bits. The maximum addend bit width and the maximum addend bit width supported by the exponent processing unit are both 8 bits. In each call, the 7-bit part of the addend and the addend is truncated in order from high to low bits. Specifically, after the exponential processing unit is called for the first time, the second shifter shifts the exponential result obtained in the first call to the left by 2 bits (because there are 2 bits of data after the part intercepted by the addend in this call) and stores the shifted exponential result in the second intermediate memory. Starting from the second call of the exponential processing unit, the second shifter shifts the exponential result obtained in the current call to the left. Since there is no more data after the intercepted part in this call, it is shifted to the left by 0 bits, that is, not shifted. The second adder adds the exponential result after shifting by 0 bits to the value stored in the second intermediate memory and stores the added result in the second intermediate memory to update the second intermediate memory. Since this second call is the last call, the value stored in the second intermediate memory after the second call is the exponent after the multiplication operation.

[0129] Based on the above-described scenario of the multiplier (mantissa processing unit and exponent processing unit) of the present disclosure being called multiple times, it can be seen that the control module may include multiple submodules, each of which can be used to perform various operations during the multiple calls, such as determining multiple calls to the mantissa processing unit, determining the number of calls, determining the data input to the mantissa processing unit in each call, determining whether the mantissa bit width matches the bit width supported by the mantissa processing unit, adjusting the mantissa input, etc. The second control module may also include multiple submodules, and similarly, these submodules can each perform various operations during the multiple calls.

[0130] Combined with the above Figure 4-Figure 6 The operation performed by the multiplier of the present disclosure on multiplying the mantissa of a first floating point number and a second floating point number when performing floating point operations is described in detail. Figure 4 In order to focus on the description of the operation of the mantissa processing unit of the multiplier disclosed herein, other units, such as the exponent processing unit and the sign processing unit, are not drawn and described. Figure 7 The multiplier disclosed herein is described as a whole. The description of the mantissa processing unit described above is also applicable to the multiplier disclosed herein. Figure 7 The situation depicted.

[0131] Figure 7 is a schematic block diagram illustrating an overall multiplier 700 according to an embodiment of the present disclosure. It should be understood that the positions, existence, and connection relationships of the various units depicted in the figure are merely exemplary and non-limiting. For example, some of the units may be integrated, while others may be separated or omitted or replaced depending on the application scenario.

[0132] The multiplier disclosed herein can be exemplarily divided into a first phase and a second phase according to the operational flow in each operation mode, as depicted by the dashed lines in the figure. In summary, in the first phase, the calculation result of the sign bit is output, the intermediate calculation result of the exponent bit is output, and the intermediate calculation result of the mantissa bit is output (for example, including the encoding process of the Booth algorithm for fixed-point multiplication of the input mantissa bit and the Wallace tree compression process described above). In the second phase, the exponent and mantissa are normalized and rounded to output the calculation result of the exponent and the calculation result of the mantissa.

[0133] like Figure 7As shown in , the multiplier disclosed herein may include a mode selection unit 702 and a first normalization processing unit 704, wherein the mode selection unit may select an operation mode according to an input mode signal (in_mode). In one embodiment, the input mode signal may correspond to the operation mode number in Table 2. For example, when the input mode signal indicates the operation mode number "1" in Table 2, the multiplier may be operated in the FP16×FP16 operation mode, and when the input mode signal indicates the operation mode number "3" in Table 2, the multiplier may be operated in the FP32×FP32 operation mode. For illustration purposes, Figure 7 Only four exemplary operation modes, FP16×FP16, BF16×BF16, FP32×FP32, and FP32×BP16, are shown. However, as mentioned above, the multiplier of the present disclosure also supports a variety of other different operation modes.

[0134] The first normalization processing unit can be configured to, when the first floating-point number or the second floating-point number is a non-normalized non-zero floating-point number, perform normalization processing on the first floating-point number or the second floating-point number according to the operation mode to obtain the corresponding exponent and mantissa, for example, perform normalization processing on the floating-point number in the data format indicated by the operation mode according to the IEEE754 standard.

[0135] Further, the multiplier includes a mantissa processing unit to perform a multiplication operation of the mantissa of the first floating-point number and the mantissa of the second floating-point number. To this end, in one or more embodiments, the mantissa processing unit may include a bit expansion circuit 706, a Booth encoder 708, a partial product generating circuit 710, a Wallace tree compressor 712 and an adder 714, wherein the bit expansion circuit can be used to perform bit expansion on the mantissa of at least one of the first floating-point number and the second floating-point number, for example, to fill the high bit with 0 to be suitable for the operation of the Booth encoder. The control circuit can perform the above multiple calls to the mantissa processing unit operation on the mantissa obtained after the bit expansion circuit performs sign bit expansion on the mantissa. Since the Booth encoder, the partial product generating circuit, the Wallace tree compressor and the adder have been combined Figure 4-Figure 6 The same description is applicable here and is therefore not repeated here.

[0136] In some embodiments, the multiplier of the present disclosure further includes a second normalization processing unit 716 and a rounding unit 718. The second normalization processing unit and the rounding unit have the same Figure 3 Specifically, for the second normalization processing unit, it can be based on Figure 7The data format indicated by the output mode signal "out_mode" shown in the figure is used to perform floating-point normalization processing on the addition result and the exponential data from the exponential processing unit to obtain a normalized exponent result and a normalized mantissa result. For example, according to the data format indicated by the output mode signal, the second normalization processing unit can adjust the bit widths of the exponent and mantissa to make them meet the requirements of the data format indicated above. For another example, when the highest bit of the mantissa is 0 and the mantissa is not 0, the second normalization processing unit can repeatedly shift the mantissa left by 1 bit and subtract 1 from the exponent until the highest bit value is 1. As for the rounding unit, in one embodiment, it can be used to perform a rounding operation on the normalized mantissa result according to the rounding mode to obtain a rounded mantissa, and use the rounded mantissa as the mantissa after the multiplication operation.

[0137] In one or more embodiments, the aforementioned output mode signal may be part of the operation mode, used to indicate the data format after the multiplication operation. For example, as described in the above Table 3, when the operation mode number is "12", the number "1" therein may be equivalent to the aforementioned "in_mode" signal, used to indicate the execution of the FP16×FP16 multiplication operation, and the number "2" therein may be equivalent to the "out_mode" signal, used to indicate that the data type of the output result is BF16. Therefore, it can be understood that in some application scenarios, the output mode signal can be merged with the aforementioned input mode signal to be provided to the mode selection unit. Based on this merged mode signal, the mode selection unit can clarify the data format of the input data and the output result in the initial stage of the multiplier operation without having to provide a separate output mode signal to the regularization, thereby further simplifying the operation.

[0138] In one or more embodiments, the aforementioned rounding operation may exemplarily include the following five rounding modes.

[0139] (1) Round to the nearest value: In this mode, when two values ​​are equally close, the even number takes precedence. The result will be rounded to the nearest representable value, but when there are two numbers that are equally close, the even number will be taken as the rounded result (in binary, it is a number ending with 0);

[0140] (2) Rounding: See the following example for an exemplary operation;

[0141] (3) Rounding towards +∞: Under this rule, the result will be rounded towards positive infinity;

[0142] (4) Round towards -∞: Under this rule, the result is rounded towards negative infinity; and

[0143] (5) Round towards 0: Under this rule, the result will be rounded towards 0.

[0144] For an example of mantissa rounding in "round up" mode, consider the following: For example, the 24-bit mantissas of two normalized floating-point numbers are multiplied to produce a 48-bit mantissa (47 to 0). After normalization (if the highest bit of the mantissa is 0, the mantissa is shifted left by 1; if the highest bit of the mantissa is 1, the mantissa remains unchanged and the temporary exponent calculated previously is incremented by 1), only bits 46 to 24 are output. If the 23rd bit of the mantissa is 0, bit (23-0) is discarded; if the 23rd bit of the mantissa is 1, bit (23-0) is added to bit 24 and discarded.

[0145] Return to Figure 7 The multiplier disclosed herein further includes an exponent processing unit 720 and a sign processing unit 722, wherein the exponent processing unit can be used to obtain the exponent after the multiplication operation according to the operation mode, the exponent of the first floating-point number, and the exponent of the second floating-point number. For example, the exponent processing circuit can add the exponent bit data of the first floating-point number, the exponent bit data of the second floating-point number, and the offset value of the corresponding input floating-point data type, and subtract the offset value of the output floating-point data type to obtain the exponent bit data of the product of the first floating-point number and the second floating-point number. In one or more embodiments, the exponent processing unit can be implemented as or include an addition and subtraction circuit, which is used to obtain the exponent after the multiplication operation according to the operation mode, the exponent of the first floating-point number, the exponent of the second floating-point number, and the operation mode.

[0146] In one embodiment, the sign processing unit may be implemented as an XOR circuit, which is used to perform an XOR operation on the sign bit data of the first floating point number and the second floating point number to obtain the sign bit data of the product of the first floating point number and the second floating point number.

[0147] Combined with the above Figure 7 The multiplier disclosed herein is described in detail as a whole. Through this description, those skilled in the art can understand that the multiplier disclosed herein supports operations in multiple operation modes, thereby overcoming the defects of multipliers in the prior art that only support a single floating-point operation. Furthermore, because the multiplier disclosed herein can be reused, it also supports high-bitwidth floating-point data, reducing operation costs and overhead. In one or more embodiments, the multiplier disclosed herein can also be arranged into or included in an integrated circuit chip or computing device to implement multiplication operations on floating-point numbers in multiple operation modes.

[0148] Figure 8 FIG. 8 is a flow chart illustrating a method 800 for performing floating point multiplication using a multiplier according to an embodiment of the present disclosure. It is understood that the multiplier described herein is the multiplier previously described in conjunction with FIG. Figure 1-Figure 7The multiplier is described in detail, so the previous description of the multiplier and its internal composition, function and operation also applies to the description here.

[0149] like Figure 8 As shown in , the method 800 may include, at step S802, utilizing the exponent processing unit of the multiplier to obtain the exponent after the multiplication operation according to the operation mode, the exponent of the first floating-point number, and the exponent of the second floating-point number. As previously mentioned, the operation mode can be one of a plurality of operation modes and can be used to indicate the data format of the floating-point number. In one or more embodiments, the operation mode can also be used to determine the data format of the floating-point number of the output result.

[0150] Next, at step S804, the method 800 can utilize the mantissa processing unit of the multiplier to obtain the mantissa after the multiplication operation according to the operation mode, the first floating-point number, and the second floating-point number. Regarding the exemplary operation of the mantissa, the present disclosure uses a Booth encoding algorithm and a Wallace tree compressor in some preferred embodiments to improve the efficiency of mantissa processing. In addition, when the first floating-point number and the second floating-point number are signed numbers, the method 800 can also be used in step S806 to obtain the sign after the multiplication operation according to the sign of the first floating-point number and the sign of the second floating-point number.

[0151] Although the above method shows the use of the disclosed multiplier to perform floating-point multiplication in the form of steps, the order of these steps does not mean that the steps of the method must be performed in the order described, but can be processed in other orders or in parallel. In addition, for the sake of simplicity, other steps of method 800 are not described here, but those skilled in the art will understand based on the content of this disclosure that the method can also be performed by using a multiplier to perform the aforementioned combined operation. Figure 1-Figure 7 Describes the various operations.

[0152] In the above embodiments of the present disclosure, the description of each embodiment has its own emphasis. For parts not described in detail in a particular embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined in any way. To keep the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0153] Figure 9is a block diagram illustrating a combined processing device 900 according to an embodiment of the present disclosure. As shown, the combined processing device 900 includes a computing device 902, which may include the multiplier disclosed herein as previously described in conjunction with the accompanying figures. Furthermore, the combined processing device includes a universal interconnect interface 904 and other processing devices 906. The computing device according to the present disclosure interacts with the other processing devices to jointly complete user-specified operations.

[0154] According to the solution disclosed herein, the other processing devices may include one or more types of general-purpose and / or specialized processors such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), and a neural network processor. The number of such processors is not limited but determined based on actual needs. In one or more embodiments, the other processing devices may serve as an interface between the computing device disclosed herein (which may be embodied as a machine learning computing device) and external data and control, performing functions including but not limited to data transfer and completing basic control of the machine learning computing device, such as starting and stopping the device. The other processing devices may also collaborate with the machine learning computing device to jointly complete computing tasks.

[0155] According to the solution disclosed herein, the universal interconnect interface can be used to transmit data and control instructions between a computing device and other processing devices. For example, the computing device can obtain required input data from other processing devices via the universal interconnect interface and write it to the storage device on the computing device chip. Furthermore, the computing device can obtain control instructions from other processing devices via the universal interconnect interface and write them to the control cache on the computing device chip. Alternatively or optionally, the universal interconnect interface can also read data from the storage module of the computing device and transmit it to other processing devices.

[0156] Optionally, the combined processing device may further include a storage device 908, which may be connected to the computing device and the other processing device, respectively. In one or more embodiments, the storage device may be used to store data of the computing device and the other processing device, and is particularly suitable for data that cannot be fully stored in the internal storage of the computing device or other processing device.

[0157] Depending on the application scenario, the combined processing device disclosed herein can be used as a system-on-chip (SoC) in devices such as mobile phones, robots, drones, video capture, and video surveillance equipment, effectively reducing the core area of ​​the control unit, increasing processing speed, and lowering overall power consumption. In this case, the universal interconnect interface of the combined processing device is connected to certain components of the device. These certain components may be, for example, a camera, display, mouse, keyboard, network card, or Wi-Fi interface.

[0158] In some embodiments, the present disclosure further discloses a chip or integrated circuit chip, which includes the above-mentioned computing device, the combination processing device, and the multiplier of the present disclosure. In other embodiments, the present disclosure further discloses a chip packaging structure, which includes the above-mentioned chip.

[0159] In some embodiments, the present disclosure further discloses a board card, which includes the above chip packaging structure. Figure 10 , which provides the aforementioned exemplary board card. In addition to the aforementioned chip 1002 , the aforementioned board card may also include other supporting components, which may include but are not limited to: a storage device 1004 , an interface device 1006 and a control device 1008 .

[0160] The memory device is connected to the chip within the chip package structure via a bus for storing data. The memory device may include multiple groups of memory cells 1010. Each group of memory cells is connected to the chip via a bus. It is understood that each group of memory cells may be DDR SDRAM ("Double Data Rate SDRAM").

[0161] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the memory device may include four groups of memory cells. Each group of memory cells may include multiple DDR4 particles (chips). In one embodiment, the chip may include four 72-bit DDR4 controllers, of which 64 bits are used for data transmission and 8 bits are used for ECC verification.

[0162] In one embodiment, each group of the memory cells may include a plurality of double data rate synchronous dynamic random access memories (DDRs) connected in parallel. DDRs can transmit data twice within one clock cycle. A controller for controlling the DDRs is provided in the chip to control data transmission and data storage in each of the memory cells.

[0163] The interface device is electrically connected to the chip in the chip packaging structure. The interface device is used to realize data transmission between the chip and an external device 1012 (such as a server or a computer). For example, in one embodiment, the interface device can be a standard PCIE interface. For example, the data to be processed is transferred to the chip by the server through the standard PCIE interface to realize data transfer. In another embodiment, the interface device can also be other interfaces. This disclosure does not limit the specific form of expression of the above-mentioned other interfaces. The interface unit can realize the switching function. In addition, the calculation results of the chip are still transmitted back to the external device (such as a server) by the interface device.

[0164] The control device is electrically connected to the chip so as to monitor the state of the chip. Specifically, the chip and the control device can be electrically connected via an SPI interface. The control device may include a single-chip microcomputer ("MCU", Micro Controller Unit). The chip may include multiple processing chips, multiple processing cores or multiple processing circuits, and may drive multiple loads. Thus, the chip can be in different working states such as multi-load and light load. The control device can realize the regulation of the working states of multiple processing chips, multiple processing and / or multiple processing circuits in the chip.

[0165] In some embodiments, the present disclosure further discloses an electronic device or apparatus, which includes the above-mentioned board. Depending on different application scenarios, the electronic device or apparatus may include a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, a headset, a mobile storage, a wearable device, a vehicle, a household appliance, and / or a medical device. The vehicle includes an airplane, a ship, and / or a vehicle; the household appliance includes a television, an air conditioner, a microwave oven, a refrigerator, an electric rice cooker, a humidifier, a washing machine, an electric light, a gas stove, and a range hood; the medical device includes an MRI machine, an ultrasound machine, and / or an electrocardiograph.

[0166] It should be noted that for the aforementioned method embodiments, for simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this disclosure is not limited by the order of the actions described, because according to this disclosure, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all optional embodiments, and the actions and modules involved are not necessarily required for this disclosure.

[0167] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0168] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, optical, acoustic, magnetic or other forms.

[0169] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0170] In addition, the functional units in the various embodiments of the present disclosure may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software program modules.

[0171] If the integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, when the technical solution of the present disclosure can be embodied in the form of a software product, the computer software product is stored in a memory, including a number of instructions for enabling a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned memory includes: U disk, read-only memory ("ROM", Read-Only Memory), random access memory ("RAM", Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program code.

[0172] The foregoing content can be better understood in accordance with the following terms:

[0173] Clause A1. A multiplier for performing floating-point multiplication, wherein the multiplier comprises:

[0174] a mantissa processing unit, configured to obtain the mantissa after the multiplication operation according to the mantissa of the floating-point number,

[0175] The mantissa processing unit includes a control circuit, and the control circuit is used to call the mantissa processing unit multiple times when the mantissa bit width of at least one of the two floating-point numbers is greater than the data bit width that can be processed by the mantissa processing unit at one time.

[0176] Item A2, a multiplier according to Item A1, wherein the two floating-point numbers include a first floating-point number and a second floating-point number, the mantissa processing unit supports a first bit width and a second bit width, the mantissa of the first floating-point number serves as a first input corresponding to the first bit width, the mantissa of the second floating-point number serves as a second input corresponding to the second bit width, the bit width of the first input is less than or equal to the first bit width, and the control circuit is used to call the mantissa processing unit multiple times to obtain the mantissa after the multiplication operation when the bit width of the second input is greater than the second bit width.

[0177] Item A3, a multiplier according to Item A1 or Item A2, wherein the two floating-point numbers include a first floating-point number and a second floating-point number, the mantissa processing unit supports a first bit width and a second bit width, the mantissa of the first floating-point number serves as a first input corresponding to the first bit width, and the mantissa of the second floating-point number serves as a second input corresponding to the second bit width, and the control circuit is used to call the mantissa processing unit multiple times to obtain the mantissa after the multiplication operation when the bit width of the first input is greater than the first bit width and the bit width of the second input is less than or equal to the second bit width, when the bit width of the second input is greater than the second bit width and the bit width of the first input is less than or equal to the first bit width, or when the bit width of the first input is greater than the first bit width and the bit width of the second input is greater than the second bit width.

[0178] Item A4, a multiplier according to any one of Items A1-A3, wherein, when the mantissa bit width of the first floating-point number is smaller than the mantissa bit width of the second floating-point number and the first bit width is larger than the second bit width, or when the mantissa bit width of the first floating-point number is larger than the mantissa bit width of the second floating-point number and the first bit width is smaller than the second bit width, the control circuit selects the mantissa of the first floating-point number as the second input corresponding to the second bit width and selects the mantissa of the second floating-point number as the first input corresponding to the first bit width.

[0179] Item A5, a multiplier according to any one of items A1-A4, wherein, when the bit width of the first input is greater than the first bit width and the bit width of the second input is less than or equal to the second bit width, the control circuit determines the number of times the mantissa processing unit is called and the data input into the mantissa processing unit in each call based on the bit width of the first input and the first bit width.

[0180] Item A6, a multiplier according to any one of items A1-A5, wherein, when the bit width of the second input is greater than the second bit width and the bit width of the first input is less than or equal to the first bit width, the control circuit determines the number of times the mantissa processing unit is called and the data input into the mantissa processing unit in each call based on the bit width of the second input and the second bit width.

[0181] Item A7, a multiplier according to any one of items A1-A6, wherein, when the bit width of the first input is greater than the first bit width and the bit width of the second input is greater than the second bit width, the control circuit determines the number of times the mantissa processing unit is called and the data input into the mantissa processing unit in each call based on the bit width of the first input and the first bit width and the bit width of the second input and the second bit width.

[0182] Item A8, a multiplier according to any one of items A1-A7, wherein the mantissa processing unit further includes a shift-and-add circuit, and the shift-and-add circuit is used to obtain the mantissa after the multiplication operation according to the mantissa result obtained each time the mantissa processing unit is called.

[0183] Item A9, a multiplier according to any one of items A1-A8, wherein the shift-addition circuit includes a shifter, an intermediate memory and an adder; when the control circuit calls the mantissa processing unit multiple times, after the first call, the shifter shifts the mantissa result obtained in the first call to obtain a shifted mantissa result and stores the shifted mantissa result in the intermediate memory; starting from the second call, the shifter shifts the mantissa result obtained in the current call to obtain the current mantissa result; the adder adds the current mantissa result to the result stored in the intermediate memory and stores the added result in the intermediate memory to update the intermediate memory; and after the last call, the result stored in the intermediate memory is used as the mantissa after the multiplication operation.

[0184] Item A10, a multiplier according to any one of Items A1-A9, wherein the multiplier further includes an exponent processing unit, the exponent processing unit being used to obtain the exponent after the multiplication operation based on the exponents of the two floating-point numbers, and the exponent processing unit including a second control circuit, the second control circuit being used to determine multiple calls to the exponent processing unit to obtain the exponent after the multiplication operation based on the exponent bit width of one of the two floating-point numbers and one of the two bit widths supported by the exponent processing unit or based on the exponent bit width of the two floating-point numbers and the two bit widths supported by the exponent processing unit.

[0185] Item A11, a multiplier according to any one of Items A1-A10, wherein the two floating-point numbers include a first floating-point number and a second floating-point number, the exponent processing unit supports a third bit width and a fourth bit width, the exponent of the first floating-point number serves as a third input corresponding to the third bit width, the exponent of the second floating-point number serves as a fourth input corresponding to the fourth bit width, the bit width of the third input is less than or equal to the third bit width, and the second control circuit is used to call the exponent processing unit multiple times to obtain the exponent after the multiplication operation when the bit width of the fourth input is greater than the fourth bit width.

[0186] Item A12. A multiplier according to any one of Items A1-A11, wherein the two floating-point numbers include a first floating-point number and a second floating-point number, the exponent processing unit supports a third bit width and a fourth bit width, the exponent of the first floating-point number serves as a third input corresponding to the third bit width, and the exponent of the second floating-point number serves as a fourth input corresponding to the fourth bit width, and the second control circuit is used to call the exponent processing unit multiple times to obtain the exponent after the multiplication operation when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is less than or equal to the fourth bit width, when the bit width of the fourth input is greater than the fourth bit width and the bit width of the third input is less than or equal to the third bit width, or when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is greater than the fourth bit width.

[0187] Item A13, a multiplier according to any one of Items A1-A12, wherein, when the exponent bit width of the first floating-point number is smaller than the exponent bit width of the second floating-point number and the third bit width is larger than the fourth bit width, or when the exponent bit width of the first floating-point number is larger than the exponent bit width of the second floating-point number and the third bit width is smaller than the fourth bit width, the second control circuit selects the exponent of the first floating-point number as the fourth input corresponding to the fourth bit width and selects the exponent of the second floating-point number as the third input corresponding to the third bit width.

[0188] Item A14, a multiplier according to any one of items A1-A13, wherein the second control circuit is used to determine the number of times the exponential processing unit is called and the data input into the exponential processing unit in each call based on the bit width of the fourth input and the third bit width when the bit width of the third input is less than or equal to the bit width of the fourth input and the third bit width is less than or equal to the fourth bit width.

[0189] Item A15, a multiplier according to any one of items A1-A14, wherein the exponent processing unit further includes a second shift-and-add circuit, and the second shift-and-add circuit is used to obtain the exponent after the multiplication operation according to the exponent result obtained each time the exponent processing unit is called.

[0190] Item A16, a multiplier according to any one of items A1-A15, wherein the mantissa processing unit includes a partial product operation unit and a partial product summation unit, wherein the partial product operation unit is used to obtain an intermediate result based on the mantissas of the two floating-point numbers, and the partial product summation unit is used to perform a sum operation on the intermediate results to obtain a sum result, and use the sum result as the mantissa after the multiplication operation.

[0191] Item A17, a multiplier according to any one of Items A1-A16, wherein the partial product operation unit includes a Booth encoding circuit, and the Booth encoding circuit is used to perform Booth encoding on the mantissa of the first floating-point number or the second floating-point number to obtain the intermediate result.

[0192] Item A18, a multiplier according to any one of items A1-A17, wherein the partial product summation unit includes an adder, and the adder is used to add the intermediate results to obtain the sum result.

[0193] Item A19, a multiplier according to any one of items A1-A18, wherein the partial product summation unit includes a Wallace tree and an adder, wherein the Wallace tree is used to sum the intermediate results to obtain a second intermediate result, and the adder is used to sum the second intermediate results to obtain the sum result.

[0194] Clause A20, a multiplier according to any one of clauses A1-A19, wherein the adder comprises at least one of a full adder, a serial adder, and a carry look-ahead adder.

[0195] Item A21, a multiplier according to any one of items A1-A20, wherein, when the number of the intermediate results is less than M, zero values ​​are added as intermediate results so that the number of the intermediate results is equal to M, where M is a preset positive integer.

[0196] Item A22, a multiplier according to any one of Items A1-A21, wherein each of the Wallace trees has M inputs and N outputs, and the number of the Wallace trees is not less than K, where N is a preset positive integer less than M, and K is a positive integer not less than the maximum bit width of the intermediate result.

[0197] Item A23, a multiplier according to any one of Items A1-A22, wherein the partial product summation unit is used to select one or more groups of the Wallace trees to sum the intermediate results, wherein each group of the Wallace trees has X Wallace trees, X is the number of bits of the intermediate result, wherein there is a carry relationship between the Wallace trees within each group, and there is no carry relationship between the Wallace trees between each group.

[0198] Clause A24. A multiplier according to any one of clauses A1-A23, wherein the multiplier further comprises:

[0199] The first normalization processing unit is configured to perform normalization processing on at least one of the two floating-point numbers to obtain a corresponding exponent and mantissa when at least one of the two floating-point numbers is a non-normalized non-zero floating-point number.

[0200] Item A25, a multiplier according to any one of items A1-A24, wherein the multiplier is used to perform the multiplication operation of the two floating-point numbers according to an operation mode, the operation mode indicates the data format of the two floating-point numbers, the mantissa processing unit is used to obtain the mantissa after the multiplication operation according to the operation mode and the mantissas of the two floating-point numbers, and the exponent processing unit is used to obtain the exponent after the multiplication operation according to the operation mode and the exponents of the two floating-point numbers.

[0201] Item A26, according to the multiplier described in any one of items A1-A25, the first normalization processing unit is also used to normalize at least one of the two floating-point numbers according to the operation mode to obtain a corresponding exponent and mantissa.

[0202] Item A27, a multiplier according to any one of Items A1-A26, wherein the data format includes at least one of half-precision floating point numbers, single-precision floating point numbers, brain floating point numbers, double-precision floating point numbers, and custom floating point numbers.

[0203] Item A28, a multiplier according to any one of items A1-A27, wherein the mantissa processing unit includes a bit number expansion circuit, and the bit number expansion circuit is used to expand the bit number of the mantissa of at least one of the first floating-point number and the second floating-point number.

[0204] Clause A29. A multiplier according to any one of clauses A1-A28, wherein the floating-point number further includes a sign, the multiplier further comprising:

[0205] The sign processing unit is used to obtain a sign after the multiplication operation according to the signs of the two floating-point numbers.

[0206] Item A30, a multiplier according to any one of items A1-A29, wherein the sign processing unit includes an XOR logic circuit, and the XOR logic circuit is used to perform an XOR operation based on the signs of the two floating-point numbers to obtain the sign after the multiplication operation.

[0207] Clause A31. The multiplier of any one of clauses A1-A30, further comprising a second normalization processing unit configured to:

[0208] The mantissa and exponent after the multiplication operation are subjected to floating point number regularization processing to obtain a regularized exponent result and a regularized mantissa result, and the regularized exponent result and the regularized mantissa result are used as the exponent after the multiplication operation and the mantissa after the multiplication operation.

[0209] Clause A32. The multiplier of any one of clauses A1-A31, further comprising:

[0210] A rounding unit is used to perform a rounding operation on the regularized mantissa result according to a rounding mode to obtain a rounded mantissa, and use the rounded mantissa as the mantissa after the multiplication operation.

[0211] Clause A33. A method of performing floating-point multiplication using a multiplier, wherein:

[0212] Utilizing the mantissa processing unit of the multiplier to obtain the mantissa after the multiplication operation according to the mantissa of the floating-point number,

[0213] The mantissa processing unit includes a control circuit, and the control circuit is used to call the mantissa processing unit multiple times when the mantissa bit width of at least one of the two floating-point numbers is greater than the data bit width that can be processed by the mantissa processing unit at one time.

[0214] Item A34, an integrated circuit chip comprising the multiplier according to any one of items A1-A31.

[0215] Item A35, a computing device comprising the multiplier according to any one of items A1-A31 or the integrated circuit chip according to item A34.

[0216] The above is a detailed introduction to the embodiments of the present disclosure. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method and core ideas of the present disclosure. At the same time, for those skilled in the art, based on the ideas of the present disclosure, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

[0217] It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, specification, and drawings of the present disclosure are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprising" used in the specification and claims of the present disclosure indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0218] It should also be understood that the terminology used in this disclosure is for the purpose of describing specific embodiments only and is not intended to limit the disclosure. As used in this disclosure and the claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should further be understood that the term "and / or" as used in this disclosure and the claims refers to any and all possible combinations of one or more of the associated listed items, including and including these combinations.

[0219] As used in this specification and claims, the term “if” can be interpreted as “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context. Similarly, the phrase “if it is determined” or “if [described condition or event] is detected” can be interpreted as meaning “upon determination” or “in response to determining” or “upon detection of [described condition or event]” or “in response to detecting [described condition or event],” depending on the context.

[0220] The above is a detailed introduction to the embodiments of the present disclosure. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method and core ideas of the present disclosure. At the same time, changes or modifications made by those skilled in the art based on the ideas of the present disclosure, on the specific implementation methods and application scope of the present disclosure, all fall within the scope of protection of the present disclosure. In summary, the contents of this specification should not be understood as limiting the present disclosure.

Claims

1. A multiplier for performing floating-point multiplication, wherein: The multiplier comprises: a mantissa processing unit, configured to obtain the mantissa after the multiplication operation according to the mantissa of the floating-point number, The mantissa processing unit includes a control circuit, wherein the control circuit is configured to call the mantissa processing unit multiple times when the mantissa bit width of at least one of the two floating-point numbers is greater than the data bit width that can be processed by the mantissa processing unit at one time; The two floating-point numbers include a first floating-point number and a second floating-point number, the mantissa processing unit supports a first bit width and a second bit width, the mantissa of the first floating-point number serves as a first input corresponding to the first bit width, and the mantissa of the second floating-point number serves as a second input corresponding to the second bit width, the bit width of the first input is less than or equal to the first bit width, and the control circuit is configured to call the mantissa processing unit multiple times to obtain the mantissa after the multiplication operation when the bit width of the second input is greater than the second bit width; or The two floating-point numbers include a first floating-point number and a second floating-point number, the mantissa processing unit supports a first bit width and a second bit width, the mantissa of the first floating-point number serves as a first input corresponding to the first bit width, and the mantissa of the second floating-point number serves as a second input corresponding to the second bit width, and the control circuit is used to call the mantissa processing unit multiple times to obtain the mantissa after the multiplication operation when the bit width of the first input is greater than the first bit width and the bit width of the second input is less than or equal to the second bit width, when the bit width of the second input is greater than the second bit width and the bit width of the first input is less than or equal to the first bit width, or when the bit width of the first input is greater than the first bit width and the bit width of the second input is greater than the second bit width.

2. The multiplier according to claim 1, wherein When the mantissa bit width of the first floating-point number is smaller than the mantissa bit width of the second floating-point number and the first bit width is larger than the second bit width, or when the mantissa bit width of the first floating-point number is larger than the mantissa bit width of the second floating-point number and the first bit width is smaller than the second bit width, the control circuit selects the mantissa of the first floating-point number as the second input corresponding to the second bit width and selects the mantissa of the second floating-point number as the first input corresponding to the first bit width.

3. The multiplier according to claim 2, wherein: When the bit width of the first input is greater than the first bit width and the bit width of the second input is less than or equal to the second bit width, the control circuit determines the number of times the mantissa processing unit is called and the data input into the mantissa processing unit in each call based on the bit width of the first input and the first bit width.

4. The multiplier according to claim 2, wherein: When the bit width of the second input is greater than the second bit width and the bit width of the first input is less than or equal to the first bit width, the control circuit determines the number of times the mantissa processing unit is called and the data input into the mantissa processing unit in each call based on the bit width of the second input and the second bit width.

5. The multiplier according to claim 2, wherein: When the bit width of the first input is greater than the first bit width and the bit width of the second input is greater than the second bit width, the control circuit determines the number of times the mantissa processing unit is called and the data input into the mantissa processing unit in each call based on the bit width of the first input and the first bit width and the bit width of the second input and the second bit width.

6. The multiplier according to any one of claims 1 to 5, wherein: The mantissa processing unit further includes a shift-addition circuit, which is used to obtain the mantissa after the multiplication operation according to the mantissa result obtained by calling the mantissa processing unit each time.

7. The multiplier according to claim 6, wherein: The shift-and-add circuit includes a shifter, an intermediate memory, and an adder. When the control circuit calls the mantissa processing unit multiple times, after the first call, the shifter shifts the mantissa result obtained in the first call to obtain a shifted mantissa result and stores the shifted mantissa result in the intermediate memory. Starting from the second call, the shifter shifts the mantissa result obtained in the current call to obtain the current mantissa result. The adder adds the current mantissa result to the result stored in the intermediate memory and stores the added result in the intermediate memory to update the intermediate memory. After the last call, the result stored in the intermediate memory is used as the mantissa after the multiplication operation.

8. The multiplier according to claim 1, wherein: The multiplier also includes an exponent processing unit, which is used to obtain the exponent after the multiplication operation based on the exponents of the two floating-point numbers. The exponent processing unit includes a second control circuit, which is used to determine multiple calls to the exponent processing unit to obtain the exponent after the multiplication operation based on the exponent bit width of one of the two floating-point numbers and one of the two bit widths supported by the exponent processing unit, or based on the exponent bit width of the two floating-point numbers and the two bit widths supported by the exponent processing unit.

9. The multiplier according to claim 8, wherein: The two floating-point numbers include a first floating-point number and a second floating-point number, the exponent processing unit supports a third bit width and a fourth bit width, the exponent of the first floating-point number serves as a third input corresponding to the third bit width, the exponent of the second floating-point number serves as a fourth input corresponding to the fourth bit width, the bit width of the third input is less than or equal to the third bit width, and the second control circuit is configured to call the exponent processing unit multiple times to obtain the exponent after the multiplication operation when the bit width of the fourth input is greater than the fourth bit width.

10. The multiplier according to claim 8, wherein The two floating-point numbers include a first floating-point number and a second floating-point number, the exponent processing unit supports a third bit width and a fourth bit width, the exponent of the first floating-point number serves as a third input corresponding to the third bit width, and the exponent of the second floating-point number serves as a fourth input corresponding to the fourth bit width, and the second control circuit is configured to call the exponent processing unit multiple times to obtain the exponent after the multiplication operation when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is less than or equal to the fourth bit width, when the bit width of the fourth input is greater than the fourth bit width and the bit width of the third input is less than or equal to the third bit width, or when the bit width of the third input is greater than the third bit width and the bit width of the fourth input is greater than the fourth bit width.

11. The multiplier according to claim 10, wherein: When the exponent bit width of the first floating-point number is smaller than the exponent bit width of the second floating-point number and the third bit width is larger than the fourth bit width, or when the exponent bit width of the first floating-point number is larger than the exponent bit width of the second floating-point number and the third bit width is smaller than the fourth bit width, the second control circuit selects the exponent of the first floating-point number as the fourth input corresponding to the fourth bit width and selects the exponent of the second floating-point number as the third input corresponding to the third bit width.

12. The multiplier according to claim 11, wherein The second control circuit is configured to determine, when the bit width of the third input is less than or equal to the bit width of the fourth input and the third bit width is less than or equal to the fourth bit width, the number of times the exponential processing unit is called and the data input to the exponential processing unit in each call according to the bit width of the fourth input and the third bit width.

13. The multiplier according to any one of claims 9 to 12, wherein: The exponential processing unit further includes a second shift-and-add circuit, and the second shift-and-add circuit is used to obtain the exponent after the multiplication operation according to the exponential result obtained each time the exponential processing unit is called.

14. The multiplier according to claim 1, wherein: The mantissa processing unit includes a partial product operation unit and a partial product summation unit, wherein the partial product operation unit is used to obtain an intermediate result according to the mantissas of the two floating-point numbers, and the partial product summation unit is used to perform an addition operation on the intermediate results to obtain a sum result, and use the sum result as the mantissa after the multiplication operation.

15. The multiplier according to claim 14, wherein: The partial product operation unit includes a Booth encoding circuit, which is used to perform Booth encoding processing on the mantissa of the first floating-point number or the second floating-point number to obtain the intermediate result.

16. The multiplier according to claim 15, wherein: The partial product summation unit includes an adder, which is used to add the intermediate results to obtain the sum result.

17. The multiplier according to claim 15, wherein: The partial product summation unit includes a Wallace tree and an adder, wherein the Wallace tree is used to sum the intermediate results to obtain a second intermediate result, and the adder is used to sum the second intermediate results to obtain the sum result.

18. The multiplier according to claim 16 or 17, wherein: The adder includes at least one of a full adder, a serial adder and a carry look-ahead adder.

19. The multiplier according to claim 17, wherein: When the number of the intermediate results is less than M, zero values ​​are added as intermediate results so that the number of the intermediate results is equal to M, where M is a preset positive integer.

20. The multiplier according to claim 19, wherein Each of the Wallace trees has M inputs and N outputs, and the number of the Wallace trees is not less than K, where N is a preset positive integer less than M, and K is a positive integer not less than the maximum bit width of the intermediate result.

21. The multiplier according to claim 20, wherein: The partial product summation unit is used to select one or more groups of the Wallace trees to sum the intermediate results, wherein each group of the Wallace trees has X Wallace trees, X is the number of bits of the intermediate result, wherein the Wallace trees within each group have a carry relationship, and the Wallace trees between each group do not have a carry relationship.

22. The multiplier according to claim 8, wherein The multiplier further comprises: The first normalization processing unit is configured to perform normalization processing on at least one of the two floating-point numbers to obtain a corresponding exponent and mantissa when at least one of the two floating-point numbers is a non-normalized non-zero floating-point number.

23. The multiplier according to claim 8, wherein: The multiplier is used to perform a multiplication operation on the two floating-point numbers according to an operation mode, the operation mode indicates a data format of the two floating-point numbers, the mantissa processing unit is used to obtain a mantissa after the multiplication operation according to the operation mode and the mantissas of the two floating-point numbers, and the exponent processing unit is used to obtain an exponent after the multiplication operation according to the operation mode and the exponents of the two floating-point numbers. 24 . The multiplier according to claim 22 , wherein the first normalization processing unit is further configured to perform normalization processing on at least one of the two floating-point numbers according to an operation mode to obtain a corresponding exponent and mantissa.

25. The multiplier according to claim 23, wherein: The data format includes at least one of half-precision floating point numbers, single-precision floating point numbers, brain floating point numbers, double-precision floating point numbers, and custom floating point numbers.

26. The multiplier according to claim 15, wherein: The mantissa processing unit includes a bit number expansion circuit, and the bit number expansion circuit is used to expand the bit number of the mantissa of at least one of the first floating-point number and the second floating-point number.

27. The multiplier according to claim 1, wherein: The floating point number also includes a sign, and the multiplier further includes: The sign processing unit is used to obtain a sign after the multiplication operation according to the signs of the two floating-point numbers.

28. The multiplier according to claim 27, wherein: The symbol processing unit includes an exclusive OR logic circuit, and the exclusive OR logic circuit is used to perform an exclusive OR operation according to the signs of the two floating-point numbers to obtain the sign after the multiplication operation.

29. The multiplier according to claim 23, further comprising a second normalization processing unit, configured to: The mantissa and exponent after the multiplication operation are subjected to floating point number regularization processing to obtain a regularized exponent result and a regularized mantissa result, and the regularized exponent result and the regularized mantissa result are used as the exponent after the multiplication operation and the mantissa after the multiplication operation.

30. The multiplier of claim 29, further comprising: A rounding unit is used to perform a rounding operation on the regularized mantissa result according to a rounding mode to obtain a rounded mantissa, and use the rounded mantissa as the mantissa after the multiplication operation.

31. A method for performing floating point multiplication using a multiplier, wherein: Utilizing the mantissa processing unit of the multiplier to obtain the mantissa after the multiplication operation according to the mantissa of the floating-point number, The mantissa processing unit includes a control circuit, wherein the control circuit is configured to call the mantissa processing unit multiple times when the mantissa bit width of at least one of the two floating-point numbers is greater than the data bit width that can be processed by the mantissa processing unit at one time; The two floating-point numbers include a first floating-point number and a second floating-point number, the mantissa processing unit supports a first bit width and a second bit width, the mantissa of the first floating-point number serves as a first input corresponding to the first bit width, and the mantissa of the second floating-point number serves as a second input corresponding to the second bit width, the bit width of the first input is less than or equal to the first bit width, and the control circuit is configured to call the mantissa processing unit multiple times to obtain the mantissa after the multiplication operation when the bit width of the second input is greater than the second bit width; or The two floating-point numbers include a first floating-point number and a second floating-point number, the mantissa processing unit supports a first bit width and a second bit width, the mantissa of the first floating-point number serves as a first input corresponding to the first bit width, and the mantissa of the second floating-point number serves as a second input corresponding to the second bit width, and the control circuit is used to call the mantissa processing unit multiple times to obtain the mantissa after the multiplication operation when the bit width of the first input is greater than the first bit width and the bit width of the second input is less than or equal to the second bit width, when the bit width of the second input is greater than the second bit width and the bit width of the first input is less than or equal to the first bit width, or when the bit width of the first input is greater than the first bit width and the bit width of the second input is greater than the second bit width.

32. An integrated circuit chip comprising the multiplier according to any one of claims 1 to 30.

33. A computing device comprising the multiplier according to any one of claims 1 to 30 or the integrated circuit chip according to claim 32.

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