Method for manufacturing circuit board and display device including circuit board

Abstract

An embodiment of the present invention relates to a method for manufacturing a circuit board and a display device, and the display device may include: a display panel including a signal pad; and a circuit board including a connection pad having a first connection pad portion and a second connection pad portion. The second connection pad portion may be thicker than the first connection pad portion and may not overlap with the first connection pad portion in a plan view. The connection pad may contact the signal pad. The first surface roughness between the first connection pad portion and the signal pad may be greater than the second surface roughness between the second connection pad portion and the signal pad.

Description

Technical Field

[0001] Exemplary embodiments of the present invention relate to a display device, and more particularly, to a method of manufacturing a circuit board and a display device including the circuit board. Background Art

[0002] Various display devices are being developed for use in multimedia devices such as televisions, mobile phones, tablet computers, navigation systems, and game consoles.

[0003] The display device includes a display panel for displaying an image. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the gate lines and the data lines. The display device also includes a circuit board, which provides the electrical signals required for displaying the image to the gate lines or the data lines.

[0004] The circuit board is electrically connected to the display panel using an anisotropic conductive film or an ultrasonic bonding process. Compared with the case of using an anisotropic conductive film, when the display panel and the circuit board are connected to each other through the ultrasonic bonding process, it is possible to improve the conductive performance between the display panel and the circuit board and simplify the manufacturing process. Summary of the invention

[0005] An exemplary embodiment of the present invention provides a method of manufacturing a circuit board and a display device including the circuit board, the method improving connection reliability between a connection pad of the circuit board and a signal pad of a display panel.

[0006] An exemplary embodiment of the present invention provides a display device, comprising: a display panel including a signal pad; and a circuit board including a connection pad, wherein the connection pad has a first connection pad portion and a second connection pad portion. The second connection pad may be thicker than the first connection pad portion and may not overlap with the first connection pad portion in a plan view. The connection pad may contact the signal pad. A first surface roughness between the first connection pad portion and the signal pad may be greater than a second surface roughness between the second connection pad portion and the signal pad.

[0007] In an exemplary embodiment, the connection pad may include a first conductive layer and a second conductive layer, the second conductive layer being disposed on the first conductive layer to expose a portion of the first conductive layer. The first connection pad portion may correspond to the portion of the first conductive layer exposed by the second conductive layer, and the second connection pad portion may correspond to a structure in which the first conductive layer and the second conductive layer may be stacked.

[0008] In an exemplary embodiment, the first conductive layer may be thicker than the second conductive layer.

[0009] In an exemplary embodiment, the circuit board may further include a sub-conductive layer provided on a side surface of the first connection pad portion and including the same material as that of the second conductive layer.

[0010] In an exemplary embodiment, in a thickness direction of the display panel, a height of the sub-conductive layer may be smaller than a thickness of the first conductive layer.

[0011] In an exemplary embodiment, the first connection pad portions and the second connection pad portions may be alternately and repeatedly arranged in a first direction in which the connection pads extend.

[0012] In an exemplary embodiment, the first conductive layer may extend in the first direction into an integral shape. The second conductive layer may include portions arranged to be spaced apart from each other by a predetermined distance in the first direction.

[0013] In an exemplary embodiment, the first conductive layer may include a material different from that of the second conductive layer.

[0014] In an exemplary embodiment, the circuit board may further include: a base substrate on which the connection pad is disposed; a driving chip disposed on the base substrate; and a connecting wire disposed on the base substrate to electrically connect the connection pad to the driving chip. The connecting wire may include a first wire layer corresponding to the first conductive layer and a second wire layer corresponding to the second conductive layer.

[0015] In an exemplary embodiment, the first wire layer and the first conductive layer may be integrally formed, and the second wire layer and the second conductive layer may be integrally formed.

[0016] In an exemplary embodiment, the first conductive layer may include copper, and the second conductive layer may include tin.

[0017] In an exemplary embodiment, in the plan view, an area of ​​the first connection pad portion may be greater than an area of ​​the signal pad.

[0018] An exemplary embodiment of the present invention provides a display device, comprising: a display panel, in which a display area and a non-display area adjacent to the display area are defined; and a circuit board electrically connected to the display panel overlapping the non-display area. The display panel may include a signal pad overlapping the non-display area. The circuit board may include a conductive pattern, the conductive pattern including: a pad portion facing the signal pad and in contact with the signal pad; and a line portion not overlapping the signal pad and connected to the pad portion. In the thickness direction of the display panel, a recessed space may be defined in the pad portion, the recessed space being recessed in a direction from a first surface of the pad portion facing the signal pad toward a second surface facing the first surface.

[0019] In an exemplary embodiment, the pad portion may include a first conductive layer and a second conductive layer, the second conductive layer being disposed on the first conductive layer to expose a portion of the first conductive layer. The recessed space may be defined in the portion of the first conductive layer exposed by the second conductive layer.

[0020] In an exemplary embodiment, a first surface roughness between the signal pad and the portion of the first conductive layer exposed by the second conductive layer that are in contact with each other may be greater than a second surface roughness between the signal pad and the second conductive layer that are in contact with each other.

[0021] In an exemplary embodiment, the line portion may include: a first line conductive layer having an overall shape in conjunction with the first conductive layer; and a second line conductive layer disposed on the first line conductive layer and having an overall shape in conjunction with the second conductive layer.

[0022] In an exemplary embodiment, the first conductive layer may be thicker than the second conductive layer, and the first conductive layer may include a material different from that of the second conductive layer.

[0023] An exemplary embodiment of the present invention provides a method for manufacturing a circuit board, the method comprising: preparing a base substrate in which a pad region and a line region are defined, the pad region and the line region being separated from each other in a plan view; forming a first conductive layer on the base substrate; removing a region of the first conductive layer that does not overlap with the pad region and the line region; forming a second conductive layer on the base substrate to cover the first conductive layer; and removing a region of the second conductive layer that overlaps with the pad region using light. As a result of using the light, a portion of the first conductive layer that overlaps with the pad region may be exposed by the second conductive layer.

[0024] In an exemplary embodiment, the method may further include: irradiating the light onto a first surface of the first conductive layer overlapping the pad region. As a result of using the light, a recessed space may be defined in the first conductive layer, the recessed space being recessed in a direction from the first surface of the first conductive layer toward a second surface facing the first surface.

[0025] In an exemplary embodiment, the first conductive layer and the second conductive layer may include materials different from each other, and the second conductive layer may expose a portion of the base substrate that does not overlap with the first conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The exemplary embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings, which illustrate non-limiting exemplary embodiments described herein.

[0027] Figure 1 is a perspective view showing an exemplary embodiment of a display device according to the present invention.

[0028] Figure 2 is an exploded perspective view showing an exemplary embodiment of a display device according to the present invention.

[0029] Figure 3 is a cross-sectional view showing an exemplary embodiment of a display device according to the present invention.

[0030] Figure 4A is a plan view showing an exemplary embodiment of a display panel according to the present invention.

[0031] Figure 4B is a cross-sectional view showing an exemplary embodiment of a portion of a display panel according to the present invention.

[0032] Figure 5 is a plan view showing an exemplary embodiment of a circuit board according to the present invention.

[0033] Figure 6 It is along Figure 5 A cross-sectional view of an exemplary embodiment of a display device according to the present invention taken along line II′.

[0034] Fig. 7A is a cross-sectional view showing an exemplary embodiment of a connection pad and a signal pad according to the present invention.

[0035] Figure 7B It is along Figure 5 A cross-sectional view of an exemplary embodiment of a circuit board according to the present invention taken along line II-II′.

[0036] Figure 8 It is shown that according to the present invention Figure 5 An enlarged view of an exemplary embodiment of portion “AA”.

[0037] Fig. 9 It is along Figure 8 A cross-sectional view of another exemplary embodiment of a circuit board according to the present invention is taken along line III-III'.

[0038] Fig.10 and Fig.11 is a cross-sectional view showing another exemplary embodiment of a display device according to the present invention.

[0039] FIG. 12A to FIG. 12D is a cross-sectional view showing an exemplary embodiment of a method of manufacturing a circuit board according to the present invention. DETAILED DESCRIPTION

[0040] Exemplary embodiments of the present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments are shown. However, exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein; rather, these embodiments are provided so that the present invention will be thorough and complete and will fully convey the concepts of the exemplary embodiments to those of ordinary skill in the art. In the accompanying drawings, the thickness of layers and regions is magnified for clarity. The same reference numerals in the drawings represent the same elements, and their descriptions will therefore be omitted.

[0041] It will be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can be an intermediate element. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element. The same number always represents the same element. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. Other words (for example, "between..." relative to "directly between...", "adjacent" relative to "directly adjacent", "on..." relative to "directly on...") used to describe the relationship between an element or layer should be interpreted in the same manner.

[0042] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be referred to as a second element, component, region, layer or part without departing from the teachings of the exemplary embodiments.

[0043] Spatially relative terms such as "under," "beneath," "lower," "above," and "upper" may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, the elements described as "under" or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "under" may include both "above" and "under" orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thus the spatially relative descriptors used herein are interpreted accordingly.

[0044] The terms used in this article are only for the purpose of describing specific embodiments and are not intended to limit exemplary embodiments. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this article, the terms "comprises, comprising" and / or "includes, including" indicate the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0045] Exemplary embodiments of the invention are described herein with reference to cross-sectional illustrations, which are schematic illustrations of idealized embodiments (and intermediate structures) of the exemplary embodiments. As such, deviations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be anticipated. Therefore, exemplary embodiments of the invention should not be construed as limited to the specific shapes of the regions shown herein, but are to include deviations in shapes due to, for example, manufacturing.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the exemplary embodiments of the present invention belong. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technical field, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0047] Figure 1 is a perspective view showing an exemplary embodiment of a display device according to the present invention. Figure 2 is an exploded perspective view showing an exemplary embodiment of a display device according to the present invention.

[0048] refer to Figure 1 The display device DD may include a display surface DD-IS for displaying the image IM. The display device DD having a flat display surface DD-IS may include a display surface DD-IS for displaying the image IM. Figure 1 , but the present invention is not limited to this example. The display device DD may include a curved or three-dimensional ("3D") display surface DD-IS. In the case where the display device DD includes a 3D display surface DD-IS, the display surface DD-IS may include multiple display areas oriented in different directions. In an exemplary embodiment, the display surface DD-IS may include a surface such as a polygonal column.

[0049] In an exemplary embodiment, the display device DD may be a flexible display device. However, the present invention is not limited to this example, and in another exemplary embodiment, the display device DD may be a rigid display device.

[0050] Although not shown, the display device DD may constitute a mobile phone together with an electronic module, a camera module, and a power module that are disposed (e.g., mounted) on a main board and provided in a bracket or a case. The display device DD may be used for large-sized electronic devices (e.g., televisions and monitors) or medium- or small-sized electronic devices (e.g., tablet computers, car navigation systems, game consoles, and smart watches).

[0051] The display surface DD-IS may be parallel to a plane defined by the first direction DR1 and the second direction DR2. The direction perpendicular to the display surface DD-IS (i.e., the thickness direction of the display device DD) will be referred to as the third direction DR3. In the present specification, the expressions "in a plan view" and "plane area" may be used to describe the shape and area of ​​an object observed in the third direction DR3. In the following, the front surface or top surface of each element, component or unit will be distinguished from the rear surface or bottom surface based on the third direction DR3. However, the directions represented by the first direction DR1, the second direction DR2, and the third direction DR3 may not be limited to this example, and in exemplary embodiments, the first direction DR1, the second direction DR2, and the third direction DR3 may be changed to indicate other directions or opposite directions.

[0052] like Figure 1 As shown in , the display surface DD-IS may include a display area DD-DA on which an image IM is displayed and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area DD-NDA may not be used to display an image. Figure 1 , application icons and a clock window are shown as examples of the image IM.

[0053] like Figure 1As shown in , the display area DD-DA may be a rectangle or a quadrilateral, and the non-display area DD-NDA may surround the display area DD-DA. However, the present invention is not limited to this example, and the shapes of the display area DD-DA and the non-display area DD-NDA may be variously changed in a mutually influential manner. In another exemplary embodiment, for example, the non-display area DD-NDA may be locally provided near only one side of the display area DD-DA, or may be omitted.

[0054] refer to Figure 2 The display device DD may include a window WM, a display module DM, a circuit board FB and a housing member BC.

[0055] The window WM may be disposed on the display module DM and may transmit an image provided from the display module DM through the transmission area TA. The window WM may include the transmission area TA and the non-transmission area NTA. The transmission area TA may have a shape corresponding to Figure 1 Therefore, the image IM displayed on the display area DD-DA of the display device DD can be provided to the user through the transmissive area TA of the window WM.

[0056] The non-transmission area NTA may have a shape corresponding to Figure 1 The shape of the non-display area DD-NDA shown in FIG. The non-transmission area NTA may have a relatively low optical transmittance compared to the transmission area TA. However, the present invention is not limited to this example, and in another exemplary embodiment, the non-transmission area NTA may be omitted.

[0057] In an exemplary embodiment, the window WM may include, for example, glass, sapphire, or plastic. Although the window WM is shown as having a single-layer structure, the window WM may include a plurality of layers. The window WM may include a base layer, and at least one printed layer disposed on the rear surface of the base layer and overlapping the non-transmissive area NTA. The printed layer may have a predetermined color. As an example, the printed layer may have black or other colors.

[0058] The display module DM may be disposed between the window WM and the case member BC. The display module DM may include a display panel DP and an input sensing unit ISU.

[0059] The display panel DP may generate an image and transmit the generated image to the window WM. In an exemplary embodiment, the display panel DP may be an organic light emitting display panel, a liquid crystal display panel, or a quantum dot light emitting display panel, but the present invention is not limited to these examples. The organic light emitting display panel may include an organic light emitting device. The liquid crystal display panel may include liquid crystal molecules. The quantum dot light emitting display panel may include quantum dots or quantum rods.

[0060] Hereinafter, an example in which the display panel DP is an organic light emitting display panel will be described. However, the present invention is not limited to this example, and in another exemplary embodiment, the present invention may be applied to implement various display panels.

[0061] The input sensing unit ISU may be disposed between the window WM and the display panel DP. The input sensing unit ISU may sense input provided from the outside. Such external input may be provided in various forms. In an exemplary embodiment, for example, the external input may include various types of external inputs, such as a part of the user's body, a stylus, light, heat, or pressure. In addition to such a touch type event caused by the user's hand, the external input may include a non-touch type event (e.g., a hovering event near the input sensing unit ISU).

[0062] The input sensing unit ISU may be directly disposed on the display panel DP. In the present specification, the statement "element A may be directly disposed on element B" means that no adhesive layer is disposed between element A and element B. In the exemplary embodiment shown, the input sensing unit ISU and the display panel DP may be manufactured by a continuous process. However, the present invention is not limited to this example, and in another exemplary embodiment, the input sensing unit ISU may be provided in the form of a separate panel and may be connected to the display panel DP using an adhesive layer. In another exemplary embodiment, the input sensing unit ISU may be omitted.

[0063] The circuit board FB may be connected to one end of the display panel DP to provide a driving signal to the display panel DP. In an exemplary embodiment, the circuit board FB may be a flexible circuit board, and the driving signal may be used to control the image display operation of the display panel DP. In addition, although not shown, a driving circuit board may be connected to one end of the circuit board FB to provide a driving signal to the circuit board FB. The circuit board FB may be provided between the display panel DP and the driving circuit board to provide the driving signal transmitted from the driving circuit board to the display panel DP.

[0064] Figure 2 A structure in which the circuit board FB is connected to the display panel DP is shown, but the present invention is not limited to this example or the illustrated exemplary embodiment. In an exemplary embodiment, the display device DD may further include a touch circuit board connected to the input sensing unit ISU, and the touch circuit board may provide a touch drive signal to the input sensing unit ISU. In addition, a method of coupling the circuit board FB to the display panel DP may be substantially the same as a method of coupling the touch circuit board to the input sensing unit ISU.

[0065] The shell member BC may be coupled to the window WM. The shell member BC may be disposed on the rear surface of the display device DD and may be coupled to the window WM to define an internal space. The shell member BC may be composed of or include a material having relatively high rigidity or strength. In an exemplary embodiment, the shell member BC may include a plurality of frames and / or plates, each of which may include, for example, at least one of glass, plastic, or metal materials. The shell member BC may stably protect the components of the display device DD disposed in the internal space from external impacts.

[0066] The housing member BC is described as comprising a highly rigid material, however, in an exemplary embodiment, the housing member BC may be composed of or comprise a flexible material. Although not shown, the display device DD in an exemplary embodiment of the present invention may have foldable or bendable properties. In this case, the components in the display device DD may also have flexible properties.

[0067] Figure 3 is a cross-sectional view showing an exemplary embodiment of a display device according to the present invention. Figure 4A is a plan view showing an exemplary embodiment of a display panel according to the present invention. Figure 4B is a cross-sectional view showing an exemplary embodiment of a portion of a display panel according to the present invention.

[0068] refer to Figure 3 ,like Figure 1 The display area DD-DA and the non-display area DD-NDA of the display device DD shown in FIG. 2 may correspond to the display area DP-DA and the non-display area DP-NDA defined in the display panel DP, respectively.

[0069] The display panel DP may include a substrate SUB, and a circuit device layer DP-CL, a display device layer DP-OLED, and an insulating layer TFL disposed on the substrate SUB.

[0070] The substrate SUB may include at least one plastic film.The substrate SUB may be a flexible substrate, and may include a plastic substrate, a glass substrate, a metal substrate, or a substrate including an organic / inorganic composite material.

[0071] The circuit device layer DP-CL may include at least one intermediate insulating layer and a circuit device. In an exemplary embodiment, the intermediate insulating layer may include at least one intermediate inorganic layer and at least one intermediate organic layer. The circuit device may include a signal line and a pixel driving circuit, etc.

[0072] The display device layer DP-OLED may include a plurality of organic light emitting diodes. The display device layer DP-OLED may further include an organic layer, such as a pixel defining layer. In an alternative exemplary embodiment, the display panel DP may be a liquid crystal display panel, and in this case, the display device layer DP-OLED may include a liquid crystal layer.

[0073] The insulating layer TFL may hermetically seal or encapsulate the display device layer DP-OLED. As an example, the insulating layer TFL may be a thin encapsulation layer. The insulating layer TFL may protect the display device layer DP-OLED from contaminating materials such as moisture, oxygen, and dust particles. Figure 3 An example in which the insulating layer TFL overlaps the display area DP-DA is shown, but the present invention is not limited to this example. In an exemplary embodiment, for example, the insulating layer TFL may overlap the non-display area DP-NDA.

[0074] refer to Figure 4A , the display device DD may include a display panel DP, a circuit board FB electrically connected to the display panel DP, and a driving circuit board PB electrically connected to the circuit board FB.

[0075] The display panel DP may include a gate driving circuit GDC, a plurality of signal lines SGL, a plurality of signal pads PD overlapping the pad area PDA, and a plurality of pixels PX.

[0076] The pixels PX may be arranged in the display area DP-DA. Each pixel PX may include an organic light emitting diode and a pixel driving circuit connected thereto. The gate driving circuit GDC, the signal line SGL, the signal pad PD and the pixel driving circuit may be included in Figure 3 In the circuit device layer DP-CL.

[0077] The gate drive circuit GDC may generate a gate signal and then may output the generated gate signal to a plurality of gate lines GL, which will be described below. The gate drive circuit GDC may include a plurality of thin film transistors provided by the same process as that of the pixel drive circuit for the pixel PX (e.g., a low temperature polysilicon (“LTPS”) process or a low temperature polysilicon oxide (“LTPO”) process).

[0078] The signal line SGL may be disposed on the substrate SUB and may overlap the display area DP-DA and the non-display area DP-NDA. The signal line SGL may include a gate line GL, a data line DL, a power line PL, and a control signal line CSL. Each gate line GL may be connected to a plurality of corresponding pixels PX in the pixels PX, and each data line DL may be connected to a plurality of corresponding pixels PX in the pixels PX. The power line PL may be connected to the pixel PX. The control signal line CSL may provide a control signal to the gate drive circuit GDC.

[0079] The signal line SGL is described as being different from the signal pad PD, but the present invention is not limited to this example. The signal line SGL and the signal pad PD may be disposed on the substrate SUB by the same process, and in an exemplary embodiment, the signal line SGL and the signal pad PD may be connected to form an integral shape.

[0080] The circuit board FB may include a first base substrate BP1, a first connection pad SP-1, a second connection pad SP-2, and a driving chip DC. The circuit board FB may be connected to an end portion of the display panel DP overlapping the non-display area DP-NDA and an end portion of the driving circuit board PB. As described above, the circuit board FB may have flexibility. In an exemplary embodiment, as Figure 2 As shown in FIG. 1 , the circuit board FB may be bent along the side surface of the display panel DP, and in this case, for example, a portion of the circuit board FB may be disposed on the rear surface of the display panel DP.

[0081] exist Figure 4A , the circuit board FB is shown as being separated from the display panel DP and the driving circuit board PB, but the circuit board FB may be connected to a portion of the non-display area DP-NDA of the display panel DP and a portion of the driving circuit board PB.

[0082] The first base substrate BP1 may include a first pad area FA1 in which the first connection pads SP-1 are disposed and a second pad area FA2 in which the second connection pads SP-2 are disposed. The first connection pads SP-1 may be input pads that receive drive signals from the drive circuit board PB, and the second connection pads SP-2 may be output pads that output electrical signals to the display panel DP. The first connection pads SP-1 may be arranged to be spaced a predetermined distance apart from each other in the first direction DR1, and the second connection pads SP-2 may also be arranged to be spaced a predetermined distance apart from each other in the first direction DR1.

[0083] In an exemplary embodiment, the second connection pads SP-2 of the circuit board FB may be respectively arranged to contact the signal pads PD of the display panel DP and face the signal pads PD of the display panel DP. According to some exemplary embodiments of the present invention, the second connection pads SP-2 and the signal pads PD may be electrically connected to each other by an ultrasonic bonding method. In an exemplary embodiment, the ultrasonic bonding method may be a method of directly bonding two different metal materials using at least one of heat, pressure, and ultrasonic vibration, for example. This will be described in more detail below.

[0084] The driving circuit board PB may include a second base substrate BP2 and driving pads MPD disposed on the second base substrate BP2. The driving pads MPD may be disposed in a driving pad area PA defined in the second base substrate BP2.

[0085] In an exemplary embodiment, the first connection pads SP-1 of the circuit board FB may be respectively connected to the driving pads MPD of the driving circuit board PB by an ultrasonic bonding process. However, the present invention is not limited to this example, and in another exemplary embodiment, the first connection pads SP-1 and the driving pads MPD may be electrically connected to each other using an anisotropic conductive film ("ACF"). Although not shown, the driving circuit board PB may include a controller that provides a plurality of driving signals to the circuit board FB through the driving pads MPD.

[0086] In a plan view, the driving chip DC may be disposed between the first connection pad SP-1 and the second connection pad SP-2. In other words, the first connection pad SP-1 and the second connection pad SP-2 may be spaced apart from each other, with the driving chip DC disposed between the first connection pad SP-1 and the second connection pad SP-2.

[0087] The driving chip DC can receive a driving signal transmitted from the driving circuit board PB through the first connection pad SP-1, and can output a data signal to be provided to the pixel PX based on the received driving signal. The data signal output from the driving chip DC can be transmitted to the signal pad PD through the second connection pad SP-2. The signal pad PD can be used to transmit the data signal transmitted from the driving chip DC to the data line DL of the signal line SGL respectively.

[0088] refer to Figure 4B , the circuit device layer DP-CL may be disposed on the substrate SUB. The circuit device layer DP-CL may include at least one insulating layer and a circuit device. The circuit device may include a signal line and a pixel driving circuit, etc. The formation of the circuit device layer DP-CL may include forming an insulating layer, a semiconductor layer and a conductive layer using a coating or deposition process, and patterning the insulating layer, the semiconductor layer and the conductive layer using a photolithography and etching process.

[0089] The circuit device layer DP-CL may include a buffer layer BFL, first and second intermediate inorganic layers 10 and 20 including an inorganic material, and an intermediate organic layer 30 including an organic material. The buffer layer BFL may include a plurality of stacked inorganic layers.

[0090] In an exemplary embodiment, the pixel driving circuit may include at least two transistors T1 and T2 for driving the organic light emitting diode OLED of the display device layer DP-OLED. Figure 4B As shown in , such transistors T1 and T2 may include a switching transistor T1 and a driving transistor T2. The switching transistor T1 may be connected to the gate line GL and the data line DL to control the operation of the driving transistor T2. The driving transistor T2 may be connected to the organic light emitting diode OLED of the display device layer DP-OLED to control the operation of the organic light emitting diode OLED.

[0091] The switching transistor T1 may include a first semiconductor pattern OSP1, a first control electrode GE1, a first input electrode DE1, and a first output electrode SE1, and the driving transistor T2 may include a second semiconductor pattern OSP2, a second control electrode GE2, a second input electrode DE2, and a second output electrode SE2.

[0092] The first through hole CH1 and the second through hole CH2 may be defined in the circuit device layer DP-CL to electrically connect the first input electrode DE1 and the first output electrode SE1 of the switching transistor T1 to the first semiconductor pattern OSP1. The third through hole CH3 and the fourth through hole CH4 may be defined in the circuit device layer DP-CL to electrically connect the second input electrode DE2 and the second output electrode SE2 of the driving transistor T2 to the second semiconductor pattern OSP2.

[0093] The display device layer DP-OLED may include an organic light emitting diode OLED. The display device layer DP-OLED may include a pixel defining layer PDL. In an exemplary embodiment, the pixel defining layer PDL may be an organic layer.

[0094] The first electrode AE ​​may be disposed on the intermediate organic layer 30. The first electrode AE ​​may be connected to the second output electrode SE2 through a fifth penetration hole CH5 penetrating the intermediate organic layer 30. A light emitting opening OM may be defined in the pixel defining layer PDL. The light emitting opening OM of the pixel defining layer PDL may expose at least a portion of the first electrode AE.

[0095] The display panel DP may include a pixel area PXA and a non-pixel area NPXA adjacent to the pixel area PXA. The pixel area PXA may be an area for emitting light to the outside and an image thereon being recognized by a user. The non-pixel area NPXA may surround the pixel area PXA. In the illustrated exemplary embodiment, the pixel area PXA may be defined as a portion corresponding to the first electrode AE ​​exposed by the light emitting opening OM.

[0096] The hole control layer HCL may be disposed in both the pixel region PXA and the non-pixel region NPXA. The hole control layer HCL may include a hole transport layer, and in an exemplary embodiment, the hole control layer HCL may further include a hole injection layer. The emission layer EML may be disposed on the hole control layer HCL.

[0097] The emission layer EML may be disposed in an area corresponding to the light emitting opening OM. The emission layer EML may be composed of or include at least one of an organic material or an inorganic material. The emission layer EML may generate light of a predetermined color. In an exemplary embodiment, the emission layer EML may be provided as an overall shape and may be disposed on the hole control layer HCL. In an exemplary embodiment, for example, the emission layer EML as an overall shape may be disposed in both the pixel area PXA and the non-pixel area NPXA. However, the present invention is not limited to this example, and in another exemplary embodiment, the emission layer EML may include a plurality of patterns respectively disposed in the pixel area PXA.

[0098] The electron control layer ECL may be disposed on the emission layer EML. The electron control layer ECL may include an electron transport layer, and in an exemplary embodiment, the electron control layer ECL may further include an electron injection layer. The hole control layer HCL and the electron control layer ECL may be provided using an open mask, and thus, the hole control layer HCL and the electron control layer ECL may be provided jointly on a plurality of pixels. The second electrode CE may be disposed on the electron control layer ECL. The second electrode CE may be a single pattern, which is jointly disposed on the electron control layer ECL respectively included in a plurality of pixels.

[0099] The insulating layer TFL may be disposed on the second electrode CE. The insulating layer TFL may be provided as a single encapsulation layer and may include a plurality of thin films.

[0100] Figure 5 is a plan view showing an exemplary embodiment of a circuit board according to the present invention. Figure 6 It is along Figure 5 A cross-sectional view of an exemplary embodiment of a display device according to the present invention taken along line II′. Fig. 7Ais a cross-sectional view showing an exemplary embodiment of a connection pad and a signal pad according to the present invention.

[0101] Figure 7B It is along Figure 5 A cross-sectional view of an exemplary embodiment of a circuit board according to the present invention taken along line II-II′.

[0102] refer to Figure 5 In addition to the driving chip DC, the circuit board FB may further include a first conductive pattern CPL1 and a second conductive pattern CPL2.

[0103] The first conductive pattern CPL1 may include a first connection line SL-1 and a first connection pad SP-1. In an exemplary embodiment, the first connection line SL-1 and the first connection pad SP-1 may be provided as an integral shape provided by the same process. The first connection pad SP-1 may be electrically coupled to a Figure 4A The driving circuit board PB shown in FIG.

[0104] The first connection line SL-1 may be disposed between the first connection pad SP-1 and the driving chip DC. An end of the first connection line SL-1 may be connected to the first connection pad SP-1, and an opposite end of the first connection line SL-1 may be connected to the driving chip DC.

[0105] The second conductive pattern CPL2 may be provided to face the first conductive pattern CPL1, and the driving chip DC is placed between the second conductive pattern CPL2 and the first conductive pattern CPL1. The second conductive pattern CPL2 may include a second connection line SL-2 and a second connection pad SP-2. In an exemplary embodiment, the second connection line SL-2 and the second connection pad SP-2 may be provided as an integral shape provided by the same process. The second connection pad SP-2 may be provided with a first conductive pattern CPL1 by an ultrasonic bonding method. Figure 4A The signal pad PD of the display panel DP shown in FIG.

[0106] The second connection line SL-2 may be disposed between the second connection pad SP-2 and the driving chip DC. An end of the second connection line SL-2 may be connected to the second connection pad SP-2, and an opposite end of the second connection line SL-2 may be connected to the driving chip DC.

[0107] In the present specification, each of the first and second connection lines SL-1 and SL-2 may be referred to as a line portion, and each of the first and second connection pads SP-1 and SP-2 may be referred to as a pad portion.

[0108] In addition, the circuit board FB may further include an insulating layer SIL disposed on the first base substrate BP1 to cover the first connection wires SL-1 and the second connection wires SL-2.

[0109] refer to Figure 6 , the substrate SUB and the first base substrate BP1 may be arranged to face each other in the third direction DR3. The signal pad PD (hereinafter referred to as "signal pad") located on the substrate SUB and the second connection pad SP-2 (hereinafter referred to as "second connection pad") located on the first base substrate BP1 may contact each other and may face each other in the third direction DR3.

[0110] As described above, the signal pad PD and the second connection pad SP- 2 may contact each other through the ultrasonic bonding method.

[0111] For details, refer to Fig. 7A The second connection pad SP-2 may be composed of or include a metal material that can be easily bonded to the signal pad PD through an ultrasonic bonding process. In an exemplary embodiment, the second connection pad SP-2 may be composed of or include copper (Cu), for example.

[0112] The signal pad PD may include a first driving conductive layer P1a, a second driving conductive layer P1b, and a third driving conductive layer P1c. The first driving conductive layer P1a may be provided on a substrate SUB. The first driving conductive layer P1a may be directly disposed on the substrate SUB. The second driving conductive layer P1b may be disposed on the first driving conductive layer P1a, and the third driving conductive layer P1c may be disposed on the second driving conductive layer P1b.

[0113] In an exemplary embodiment, the first driving conductive layer P1a and the third driving conductive layer P1c may include the same material. In an exemplary embodiment, for example, each of the first driving conductive layer P1a and the third driving conductive layer P1c may include titanium (Ti), and the second driving conductive layer P1b may include aluminum (Al). In an exemplary embodiment, the thickness of the second driving conductive layer P1b in the third direction DR3 may be greater than the thickness of each of the first driving conductive layer P1a and the third driving conductive layer P1c.

[0114] The first driving conductive layer P1a including titanium can be easily bonded to the substrate SUB including glass or polyimide and the second driving conductive layer P1b including aluminum by an ultrasonic bonding method. In addition, the third driving conductive layer P1c including titanium can be easily bonded to the second driving conductive layer P1b including aluminum by an ultrasonic bonding method.

[0115] In an exemplary embodiment, the third driving conductive layer P1c including titanium (Ti) may be attached to the second connection pad SP-2 including copper (Cu) by an ultrasonic bonding method. In addition, although not shown, in the case where the second connection pad SP-2 and the third driving conductive layer P1c are connected to each other by an ultrasonic bonding process between the second connection pad SP-2 and the signal pad PD, at least a portion of the second driving conductive layer P1b may be adhered to the second connection pad SP-2.

[0116] refer to Figure 7B , a contact area CTA and a non-contact area NCTA adjacent to the contact area CTA may be defined in the circuit board FB. The contact area CTA may correspond to the second pad area FA2 in which the second connection pad SP-2 is disposed, and the non-contact area NCTA may correspond to the remaining area except the contact area CTA. In this specification, the contact area may refer to an area in which two metal materials are bonded to each other by an ultrasonic bonding technique.

[0117] In an exemplary embodiment, the circuit board FB may include a first conductive layer CL1 and a second conductive layer CL2. The first conductive pattern CPL1 and the second conductive pattern CPL2 of the circuit board FB may include at least one of the first conductive layer CL1 and the second conductive layer CL2. The first conductive layer CL1 may be disposed on the first base substrate BP1, and the second conductive layer CL2 may be disposed on the first base substrate BP1 to cover the first conductive layer CL1.

[0118] The first conductive layer CL1 may be thicker than the second conductive layer CL2 when measured in the third direction DR3. The first conductive layer CL1 may be a layer for ultrasonic bonding with the signal pad PD, and the second conductive layer CL2 may serve as a cover layer to prevent the first conductive layer CL1 from being oxidized by oxygen supplied from the outside.

[0119] Hereinafter, the stacking structure of the second conductive pattern CPL2 bonded to the signal pad PD of the display panel DP by the ultrasonic bonding process will be mainly described. Although not described in detail, the first conductive pattern CPL1 electrically bonded to the driving circuit board PB may also have the same structure as that of the second conductive pattern CPL2. In this case, the circuit board FB may include a contact area, and the contact area is defined as a first connection pad SP-1 corresponding to the first conductive pattern CPL1.

[0120] In detail, the first conductive layer CL1 may include a first conductive portion CL1a corresponding to the contact area CTA and a second conductive portion CL1b corresponding to the non-contact area NCTA. The second conductive layer CL2 may include: a third conductive portion CL2a disposed on the first conductive portion CL1a and corresponding to the contact area CTA; and a fourth conductive portion CL2b disposed on the second conductive portion CL1b and corresponding to the non-contact area NCTA.

[0121] The first conductive portion CL1a and the third conductive portion CL2a may correspond to the second connection pad SP-2, and the second conductive portion CL1b and the fourth conductive portion CL2b may correspond to the second connection line SL-2. In this specification, the second conductive portion CL1b and the fourth conductive portion CL2b of the second connection line SL-2 will be described as a wire layer. In an exemplary embodiment, the third conductive portion CL2a and the first conductive portion CL1a may be provided as an integral shape provided by the same process, and the fourth conductive portion CL2b and the second conductive portion CL1b may be provided as an integral shape provided by the same process.

[0122] In particular, in a plan view, the third conductive portion CL2a corresponding to the contact area CTA may have an area smaller than that of the first conductive portion CL1a. The third conductive portion CL2a may overlap a portion of the first conductive portion CL1a without overlapping the entirety of the first conductive portion CL1a. In contrast, the fourth conductive portion CL2b corresponding to the non-contact area NCTA may overlap the entirety of the second conductive portion CL1b. Therefore, the second conductive layer CL2 may expose at least a portion of the first conductive layer CL1 corresponding to the contact area CTA.

[0123] In an exemplary embodiment, the second conductive layer CL2 may be disposed on the first base substrate BP1 to completely cover the first conductive layer CL1. Thereafter, a portion of the second conductive layer CL2 overlapping the contact area CTA may be removed by strong light (e.g., a laser beam) so that a portion of the first conductive portion CL1a is exposed through the second conductive layer CL2 overlapping the contact area CTA, as shown in FIG. Figure 7B as shown in .

[0124] In an exemplary embodiment, the second connection pad SP-2 corresponding to the contact area CTA may include a first connection pad portion SC1 and a second connection pad portion SC2. The first connection pad portion SC1 may correspond to a portion of the first conductive layer CL1 disposed in the contact area CTA and exposed by the second conductive layer CL2. The second connection pad portion SC2 may correspond to a portion of the first conductive layer CL1 and the second conductive layer CL2 stacked in the contact area CTA and not overlapping the first connection pad portion SC1.

[0125] According to an exemplary embodiment of the present invention, Figure 7B As shown in , the first connection pad portion SC1 may consist of only the first conductive layer CL1, and the second connection pad portion SC2 may consist of the stacked first conductive layer CL1 and the second conductive layer CL2. As a result, when measured in the third direction DR3, the thickness of the second connection pad portion SC2 may be greater than the thickness of the first connection pad portion SC1.

[0126] In an exemplary embodiment, the first conductive layer CL1 and the second conductive layer CL2 may be composed of or include different materials. In an exemplary embodiment, for example, the first conductive layer CL1 may include copper (Cu), and the second conductive layer CL2 may include tin (Sn). The second conductive layer CL2 including tin (Sn) may cover the first conductive layer CL1, and thus it is possible to prevent the first conductive layer CL1 from being oxidized by oxygen supplied from the outside. In addition, as Figure 5 The driving chip DC shown in FIG. 4 may be disposed on the second conductive layer CL2 .

[0127] As reference Fig. 7A As described, the third driving conductive layer P1c of the signal pad PD contacting the second connection pad SP-2 may include titanium (Ti). Generally, titanium is a metal that can be easily bonded to copper or aluminum (Al) by an ultrasonic bonding method. However, titanium is not easily bonded to tin (Sn) by an ultrasonic bonding method.

[0128] In detail, since the first connection pad portion SC1 is composed of only a single layer of the first conductive layer CL1, an ultrasonic bonding process may be easily performed between the first connection pad portion SC1 and the signal pad PD. The first connection pad portion SC1 may include only the first conductive portion CL1a. In contrast, since the second connection pad portion SC2 has a structure in which the first conductive portion CL1a and the third conductive portion CL2a are stacked, the third conductive portion CL2a may face the signal pad PD. As a result, the second connection pad portion SC2 including tin (Sn) may not be easily bonded to the signal pad PD through an ultrasonic bonding process.

[0129] According to an exemplary embodiment of the present invention, the second connection pad SP-2 and the signal pad PD contacting each other by an ultrasonic bonding method may have a predetermined surface roughness (hereinafter referred to as roughness "Ra"). In an exemplary embodiment, for example, due to friction between the second connection pad SP-2 and the signal pad PD caused by an ultrasonic process, the interface between the second connection pad SP-2 and the signal pad PD may become rough.

[0130] The first interface between the first connection pad portion SC1 and the signal pad PD may have a first surface roughness. The second interface between the second connection pad portion SC2 and the signal pad PD may have a second surface roughness. The surface roughness may be measured based on the international standard (ISO 1302:1992) summarized in Table 1 below. The relationship between the surface roughness Ra and the roughness grade number is as follows:

[0131] [Table 1]

[0132]

[0133] According to an exemplary embodiment of the present invention, the first surface roughness may be greater than the second surface roughness. The first conductive portion CL1a corresponding to the first connection pad portion SC1 may include copper (Cu), and the third conductive portion CL2a corresponding to the second connection pad portion SC2 may include tin (Sn). In an ultrasonic process, friction between copper (Cu) and titanium (Ti) may occur more actively than friction between tin (Sn) and titanium (Ti). Therefore, the first surface roughness between the first connection pad portion SC1 and the signal pad PD may be greater than the second surface roughness between the second connection pad portion SC2 and the signal pad PD. Figure 6 and Figure 7B As shown in , the circuit board FB may further include a sub-conductive layer CL2s, which is disposed on a side surface of the first conductive portion CL1a corresponding to the first connection pad portion SC1. The sub-conductive layer CL2s may be provided by the same process as that for the second conductive layer CL2, and may include the same material as that of the second conductive layer CL2 (i.e., tin (Sn)).

[0134] like Figure 6 As shown in , when measured in the third direction DR3, the height TH1 of the sub-conductive layer CL2s can be less than the thickness TH2 of the first conductive portion CL1a overlapping the first connecting pad portion SC1, and in this case, it is possible to facilitate the ultrasonic bonding process between the first conductive portion CL1a and the signal pad PD.

[0135] In the illustrated exemplary embodiment, the third conductive portion CL2a overlapping the contact area CTA is described as being disposed on the first conductive portion CL1a, but the present invention is not limited to this example. In an exemplary embodiment, for example, the second conductive layer CL2 may be provided to completely expose a portion of the first conductive layer CL1 overlapping the contact area CTA.

[0136] Figure 8 It is shown that according to the present invention Figure 5 An enlarged view of another exemplary embodiment of portion “AA” of FIG. Fig. 9It is along Figure 8 A cross-sectional view of another exemplary embodiment of a circuit board according to the present invention is taken along line III-III'.

[0137] Except for the different shapes of the second connection pads SP-2a and SP-2b, as shown in FIG. Figure 8 and Fig. 9 The second conductive patterns CPL2a and CPL2b shown in FIG. Figure 7B The second conductive pattern CPL2 shown in FIG. 1 has substantially the same structure. Therefore, for the sake of brevity of description, repeated description of previously described elements may be omitted. The second conductive pattern CPL2a may include a second connection line SL-2a and a second connection pad SP-2a, and the second conductive pattern CPL2b may include a second connection line SL-2b and a second connection pad SP-2b.

[0138] In an exemplary embodiment, in order to improve the connection reliability in the ultrasonic bonding process, each of the second connection pads SP-2a and SP-2b may have an area larger than that of the signal pad PD in a plan view. Therefore, the contact area between the first connection pad portion SC1 of each of the second connection pads SP-2a and SP-2b and the signal pad PD may be increased. However, the present invention is not limited to this example, and in another exemplary embodiment, each of the second connection pads SP-2a and SP-2b may be provided to have the same area as that of the signal pad PD in a plan view.

[0139] refer to Figure 8 , each of the second connection pads SP-2a and SP-2b may overlap with the contact area CTA. In particular, the contact area CTA may include a first sub-area CTA-C and a second sub-area CTA-N. The first sub-area CTA-C and the second sub-area CTA-N may be alternately and repeatedly arranged in the second direction DR2.

[0140] For details, refer to Fig. 9 , the first sub-area CTA-C may correspond to Figure 7B The first connection pad portion SC1, and the second sub-area CTA-N may correspond to Figure 7B The first connection pad portion SC1 may have a single-layer structure of the first conductive portion CL1a, and the second connection pad portion SC2 may have a structure in which the first conductive portion CL1a and the third conductive portion CL2a-1 are stacked. The first conductive portion CL1a and the third conductive portion CL2a-1 may correspond to the second connection pad SP-2a, and the second conductive portion CL1b and the fourth conductive portion CL2b may correspond to the second connection line SL-2a.

[0141] Therefore, the first connection pad portion SC1 and the second connection pad portion SC2 may be alternately and repeatedly arranged in the second direction DR2. Here, the first conductive layer CL1 overlapping the contact area CTA may be provided as an overall shape extending in the second direction DR2. In contrast, the second conductive layer CL2 overlapping the contact area CTA may include portions spaced apart from each other by a predetermined distance in the second direction DR2.

[0142] In an exemplary embodiment, the second conductive layer CL2 may be disposed on the first base substrate BP1 to completely cover the first conductive layer CL1. Fig. 9 As shown in FIG. 1 , in order to form a third conductive portion CL2a-1 exposing a portion of the first conductive portion CL1a, a portion of the second conductive layer CL2 overlapping the contact area CTA may be removed by a laser beam. In this case, the laser beam may be irradiated onto portions of the second conductive layer CL2 spaced apart from each other by a predetermined distance in the second direction DR2.

[0143] Fig.10 and Fig.11 is a cross-sectional view showing another exemplary embodiment of a display device according to the present invention.

[0144] Except for the different shape of the second connection pad SP-2z, as shown in FIG. Fig.10 The circuit board FBz shown in FIG. 1 may have a Figure 6 and Figure 7B The circuit board FB shown in FIG. 1 has substantially the same structure. Therefore, for the sake of brevity of description, repeated description of previously described elements may be omitted.

[0145] refer to Fig.10 and Fig.11 , the second connection pad SP-2z may have a single-layer structure composed of a first conductive portion CL1az of the first conductive layer CL1 overlapping the contact area CTA. The second connection line SL-2z may have a stacked structure including a second conductive portion CL1b of the first conductive layer CL1 overlapping the non-contact area NCTA and a fourth conductive portion CL2b of the second conductive layer CL2 disposed on the second conductive portion CL1b. However, the present invention is not limited to this example, and in another exemplary embodiment, the second connection pad SP-2z may include a portion of the second conductive layer CL2 that overlaps the contact area CTA but is disposed to expose the first conductive layer CL1, such as Figure 7B as shown in .

[0146] In an exemplary embodiment, a recessed space OPT may be defined in the first conductive layer CL1, the recessed space OPT overlaps the contact area CTA and is recessed in the third direction DR3. In an exemplary embodiment, for example, at least one recessed space OPT may be defined in the second connection pad SP-2z, the at least one recessed space OPT being recessed in a direction from a top surface of the second connection pad SP-2z facing the signal pad PD of the display panel DP toward a bottom surface of the second connection pad SP-2z facing the first base substrate BP1.

[0147] Due to the recessed space OPT defined in the second connection pad SP-2z, the friction between the signal pad PD and the second connection pad SP-2z may increase during the ultrasonic bonding process between the signal pad PD and the second connection pad SP-2z, which may result in an increase in the surface roughness between the signal pad PD and the second connection pad SP-2z.

[0148] In such Figure 7B As shown in FIG. 1 , the circuit board FBz includes a portion of the second conductive layer CL2, which overlaps the contact area CTA but is arranged to expose the first conductive layer CL1. Fig.11 Unlike the structure shown in , the recessed space OPT may not overlap with the portion of the second conductive layer CL2.

[0149] FIG. 12A to FIG. 12D is a cross-sectional view showing an exemplary embodiment of a method of manufacturing a circuit board according to the present invention.

[0150] refer to Fig. 12A , the first conductive layer CL1 may be disposed on the first base substrate BP1. Thereafter, the first conductive layer CL1 may be patterned to have a Figure 5 The shapes of the first conductive pattern CPL1 and the second conductive pattern CPL2 shown in FIG. 8 are the same shape.

[0151] Afterwards, if Fig. 12B As shown in FIG. 1 , the second conductive layer CL2 may be disposed on the first base substrate BP1 to cover the first conductive layer CL1. The second conductive layer CL2 may be provided by dipping the first base substrate BP1 on which the first conductive layer CL1 is disposed into a container filled with a material for the second conductive layer CL2.

[0152] The material in the container may be tin (Sn), and in this case, the second conductive layer CL2 may be disposed on the first conductive layer CL1, but may not be disposed on the first base substrate BP1 including silicon. As a result, the second conductive layer CL2 may be disposed on the first base substrate BP1 to have a shape corresponding to the first conductive layer CL1.

[0153] Afterwards, if Fig. 12C As shown in FIG. 1 , at least a portion of the second conductive layer CL2 overlapping the contact area CTA may be removed by strong light (eg, laser beam LR). As a result, a portion of the first conductive layer CL1 overlapping the contact area CTA may be exposed by the removed portion of the second conductive layer CL2.

[0154] In an exemplary embodiment, the second conductive layer CL2 overlapping the contact area CTA may be completely removed by the laser beam LR. In this case, during the ultrasonic bonding process, the signal pad PD of the display panel DP may face the first conductive layer CL1 overlapping the contact area CTA.

[0155] In an exemplary embodiment, the second conductive layer CL2 overlapping the contact area CTA may be partially removed by the laser beam LR. According to this exemplary embodiment, the resulting structure may have a structure corresponding to Figure 7B or Fig. 9 In this case, during the ultrasonic bonding process, the signal pad PD of the display panel DP may face each of the first conductive layer CL1 and the second conductive layer CL2 overlapping the contact area CTA.

[0156] In addition, the first conductive layer CL1 may be partially removed by the laser beam LR. Fig.10 The recess space OPT defined in the second connection pad may be provided by the laser beam LR. In this case, the intensity of the laser beam LR irradiated onto the first conductive layer CL1 may be greater than the intensity of the laser beam LR irradiated onto the second conductive layer CL2 overlapping the contact area CTA.

[0157] refer to Fig.12D Since at least a portion of the second conductive layer CL2 overlapping the contact area CTA is removed by the laser beam LR, the first conductive layer CL1 may be partially exposed. The second conductive layer CL2 is shown to include a portion overlapping the contact area CTA, but in an exemplary embodiment, such a portion of the second conductive layer CL2 may be omitted.

[0158] In addition, since the second conductive layer CL2 overlapping the contact area CTA is partially removed by the laser beam LR, the second conductive layer CL2 may be separated into the sub-conductive layer CL2s and the fourth conductive portion CL2b.

[0159] According to some exemplary embodiments of the present invention, connection pads of a circuit board and signal pads of a display panel are provided to contact each other through an ultrasonic bonding process, and thus connection reliability between the display panel and the circuit board may be improved.

[0160] While exemplary embodiments of the present invention have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made without departing from the spirit and scope of the following claims.

Claims

1. A display device, in, The display device comprises: A display panel including a signal pad; and A circuit board comprising a connection pad, the connection pad comprising a first connection pad portion and a second connection pad portion, the second connection pad portion being thicker than the first connection pad portion and not overlapping the first connection pad portion in a plan view, wherein the connection pad contacts the signal pad; and The first surface roughness between the first connection pad portion and the signal pad is greater than the second surface roughness between the second connection pad portion and the signal pad.

2. The display device according to claim 1, in, The connection pad includes a first conductive layer and a second conductive layer, the second conductive layer being disposed on the first conductive layer to expose a portion of the first conductive layer, The first connection pad portion corresponds to the portion of the first conductive layer exposed by the second conductive layer, and The second connection pad portion corresponds to a structure in which the first conductive layer and the second conductive layer are stacked.

3. The display device according to claim 2, in, The first conductive layer is thicker than the second conductive layer.

4. The display device according to claim 2, in, The circuit board further includes a sub-conductive layer provided on a side surface of the first connection pad portion and including the same material as that of the second conductive layer.

5. The display device according to claim 4, in, In the thickness direction of the display panel, the height of the sub-conductive layer is smaller than the thickness of the first conductive layer.

6. The display device according to claim 2, in, The first connection pad portions and the second connection pad portions are alternately and repeatedly arranged in a first direction, and the connection pads extend in the first direction.

7. The display device according to claim 6, in, The first conductive layer extends in the first direction into an integral shape, and The second conductive layer includes portions arranged to be spaced apart from each other by a predetermined distance in the first direction.

8. The display device according to claim 2, in, The first conductive layer includes a material different from a material of the second conductive layer.

9. The display device according to claim 2, in, The circuit board also includes: A base substrate, the connection pads are arranged on the base substrate; A driving chip is disposed on the base substrate; and a connecting wire, disposed on the base substrate, to electrically connect the connecting pad to the driving chip, The connecting line includes a first conductive line layer corresponding to the first conductive layer and a second conductive line layer corresponding to the second conductive layer.

10. The display device according to claim 9, in, The first wire layer and the first conductive layer are integrally formed, and The second wire layer and the second conductive layer are integrally formed.

11. The display device according to claim 2, in, The first conductive layer includes copper, and the second conductive layer includes tin.

12. The display device according to claim 1, in, In the plan view, an area of ​​the first connection pad portion is larger than an area of ​​the signal pad.

13. A display device, in, The display device comprises: a display panel, a display area and a non-display area adjacent to the display area being defined in the display panel, the display panel comprising a signal pad overlapping the non-display area; and a circuit board electrically connected to the display panel overlapping the non-display area, the circuit board comprising a conductive pattern including a pad portion facing the signal pad and in contact with the signal pad, and a line portion not overlapping the signal pad and connected to the pad portion, A recessed space is defined in the pad portion in a thickness direction of the display panel, the recessed space being recessed in a direction from a first surface of the pad portion facing the signal pad toward a second surface facing the first surface.

14. The display device according to claim 13, in, The pad portion comprises: a first conductive layer; and a second conductive layer disposed on the first conductive layer to expose a portion of the first conductive layer, The recessed space is defined in the portion of the first conductive layer exposed by the second conductive layer.

15. The display device according to claim 14, in, A first surface roughness between the signal pad and the portion of the first conductive layer exposed by the second conductive layer that are in contact with each other is greater than a second surface roughness between the signal pad and the second conductive layer that are in contact with each other.

16. The display device according to claim 14, in, The line portion comprises: a first line conductive layer having an overall shape together with the first conductive layer; and The second line conductive layer is disposed on the first line conductive layer and has an integral shape with the second line conductive layer.

17. The display device according to claim 14, in, The first conductive layer is thicker than the second conductive layer, and The first conductive layer includes a material different from a material of the second conductive layer.

18. A method for manufacturing a circuit board, in, The method comprises: preparing a base substrate in which a pad region and a line region are defined, the pad region and the line region being separated from each other in a plan view; forming a first conductive layer on the base substrate; removing an area of ​​the first conductive layer that does not overlap the pad area and the line area; forming a second conductive layer on the base substrate to cover the first conductive layer; and removing the area of ​​the second conductive layer overlapping the pad area using light, Wherein, as a result of using the light, a portion of the first conductive layer overlapping the pad region is exposed by the second conductive layer.

19. The method according to claim 18, in, The method further includes: irradiating the light onto a first surface of the first conductive layer overlapping the pad region, Wherein, as a result of using the light, a recessed space is defined in the first conductive layer, the recessed space being recessed in a direction from the first surface of the first conductive layer toward a second surface facing the first surface.

20. The method according to claim 19, in, The first conductive layer and the second conductive layer include materials different from each other, and The second conductive layer exposes a portion of the base substrate that does not overlap with the first conductive layer.

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