A high-speed voltage-mode transmitter with impedance correction circuit

Abstract

The present invention relates to a high-speed voltage mode transmitter with an impedance correction circuit. The present invention comprises an impedance correction circuit, a logic control circuit, a data parallel-to-serial module and a differential drive module. The parallel signal TX_Data <n:0>After the serial signal is outputted through the data parallel-to-serial circuit, it is connected to the differential drive module, which includes multiple groups of differential drive units. The output of the differential drive module is connected to the impedance correction circuit, and the control signal TX_R<31:0> is generated by judgment, and the input logic control circuit controls the number of differential drive units turned on. The present invention can effectively improve the output resistance deviation caused by the process, voltage and temperature, and reduce the influence of reflection caused by impedance mismatch on signal integrity; thereby improving the signal quality and ensuring the integrity of the signal.< / n:0>

Description

Technical Field

[0001] The present invention relates to the fields of signal communication such as aviation, navigation and industrial control, and in particular to a high-speed voltage-mode transmitter with an impedance correction circuit. Background Art

[0002] Due to the problem of high power consumption in current mode transmitters, voltage mode transmitters are generally used. Existing voltage mode transmitters use MOS tubes as output resistors, or use two resistors for positive and negative in a drive unit. The linearity of voltage mode transmitters with this structure is poor and is greatly affected by process, voltage and temperature (PVT). Due to process deviations, the design value and the actual resistance value may differ greatly, resulting in impedance matching problems in actual applications, affecting signal integrity. Summary of the invention

[0003] In order to solve the above-mentioned technical problems existing in the background technology, the present invention provides a high-speed voltage mode transmitter with an impedance correction circuit, which can effectively improve the output resistance deviation caused by process, voltage and temperature, and reduce the impact of reflection caused by impedance mismatch on signal integrity; thereby improving signal quality and ensuring signal integrity.

[0004] The technical solution of the present invention is: the present invention is a high-speed voltage mode transmitter with an impedance correction circuit, and its special feature is that: the transmitter includes an impedance correction circuit, a logic control circuit, a data parallel-to-serial module and a differential drive module, the impedance correction circuit is connected to the differential drive module through the logic control circuit, the data parallel-to-serial module is connected to the differential drive module, the differential drive module includes multiple groups of differential drive units, and the multiple groups of differential drive units are connected in parallel and then connected to the impedance correction circuit.

[0005] Preferably, the differential driving unit includes two driving units, namely a first driving unit and a second driving unit. The first driving unit includes a first NAND gate, a first NOT gate, a PMOS tube M1, an NMOS tube M2, a resistor Ro1 and a power supply VDD1. The first NAND gate is connected to the gates of the PMOS tube M1 and the NMOS tube M2 through the first NOT gate, the power supply VDD1 is connected to the source end of the PMOS tube M1, the source end of the NMOS tube M2 is grounded, and the drain ends of the PMOS tube M1 and the NMOS tube M2 are connected in series with the resistor Ro1 for output. The second driving unit includes a second NAND gate, a second NOT gate, a PMOS The second NAND gate is connected to the gates of the PMOS tube M3 and the NMOS tube M4 through the first NAND gate, the power supply VDD2 is connected to the source end of the PMOS tube M3, the source end of the NMOS tube M4 is grounded, the drain ends of the PMOS tube M3 and the NMOS tube M4 are connected in series with the resistor Ro2 for output, the logic control circuit is connected to one input end of the first NAND gate and the second NAND gate respectively, the data parallel-to-serial module outputs data Data_A to the other input end of the first NAND gate, and outputs data Data_B to the other input end of the second NAND gate.

[0006] Preferably, each first driving unit in the plurality of differential driving units is connected in parallel to output a voltage VoutA to the impedance correction circuit, and each second driving unit in the plurality of differential driving units is connected in parallel to output a voltage VoutB to the impedance correction circuit.

[0007] Preferably, the impedance correction circuit includes a power supply VDD, a comparator P1, a comparator P2, a resistor R1, a resistor R2, a resistor R3 and a state machine, the power supply VDD is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the positive input end of the comparator P1 and one end of the resistor R2, the other end of the resistor R2 is connected to the positive input end of the comparator P2 and one end of the resistor R3, the other end of the resistor R3 is grounded, the output voltage VoutA of the first drive unit after being connected in parallel is connected to the negative input end of the comparator P1, the output voltage VoutB of the second drive unit after being connected in parallel is connected to the negative input end of the comparator P2, the output ends of the comparator P1 and the comparator P2 are connected to the state machine, and the state machine is connected to the logic control circuit.

[0008] Preferably, the differential drive unit is 2 n Group, n is 2 or more.

[0009] In a high-speed serial interface, a serialization circuit is used to convert low-speed parallel signal input into high-speed serial signal output. The frequency of the last-stage serial output driver in the overall circuit is the highest, and it is responsible for driving the serial data to a channel with low-pass characteristics. The driving capability, output impedance, pre-emphasis / de-emphasis characteristics, and power consumption of the output stage determine the performance and power consumption of the entire transmitter, and therefore it is the core circuit of the transmitter.

[0010] The present invention is directed to a high-speed serial transmitter, and proposes a voltage-mode output drive circuit with high-precision and wide-range impedance correction. The design of the high-speed voltage-mode transmitter with an impedance correction circuit can realize the configurability of the output impedance by connecting multiple groups of differential drive units DRV_diff_unit in parallel. Each group of differential drive units includes two drive units. The pull-up resistor in the drive unit is realized by a PMOS series resistor Ro, and the pull-down resistor is realized by an NMOS series resistor Ro. Sharing the same resistor Ro can reduce the area of ​​the output drive stage. Connecting it at the common point of the PMOS tube and the NMOS tube can reduce the parasitic capacitance, speed up the charging and discharging speed caused by the switching of the MOS tube, and improve the quality of the output signal. Therefore, the present invention can effectively improve the output resistance deviation caused by the process, voltage and temperature, and reduce the influence of the reflection caused by the impedance discontinuity on the signal; thereby improving the signal quality and ensuring the integrity of the signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic diagram of a driving unit circuit of the present invention;

[0012] Figure 2 It is a circuit schematic diagram of the present invention;

[0013] Figure 3 It is a circuit principle diagram of the differential driving module of the present invention connected to the impedance correction circuit. DETAILED DESCRIPTION

[0014] The high-speed voltage-mode transmitter with an impedance correction circuit provided by the present invention includes an impedance correction circuit (R_Comp circuit), a logic control circuit (Ctrl_Logic circuit), a data parallel-to-serial module (MUX module) and a differential drive module (DRV_diff module). The impedance correction circuit is connected to the differential drive module through the logic control circuit, and the data parallel-to-serial module is connected to the differential drive module. The differential drive module includes multiple groups of differential drive units (DRV_diff_unit), and the multiple groups of differential drive units are connected in parallel and connected to the impedance correction circuit. The differential drive unit includes two drive units, namely a first drive unit and a second drive unit. After each first drive unit in the multiple groups of differential drive units is connected in parallel, it outputs a voltage VoutA to the impedance correction circuit, and after each second drive unit in the multiple groups of differential drive units is connected in parallel, it outputs a voltage VoutB to the impedance correction circuit. The differential drive unit is 2 n groups, n is 2 or more. That is, the differential drive units can be 4 groups, 8 groups, 16 groups or 32 groups.

[0015] Parallel signal TX_Data <n:0>After the serial signal is output through the data parallel-to-serial module, it is connected to the differential drive module. The differential drive module includes multiple groups of differential drive units (DRV_diff_unit). The output of the differential drive module is connected to the impedance correction circuit. The control signal TX_R<31:0> is generated by judgment, and the input logic control circuit controls the number of differential drive units turned on.

[0016] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0017] See also Figure 1 The driving unit of the present invention comprises a NAND gate, a NOT gate, a PMOS tube M, an NMOS tube M0, a resistor Ro and a power supply VDD. The NAND gate is respectively connected to the gates of the PMOS tube M and the NMOS tube M0 through the NOT gate, the power supply VDD is connected to the source end of the PMOS tube M, the source end of the NMOS tube M0 is grounded, and the drain ends of the PMOS tube M and the NMOS tube M0 are connected in series with a resistor Ro for output, that is, the PMOS tube M and the NMOS tube M0 share the same resistor Ro, which is connected at the common point of the PMOS tube M and the NMOS tube M0. In this unit, the pull-up resistor is realized by the PMOS tube M connected in series with the resistor Ro, and the pull-down resistor is realized by the NMOS tube M0 connected in series with the same resistor Ro. Sharing the same resistor Ro can reduce the area of ​​the output driving stage. At the same time, the resistor Ro is connected at the common point of the PMOS tube M and the NMOS tube M0, which can reduce the parasitic capacitance, speed up the charging and discharging speed caused by the switching of the MOS tube, and improve the quality of the output signal.

[0018] See also Figure 2 The DRV_diff_unit of the present invention includes two driving units, namely a first driving unit and a second driving unit. The first driving unit includes a first NAND gate, a first NOT gate, a PMOS tube M1, an NMOS tube M2, a resistor Ro1 and a power supply VDD1. The first NAND gate is connected to the gates of the PMOS tube M1 and the NMOS tube M2 through the first NOT gate. The power supply VDD1 is connected to the source end of the PMOS tube M1, the source end of the NMOS tube M2 is grounded, and the drain ends of the PMOS tube M1 and the NMOS tube M2 are connected in series with the resistor Ro1 for output. The second driving unit includes a second NAND gate, a second NOT gate, PMOS tube M3, NMOS tube M4, resistor Ro2 and power supply VDD2, the second NAND gate is connected to the gates of PMOS tube M3 and NMOS tube M4 respectively through the first NAND gate, the power supply VDD2 is connected to the source end of PMOS tube M3, the source end of NMOS tube M4 is grounded, the drain ends of PMOS tube M3 and NMOS tube M4 are connected in series with resistor Ro2 for output, the logic control circuit is connected to one input end of the first NAND gate and the second NAND gate respectively, the MUX module outputs data Data_A to the other input end of the first NAND gate, and outputs data Data_B to the other input end of the second NAND gate. After each first drive unit in the multiple groups of differential drive units is connected in parallel, the output voltage VoutA is given to the impedance correction circuit, and after each second drive unit in the multiple groups of differential drive units is connected in parallel, the output voltage VoutB is given to the impedance correction circuit.

[0019] In the front-end circuit of the transmitter, the MUX module converts multiple low-speed parallel signals TX_Data <n:0>Converted into higher-speed serial data Data_A and Data_B, and then input to the differential drive module. The differential drive module adopts a symmetrical differential structure, consisting of multiple groups of DRV_diff_unit in parallel, to reduce the impact of noise on signal integrity. The output impedance of the differential drive module is required to be around 50Ω.

[0020] The Ctrl_Logic circuit generates the control signal TR_R<31:0> for the DRV_diff_unit operation according to the resistor feedback control signal Ctrl_R<4:0>. The control signal controls the number of DRV_diff_unit turned on in the circuit, thereby adjusting the number of output resistors in parallel. When the number of DRV_diff_unit modules turned on increases, the resistance can be reduced; when the number of DRV_diff_unit modules turned on decreases, the resistance can be increased.

[0021] In order to realize the configurability of the output resistance, in this embodiment, the differential driving module is realized by connecting 32 groups of DRV_diff_unit in parallel.

[0022] In DRV_diff_unit, the pull-up resistance value of the first driving unit is the sum of the on-resistance R_p_on of the PMOS tube M1 and the resistance Ro1, and the pull-down resistance value is the sum of the on-resistance R_n_on of the NMOS tube M2 and the resistance Ro1. Among them, a compromise is made between the MOS size impedance and resistance, and Ro1 is set to be larger as the dominant, with resistance Ro1 = 800Ω, R_p_on = 200Ω, R_n_on = 200Ω, then the pull-up resistance value and the pull-down resistance value are both 1000Ω. The initial state is set to 20 groups of DRV_diff_unit open, at which time the parallel resistance of the 20 first driving units in the 20 groups of DRV_diff_unit is 50Ω. Similarly, according to the above design, the parallel resistance of the 20 second driving units is also 50Ω.

[0023] The impedance correction circuit controls the remaining 12 groups of DRV_diff_unit to turn on or off to achieve an overall output impedance of 50Ω. This structure can calibrate the pull-up resistor and the pull-down resistor to achieve a 5% correction accuracy and a ±40% correction range.

[0024] See also Figure 3 The impedance correction circuit of the present invention includes a power supply VDD, a comparator P1, a comparator P2, a resistor R1, a resistor R2, a resistor R3 and a state machine, the power supply VDD is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the positive input end of the comparator P1 and one end of the resistor R2, the other end of the resistor R2 is connected to the positive input end of the comparator P2 and one end of the resistor R3, the other end of the resistor R3 is grounded, the output voltage VoutA of the first driving unit after being connected in parallel is connected to the negative input end of the comparator P1, the output voltage VoutB of the second driving unit after being connected in parallel is connected to the negative input end of the comparator P2, the output ends of the comparator P1 and the comparator P2 are connected to the state machine, and the state machine is connected to the Ctrl_Logic circuit.

[0025] The impedance correction circuit divides the voltages VoutA and VoutB by DRV_diff_unit and an external precision 100Ω resistor. The resistance ratio of the internal resistors R1, R2 and R3 of the impedance correction circuit is 1:2:1. The reference voltages Vref_u and Vref_d are obtained by voltage division. VoutA is compared with Vref_u, and VoutB is compared with Vref_d. The internal correction unit of the state machine is turned on or off by clock triggering until the output voltage is equal to the reference voltage. At this time, the resistance feedback control signal Ctrl_R<4:0> of the state machine is output to the Ctrl_Logic circuit to control the opening and closing of 16 groups of DRV_diff_unit respectively, so as to realize the correction of the driver output impedance to 50Ω.

[0026] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-speed voltage-mode transmitter with an impedance correction circuit, characterized in that: The transmitter includes an impedance correction circuit, a logic control circuit, a data parallel-to-serial module and a differential drive module. The impedance correction circuit is connected to the differential drive module through the logic control circuit. The data parallel-to-serial module is connected to the differential drive module. The differential drive module includes multiple groups of differential drive units. The multiple groups of differential drive units are connected in parallel and connected to the impedance correction circuit. The differential drive unit includes two drive units, namely a first drive unit and a second drive unit. The first drive unit includes a first NAND gate, a first NOT gate, a PMOS tube M1, an NMOS tube M2, a resistor Ro1 and The power supply VDD1, the first NAND gate is respectively connected to the gates of the PMOS tube M1 and the NMOS tube M2 through the first NOT gate, the power supply VDD1 is connected to the source end of the PMOS tube M1, the source end of the NMOS tube M2 is grounded, the drain ends of the PMOS tube M1 and the NMOS tube M2 are connected in series with the resistor Ro1 for output, the second driving unit includes a second NAND gate, a second NOT gate, a PMOS tube M3, an NMOS tube M4, a resistor Ro2 and a power supply VDD2, the second NAND gate is respectively connected to the gates of the PMOS tube M3 and the NMOS tube M4 through the first NOT gate The power supply VDD2 is connected to the source end of the PMOS tube M3, the source end of the NMOS tube M4 is grounded, the drain ends of the PMOS tube M3 and the NMOS tube M4 are connected in series with the resistor Ro2 for output, the logic control circuit is respectively connected to one input end of the first NAND gate and the second NAND gate, the data parallel-to-serial module outputs data Data_A to the other input end of the first NAND gate, and outputs data Data_B to the other input end of the second NAND gate, the impedance correction circuit includes a power supply VDD, a comparator P1, a comparator P2, a resistor R1, a resistor R2, a resistor R3 and a state machine, the power supply VDD is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the positive input end of the comparator P1 and one end of the resistor R2, the other end of the resistor R2 is connected to the positive input end of the comparator P2 and one end of the resistor R3, the other end of the resistor R3 is grounded, the output voltage VoutA of the first drive units after being connected in parallel is connected to the negative input end of the comparator P1, the output voltage VoutB of the second drive units after being connected in parallel is connected to the negative input end of the comparator P2, the output ends of the comparator P1 and the comparator P2 are connected to the state machine, and the state machine is connected to a logic control circuit.

2. The high-speed voltage-mode transmitter with impedance correction circuit according to claim 1, characterized in that: After being connected in parallel, each first driving unit in the plurality of differential driving units outputs a voltage VoutA to the impedance correction circuit, and after being connected in parallel, each second driving unit in the plurality of differential driving units outputs a voltage VoutB to the impedance correction circuit.

3. The high-speed voltage mode transmitter with impedance correction circuit according to claim 1 or 2, characterized in that: The differential drive unit is 2 n Group, n is 2 or more.

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