Branch prediction based on load path history

Abstract

The branch prediction method and system include: for a branch instruction fetched by a processor, indexing a branch identification (ID) table based on a function of a program counter (PC) value of the branch instruction, wherein each entry of the branch ID table includes at least a tag field and a precision counter. For a tag hit at an entry indexed by a PC value, if the value of the corresponding precision counter is greater than or equal to zero, a prediction counter is selected from a prediction counter pool based on a function of the PC value and a load path history, wherein the prediction counter includes a corresponding confidence value and a prediction value. If the associated confidence value is greater than zero, the memory-dependent branch prediction of the branch instruction is assigned the prediction value of the selected prediction counter, and the branch prediction from the conventional branch predictor is overwritten.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to non-provisional application No. 16 / 136,151, filed on September 19, 2018, entitled “Branch Prediction Based on Load Path History,” which is assigned to the assignee of the present application and is expressly incorporated herein by reference. Technical Field

[0003] The disclosed aspects relate to branch prediction in a processing system. More specifically, exemplary aspects relate to using load path history as context information in prediction of hard-to-predict branch instructions, such as memory-dependent branch instructions. Background Art

[0004] The processing system may employ instructions that cause a change in control flow, such as branch instructions. The direction of a branch instruction may be based, for example, on the circumstances of a conditional evaluation, but such an evaluation may not be known until processing of the branch instruction has progressed deep into the processor's instruction pipeline. To avoid the pipeline from being stalled until the evaluation is known, the processor may employ a branch prediction mechanism to predict the direction of a branch instruction early in the pipeline. Based on the prediction, the processor may speculatively fetch and execute instructions from the predicted address in one of two paths: a "taken" path, which begins at the branch target address, and whose corresponding direction is referred to as a "taken direction"; or a "not taken" path, which begins at the next sequential address after the conditional branch instruction, and whose corresponding direction is referred to as a "not taken direction".

[0005] When the condition is evaluated and the actual branch direction is determined, if the branch is mispredicted (i.e., execution follows the wrong path), the speculatively fetched instructions can be cleared from the pipeline and new instructions can be fetched from the correct next address in the correct path. Thus, improving the accuracy of branch predictions mitigates the penalties associated with mispredicted and wrong-path instruction execution, and correspondingly improves the performance and energy utilization of the processing system.

[0006] Therefore, it can be seen that branch prediction plays an important role in high-performance pipeline processors. Conventional branch predictors can use context information when making branch predictions. Such context information can include global and / or local branch history, branch path history, branch target history, etc. However, conventional branch predictors are considered to be unable to accurately predict certain types of branch instructions, including branch instructions whose directions may be irrelevant to the above-mentioned context information. One class of such difficult-to-predict branch instructions includes memory-dependent branch instructions, where the direction or result of the branch instruction depends directly or indirectly on a value loaded from memory.

[0007] Figure 1A code snippet is shown, including pseudocode 100 juxtaposed with corresponding program instructions 110, as an example of a difficult to predict memory-dependent branch instruction. The shown portion of pseudocode 100 includes a program that receives a data value from a data array "A" in a memory. Specifically, for the pseudocode "if(a(i[a]>16)" that appears in the "for" loop for the "i" value in pseudocode 100, the corresponding program instruction may include loading the value of the array element at address A[i] in the memory into register R1, and then evaluating the branch instruction "X" based on whether the loaded value in the register is "R1>16". In other words, the result of the branch instruction "X" depends on the data value of the array element at address A[i] stored in the memory, and therefore, the branch instruction "X" is called a memory-dependent branch instruction. The branch instruction "X" is difficult to predict using a conventional branch predictor because the data value at address "A[i]" in the memory is not easy to predict in the case of poor correlation with the above-mentioned context information (such as global and / or local branch history, branch path history, branch target history, etc.).

[0008] Program instructions involving memory-dependent branch instructions may be encountered in various other instruction sequences / applications.Therefore, there is a need in the art to overcome the limitations of conventional branch predictors and to be able to accurately predict even the above-mentioned types of difficult-to-predict branch instructions. Summary of the invention

[0009] Exemplary aspects of the invention relate to systems and methods for branch prediction for hard-to-predict branch instructions, such as memory dependent branch instructions.

[0010] For example, one exemplary aspect relates to a branch prediction method in a processor, the method comprising: for a branch instruction fetched by the processor for execution, indexing a branch identification (ID) table based on a function of a program counter (PC) value of the branch instruction, wherein the branch ID table includes one or more entries, each entry including at least a tag field and a precision counter. For a tag hit at an entry of the branch ID table indexed by the PC value, wherein the tag field of the entry matches the PC value, if the value of the precision counter is greater than or equal to zero, the method comprises selecting a prediction counter from a prediction counter pool comprising a plurality of prediction counters, wherein each of the plurality of prediction counters in the prediction counter pool comprises at least a corresponding confidence value and a prediction value, wherein the selection is based on a function of the PC value and a load path history, and wherein the load path history comprises information from a previous load instruction executed by the processor. The method further comprises: if the confidence value of the selected prediction counter is greater than zero, assigning a memory-dependent branch prediction of the branch instruction to the prediction value of the selected prediction counter.

[0011] Another exemplary aspect relates to an apparatus comprising a processor configured to execute instructions, wherein the processor comprises at least a branch predictor based on a load path history. The branch predictor based on the load path history comprises: a branch identification (ID) table comprising one or more entries, each entry comprising at least a tag field and a precision counter; and a prediction counter pool comprising a plurality of prediction counters. For a branch instruction fetched by the processor for execution, the branch identification (ID) table is indexed based on a function of a program counter (PC) value of the branch instruction. For a tag hit at an entry of the branch ID table indexed by the PC value, wherein the tag field of the entry matches the PC value, if the value of the precision counter is greater than or equal to zero, a prediction counter is selected from the prediction counter pool, wherein each of the plurality of prediction counters in the prediction counter pool comprises at least a corresponding confidence value and a prediction value, wherein the prediction counter is selected based on a function of the PC value and a load path history, wherein the load path history comprises information from a previous load instruction executed by the processor. The branch predictor based on the load path history is configured to: if the confidence value of the selected prediction counter is greater than zero, assign a memory-dependent branch prediction of the branch instruction to the prediction value of the selected prediction counter.

[0012] Another exemplary aspect relates to an apparatus comprising a component for executing instructions; and a component for storing one or more entries for predicting memory-dependent branch instructions, each entry comprising at least a component for storing a tag value and a component for storing a precision value for the entry, wherein for a branch instruction fetched for execution by the component for executing instructions, the component for storing the entry is indexed based on a function of a program counter (PC) value of the branch instruction. The apparatus also includes: a plurality of components for indicating prediction values ​​and associated confidence values; wherein for a tag hit at an entry of a branch ID table indexed by the PC value, wherein the tag value matches the PC value, if the precision value is greater than or equal to zero, a component for selecting one of the plurality of components for indicating based on a function of the PC value and a load path history, wherein the load path history includes information from previous load instructions executed by the component for executing. The apparatus also includes a component for assigning a memory-dependent branch prediction for the branch instruction as the prediction value of the selected component for indicating if the associated confidence value is greater than zero.

[0013] Another exemplary aspect relates to a non-transitory computer-readable storage medium including code that, when executed by a computer, causes the computer to perform branch prediction in a processor, the non-transitory computer-readable storage medium including: for a branch instruction fetched by the processor for execution, code for indexing a branch identification (ID) table based on a function of a program counter (PC) value of the branch instruction, wherein the branch ID table includes one or more entries, each entry including at least a tag field and a precision counter. For a tag hit at an entry of the branch ID table indexed by the PC value, wherein the tag field of the entry matches the PC value, if the value of the precision counter is greater than or equal to zero, code for selecting a prediction counter from a prediction counter pool including a plurality of prediction counters is provided, wherein each of the plurality of prediction counters in the prediction counter pool includes at least a corresponding confidence value and a prediction value, wherein the code for selecting is based on a function of the PC value and a load path history, wherein the load path history includes information from previous load instructions executed by the processor. Also included is code for assigning a memory-dependent branch prediction of the branch instruction to the prediction value of the selected prediction counter if the confidence value of the selected prediction counter is greater than zero. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are presented to aid in describing various aspects of the invention and are provided solely for illustration of the various aspects and not limitation of the invention.

[0015] Figure 1 An example instruction sequence is shown, which shows a memory-dependent branch instruction.

[0016] Figure 2 A load path history based branch predictor in accordance with aspects of the present disclosure is shown.

[0017] Figure 3 A processing system incorporating an exemplary load path history based branch predictor in accordance with aspects of the present disclosure is shown.

[0018] Figure 4 A branch prediction method using an exemplary load path history based branch predictor according to aspects of the present disclosure is shown.

[0019] Figure 5 An exemplary computing device is depicted in which an aspect of the present disclosure may be advantageously employed. DETAILED DESCRIPTION

[0020] Aspects of the present invention are disclosed in the following description and related drawings relating to specific aspects of the present invention. Alternative aspects may be designed without departing from the scope of the present invention. In addition, well-known elements of the present invention will not be described in detail or will be omitted to avoid blurring the relevant details of the present invention.

[0021] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects. Likewise, the term "aspects of the invention" does not require that all aspects of the invention include the discussed feature, advantage, or mode of operation.

[0022] The terms used herein are for the purpose of describing particular aspects only and are not intended to limit the various aspects of the present invention. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be further understood that when used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0023] In addition, many aspects are described in terms of sequences of actions to be performed, for example, by elements of a computing device. It will be appreciated that the various actions described herein may be performed by specific circuits (e.g., application specific integrated circuits (ASICs)), by program instructions executed by one or more processors, or by a combination of the two. In addition, it may be considered that the sequences of actions described herein are fully embodied in any form of computer-readable storage medium having stored therein a corresponding set of computer instructions, which, when executed, causes an associated processor to perform the functions described herein. Therefore, various aspects of the present invention may be embodied in many different forms, all of which are considered to be within the scope of the claimed subject matter. In addition, for each aspect described herein, the corresponding form of any such aspect may be described herein as, for example, "logic configured to perform the described actions."

[0024] Various aspects of the present disclosure relate to improving performance related to processing difficult-to-predict branch instructions such as memory-related branch instructions. More specifically, exemplary aspects relate to using exemplary context information (referred to herein as "load path history") as a proxy for memory addresses in branch predictions for memory-related branch instructions. The load path history of a load instruction may include information from a previous load instruction. An exemplary load path history may be constructed by moving the least significant N non-zero bits (i.e., bits 2 to N+1, where N is a positive integer) of each program counter (PC) value of a previous load instruction into an exemplary load path history register. By using the load path history, rather than the memory address, prediction of memory-related branch instructions may be performed early in the instruction pipeline of a processor (e.g., in the fetch stage). According to exemplary aspects herein, an exemplary covering branch predictor is also disclosed that may be indexed and tagged using a hash of the PC of a branch instruction, a load path history, or both.

[0025] As background, it is recognized herein that the branch outcome of a memory dependent branch instruction may be related to the memory address of one or more load instructions that feed the branch instruction (e.g., a load instruction loads register "R5" which is located in Figure 1 In another example, a code snippet with three instructions enumerated by numbers 1-3 is described in the following paragraph, where in instruction 1, a load instruction loads a value from a memory address ADDR into a register R1; in instruction 2, the loaded value in register R1 is compared with a value "0"; and in instruction 3, a branch on not equal (BNE) instruction branches in a direction set by a value LABEL. The branch instruction BNE depends on the value loaded from the memory address (ADDR) and is therefore a memory-dependent branch instruction.

[0026] 1. Load R1, MEM[ADDR]

[0027] 2.CMP R1, 0x0

[0028] 3.BNE tag

[0029] In a known method for predicting a BNE instruction, a memory-dependent branch instruction depends on a data value at a memory address ADDR, and the prediction of the branch instruction may be based on the memory address ADDR. For example, a branch predictor may use the memory address ADDR to index a prediction table containing predictions, read out the index prediction, and use the index prediction, for example, to replace a default branch prediction provided by a conventional branch predictor that depends on the aforementioned conventional context information. However, since the memory address ADDR is used to index the prediction table, the branch prediction process using this method can only be started after the memory address ADDR becomes available, which may be delayed in the instruction pipeline (e.g., at the address generation stage "AGEN" in the back end of the conventional instruction pipeline). In addition, complex tracking logic may be relied upon to detect a specific instance of a load instruction that depends on loading data from the memory address ADDR. These shortcomings prevent the known methods from delivering valid predictions early enough in the pipeline to avoid wasting a lot of resources due to executing the wrong path instructions.

[0030] To overcome the above disadvantages, in an exemplary aspect, as described above, load path history is used to predict memory-dependent branch instructions (e.g., BNE) rather than relying on a memory address (e.g., ADDR) from which a load instruction providing the memory-dependent branch instruction loads its data.

[0031] Reference now Figure 2 , an exemplary branch predictor that uses load path history to predict memory-related branch instructions is shown, which exemplary branch predictor is referred to as a load path history-based predictor (LdPHistPred) 200 hereinafter. The components of the load path history-based predictor 200 are first briefly enumerated, and then the operation and interaction of these components are discussed in detail. Thus, at a high level, the load path history-based predictor 200 includes a branch identification (ID) table 201 and N prediction counters in a prediction counter pool 210a-n (where N is a positive integer and is greater than or equal to 1).

[0032] In one implementation, the branch ID table 201 may be a direct-mapped table, wherein each of the one or more entries of the branch ID table 201 may be indexed using the PC of the branch instruction and also tagged with the PC of the branch instruction, as shown in a tag field 202 in the branch ID table 201. In addition to the tag field 202, each entry of the branch ID table 201 also includes two timestamps, shown in the last hit timestamp 204 and last prediction timestamp 206 fields, respectively. Each entry also includes a signed precision counter 208 that increments when a prediction made using the entry is correct and decrements when the prediction is incorrect. In one implementation, each of the last hit timestamp 204, the last prediction timestamp 206, and the precision counter 208 may be N bits wide.

[0033] The N prediction counters in the prediction counter pool 210a-n may each include, for example, a 2-bit prediction counter having a bit 0 and a bit 1, where bit 0 indicates a confidence and bit 1 indicates a prediction direction made by the corresponding 2-bit prediction counter. A function such as a hash of a branch instruction PC may be used to select a particular prediction counter in the prediction counter pool 210a-n to be used for an entry indexed by a branch instruction PC.

[0034] Additionally, the load path history based predictor 200 may be enhanced with two tables that track the performance of the load path history based predictor 200 for different branch instruction PCs.

[0035] The first of the two lists is called the golden list, which stores the PCs of branch instructions for which the load path history-based predictor 200 performs well (described further). If the value of the signed precision counter 208 is much greater than 0 (or "precision >> 0"), the PC of the branch instruction may be inserted into the golden list when the associated entry is evicted from the branch ID table 201.

[0036] The second of the two lists, referred to as the blacklist, stores the PCs of branch instructions for which the load path history-based predictor 200 performs poorly. If the value of the signed precision counter 208 is much less than 0 (or "precision << 0"), the branch instruction is inserted into the blacklist when the associated entry is evicted from the branch ID table 201.

[0037] Now refer to Figure 2 Describes a process for predicting the direction of a branch instruction, such as a hard-to-predict memory-dependent branch instruction. For a branch instruction fetched by a processor (an example implementation of such a processor will be described in Figure 3), the PC of the branch instruction (or a function or hash thereof) may be used to index the branch ID table 201. As previously described, the load path history for a load instruction may include information from previous load instructions. An exemplary load path history may be constructed by moving the least significant N non-zero bits (e.g., bits 2 to N+1) of each program counter (PC) value of a previous load instruction into an exemplary load path history register 220.

[0038] As will be recalled, branch ID table 201 includes a tag field 202 for each of its entries, where, for example, if at an index entry using a hash of the branch instruction's PC, tag field 202 matches the branch instruction's PC, a tag hit is said to have occurred; otherwise, if there is a mismatch, a tag miss is said to have occurred. Figure 2 , entry 201x is representatively shown as an index entry to facilitate the following discussion.

[0039] In the event of a tag hit for entry 201x, the last hit timestamp 204 is updated with the time at which the tag hit occurred (e.g., derived from a clock, not shown). In addition, the precision counter 208 of entry 201x is consulted, and if the value of the precision counter 208 is >= 0, the corresponding prediction counter of the prediction counter pool 210a-n is read out. The corresponding prediction counter of entry 201x can be selected using a hash of the PC of the branch instruction and the current value of the load path history register 220.

[0040] If the value of the prediction counter at the selected prediction counter is confident (e.g., the confidence bit of the selected prediction counter is set), the value obtained from the prediction counter is used to predict the branch instruction. In this regard, the default branch predictor that may be present in a processor with conventional branch prediction may be overridden, and the prediction obtained from the above process of consulting the load path history based predictor 200 may be used instead. Once the prediction is obtained, the last prediction timestamp 206 of the entry 201x in the branch ID table 201 is also updated with the time at which the prediction was obtained.

[0041] On the other hand, if there is a tag miss at entry 201x, the load path history based predictor 200 is not used to predict the branch instruction; a default branch predictor may be used.

[0042] By using the load path history, the load instructions that will load data values ​​from the memory addresses, and the data values ​​evaluated by the memory-related branch instructions in the manner described above, the direction of the memory-related branch instructions can be accurately predicted, for example, if there is a label hit for the memory-related branch instruction in the branch ID table 201. The next section discusses how to train the load path history-based predictor 200 to provide such accurate predictions for memory-related branch instructions.

[0043] In an exemplary aspect, if the default branch predictor predicts incorrectly, or if the load path history based predictor 200 receives a tag hit at prediction time, training of the load path history based predictor 200 may be initiated. Thus, there are two scenarios for training the load path history based predictor 200: in the case of a tag hit of the branch ID table 201 or in the case of a tag miss, which will be discussed in turn below.

[0044] In the first training process, in the case of a tag hit in the branch ID table 201, the precision counter 208 can be updated as follows: if the prediction made using the load path history-based predictor 200 (for example, obtained from the corresponding prediction counter of the N prediction counters in the prediction counter pool 210a-n) is correct, that is, if the evaluation result / direction of the branch instruction matches the prediction made using the load path history-based predictor 200, then the precision counter is incremented; otherwise, in the case of an incorrect prediction, the precision counter 208 can be decremented.

[0045] The appropriately selected prediction counters in the prediction counter pool 210A-N (e.g., selected using a hash of the PC of the branch instruction and the load path history) can be updated as follows. If the prediction bits of the selected prediction counter (e.g., where a value of "1" indicates taken and a value of "0" indicates not taken) match the evaluation result / direction of the branch instruction, the confidence bits in the prediction counter are set to a confident value (e.g., a value of "1"); otherwise, if the prediction bits of the selected prediction counter do not match the evaluation result / direction of the branch instruction, the confidence bits are reset to a non-confident value (e.g., a value of "0") and the prediction bits are set to the result of the matching branch instruction.

[0046] In the second training process, when the tag in the branch ID table 201 misses, an attempt is made to allocate an entry in the branch ID table 201 (note that the allocation and replacement of entries in the branch ID table 201 will be discussed in more detail in the following sections). If the allocation attempt is successful, the allocation entry of the branch ID table 201 can be updated by setting the corresponding tag field 202 to the PC of the branch instruction and appropriately updating the last hit timestamp 204 and the last prediction timestamp 206 with the corresponding timestamps as described above. The precision counter 208 can be set to "0" and the corresponding prediction counters of the prediction counter pool 210a-n can be set in a manner consistent with the description above for a tag hit in the branch ID table 201.

[0047] Allocation and replacement of entries of branch ID table 201 will now be discussed in more detail. Entries in branch ID table 201 may be allocated at a certain point in time (the current time as shown by the local clock) if one of the following conditions is met, where X is a selectable large number, such as 16K.

[0048] 1. Condition 1: The entry of the branch ID table 201 indexed by the PC of the branch instruction shows low activity, for example, as defined by the last hit timestamp 204 (or hitTime)+X, which is less than the current time (or "hitTime+1*X"). <currentTime”)

[0049] 2. Condition 2: The index entry shows that the low reward, for example defined by the last predicted timestamp 206 (or predTime) + 8*X, is less than the current time (or "predTime + 8*X < currentTime").

[0050] 3. Condition 3: the index entry shows bad precision, for example as defined by the value of precision counter 208, less than zero (or "precision < 0"); or

[0051] 4. Condition 4: The branch instruction being attempted is on the previously defined golden list

[0052] Note herein that if a branch instruction is on the blacklist, no allocation is performed for the branch instruction in the branch ID table 201. The foregoing heuristics or conditions provide protection against situations where, for example, the instruction footprint is too large (thus, condition 1 is satisfied, where the PC of a particular branch instruction may show low activity in the instruction sequence), the data value stored at the memory location changes (which indicates that using the load path history to predict the data value may not be accurate), or the allocation entry is no longer needed.

[0053] Reference now Figure 3, an exemplary processing system 300 in which various aspects of the present disclosure may be employed is shown. The processing system 300 is shown to include a processor 310 coupled to an instruction cache 308. Although not shown in this view, additional components may also be present, such as functional units, input / output units, interface structures, memory structures, etc., but since they may not be closely related to the present disclosure, these additional components are not explicitly identified or described. As shown, the processor 310 may be configured to receive instructions from the instruction cache 308 and execute the instructions using, for example, an execution pipeline 312. The execution pipeline 312 may be configured to include one or more pipeline stages for performing instruction extraction (IF), instruction decoding (ID), one or more execution stages (EX1, EX2, ...) and write-back (WB) operations, as known in the art. Representatively, branch instructions are shown in the instruction cache 308 and are identified as branch instructions 302.

[0054] In an exemplary implementation, the branch instruction 302 may have a corresponding address or program counter (PC) value 302pc. The processor 310 is generally shown as including a default conventional branch predictor 306, which may also include a branch prediction unit (such as a history table including a history of behavior of previous branch instructions), a state machine (such as a branch prediction counter), etc., as known in the art. In other words, the branch predictor 306 can use the conventional context information discussed above to predict branch instructions that are not difficult-to-predict branch instructions. When the processor 310 fetches the branch instruction 302 for execution, for a conventional branch instruction, logic such as a hash 305 (e.g., implementing an XOR function) can access the branch predictor 306 using the address or PC value 302pc and / or other information from the branch instruction 302 and retrieve a prediction 307, which represents the default prediction of the branch instruction 302.

[0055] In an exemplary aspect, the processor 310 also includes a load path history based predictor 200 (described above with reference to Figure 2 describes an example implementation thereof). Figure 2As discussed, the branch ID table 201 of the load path history based predictor 200 may be indexed using a hash of the PC value 302pc of the branch instruction 302 (e.g., obtained from logic such as hash 304) and the load path history from the load path history register 220. The output of the load path history based predictor 200 obtained using the above process is shown as a memory-dependent branch prediction 322, but may generally represent the branch prediction of the branch predictor 306 for any difficult-to-predict branch instruction that is covered by it. For example, if the load path history based predictor 200 is used to predict a branch instruction, the memory-dependent branch prediction 322 may be used as the prediction for the branch instruction 302 in place of the prediction 307 provided by the branch predictor 306. For example, as may be appreciated, since the memory-dependent branch prediction 322 may be obtained based on the load path history register 220 and the branch instruction PC 302pc, the memory-dependent branch prediction 322 may be available very early in the execution pipeline 312 (e.g., at the instruction fetch IF stage).

[0056] continue Figure 3 , a branch instruction 302 may be speculatively executed in an execution pipeline 312 (based on a direction derived from a prediction 307 or a memory-dependent branch prediction 322). After traversing one or more pipeline states, the actual evaluation of the branch instruction 302 will be known, and this is shown as an evaluation 313. The evaluation 313 is compared to the prediction (i.e., the prediction 307 or the memory-dependent branch prediction 322, as the case may be) of the predictively executed branch instruction 302 in a prediction check block 314 to determine whether the evaluation 313 matches the direction speculatively executed, or in other words, to determine whether the branch instruction 302 was correctly predicted or mispredicted). In an example implementation, a bus 315 includes information including the correct evaluation 313 (taken / not taken) and whether the branch instruction 302 was correctly predicted or mispredicted. The information on the bus 315 may be provided to the load path history based predictor 200 and the default branch predictor 306. For example, updating the precision counter 208 during the above training of the branch ID table 201 may use the information on the bus 315 to determine whether the evaluation result / direction of the branch instruction (i.e., the correct evaluation 313) matches the prediction made using the load path history-based predictor 200 (i.e., the memory-dependent branch prediction 322). Figure 2 In a manner consistent with the description of the load path history based predictor 200 , the load path history based predictor 200 is incorporated into the processing system 300 .

[0057] Therefore, it should be understood that the exemplary aspects include various methods for performing the processes, functions and / or algorithms disclosed herein. For example, Figure 4(and the following Figure 2-3 ) shows a branch prediction method 400 in a processor (eg, processor 310).

[0058] In block 402, for a branch instruction (e.g., branch instruction 302) fetched by a processor for execution, a branch identification (ID) table (e.g., branch ID table 201) is indexed based on a function of a program counter (PC) value (e.g., 302pc) of the branch instruction, wherein the branch ID table includes one or more entries, each entry (e.g., entry 201x) including at least a tag field (e.g., tag field 202) and a precision counter (e.g., precision counter 208).

[0059] In block 404, for a tag hit, where the tag field at the entry of the branch ID table corresponding to the index (e.g., entry 201x) matches the PC value, and if the value of the precision counter is greater than or equal to zero, a prediction counter is selected from a prediction counter pool (e.g., prediction counter pools 210a-n) comprising a plurality of prediction counters, where each prediction counter of the plurality of prediction counters in the prediction counter pool includes at least a corresponding confidence value (e.g., bit 0) and a prediction value (e.g., bit 1), where the selection is based on a function of the PC value and a load path history (e.g., from load path history register 220), where the load path history includes information from previous load instructions executed by the processor.

[0060] Block 406 includes assigning a memory-dependent branch prediction (eg, prediction 322 ) for the branch instruction as the prediction value for the selected prediction counter if the confidence value for the selected prediction counter is greater than zero.

[0061] Now about Figure 5 Example devices in which example aspects of the present disclosure may be utilized are discussed. Figure 5 5 shows a block diagram of a computing device 500. The computing device 500 may correspond to Figure 3 An exemplary implementation of the processing system 300, wherein the processor 310 may include Figure 2 The load path history based predictor 200 is shown in this view as having a branch ID table 201, a prediction counter pool 210a-n and a load path history register 220, and the reference Figure 2-3 Other details shown and described are omitted for clarity.A memory 510 is also shown in communication with the processor 310.

[0062] Figure 5 Also shown is a display controller 526 coupled to the processor 310 and the display 528. In some cases, the computing device 500 can be used for wireless communication, and Figure 5Also shown in dashed lines are optional blocks, such as a coder / decoder (CODEC) 534 (e.g., an audio and / or voice CODEC) coupled to the processor 310, and to which a speaker 536 and a microphone 538 may be coupled, and a wireless antenna 542 coupled to a wireless controller 540, which is coupled to the processor 310. Where one or more of these optional blocks are present, in certain aspects, the processor 310, display controller 526, memory 510, and wireless controller 540 are included in a system-in-package or system-on-chip device 522.

[0063] Thus, in certain aspects, input device 530 and power supply 544 are coupled to system-on-chip device 522. Additionally, in certain aspects, as Figure 5 As shown, with the presence of one or more optional blocks, the display 528, input device 530, speaker 536, microphone 538, wireless antenna 542, and power supply 544 are external to the system-on-chip device 522. However, each of the display 528, input device 530, speaker 536, microphone 538, wireless antenna 542, and power supply 544 may be coupled to a component of the system-on-chip device 522, such as an interface or controller.

[0064] It should be noted that although Figure 5 The computing device, processor 310, and memory 510 are depicted generally, but they may also be integrated into a set-top box, server, music player, video player, entertainment unit, navigation device, personal digital assistant (PDA), fixed location data unit, computer, portable computer, tablet computer, communication device, mobile phone, or other similar device.

[0065] In addition, it should be understood that various aspects of the present disclosure may also include an apparatus (e.g., processing system 300) comprising: a component for executing instructions (e.g., processor 310); a component for storing one or more entries for predicting memory-related branch instructions (e.g., branch ID table 201), each entry comprising at least a component for storing a tag value (e.g., a tag field) and a component for storing a precision value of the entry (e.g., precision counter 208), wherein for a branch instruction fetched for execution by the component for executing instructions, the component for storing the entry is indexed based on a function of a program counter (PC) value of the branch instruction (e.g., PC value 302pc of branch instruction 302). The apparatus may also include a plurality of components (e.g., prediction counter pools 210a-n) for indicating prediction values ​​(e.g., bit 0) and associated confidence values ​​(e.g., bit 1); wherein for a tag hit at an entry of a branch ID table indexed by a PC value, where the tag value of the entry matches the PC value, if the precision value is greater than or equal to zero, components for selecting one of the plurality of components for indicating based on a function (e.g., hash 304) of the PC value and a load path history (e.g., from load path history register 220), where the load path history includes information from previous load instructions executed by the component for executing the instruction. The apparatus also includes components (e.g., load path history-based predictor 200) for assigning a memory-dependent branch prediction for the branch instruction as the prediction value of the selected component for indicating if the associated confidence value is greater than zero.

[0066] It should be understood by those skilled in the art that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the specification above may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0067] In addition, it will be appreciated by those skilled in the art that the various illustrative logic blocks, modules, circuits and algorithm steps described in conjunction with the various aspects disclosed herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, frames, modules, circuits and steps have been generally described above in terms of their functions. Whether this functionality is implemented as hardware or software depends on specific applications and the design constraints imposed on the entire system. The technician can implement the described functions in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the scope of the present invention.

[0068] The methods, sequences and / or algorithms described in conjunction with the various aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Alternatively, the storage medium may be integral to the processor.

[0069] Thus, one aspect of the invention may include a computer readable medium embodying a method for predicting memory related branch instructions.Thus, the invention is not limited to the examples shown, and any means for performing the functions described herein are included in aspects of the invention.

[0070] Although the foregoing disclosure shows illustrative aspects of the present invention, it should be noted that various changes and modifications may be made herein without departing from the scope of the present invention as defined by the appended claims. The functions, steps and / or actions of the method claims according to the various aspects of the present invention described herein do not need to be performed in any particular order. In addition, although the elements of the present invention may be described or claimed in the singular, plural forms are contemplated unless the limitation to the singular form is explicitly indicated.

Claims

1. A branch prediction method in a processor, the method comprising: For a branch instruction fetched by the processor for execution, indexing a branch identification table based on a function of a program counter PC value of the branch instruction, wherein the branch identification table includes one or more entries, each entry including at least a tag field and a precision counter; for a tag hit at an entry of the branch identification table indexed by the PC value, wherein the tag field of the entry matches the PC value, if the value of the precision counter is greater than or equal to zero, selecting a prediction counter from a prediction counter pool comprising a plurality of prediction counters, wherein each prediction counter of the plurality of prediction counters in the prediction counter pool comprises at least a corresponding confidence value and a prediction value, wherein said selecting is based on a function of said PC value and a load path history, wherein the load path history includes information from previous load instructions executed by the processor; as well as If the confidence value of the selected prediction counter is greater than zero, a memory dependent branch prediction for the branch instruction is assigned as the prediction value of the selected prediction counter.

2. The method according to claim 1, further comprising: The branch instruction is speculatively executed based on the memory dependent branch prediction.

3. The method according to claim 2, comprising: Overlaying a branch prediction from a branch predictor of the processor, the branch predictor providing a branch prediction based on context information, the context information comprising one or more of a global branch history, a local branch history, a branch path history, or a branch target history.

4. The method of claim 1, wherein the branch instruction is a memory dependent branch instruction whose direction depends on a value loaded from a memory address by a previous load instruction.

5. The method according to claim 1, comprising: The load path history is determined from a load path register formed by shifting in one or more least significant bits of a PC value of a previous load instruction. 6 . The method of claim 1 , wherein each prediction counter of the plurality of prediction counters in the prediction counter pool is a 2-bit counter, wherein a first bit comprises the confidence value and a second bit comprises the prediction value.

7. The method of claim 1, wherein each entry of the branch identification table further comprises a last hit timestamp and a last prediction timestamp, and wherein for the tag hit, the last hit timestamp is updated with the time when the tag hit occurs.

8. The method of claim 7 , wherein upon obtaining the prediction value of the selected prediction counter used to assign the memory-dependent branch prediction of the branch instruction as the prediction value of the selected prediction counter, the last prediction timestamp is updated with the time at which the prediction value of the selected prediction counter was obtained.

9. The method according to claim 8, further comprising: For the tag hit, if the memory-dependent branch prediction of the branch instruction matches a correct direction for a subsequent evaluation of the branch instruction, the precision counter is incremented and the confidence value of the selected prediction counter is set to a confident value.

10. The method according to claim 9, further comprising: For the tag hit, if the memory-dependent branch prediction of the branch instruction does not match the correct direction of a subsequent evaluation of the branch instruction, decrementing the precision counter, resetting the confidence value of the selected prediction counter to a non-confident value, and updating the prediction value of the selected prediction counter to match the correct direction.

11. The method of claim 8, wherein for a tag miss, wherein the tag field at the entry of the branch identification table corresponding to the index does not match the PC value of the branch instruction, the branch instruction is predicted based on a branch prediction obtained from a branch predictor of the processor, the branch predictor providing a branch prediction based on context information, the context information comprising one or more of a global branch history, a local branch history, a branch path history, or a branch target history.

12. The method according to claim 11, further comprising: The branch instructions are assigned the same or different entries of the branch identification table based on one or more heuristics used to determine the assignment in the branch identification table.

13. The method of claim 12, wherein the one or more heuristics are based on one or more of: a size of a footprint of instructions executed by the processor, a data value on which the branch instruction, being a memory-dependent branch instruction, depends, or a current usage of entries in the branch identification table.

14. The method according to claim 13, wherein at least a golden list and a black list are associated with the branch identification table, wherein upon eviction from the branch identification table, PCs of branch instructions for which memory-dependent branch predictions have high performance are inserted into the golden list, and PCs of branch instructions for which memory-dependent branch predictions have low performance are inserted into the black list.

15. The method of claim 14, wherein the one or more heuristics are determined based on one or more of: the last hit timestamp, the last prediction timestamp, the precision counter value, and the presence of the PC value in the blacklist or the gold list.

16. An apparatus comprising: a processor configured to execute instructions, wherein the processor includes at least a branch predictor based on a load path history, The branch predictor based on load path history includes: A branch identification table, including one or more entries, each entry including at least a tag field and a precision counter; and A prediction counter pool, including a plurality of prediction counters; wherein for a branch instruction fetched by the processor for execution, the branch identification table is indexed based on a function of a program counter PC value of the branch instruction; for a tag hit at an entry of the branch identification table indexed by the PC value, where the tag field of the entry matches the PC value, if the value of the precision counter is greater than or equal to zero, selecting a prediction counter from the prediction counter pool, wherein each prediction counter of the plurality of prediction counters in the prediction counter pool comprises at least a corresponding confidence value and a prediction value, wherein the prediction counter is selected based on a function of the PC value and a load path history, wherein the load path history includes information from previous load instructions executed by the processor; and The load path history based branch predictor is configured to assign a memory dependent branch prediction of the branch instruction as the prediction value of the selected prediction counter if the confidence value of the selected prediction counter is greater than zero.

17. The apparatus of claim 16, wherein the processor is configured to speculatively execute the branch instruction based on the memory dependent branch prediction.

18. The apparatus of claim 17, wherein the processor further comprises a branch predictor configured to: provide branch predictions based on context information, the context information comprising one or more of a global branch history, a local branch history, a branch path history, or a branch target history, and Wherein the processor is configured to override a branch prediction from the branch predictor to speculatively execute the branch instruction based on the memory dependent branch prediction.

19. The apparatus of claim 16, wherein the branch instruction is a memory dependent branch instruction whose direction depends on a value loaded from a memory address by a previous load instruction.

20. The apparatus of claim 16, wherein the load path history based branch predictor further comprises a load path register comprising one or more least significant bits of a PC value of a previous load instruction, wherein the load path register is configured to provide the load path history.

21. The apparatus of claim 16, wherein each prediction counter of the plurality of prediction counters in the prediction counter pool is a 2-bit counter, wherein a first bit comprises the confidence value and a second bit comprises the prediction value.

22. The apparatus of claim 16, wherein each entry of the branch identification table further comprises a last hit timestamp and a last prediction timestamp, and wherein for the tag hit, the last hit timestamp is updated with the time at which the tag hit occurs.

23. The apparatus of claim 22, wherein the last prediction timestamp is updated with a time at which the prediction value of the selected prediction counter is obtained to be assigned as the memory-dependent branch prediction of the branch instruction.

24. The apparatus of claim 22, wherein for the tag hit, if the memory-dependent branch prediction of the branch instruction matches a correct direction for a subsequent evaluation of the branch instruction, the precision counter is incremented and the confidence value of the selected prediction counter is set to a confident value.

25. The apparatus of claim 24, wherein for the tag hit, if the memory-dependent branch prediction of the branch instruction does not match a correct direction for a subsequent evaluation of the branch instruction, the precision counter is decremented, the confidence value of the selected prediction counter is reset to a non-confident value, and the prediction value of the selected prediction counter is updated to match the correct direction.

26. The apparatus of claim 22, wherein the processor further comprises a branch predictor configured to provide branch predictions based on context information, the context information comprising one or more of a global branch history, a local branch history, a branch path history, or a branch target history, Wherein for a tag miss, wherein the tag field at the entry of the branch identification table corresponding to the index does not match the PC value of the branch instruction, the processor is configured to: predict the branch instruction based on a branch prediction obtained from the branch predictor.

27. The apparatus of claim 26, wherein the same or different entries of the branch identification table are assigned for the branch instruction based on one or more heuristics for determining assignments in the branch identification table.

28. The apparatus of claim 27, wherein the one or more heuristics are based on one or more of: a size of a footprint of instructions executed by the processor, a data value on which the branch instruction, being a memory-dependent branch instruction, depends, or a current usage of entries in the branch identification table.

29. The apparatus of claim 28, wherein the load path history-based branch predictor further comprises at least a golden list and a black list associated with the branch identification table, wherein upon eviction from the branch identification table, a PC of a branch instruction for which a memory-dependent branch prediction has a high performance is inserted into the golden list, and a PC of a branch instruction for which a memory-dependent branch prediction has a low performance is inserted into the black list.

30. The apparatus of claim 29, wherein the one or more heuristics are determined based on one or more of: the last hit timestamp, the last prediction timestamp, the precision counter value, and the presence of the PC value in the blacklist or the gold list.

31. The apparatus of claim 16, integrated into a device selected from the group consisting of: a set-top box, a server, a music player, a video player, a navigation device, a personal digital assistant (PDA), a fixed location data unit, a computer, a communication device.

32. An apparatus comprising: A component for executing instructions; means for storing one or more entries for predicting memory-dependent branch instructions, each entry comprising at least means for storing a tag value and means for storing a precision value for said entry, wherein for a branch instruction fetched for execution by said means for executing instructions, said means for storing said one or more entries is indexed based on a function of a program counter PC value of said branch instruction; a plurality of components for indicating predicted values ​​and associated confidence values; wherein for a tag hit at an entry of the branch identification table indexed by the PC value, wherein the tag value matches the PC value, if the precision value is greater than or equal to zero, selecting a component of one of the plurality of components for indicating based on a function of the PC value and a load path history, wherein the load path history includes information from a previous load instruction executed by the component for executing instructions; as well as Means for assigning a memory dependent branch prediction for the branch instruction as the prediction value for the selected indicated means if the associated confidence value is greater than zero.

33. A non-transitory computer-readable storage medium comprising code, which when executed by a computer causes the computer to perform branch prediction in a processor, the non-transitory computer-readable storage medium comprising: For a branch instruction fetched by the processor for execution, code for indexing a branch identification table based on a function of a program counter (PC) value of the branch instruction, wherein the branch identification table includes one or more entries, each entry including at least a tag field and a precision counter; for a tag hit at an entry of the branch identification table indexed by the PC value, wherein the tag field of the entry matches the PC value, if the value of the precision counter is greater than or equal to zero, code for selecting a prediction counter from a prediction counter pool comprising a plurality of prediction counters, wherein each prediction counter of the plurality of prediction counters in the prediction counter pool comprises at least a corresponding confidence value and a prediction value, wherein the code for selecting is based on a function of the PC value and a load path history, wherein the load path history includes information from previous load instructions executed by the processor; as well as Code for assigning a memory dependent branch prediction for the branch instruction as the prediction value for the selected prediction counter if the confidence value for the selected prediction counter is greater than zero.

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