Local optimization method and system for quantum circuits

Abstract

A technique for facilitating local optimization of a quantum circuit is provided. In one example, a computer-implemented method includes: applying respective weights to a plurality of matrix elements of a first matrix corresponding to the quantum circuit according to respective numbers of quantum gates between respective pairs of qubits in the quantum circuit by a device operably coupled to a processor; transforming the first matrix into a second matrix based on respective weights of the matrix elements by the device; and permuting corresponding qubits in the quantum circuit according to the second matrix by the device, thereby obtaining a permuted quantum circuit.

Description

Background Art

[0001] The present disclosure relates to quantum computing and, more particularly, to quantum circuit design and optimization.

[0002] As computer technology advances and conventional computing devices decrease in physical size, there has been growing interest in quantum computing as a technique by which computing technology can continue to advance beyond the physical limitations of traditional (classical) computers.

[0003] Quantum computing algorithms can be designed by first constructing a quantum circuit, which includes corresponding quantum bits (qubits) and corresponding quantum gates that facilitate interactions between pairs of qubits, and then mapping the constructed quantum circuit onto a quantum computing architecture. In order to execute quantum algorithms on current and near-term hardware, it is desirable to efficiently map quantum circuits onto quantum devices that may have limited local physical connections.

[0004] The efficiency of compiling a quantum algorithm onto a particular hardware architecture can be measured, for example, by the gate count and depth of the compiled algorithm. As described in U.S. Patent Application Publication No. 2006 / 0123363, "METHOD AND APPARATUS FOR AUTOMATIC DESIGN OF QUANTUMCIRCUITS" by Williams et al., the gate count of quantum circuits can be reduced by "compactification techniques". Paragraph 83 of Williams et al. states the following:

[0005] One embodiment applies a deterministic circuit reduction operator to find patterns between subcircuits and / or gates that can be eliminated or rewritten to more compact gates. Another embodiment computes a circuit for a particular unitary matrix U, and also computes a circuit for the inverse matrix of U. The two computed circuits are then checked to determine which is smaller and that circuit is used. Another embodiment is referred to as randomized compaction, which uses a heuristic approach to arrive at a compact circuit.

[0006] In addition to optimizing gate counts associated with quantum circuits, there is a need in the art for techniques that can optimize circuits with locally interacting hardware (eg, leaving the circuits substantially unmodified). Summary of the invention

[0007] The following is an overview to provide a basic understanding of one or more embodiments of the invention. This overview is not intended to identify key or important elements, or to delineate any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to a more detailed description that is presented later. In one or more embodiments described herein, a system, computer-implemented method, apparatus, and / or computer program product that facilitates local optimization of quantum circuits is described.

[0008] According to an embodiment, a system may include a memory storing computer executable components and a processor executing the computer executable components stored in the memory. The computer executable components may include a matrix weighting component that applies respective weights to a plurality of matrix elements of a first matrix corresponding to the quantum circuit according to respective numbers of quantum gates between respective pairs of qubits in the quantum circuit, a bandwidth reduction component that transforms the first matrix into a second matrix based on respective weights of the matrix elements, and a permutation component that permutes respective qubits in the quantum circuit according to the second matrix to obtain a permuted quantum circuit. Among other advantages, the system according to this embodiment has the advantages of improved efficiency for quantum computing operations (in terms of, for example, power consumption, required processing cycles, etc.) and improved ability to implement quantum circuits on quantum computer hardware.

[0009] In some embodiments, the bandwidth reduction component may include a search component that generates an ordered list of qubits based on the respective weights of the respective matrix elements, and the bandwidth reduction component may transform the first matrix into the second matrix based on the ordered list of qubits. The system according to this embodiment has the advantage of improved quantum circuit optimization performance and other advantages. In other embodiments, the search component may select a qubit in the quantum circuit as the first qubit in the ordered list of qubits, the qubit having a first number of inter-qubit connections and a first combined matrix element weight. The search component may further store the qubit in the ordered list of qubits by increasing the number of inter-qubit connections from the first number of inter-qubit connections and the first combined matrix element weights and reducing the combined matrix element weights, respectively. The system according to these embodiments has the advantage of further improved quantum circuit optimization performance and other advantages. In further embodiments, the bandwidth reduction component may reverse the ordered list of qubits, thereby generating a qubit reversed ordered list, and based on the qubit reversed ordered list, transform the first matrix into the second matrix. In addition or alternatively, the bandwidth reduction component may transform the first matrix into the second matrix via a breadth-first search. The system according to these embodiments has the advantage of improved optimization efficiency for various quantum circuit configurations and other advantages. In other embodiments, the system may include a SWAP mapping component that maps the SWAP gates to individual qubits of the permuted quantum circuit. The system according to this embodiment has the advantage of reduced SWAP gates and / or associated physical connections in the associated quantum circuit, as well as other advantages. In other embodiments, the first matrix may have a first bandwidth, and the second matrix may have a second bandwidth that is less than the first bandwidth. The system according to this embodiment has the advantage of reduced quantum circuit complexity, for example, approximately on the order of magnitude of the difference between the first bandwidth and the second bandwidth, as well as other advantages.

[0010] According to another embodiment, a computer-implemented method may include: applying, by a device operatively coupled to a processor, respective weights to a plurality of matrix elements of a first matrix corresponding to a quantum circuit according to respective numbers of quantum gates between respective pairs of qubits in the quantum circuit; transforming, by the device, the first matrix into a second matrix based on respective weights of the matrix elements; and permuting, by the device, respective qubits in the quantum circuit according to the second matrix to obtain a permuted quantum circuit. The computer-implemented method according to this embodiment has the advantages of improved efficiency for quantum computing operations (in terms of, for example, power consumption, required processing cycles, etc.) and improved ability to implement quantum circuits on quantum computer hardware, among other advantages.

[0011] In some embodiments, the transformation may include generating an ordered list of qubits based on the respective weights of the respective matrix elements, and transforming the first matrix into a second matrix based on the ordered list of qubits. The computer-implemented method according to the present embodiment has the advantage of improved quantum circuit optimization performance, among other advantages. In other embodiments, the generation may include selecting a qubit in the quantum circuit as the first qubit in the ordered list of qubits, the qubit having a first number of inter-qubit connections and a first combined matrix element weighting, and storing the qubit in the ordered list of qubits by increasing the number of inter-qubit connections and reducing the combined matrix element weighting from the first number of inter-qubit connections and the first combined matrix element weighting, respectively. The computer-implemented method according to the present embodiment has the advantage of further improved quantum circuit optimization performance, among other advantages. In further embodiments, the transformation may include inverting the ordered list of qubits, thereby generating a qubit inversion ordered list, and transforming the first matrix into the second matrix based on the qubit inversion ordered list. Additionally or alternatively, the generation may include transforming the first matrix into the second matrix via a breadth-first search. The system according to these embodiments has the advantage of improved optimization efficiency for various quantum circuit configurations, as well as other advantages.

[0012] According to a further embodiment, a computer program product for local optimization of a quantum circuit may include a computer-readable storage medium having program instructions embodied therewith. The program instructions may be executed by a processing component to cause the processing component to apply respective weights to a plurality of matrix elements of a first matrix corresponding to the quantum circuit according to respective numbers of quantum gates between respective pairs of qubits in the quantum circuit, transform the first matrix into a second matrix based on respective weights of the matrix elements, and permute respective qubits in the quantum circuit according to the second matrix to obtain a permuted quantum circuit. Among other advantages, the computer program product according to the present embodiment has the advantages of improved efficiency of quantum computing operations (in terms of, for example, power consumption, required processing cycles, etc.) and improved ability to implement quantum circuits on quantum computer hardware.

[0013] In some embodiments, the program instructions may cause the processor to generate an ordered list of qubits based on the respective weights of the respective matrix elements, and transform the first matrix into a second matrix based on the ordered list of qubits. The computer program product according to the present embodiment has the advantages of improved quantum circuit optimization performance and other advantages. In other embodiments, the program instructions may cause the processor to transform the first matrix into the second matrix via a breadth-first search. The computer program product according to the present embodiment has the advantages of improved optimization efficiency for various quantum circuit configurations and other advantages.

[0014] According to an additional embodiment, the system may include a memory storing computer executable components and a processor executing the computer executable components stored in the memory. These computer executable components may include a graph weighting component that applies weights to edges of a graph corresponding to a quantum circuit according to the number of quantum gates between pairs of qubits in the quantum circuit, a graph modification component that repositions the vertices of the graph based on the degree of each vertex in the graph and the weight of each edge in the graph to obtain a modified graph, and a permutation component that permutes each qubit in the quantum circuit according to the modified graph to obtain a permuted quantum circuit. Among other advantages, the system according to this embodiment has the advantages of improved efficiency for quantum computing operations (in terms of, for example, power consumption, required processing cycles, etc.) and improved ability to implement quantum circuits on quantum computer hardware.

[0015] In some embodiments, the graph modification component may include a search component that generates an ordered list of qubits based on the degree of each vertex of the graph and the weight of each edge of the graph, and the graph modification component may reposition the vertices of the graph based on the ordered list of qubits. The system according to this embodiment has the advantage of improved quantum circuit optimization performance and other advantages. In other embodiments, the search component may select a qubit corresponding to a vertex of the graph as the first qubit in the ordered list of qubits, the qubit having a first degree and a first combined edge weight, and store the qubit in the ordered list of qubits by increasing the degree and decreasing the combined edge weight from the first degree and the first combined edge weight, respectively. The system according to this embodiment has the advantage of further improved quantum circuit optimization performance and other advantages. In another embodiment, the graph modification component may reverse the ordered list of qubits to obtain a reversed ordered list of qubits, and reposition the vertices of the graph based on the reversed ordered list of qubits. In addition or alternatively, the graph modification component may reposition the vertices of the graph via a breadth-first search. The system according to these embodiments has the advantage of improved optimization efficiency for various quantum circuit configurations and other advantages.

[0016] According to yet another embodiment, a computer-implemented method may include: applying, by a device operatively coupled to a processor, respective weights to edges of a graph corresponding to a quantum circuit according to respective numbers of quantum gates between respective pairs of qubits in the quantum circuit; repositioning, by the device, vertices of the graph based on the degrees of respective vertices in the graph and the weights of respective edges in the graph, resulting in a modified graph; and permuting, by the device, respective qubits in the quantum circuit according to the modified graph, resulting in a permuted quantum circuit. The computer-implemented method according to this embodiment has the advantages of improved efficiency for quantum computing operations (in terms of, for example, power consumption, required processing cycles, etc.) and improved ability to implement quantum circuits on quantum computer hardware, among other advantages.

[0017] In some embodiments, the repositioning may include generating an ordered list of qubits based on the degrees of the respective vertices of the graph and the weights of the respective edges of the graph, and repositioning the vertices of the graph based on the ordered list of qubits. The computer-implemented method according to the present embodiment has the advantage of improved quantum circuit optimization performance, among other advantages. In other embodiments, the repositioning may include selecting a qubit corresponding to a vertex of the graph as the first qubit in the ordered list of qubits, the qubit having a first degree and a first combined edge weight, and storing the qubit in the ordered list of qubits by increasing the degree and decreasing the combined edge weight from the first degree and the first combined edge weight, respectively. The computer-implemented method according to the present embodiment has the advantage of further improved quantum circuit optimization performance, among other advantages. In other embodiments, the repositioning may include repositioning the vertices of the graph via a breadth-first search. The computer-implemented method according to these embodiments has the advantage of improved optimization efficiency for different quantum circuit configurations, among other advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a block diagram of a system that facilitates local optimization of quantum circuits according to one or more embodiments described herein.

[0019] Figure 2 is a simplified diagram of an example quantum circuit prior to local optimization according to one or more embodiments described herein.

[0020] Figure 3 is a simplified diagram of an example qubit configuration prior to local optimization according to one or more embodiments described herein.

[0021] Figure 4 is a simplified diagram of an example quantum SWAP gate according to one or more embodiments described herein.

[0022] Figure 5is after local optimization according to one or more embodiments described herein Figure 2 A simplified diagram of a quantum circuit.

[0023] Figure 6 is after local optimization according to one or more embodiments described herein Figure 3 A simplified diagram of the qubit configuration.

[0024] Figure 7-8 is a simplified diagram of various matrices associated with various quantum circuits according to one or more embodiments described herein.

[0025] Fig. 9 is a block diagram of a system that facilitates optimization of a matrix corresponding to a quantum circuit according to one or more embodiments described herein.

[0026] Fig.10 is a simplified diagram of an example quantum circuit prior to local optimization according to one or more embodiments described herein.

[0027] Fig.11 According to one or more embodiments described herein Fig.10 A simplified diagram of the matrix associated with a quantum circuit.

[0028] Fig.12 is after local optimization according to one or more embodiments described herein Fig.10 A simplified diagram of a quantum circuit.

[0029] Fig.13 According to one or more embodiments described herein Fig.12 A simplified diagram of the matrix associated with a quantum circuit.

[0030] Fig.14 is a block diagram of another system that facilitates local optimization of quantum circuits according to one or more embodiments described herein.

[0031] Figure 15-16 According to one or more embodiments described herein, Fig.10 and Fig.12 A simplified diagram of the graph associated with a quantum circuit.

[0032] Fig.17 is a block diagram of a system that facilitates optimization of a graph corresponding to a quantum circuit according to one or more embodiments described herein.

[0033] Fig.18 is a block diagram of a system that facilitates mapping SWAP gates of a locally optimized quantum circuit according to one or more embodiments described herein.

[0034] Figure 19-20is a simplified diagram of corresponding example, non-limiting processing components according to one or more embodiments described herein.

[0035] Figure 21-22 is a flow chart of a corresponding example, non-limiting computer-implemented method for facilitating local optimization of quantum circuits according to one or more embodiments described herein.

[0036] Fig.23 is a block diagram of an example, non-limiting operating environment in which one or more embodiments described herein may be implemented. DETAILED DESCRIPTION

[0037] The following detailed description is illustrative only and is not intended to limit the embodiments and / or the application or uses of the embodiments. In addition, there is no intention to be bound by any express or implied information presented in the previous background or summary sections or in the detailed description section.

[0038] One or more embodiments are now described with reference to the accompanying drawings, wherein the same reference numerals are used to refer to the same elements throughout the text. In the following description, for the purpose of explanation, many specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it is apparent that one or more embodiments may be practiced without these specific details in different circumstances.

[0039] Now referring to the accompanying drawings, Figure 1 1 is a block diagram of a system 100 for facilitating local optimization of quantum circuits according to one or more embodiments described herein. Figure 1 As shown, system 100 includes a matrix weighting component 110 that applies respective weights to matrix elements of a matrix (e.g., a first matrix) corresponding to a quantum circuit. In one aspect, the weights applied by matrix weighting component 110 may correspond to respective numbers of quantum gates between respective qubit pairs in the quantum circuit. Specific, non-limiting examples of matrices that may be processed by matrix weighting component 110 are described below. Figure 7 , 8 , 11 and 13 are further described in detail.

[0040] In one aspect, the matrix corresponding to a given quantum circuit may be generated by the matrix weighting component 110 itself, or alternatively, the matrix may be provided to the matrix weighting component 110 via one or more components external to the system 100. The matrix may be, for example, an nxn square sparse matrix, where n is the number of qubits in the quantum circuit. As described above, the matrix weighting component 110 may weight the elements of the matrix according to the respective numbers of quantum gates between the respective qubit pairs in the underlying quantum circuit. The qubits of the quantum circuit may be indexed, and the matrix may be filled accordingly. For example, for the matrix M, the matrix element M may be i,j may be filled with a value corresponding to the number of quantum gates between a first qubit with index i and a second qubit with index j. Qubits in the circuit that do not have quantum gates between each other may have corresponding values ​​of 0 and / or other suitable empty values ​​in the matrix.

[0041] like Figure 1 As further shown, the system 100 includes a bandwidth reduction component 120 that can transform a matrix (e.g., a first matrix) processed by the matrix weighting component 110 into a different second matrix based on respective weights of respective matrix elements applied by the matrix weighting component 110. In one aspect, the second matrix processed by the bandwidth reduction component 120 can have a bandwidth that is less than the bandwidth of the original matrix processed by the matrix weighting component 110, thereby resulting in increased simplicity of the underlying quantum circuit, as described in more detail below.

[0042] Figure 1 The system 100 in further includes a permutation component 130, which can permute corresponding qubits in the underlying quantum circuit according to a second matrix processed by the bandwidth reduction component 120, thereby obtaining a permuted quantum circuit. In one aspect, the matrix weighting component 110, the bandwidth reduction component 120, and the permutation component 130 can operate together to improve the efficiency of quantum circuits on hardware with local connectivity by utilizing bandwidth and profile reduction in corresponding sparse matrices. By doing so, the system 100 solves the problem of optimizing quantum circuits for hardware with local interactions, thereby generating a solution that can generate simpler and / or more efficient quantum circuits compared to quantum circuits generated via conventional techniques. This in turn can increase the speed of quantum computers, reduce the power usage of quantum computers, reduce the processing cycles and / or other computing resources utilized by quantum computers, reduce the time and / or processing cycles used to map quantum circuits to quantum hardware, etc. Other advantages of the embodiments provided herein can also be achieved.

[0043] Go to Figure 2, the diagram 200 depicts an example modular multiplication quantum circuit U7, which can be mapped to Figure 3 300 in FIG. 2 . As shown in diagram 200 , the modular multiplication circuit interacts through a series of controlled-not (CNOT) gates between qubits 1 and 2, qubits 0 and 1, and qubits 0 and 3. However, because qubits 0 and 3 are not directly connected to each other in the hardware architecture shown in diagram 300 , the mapping of the quantum circuit shown in diagram 200 to the architecture shown in diagram 300 will include additional SWAP gates, here between qubits 0 and 2 and between qubits 2 and 3, in order to mediate the CNOT gate between qubits 0 and 3. Figure 4 The simplified diagram 400 in FIG. 4 shows a quantum circuit diagram of an example SWAP gate between two qubits.

[0044] In contrast, by utilizing one or more local optimization techniques as described herein, as described above with respect to Figure 1 By relabeling and / or otherwise redistributing the individual qubits of the quantum circuit, the quantum circuit shown in the simplified diagram 200 can be replaced by Figure 5 The quantum circuit shown in the simplified diagram 500 can be mapped to Figure 6 600 in the diagram. In one aspect, by mapping the quantum circuit shown in the diagram 500 onto the quantum hardware in the manner shown in the diagram 600, quantum gates can be established only between the directly connected quantum bits of the hardware architecture. This can in turn reduce the number of SWAP gates used by the quantum circuit while keeping the number of other quantum gates used by the quantum circuit unchanged.

[0045] Return to Figure 1 , the matrix weighting component 110 and the bandwidth reduction component 120 can process each two-qubit gate of the quantum circuit as a sparse matrix. In this way, the bandwidth reduction component 120 can promote the local optimization of the quantum circuit by reducing the bandwidth of its corresponding matrix.

[0046] Figure 7 The diagrams 700 and 702 in FIG. 1 depict sparse matrices corresponding to an example quantum circuit before and after optimization by the bandwidth reduction component 120, respectively. In one aspect, the sparse matrix can be represented as A ij , where the matrix A ij Each element of may correspond to the number of two-qubit gates between qubits i and j in the corresponding circuit. In the matrices depicted by diagrams 700 and 702, the element A associated with a quantum gate is ijElements not associated with quantum gates are left blank, represented by squares. As will be discussed further with respect to various examples below, various matrix elements may also be given different (eg, greater) weights based on different numbers of quantum gates between corresponding qubit pairs.

[0047] In one aspect, bandwidth reduction component 120 can initially process the matrix shown in diagram 700 by finding a permutation of the rows and columns of the matrix that moves the non-zero elements of the matrix as close to the main diagonal as possible, thereby minimizing the bandwidth of the matrix. For example, before optimization, the matrix shown in diagram 700 has elements that are spatially dispersed throughout the matrix, while after optimization, the elements of the matrix shown in diagram 702 are substantially aligned with the main diagonal of the matrix, which can be visualized as a diagonal line extending from (0,0) to (7,7) (not shown). By doing so, the resulting quantum circuit can prioritize connections between directly adjacent qubits (e.g., to connect qubits that are directly adjacent to each other). Figure 3 and Figure 6 ), thereby reducing the number of SWAP gates associated with the circuit to facilitate simplified circuit design on quantum hardware.

[0048] In one aspect, the bandwidth reduction component 120 can utilize any suitable algorithm or combination of algorithms to find a permutation of the rows and columns of a symmetric matrix that moves each non-zero element toward the main diagonal of the matrix. For example, the bandwidth reduction component 120 can utilize an algorithm similar to that used to reduce the memory footprint in a sparse LU (lower-upper) decomposition and / or increase the stability of an iLU (inverse LU) preconditioner.

[0049] By way of specific non-limiting example, the bandwidth reduction component 120 can utilize a breadth-first search technique, such as Cuthill-McKee reordering, which starts at the lowest degree node or vertex and sorts the vertices by increasing degree. In some instances, the resulting sorted vertices can be reversed (e.g., using a reverse Cuthill-McKee sort) to improve bandwidth reduction performance.

[0050] However, it should be understood that bandwidth reduction component 120 may utilize any suitable technique or combination of techniques to reduce the bandwidth of the quantum circuit matrix. Additionally, neither the specification nor the claimed subject matter is intended to be limited to any particular algorithm unless expressly stated otherwise.

[0051] In another aspect, the weights applied by the matrix weighting component 110 and utilized by the bandwidth reduction component 120 can preferentially place qubit pairs associated with multiple quantum gates adjacent to each other, thereby further reducing the number of SWAP gates and / or other physical overhead associated with the corresponding quantum circuit. A graphical example of weighted matrix bandwidth reduction that can be performed by the bandwidth reduction component 120 is represented by Figure 8 800 and 802. Here, the quantum circuit associated with the matrices shown in diagrams 800 and 802 is a five-qubit circuit that is physically configured such that each qubit in the circuit is connected to each other qubit in the circuit through at least one quantum gate. Therefore, as shown by the matrices shown in diagrams 800 and 802, each element of the matrix (except those directly on the main diagonal) is non-zero.

[0052] like Figure 8 As further shown, each matrix element may be assigned different weights according to a weighting scale, for example, by the matrix weighting component 110. Here, the weighting scale may correspond to the number of quantum gates corresponding to each qubit pair in the quantum circuit. Thus, for example, a matrix element with a weight of 1 may correspond to a qubit pair connected by one quantum gate, a matrix element with a weight of 2 may correspond to a qubit pair connected by two quantum gates, and so on.

[0053] Diagram 800 shows an example quantum circuit matrix prior to optimization by bandwidth reduction component 120. Because canonical bandwidth minimization techniques operate only on the matrix structure, these techniques will leave the matrix shown in diagram 800 unchanged because every element of the matrix except those along the main diagonal is non-zero. In contrast, by utilizing Figure 8 The illustrated element weight, bandwidth reduction component 120 can facilitate additional local optimization by prioritizing repeated interactions between qubits. This in turn can increase the number of quantum gates shared between adjacent qubits in the quantum circuit, thereby reducing SWAP counts and / or other physical overhead associated with the circuit.

[0054] Diagram 802 shows an example of a weighted quantum circuit matrix after optimization by bandwidth reduction component 120. As shown in diagram 802, bandwidth reduction component 120 may move the largest weight elements of the matrix toward the main diagonal, thereby rearranging the qubits in the corresponding quantum circuit to better accommodate repeated interactions between pairs of qubits.

[0055] Now turn to Fig. 9, a block diagram of a system 900 for facilitating optimization of a matrix corresponding to a quantum circuit according to one or more embodiments described herein is shown. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Fig. 9 As shown, the system 900 includes a bandwidth reduction component 120, which can be described above with respect to Figure 1 In one aspect, the bandwidth reduction component 120 can include a search component 910 that can generate an ordered list 920 of qubits based on the respective weights of these matrix elements (e.g., as assigned by the matrix weighting component 110). The bandwidth reduction component 120 can then transform the original (first) matrix processed by the matrix weighting component 110 into an optimized (second) matrix based on the ordered list 920 generated by the search component 910.

[0056] In one aspect, search component 910 may begin generating ordered list 920 by selecting a qubit in the associated quantum circuit as a first qubit in ordered list 920, the qubit having a first number of inter-qubit connections and a first combined matrix element weight. By way of non-limiting example, search component 910 may select a qubit in the quantum circuit having a lowest number of inter-qubit connections (e.g., corresponding to a row of the matrix weighted by matrix weighting component 110 with the lowest degree) and the lowest combined weight. Search component 910 may then store the qubit in ordered list 920 by increasing the number of inter-qubit connections and decreasing the combined matrix element weight from the first number of inter-qubit connections and the first combined matrix element weight, respectively. In other words, referring to a matrix weighted by a matrix weighting component, search component 910 can traverse the matrix starting with a qubit having the lowest degree and the lowest weight, and add qubits to ordered list 920 through a search traversal in which the qubits are ordered by lowest degree and highest weight, e.g., degrees ordered from lowest to highest and weights ordered from highest to lowest.

[0057] On the other hand, the search component 910 can invert the generated ordered list 920 to obtain an inverted ordered list. The bandwidth reduction component 120 can then utilize the inverted ordered list to transform the original quantum circuit matrix into an optimized matrix. Figure 7As a non-limiting example, the search component 910 can use one or more search algorithms (e.g., a Cuthill-McKee search) to generate an ordered list [0, 4, 2, 1, 5, 7, 3, 6] based on the original matrix shown by the simplified diagram 700. The search component 910 can then, for example, reverse the list to obtain [6, 3, 7, 5, 1, 2, 4, 0], which the bandwidth reduction component 120 can use to rearrange the elements of the matrix according to the reversed list in the order specified by the list. Thus, for example, the bandwidth reduction component can reassign element 6 as shown in the simplified diagram 700 to element 0 as shown in the simplified diagram 702, reassign element 3 as shown in the simplified diagram 700 to element 1 as shown in the simplified diagram 702, and so on, until each element of the matrix has been reassigned. In a further aspect, the bandwidth reduction component 120 can use the original ordered list 920 or the reversed ordered list, for example, based on determining which ordered list better reduces the bandwidth of the matrix.

[0058] As described above, search component 910 can provide improved local quantum circuit optimization compared to conventional techniques by incorporating matrix element weights (e.g., applied by matrix weighting component 110). Figure 8 As illustrated, search component 910 can generate an ordered list 920 of qubits based on the degrees and weights, thereby generating an optimized quantum circuit matrix as shown by diagram 802, which can improve circuit performance compared to techniques operating on degrees alone. Figure 8 Using weighted matrix traversal in the manner shown, search component 910 can reduce the gate count and / or depth of a quantum circuit by up to an order of magnitude.

[0059] In one aspect, the search component 910 can generate the ordered list 920 via one or more breadth-first search techniques (e.g., a weighted Cuthill-McKee search). However, it should be understood that the search component 910 can utilize any suitable search algorithm or combination of algorithms to generate the ordered list 920 and / or transform the associated matrix.

[0060] See next Figure 10-13 , shows a specific, non-limiting example of quantum circuit optimization that can be performed according to various aspects described herein. Specifically, Figure 10-13 Various circuit optimizations that can be performed for a quantum circuit of the Simon algorithm are shown, which is used here as an example due to the knowledge of the algorithm in the art. It should be understood that other quantum circuits can be optimized in a similar manner.

[0061] Fig.10A conventional quantum circuit for the Simon algorithm is shown in the simplified diagram 1000 in FIG. Here, the circuit contains 26 quantum gates with a gate depth of 14. Fig.11 The circuit shown by diagram 1000 is represented in matrix form by diagram 1100. As shown in diagram 1100, the matrix corresponding to the circuit shown in diagram 1000 has a bandwidth of 7 and a weighting profile of 37 (e.g., a measure of the degree to which the higher weighted elements in the matrix have been moved to the main diagonal).

[0062] In one aspect, by performing one or more circuit optimization techniques as described above, Fig.10 The quantum circuit shown in the simplified diagram 1000 in FIG. 1 can be transformed (e.g., by replacing component 130) into Fig.12 1200 in the diagram. Due to the above operations, the circuit shown by the diagram 1200 can still utilize 26 quantum gates, but the circuit depth can be reduced from 14 to 10. This in turn can significantly reduce the number of SWAP gates and / or other interconnects used to map the circuit shown by the diagram 1200 onto quantum hardware. For example, for an example quantum hardware implementation, the gate count (including SWAP gates and other similar gates) mapped to the hardware can be reduced by a factor of about 33% compared to the circuit shown in the diagram 1000, and the circuit depth can be similarly reduced by a factor of about 42%. Fig.13 The circuit shown by diagram 1200 is represented in matrix form by diagram 1300. Compared to the matrix shown by diagram 1100, the matrix bandwidth can be reduced from 7 to 4, and the weighting profiles can be reduced from 37 to 23.

[0063] Next, refer to Fig.14 , a block diagram of an alternative system 1400 for facilitating local optimization of quantum circuits according to various embodiments described herein is shown. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Fig.14 As shown, the system 1400 includes a graph weighting component 1410, which can apply respective weights to edges of a graph corresponding to a quantum circuit according to respective numbers of quantum gates between respective qubit pairs in the quantum circuit.

[0064] In one aspect, a graph corresponding to a given quantum circuit may be generated by the graph weighting component 1410 itself, or alternatively, the graph may be provided to the graph weighting component 1410 via one or more components external to the system 1400. The graph may include, for example, individual vertices corresponding to qubits in the circuit and individual edges corresponding to quantum gates shared by individual qubit pairs in the quantum circuit. In one example, the graph weighting component 1410 may weight the individual edges of the graph according to the individual numbers of quantum gates between individual qubit pairs in the underlying quantum circuit. The qubits of the quantum circuit may be indexed, and the graph may be populated accordingly.

[0065] In one aspect, the techniques used by the graph weighting component 1410 to generate and / or weight a graph corresponding to a quantum circuit can be similar to those used to generate and / or weight elements of a matrix as described above with respect to the matrix weighting component 110. As a specific non-limiting example, Fig.15 The schematic diagram 1500 in FIG. Fig.10 1500. As described above, the graph shown by diagram 1500 may include vertices corresponding to individual qubits in the underlying quantum circuit and edges representing individual quantum gates in the circuit. Since the qubits with indices 1 and 6 in diagram 1000 are connected by two quantum gates, the edge between vertices 1 and 6 in diagram 1500 may be given a weight of 2 by graph weighting component 1410. This weighting is represented in diagram 1500 by the double line connecting vertices 1 and 6. However, it should be understood that this representation is for illustrative purposes only and that weights may be applied to the individual edges in the graph in any suitable manner.

[0066] Back to Fig.14 , system 1400 further includes a graph modification component 1420 that can reposition vertices within a graph generated and / or processed by graph weighting component 1410 to produce a modified graph. In one aspect, graph modification component 1420 can reposition vertices in a graph based on the degree of each vertex in the graph (i.e., the number of vertices connected to a given vertex via an edge), the weight of each edge in the graph, and / or other suitable factors. Fig.14 The system 1400 shown may further include a replacement component 130 that can replace the modified image in a manner similar to the above matrix for the modification. Figure 1 The described manner permutes individual qubits in the qubits in the quantum circuit in a similar manner. In one aspect, system 1400 solves the problem of optimizing quantum circuits for hardware with local interactions, thereby producing a solution that can produce simpler and / or more efficient quantum circuits than those produced via conventional techniques.

[0067] In one aspect, graph modification component 1420 can reposition vertices in a graph via one or more graph relabeling techniques. More specifically, graph modification component 1420 can reposition labels applied to individual vertices in the graph, and further reposition corresponding qubits in a quantum circuit, while keeping the underlying physical structure of the graph otherwise unchanged. By way of non-limiting example, Fig.16 The simplified diagram 1600 in FIG. 1 shows the graph shown in simplified diagram 1500 after being processed by the graph modification component 1420. As shown in simplified diagram 1600, the graph modification component 1420 can relabel the vertices in the graph so as to optimize the local connections associated with the underlying quantum circuit without physically changing the structure of the graph itself. In one aspect, the graph structure shown by simplified diagram 1600 can produce the same Fig.12 A quantum circuit similar to the quantum circuit shown by diagram 1200 in FIG. 1 (eg, via permutation component 130 ).

[0068] Now turn to Fig.17 , a block diagram of a system 1700 for facilitating optimization of a graph corresponding to a quantum circuit according to one or more embodiments described herein is shown. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Fig.17 As shown, system 1700 includes a graphics modification component 1420, which can be as described above with respect to Fig.14 In one aspect, graph modification component 1420 can include search component 1710 that can generate an ordered list of qubits 1720 based on the degrees of the respective vertices in the graph and the respective weights applied to the vertices, e.g., by graph weighting component 1410. Graph modification component 1420 can then reposition vertices within the graph based on ordered list 1720 generated by search component 1710, e.g., by relabeling the vertices in the graph in the manner shown in diagrams 1500 and 1600.

[0069] In one aspect, the search component 1710 may begin generating the ordered list 1720 by selecting a qubit corresponding to a vertex in the graph having a first degree and a first combined edge weight as the first qubit in the ordered list 1720. As a non-limiting example, the search component 1710 may select the qubit in the quantum circuit corresponding to a vertex in the graph having the lowest degree (and, accordingly, the lowest number of connections between qubits) and the lowest total edge weight associated with the edges connected to the vertex. The search component 1710 may then store the qubits in the ordered list 1720 by increasing the degree and decreasing the combined edge weight from the first degree and the first combined edge weight, respectively. In another aspect, the search component 1710 may invert the generated ordered list 1720 to obtain an inverted ordered list. Subsequently, the graph modification component 1420 may use the inverted ordered list to relabel or reposition various nodes of the quantum circuit graph.

[0070] As described above, search component 1710 can provide improved local quantum circuit optimization compared to conventional techniques by incorporating graph edge weights (e.g., as applied by graph weighting component 1410). Figure 15-16 As illustrated, search component 1710 can generate an ordered list of qubits 1720 based on both degree and weight, thereby generating an optimized quantum circuit graph, as shown by simplified diagram 1600, which can improve circuit performance compared to techniques that operate on degree alone. Figure 15-16 Using weighted graph traversal in the manner shown, search component 1710 can reduce the gate count and / or depth of a quantum circuit by up to an order of magnitude.

[0071] In one aspect, search component 1710 can be configured to perform a search via a process similar to that described above with respect to Fig. 9 The search component 910 is described as utilizing one or more of the techniques to generate the ordered list 1720. These techniques may include a breadth-first search technique, such as a weighted Cuthill-McKee search. However, as with the search component 910, it should be understood that the search component 1710 may utilize any suitable search algorithm or combination of algorithms to generate the ordered list 1720 and / or transform the associated graph.

[0072] See now Fig.18 , a block diagram of a system 1800 for facilitating mapping of multiple SWAP gates of a local optimization quantum circuit according to one or more embodiments described herein is shown. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Fig.18The illustrated system 1800 includes a SWAP mapping component 1810 that can map SWAP gates to individual qubits of a permuted quantum circuit, for example, as generated by the permutation component 130 according to the above description of Figure 1 and / or Fig.14 In one aspect, a SWAP mapping component 1810 can be utilized to facilitate directly mapping a permutation quantum circuit generated by a permutation component 130 to quantum hardware, or alternatively, one or more transpiler components and / or other processing steps can be inserted between the permutation component 130 and the SWAP mapping component 1810. As described above, the permutation component 130 can utilize different techniques as described herein to generate a quantum circuit with improved local connectivity. As such, the number of SWAP gates used by the SWAP mapping component 1810 used in the system 1800 can be lower than the number of SWAP gates associated with a conventional quantum circuit. Other advantages can also be achieved.

[0073] Next, refer to Fig.19 , shows a processing component 1900 that can be used to implement one or more aspects described herein according to one or more embodiments. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted.

[0074] like Fig.19 As shown, the processing component 1900 can be associated with at least one processor 1910 (e.g., a central processing unit, a graphics processing unit, etc.), which can be used to implement one or more of the matrix weighting component 110, the bandwidth reduction component 120, and / or the permutation component 130 as described above. The processor 1910 can be connected to one or more additional subcomponents of the processing component 1900, such as a communication component 1930 and / or a memory 1940, via a data bus 1920. Although the communication component 1930 is shown as being implemented separately from the processor 1910, in some embodiments, the processor 1910 can be additionally used to implement the communication component 1930. In other embodiments, the communication component 1930 can be external to the processing component 1900 and communicate with the processing component 1900 via a separate communication link.

[0075] According to one or more embodiments described herein, memory 1940 may be used by processing component 1900 to store data used by processing component 1900. Additionally or alternatively, memory 1940 may have machine-readable instructions stored thereon that, when executed by processing component 1900, cause processing component 1900 (and / or its one or more processors 1910) to implement matrix weighting component 110, bandwidth reduction component 120, and / or permutation component 130, as described above.

[0076] Fig. 20 Another processing component 2000 that can be used to implement one or more aspects described herein according to one or more embodiments is shown. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted.

[0077] like Fig. 20 As shown, the processing component 2000 can be associated with at least one processor 2010, which can be used to implement one or more of the graph weighting component 1410, the graph modification component 1420, and / or the replacement component 130 described above. The processor 2010 can be connected to one or more additional subcomponents of the processing component 2000 via a data bus 2020, such as a communication component 2030 and / or a memory 2040. In one aspect, the communication component 2030 can be similar to the above-mentioned Fig.19 The communication component 1930 is configured in the described manner.

[0078] Similar to the above Fig.19 As described, the memory 1940 may be utilized by the processing component 2000 to store data utilized by the processing component 2000 in accordance with one or more embodiments described herein. Additionally or alternatively, the memory 2040 may have machine-readable instructions stored thereon that, when executed by the processing component 2000, cause the processing component (and / or its one or more processors 2010) to implement the graph weighting component 1410, the graph modification component 1420, and / or the permutation component 130 as described above.

[0079] In various embodiments, Figure 19-20The processing components 1900, 2000 shown in the figure can be or include hardware, software (e.g., a set of threads, a set of processes, software in execution, etc.) or a combination of hardware and software that performs computing tasks (e.g., computing tasks associated with received data). For example, the processing components 1900, 2000 can perform simulations of large and / or complex multi-qubit circuits and / or perform other operations that cannot be performed by humans (e.g., greater than the capabilities of the human brain). For example, the amount of data processed by the processing components 1900, 2000 in a period of time, the speed of data processing, and / or the type of data can be larger, faster, and of different data types than can be processed by a single human brain in the same period of time, respectively. For example, the data processed by the processing components 1900, 2000 can be raw data (e.g., raw text data, raw digital data, etc.) and / or compressed data (e.g., compressed text data, compressed digital data, etc.) associated with one or more computing devices. In addition, the processing components 1900, 2000 can be fully operable to perform one or more other functions (e.g., fully powered on, fully executed, etc.) while also processing the above data.

[0080] Fig.21 A flow chart illustrating an example, non-limiting computer-implemented method 2100 for facilitating local optimization of quantum circuits according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted.

[0081] At 2102, a device operably coupled to a processor (e.g., processor 1910 of processing component 1900) may apply respective weights to matrix elements of a first matrix corresponding to a quantum circuit (e.g., via matrix weighting component 110). In one aspect, the weights may be applied according to respective numbers of quantum gates between respective qubit pairs in the quantum circuit.

[0082] At 2104 , the device can transform the first matrix into a second matrix based on the respective weights of the matrix elements as applied at 2102 (eg, by the bandwidth reduction component 120 ).

[0083] At 2106, the apparatus may permute corresponding qubits in the quantum circuit according to the second matrix generated at 2104 (eg, by permutation component 130), thereby generating a permuted quantum circuit.

[0084] Fig. 22 A flow chart of an alternative example, non-limiting computer-implemented method 2200 for facilitating local optimization of a quantum circuit according to one or more embodiments described herein is shown. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted.

[0085] At 2202, a device operably coupled to a processor (e.g., processor 2010 of processing component 2000) may apply respective weights to edges of a graph corresponding to a quantum circuit (e.g., via graph weighting component 1410). In one aspect, the weights may be applied based on respective numbers of quantum gates between respective qubit pairs in the quantum circuit.

[0086] At 2204 , the device may reposition (eg, via graph modification component 1420 ) vertices of the graph based on the degree of each of the vertices of the graph and the weight of each of the edges of the graph applied at 2202 , thereby obtaining a modified graph.

[0087] At 2206, the apparatus may permute (eg, via permutation component 130) individual qubits in the quantum circuit according to the modified pattern generated at 2204, thereby obtaining a permuted quantum circuit.

[0088] In order to simplify the explanation, the computer-implemented method is depicted and described as a series of actions. It should be understood that the present invention is not limited to the actions shown and / or the order of the actions, for example, the actions can occur in different orders and / or simultaneously, and occur together with other actions not presented and described herein. In addition, not all the actions shown are computer-implemented methods that are implemented according to the disclosed subject matter. In addition, it will be understood and appreciated by those skilled in the art that the computer-implemented method may alternatively be represented as a series of interrelated states via state diagrams or events. In addition, it should be further understood that the computer-implemented method disclosed hereinafter and throughout this specification can be stored on an article of manufacture so that such a computer-implemented method can be transmitted and transferred to a computer. As used herein, the term article of manufacture is intended to encompass a computer program accessible from any computer-readable device or storage medium.

[0089] Furthermore, because the configuration of data packets and / or the communication between processing components is established from a combination of electrical and mechanical components and circuits, a human cannot replicate or execute the configuration of data packets and / or the communication between processing components. For example, a human cannot generate data for transmission over a wired network and / or a wireless network between processing components, etc. Furthermore, a human cannot package data that may include a bit sequence corresponding to information generated during one or more processes as described above, cannot send data that may include a bit sequence corresponding to information generated during one or more processes as described above, etc.

[0090] To provide context for various aspects of the disclosed subject matter, Fig.23 The following discussion is intended to provide a general description of a suitable environment in which aspects of the disclosed subject matter may be implemented. Fig.23A block diagram of an example non-limiting operating environment in which one or more embodiments described herein may be facilitated is shown. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Fig.23 , a suitable operating environment 2300 for implementing various aspects of the present disclosure may also include a computer 2312. The computer 2312 may also include a processing unit 2314, a system memory 2316, and a system bus 2318. The system bus 2318 couples system components including, but not limited to, the system memory 2316 to the processing unit 2314. The processing unit 2314 may be any of the different available processors. Dual microprocessors and other multi-processor architectures may also be used as the processing unit 2314. The system bus 2318 may be any of several types of bus structures including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using various available bus architectures, including but not limited to Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE1394), and Small Computer System Interface (SCSI). The system memory 2316 may also include volatile memory 2320 and non-volatile memory 2322. A basic input / output system (BIOS) containing basic routines such as transferring information between elements within the computer 2312 during startup is stored in the non-volatile memory 2322. As an illustration and not limitation, the non-volatile memory 2322 may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, or a non-volatile random access memory (RAM) (e.g., a ferroelectric RAM (FeRAM)). The volatile memory 2320 may also include a random access memory (RAM) that acts as an external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM.

[0091] The computer 2312 may also include removable / non-removable, volatile / nonvolatile computer storage media. Fig.23For example, disk storage 2324 is shown. Disk storage 2324 may also include, but is not limited to, devices such as a magnetic disk drive, a solid state drive, a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. Disk storage 2324 may also include storage media, either separately or in combination with other storage media, including but not limited to optical disk drives, such as compact disk ROM devices (CD-ROM), CD recordable drives (CD-R drives), CD rewritable drives (CD-RW drives), digital versatile disk ROM drives (DVD-ROM), or Blu-ray disk drives. To facilitate connecting disk storage 2324 to system bus 2318, a removable or non-removable interface, such as interface 2326, is typically used. Fig.23 Also depicted is software that acts as an intermediary between a user and the basic computer resources described in the appropriate operating environment 2300. Such software may also include, for example, an operating system 2328. The operating system 2328, which may be stored on disk storage 2324, is used to control and allocate the resources of the computer 2312. System applications 2330 utilize the management of resources by the operating system 2328 through program modules 2332 and program data 2334 (e.g., stored in system memory 2316 or on disk storage 2324). It should be understood that the present disclosure may be implemented with different operating systems or combinations of operating systems. A user enters commands or information into the computer 2312 through an input device 2336. The input device 2336 includes, but is not limited to, a pointing device such as a mouse, a trackball, a stylus, a touchpad, a keyboard, a microphone, a joystick, a game pad, a satellite dish, a scanner, a TV tuner card, a digital camera, a digital video camera, a webcam, etc. These and other input devices are connected to the processing unit 2314 via an interface port 2338 through the system bus 2318. Interface ports 2338 include, for example, serial ports, parallel ports, game ports, and universal serial bus (USB). Output devices 2340 use some of the same types of ports as input devices 2336. Thus, for example, a USB port can be used to provide input to computer 2312, and output information to output device 2340 from computer 2312. Output adapter 2342 is provided to illustrate that there are some output devices 2340 that require special adapters, such as monitors, speakers, and printers and other output devices 2340. As an illustration and not limitation, output adapter 2342 includes a video and sound card that provides a connection means between output device 2340 and system bus 2318. It should be noted that other devices and / or device systems provide both input and output capabilities, such as remote computer 2344.

[0092] The computer 2312 can operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 2344. The remote computer 2344 can be a computer, a server, a router, a network PC, a workstation, a microprocessor-based appliance, a peer device or other public network node, etc., and can also generally include many or all of the elements described with respect to the computer 2312. For the sake of simplicity, only a memory storage device 2346 with the remote computer 2344 is shown. The remote computer 2344 is logically connected to the computer 2312 through a network interface 2348 and then physically connected via a communication connection 2350. The network interface 2348 includes a wired and / or wireless communication network, such as a local area network (LAN), a wide area network (WAN), a cellular network, etc. LAN technologies include fiber distributed data interface (FDDI), copper distributed data interface (CDDI), Ethernet, token ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks (such as integrated services digital network (ISDN)) and its variants, packet switching networks, and digital subscriber lines (DSL). The communication connection 2350 refers to the hardware / software used to connect the network interface 2348 to the system bus 2318. Although the communication connection 2350 is shown internal to the computer 2312 for clarity of illustration, it can also be external to the computer 2312. The hardware / software used for connection to the network interface 2348 can also include (for exemplary purposes only) internal and external technologies such as modems including conventional telephone grade modems, cable modems and DSL modems, ISDN adapters and Ethernet cards.

[0093] Various embodiments of the present invention may be systems, methods, devices and / or computer program products at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium having computer-readable program instructions thereon, and the computer-readable program instructions are used to cause a processor to perform one or more aspects of the present invention. A computer-readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may also include the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device (such as a punch card) or a raised structure in a groove with instructions recorded thereon), and any suitable combination of the above. Computer-readable storage media as used herein should not be interpreted as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0094] Computer-readable program instructions as described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives computer-readable program instructions from the network, and forwards computer-readable program instructions to be stored in a computer-readable storage medium in the corresponding computing / processing device. The computer-readable program instructions for performing the operation of one or more embodiments of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcodes, firmware instructions, state setting data, configuration data of an integrated circuit, or source code or object code written in any combination of one or more programming languages, including object-oriented Smalltalk, C++ and other programming languages, and procedural programming languages, such as "C" programming language or similar programming languages. These computer-readable program instructions can be executed completely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer, partially on a remote computer, or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network (including a local area network (LAN) or a wide area network (WAN)), or can be connected to an external computer (for example, by using the Internet of an Internet service provider). In some embodiments, electronic circuits (including, for example, programmable logic circuits, field programmable gate arrays (FPGAs) or programmable logic arrays (PLAs)) can execute computer-readable program instructions to personalize the electronic circuits by utilizing the state information of the computer-readable program instructions, so as to perform one or more aspects of the present invention.

[0095] One or more aspects of the present invention are described herein with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to one or more embodiments of the present invention. It should be understood that each square frame of the flowchart and / or block diagram and the combination of the square frames in the flowchart and / or block diagram can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine, which is executed by the processor of a computer or other programmable data processing device to create a device for implementing the function / action specified in one or more square frames of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can guide a computer, a programmable data processing device and / or other devices that function in a specific manner, so that the computer-readable storage medium with instructions stored therein includes a product, which includes instructions for implementing various aspects of the function / action specified in one or more square frames in the flowchart and / or block diagram. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, so that a series of operational actions are performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0096] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to different embodiments of the present invention. To this end, each box in the flow chart or block diagram can represent a part of a module, segment or instruction, which includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box may not occur in the order marked in the figure. For example, depending on the functions involved, the two boxes shown in succession can actually be executed substantially at the same time, or these boxes can sometimes be executed in the opposite order. It will also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a system based on special-purpose hardware, and the system based on special-purpose hardware performs a specified function or action or performs a combination of special-purpose hardware and computer instructions.

[0097] Although the above has described multiple parts of this theme in the general context of computer executable instructions of a computer program product running on a computer and / or multiple computers, it will be appreciated by those skilled in the art that this disclosure can also or can be implemented in conjunction with other program modules. Typically, program modules include routines, programs, components, data structures, etc. that perform specific tasks and / or implement specific abstract data types. In addition, it will be appreciated by those skilled in the art that the computer-implemented method of the present invention can be practiced with other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, large computers, and computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer or industrial electronic products, etc. The illustrated aspects can also be practiced in a distributed computing environment in which tasks are performed by a remote processing device linked by a communication network. However, some aspects of the present disclosure (if not all) can be practiced on a stand-alone computer. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

[0098] As used in this application, the terms "component", "system", "platform", "interface", etc. may refer to and / or may include computer-related entities or entities related to an operating machine having one or more specific functions. The entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process, a processor, an object, an executable file, a thread of execution, a program, and / or a computer running on a processor. As an illustration, both an application running on a server and a server may be a component. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In another example, a corresponding component may be executed from different computer-readable media having different data structures stored thereon. Components may communicate via local and / or remote processes, such as according to a signal with one or more data packets (e.g., data from a component interacting with another component in a local system, a distributed system, and / or interacting with other systems via a signal across a network (such as the Internet)). As another example, a component may be a device having a specific function provided by a mechanical component operated by an electrical or electronic circuit, which is operated by a software or firmware application executed by a processor. In this case, the processor may be internal or external to the device and may execute at least a portion of a software or firmware application. As yet another example, a component may be a device that provides a particular functionality through an electronic component without a mechanical component, where the electronic component may include a processor or other device for executing software or firmware that at least partially imparts the functionality of the electronic component. In one aspect, the component may emulate the electronic component via, for example, a virtual machine within a cloud computing system.

[0099] In addition, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X employs A or B" is intended to mean any natural inclusive arrangement. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied in any of the foregoing cases. In addition, the articles "a" and "an" used in this specification and the drawings should generally be interpreted as meaning "one or more" unless otherwise specified or clear from the context that they are for the singular form. As used herein, the terms "example" and / or "exemplary" are used to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited to such examples. In addition, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be interpreted as being preferred or advantageous over other aspects or designs, nor is it intended to exclude equivalent exemplary structures and techniques known to those of ordinary skill in the art.

[0100] As used in this specification, the term "processor" may refer to substantially any computing processing unit or device, including but not limited to a single-core processor; a single processor with software multithreaded execution capability; a multi-core processor; a multi-core processor with software multithreaded execution capability; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. In addition, a processor may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, the processor may utilize nanoscale architectures, such as but not limited to transistors, switches, and gates based on molecules and quantum dots, in order to optimize space usage or enhance the performance of user devices. The processor may also be implemented as a combination of computing processing units. In this disclosure, terms such as "storage", "storage device", "data storage", "data storage device", "data storage device", "database", and substantially any other information storage component related to the operation and function of the component are used to refer to a "memory component", an entity embodied in a "memory", or a component including a memory. It should be understood that the memory and / or memory components described herein may be volatile memory or non-volatile memory, or may include both volatile memory and non-volatile memory. As an illustration and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include RAM, which may, for example, act as an external cache memory. As an illustration and not limitation, RAM is available in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). In addition, the memory components of the system or computer-implemented method disclosed herein are intended to include, but are not limited to, including these and any other suitable types of memory.

[0101] The foregoing includes only examples of systems and computer-implemented methods. Of course, for the purpose of describing the present disclosure, it is not possible to describe every conceivable combination of components or computer-implemented methods, but one of ordinary skill in the art will recognize that many further combinations and arrangements of the present disclosure are possible. In addition, with respect to the use of the terms "including," "having," "having," and the like in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in a manner similar to the term "comprising," as "comprising" is interpreted when used as a transitional word in the claims. Descriptions of different embodiments have been presented for illustrative purposes, but the descriptions are not intended to be exhaustive or limited to the disclosed embodiments. Various modifications and variations will be apparent to one of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements in technology found on the market, or to enable one of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A computer-implemented method comprising: applying, by a device operatively coupled to the processor, respective weights to a plurality of matrix elements of a first matrix corresponding to a quantum circuit according to respective numbers of quantum gates between respective pairs of qubits in the quantum circuit; transforming, by the device, the first matrix into a second matrix based on respective weights of the matrix elements; The device permutes each qubit in the quantum circuit according to the second matrix, thereby obtaining a permuted quantum circuit; as well as mapping the permuted quantum circuit onto a quantum computing architecture, The transformation includes: generating an ordered list of qubits based on the respective weights of the matrix elements; and The first matrix is ​​transformed into the second matrix based on the ordered list of qubits.

2. The computer-implemented method of claim 1 , wherein said generating comprises: selecting a qubit in the quantum circuit as a first qubit in the ordered list of qubits, the qubit having a first number of inter-qubit connections and a first combinatorial matrix element weight; and The qubits are stored in the ordered list of qubits by increasing the number of inter-qubit connections and decreasing the combinatorial matrix element weights from the first number of inter-qubit connections and the first combinatorial matrix element weights, respectively.

3. The computer-implemented method of claim 1 , wherein the transforming further comprises: inverting the ordered list of qubits to produce a reversed ordered list of qubits; and Based on the qubit inversion ordered list, the first matrix is ​​transformed into the second matrix.

4. The computer-implemented method of claim 1 , wherein said generating comprises: The first matrix is ​​transformed into the second matrix via a breadth-first search.

5. A computer system comprising a memory storing machine-readable instructions and a processor for executing the machine-readable instructions, wherein when the machine-readable instructions are executed by the processor, the processor implements all the steps of the method according to any one of claims 1 to 4.

6. A computer program product comprising computer program instructions for performing all the steps of the method according to any one of claims 1 to 4 when the computer program instructions are executed on a computer system.

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